pci-dma.c 6.1 KB

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  1. #include <linux/dma-mapping.h>
  2. #include <linux/dmar.h>
  3. #include <linux/bootmem.h>
  4. #include <linux/pci.h>
  5. #include <asm/proto.h>
  6. #include <asm/dma.h>
  7. #include <asm/iommu.h>
  8. #include <asm/calgary.h>
  9. #include <asm/amd_iommu.h>
  10. static int forbid_dac __read_mostly;
  11. struct dma_mapping_ops *dma_ops;
  12. EXPORT_SYMBOL(dma_ops);
  13. static int iommu_sac_force __read_mostly;
  14. #ifdef CONFIG_IOMMU_DEBUG
  15. int panic_on_overflow __read_mostly = 1;
  16. int force_iommu __read_mostly = 1;
  17. #else
  18. int panic_on_overflow __read_mostly = 0;
  19. int force_iommu __read_mostly = 0;
  20. #endif
  21. int iommu_merge __read_mostly = 0;
  22. int no_iommu __read_mostly;
  23. /* Set this to 1 if there is a HW IOMMU in the system */
  24. int iommu_detected __read_mostly = 0;
  25. /* This tells the BIO block layer to assume merging. Default to off
  26. because we cannot guarantee merging later. */
  27. int iommu_bio_merge __read_mostly = 0;
  28. EXPORT_SYMBOL(iommu_bio_merge);
  29. dma_addr_t bad_dma_address __read_mostly = 0;
  30. EXPORT_SYMBOL(bad_dma_address);
  31. /* Dummy device used for NULL arguments (normally ISA). Better would
  32. be probably a smaller DMA mask, but this is bug-to-bug compatible
  33. to older i386. */
  34. struct device x86_dma_fallback_dev = {
  35. .bus_id = "fallback device",
  36. .coherent_dma_mask = DMA_32BIT_MASK,
  37. .dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
  38. };
  39. EXPORT_SYMBOL(x86_dma_fallback_dev);
  40. int dma_set_mask(struct device *dev, u64 mask)
  41. {
  42. if (!dev->dma_mask || !dma_supported(dev, mask))
  43. return -EIO;
  44. *dev->dma_mask = mask;
  45. return 0;
  46. }
  47. EXPORT_SYMBOL(dma_set_mask);
  48. #ifdef CONFIG_X86_64
  49. static __initdata void *dma32_bootmem_ptr;
  50. static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
  51. static int __init parse_dma32_size_opt(char *p)
  52. {
  53. if (!p)
  54. return -EINVAL;
  55. dma32_bootmem_size = memparse(p, &p);
  56. return 0;
  57. }
  58. early_param("dma32_size", parse_dma32_size_opt);
  59. void __init dma32_reserve_bootmem(void)
  60. {
  61. unsigned long size, align;
  62. if (max_pfn <= MAX_DMA32_PFN)
  63. return;
  64. /*
  65. * check aperture_64.c allocate_aperture() for reason about
  66. * using 512M as goal
  67. */
  68. align = 64ULL<<20;
  69. size = round_up(dma32_bootmem_size, align);
  70. dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
  71. 512ULL<<20);
  72. if (dma32_bootmem_ptr)
  73. dma32_bootmem_size = size;
  74. else
  75. dma32_bootmem_size = 0;
  76. }
  77. static void __init dma32_free_bootmem(void)
  78. {
  79. if (max_pfn <= MAX_DMA32_PFN)
  80. return;
  81. if (!dma32_bootmem_ptr)
  82. return;
  83. free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);
  84. dma32_bootmem_ptr = NULL;
  85. dma32_bootmem_size = 0;
  86. }
  87. void __init pci_iommu_alloc(void)
  88. {
  89. /* free the range so iommu could get some range less than 4G */
  90. dma32_free_bootmem();
  91. /*
  92. * The order of these functions is important for
  93. * fall-back/fail-over reasons
  94. */
  95. gart_iommu_hole_init();
  96. detect_calgary();
  97. detect_intel_iommu();
  98. amd_iommu_detect();
  99. pci_swiotlb_init();
  100. }
  101. unsigned long iommu_num_pages(unsigned long addr, unsigned long len)
  102. {
  103. unsigned long size = roundup((addr & ~PAGE_MASK) + len, PAGE_SIZE);
  104. return size >> PAGE_SHIFT;
  105. }
  106. EXPORT_SYMBOL(iommu_num_pages);
  107. #endif
  108. /*
  109. * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
  110. * documentation.
  111. */
  112. static __init int iommu_setup(char *p)
  113. {
  114. iommu_merge = 1;
  115. if (!p)
  116. return -EINVAL;
  117. while (*p) {
  118. if (!strncmp(p, "off", 3))
  119. no_iommu = 1;
  120. /* gart_parse_options has more force support */
  121. if (!strncmp(p, "force", 5))
  122. force_iommu = 1;
  123. if (!strncmp(p, "noforce", 7)) {
  124. iommu_merge = 0;
  125. force_iommu = 0;
  126. }
  127. if (!strncmp(p, "biomerge", 8)) {
  128. iommu_bio_merge = 4096;
  129. iommu_merge = 1;
  130. force_iommu = 1;
  131. }
  132. if (!strncmp(p, "panic", 5))
  133. panic_on_overflow = 1;
  134. if (!strncmp(p, "nopanic", 7))
  135. panic_on_overflow = 0;
  136. if (!strncmp(p, "merge", 5)) {
  137. iommu_merge = 1;
  138. force_iommu = 1;
  139. }
  140. if (!strncmp(p, "nomerge", 7))
  141. iommu_merge = 0;
  142. if (!strncmp(p, "forcesac", 8))
  143. iommu_sac_force = 1;
  144. if (!strncmp(p, "allowdac", 8))
  145. forbid_dac = 0;
  146. if (!strncmp(p, "nodac", 5))
  147. forbid_dac = -1;
  148. if (!strncmp(p, "usedac", 6)) {
  149. forbid_dac = -1;
  150. return 1;
  151. }
  152. #ifdef CONFIG_SWIOTLB
  153. if (!strncmp(p, "soft", 4))
  154. swiotlb = 1;
  155. #endif
  156. gart_parse_options(p);
  157. #ifdef CONFIG_CALGARY_IOMMU
  158. if (!strncmp(p, "calgary", 7))
  159. use_calgary = 1;
  160. #endif /* CONFIG_CALGARY_IOMMU */
  161. p += strcspn(p, ",");
  162. if (*p == ',')
  163. ++p;
  164. }
  165. return 0;
  166. }
  167. early_param("iommu", iommu_setup);
  168. int dma_supported(struct device *dev, u64 mask)
  169. {
  170. struct dma_mapping_ops *ops = get_dma_ops(dev);
  171. #ifdef CONFIG_PCI
  172. if (mask > 0xffffffff && forbid_dac > 0) {
  173. dev_info(dev, "PCI: Disallowing DAC for device\n");
  174. return 0;
  175. }
  176. #endif
  177. if (ops->dma_supported)
  178. return ops->dma_supported(dev, mask);
  179. /* Copied from i386. Doesn't make much sense, because it will
  180. only work for pci_alloc_coherent.
  181. The caller just has to use GFP_DMA in this case. */
  182. if (mask < DMA_24BIT_MASK)
  183. return 0;
  184. /* Tell the device to use SAC when IOMMU force is on. This
  185. allows the driver to use cheaper accesses in some cases.
  186. Problem with this is that if we overflow the IOMMU area and
  187. return DAC as fallback address the device may not handle it
  188. correctly.
  189. As a special case some controllers have a 39bit address
  190. mode that is as efficient as 32bit (aic79xx). Don't force
  191. SAC for these. Assume all masks <= 40 bits are of this
  192. type. Normally this doesn't make any difference, but gives
  193. more gentle handling of IOMMU overflow. */
  194. if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
  195. dev_info(dev, "Force SAC with mask %Lx\n", mask);
  196. return 0;
  197. }
  198. return 1;
  199. }
  200. EXPORT_SYMBOL(dma_supported);
  201. static int __init pci_iommu_init(void)
  202. {
  203. calgary_iommu_init();
  204. intel_iommu_init();
  205. amd_iommu_init();
  206. gart_iommu_init();
  207. no_iommu_init();
  208. return 0;
  209. }
  210. void pci_iommu_shutdown(void)
  211. {
  212. gart_iommu_shutdown();
  213. }
  214. /* Must execute after PCI subsystem */
  215. fs_initcall(pci_iommu_init);
  216. #ifdef CONFIG_PCI
  217. /* Many VIA bridges seem to corrupt data for DAC. Disable it here */
  218. static __devinit void via_no_dac(struct pci_dev *dev)
  219. {
  220. if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
  221. printk(KERN_INFO "PCI: VIA PCI bridge detected."
  222. "Disabling DAC.\n");
  223. forbid_dac = 1;
  224. }
  225. }
  226. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
  227. #endif