Kconfig 8.7 KB

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  1. #
  2. # EDAC Kconfig
  3. # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
  4. # Licensed and distributed under the GPL
  5. #
  6. menuconfig EDAC
  7. bool "EDAC (Error Detection And Correction) reporting"
  8. depends on HAS_IOMEM
  9. depends on X86 || PPC || TILE
  10. help
  11. EDAC is designed to report errors in the core system.
  12. These are low-level errors that are reported in the CPU or
  13. supporting chipset or other subsystems:
  14. memory errors, cache errors, PCI errors, thermal throttling, etc..
  15. If unsure, select 'Y'.
  16. If this code is reporting problems on your system, please
  17. see the EDAC project web pages for more information at:
  18. <http://bluesmoke.sourceforge.net/>
  19. and:
  20. <http://buttersideup.com/edacwiki>
  21. There is also a mailing list for the EDAC project, which can
  22. be found via the sourceforge page.
  23. if EDAC
  24. comment "Reporting subsystems"
  25. config EDAC_DEBUG
  26. bool "Debugging"
  27. help
  28. This turns on debugging information for the entire EDAC
  29. sub-system. You can insert module with "debug_level=x", current
  30. there're four debug levels (x=0,1,2,3 from low to high).
  31. Usually you should select 'N'.
  32. config EDAC_DECODE_MCE
  33. tristate "Decode MCEs in human-readable form (only on AMD for now)"
  34. depends on CPU_SUP_AMD && X86_MCE_AMD
  35. default y
  36. ---help---
  37. Enable this option if you want to decode Machine Check Exceptions
  38. occurring on your machine in human-readable form.
  39. You should definitely say Y here in case you want to decode MCEs
  40. which occur really early upon boot, before the module infrastructure
  41. has been initialized.
  42. config EDAC_MCE_INJ
  43. tristate "Simple MCE injection interface over /sysfs"
  44. depends on EDAC_DECODE_MCE
  45. default n
  46. help
  47. This is a simple interface to inject MCEs over /sysfs and test
  48. the MCE decoding code in EDAC.
  49. This is currently AMD-only.
  50. config EDAC_MM_EDAC
  51. tristate "Main Memory EDAC (Error Detection And Correction) reporting"
  52. help
  53. Some systems are able to detect and correct errors in main
  54. memory. EDAC can report statistics on memory error
  55. detection and correction (EDAC - or commonly referred to ECC
  56. errors). EDAC will also try to decode where these errors
  57. occurred so that a particular failing memory module can be
  58. replaced. If unsure, select 'Y'.
  59. config EDAC_MCE
  60. bool
  61. config EDAC_AMD64
  62. tristate "AMD64 (Opteron, Athlon64) K8, F10h"
  63. depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
  64. help
  65. Support for error detection and correction of DRAM ECC errors on
  66. the AMD64 families of memory controllers (K8 and F10h)
  67. config EDAC_AMD64_ERROR_INJECTION
  68. bool "Sysfs HW Error injection facilities"
  69. depends on EDAC_AMD64
  70. help
  71. Recent Opterons (Family 10h and later) provide for Memory Error
  72. Injection into the ECC detection circuits. The amd64_edac module
  73. allows the operator/user to inject Uncorrectable and Correctable
  74. errors into DRAM.
  75. When enabled, in each of the respective memory controller directories
  76. (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  77. - inject_section (0..3, 16-byte section of 64-byte cacheline),
  78. - inject_word (0..8, 16-bit word of 16-byte section),
  79. - inject_ecc_vector (hex ecc vector: select bits of inject word)
  80. In addition, there are two control files, inject_read and inject_write,
  81. which trigger the DRAM ECC Read and Write respectively.
  82. config EDAC_AMD76X
  83. tristate "AMD 76x (760, 762, 768)"
  84. depends on EDAC_MM_EDAC && PCI && X86_32
  85. help
  86. Support for error detection and correction on the AMD 76x
  87. series of chipsets used with the Athlon processor.
  88. config EDAC_E7XXX
  89. tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
  90. depends on EDAC_MM_EDAC && PCI && X86_32
  91. help
  92. Support for error detection and correction on the Intel
  93. E7205, E7500, E7501 and E7505 server chipsets.
  94. config EDAC_E752X
  95. tristate "Intel e752x (e7520, e7525, e7320) and 3100"
  96. depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
  97. help
  98. Support for error detection and correction on the Intel
  99. E7520, E7525, E7320 server chipsets.
  100. config EDAC_I82443BXGX
  101. tristate "Intel 82443BX/GX (440BX/GX)"
  102. depends on EDAC_MM_EDAC && PCI && X86_32
  103. depends on BROKEN
  104. help
  105. Support for error detection and correction on the Intel
  106. 82443BX/GX memory controllers (440BX/GX chipsets).
  107. config EDAC_I82875P
  108. tristate "Intel 82875p (D82875P, E7210)"
  109. depends on EDAC_MM_EDAC && PCI && X86_32
  110. help
  111. Support for error detection and correction on the Intel
  112. DP82785P and E7210 server chipsets.
  113. config EDAC_I82975X
  114. tristate "Intel 82975x (D82975x)"
  115. depends on EDAC_MM_EDAC && PCI && X86
  116. help
  117. Support for error detection and correction on the Intel
  118. DP82975x server chipsets.
  119. config EDAC_I3000
  120. tristate "Intel 3000/3010"
  121. depends on EDAC_MM_EDAC && PCI && X86
  122. help
  123. Support for error detection and correction on the Intel
  124. 3000 and 3010 server chipsets.
  125. config EDAC_I3200
  126. tristate "Intel 3200"
  127. depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
  128. help
  129. Support for error detection and correction on the Intel
  130. 3200 and 3210 server chipsets.
  131. config EDAC_X38
  132. tristate "Intel X38"
  133. depends on EDAC_MM_EDAC && PCI && X86
  134. help
  135. Support for error detection and correction on the Intel
  136. X38 server chipsets.
  137. config EDAC_I5400
  138. tristate "Intel 5400 (Seaburg) chipsets"
  139. depends on EDAC_MM_EDAC && PCI && X86
  140. help
  141. Support for error detection and correction the Intel
  142. i5400 MCH chipset (Seaburg).
  143. config EDAC_I7CORE
  144. tristate "Intel i7 Core (Nehalem) processors"
  145. depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
  146. help
  147. Support for error detection and correction the Intel
  148. i7 Core (Nehalem) Integrated Memory Controller that exists on
  149. newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
  150. and Xeon 55xx processors.
  151. config EDAC_I82860
  152. tristate "Intel 82860"
  153. depends on EDAC_MM_EDAC && PCI && X86_32
  154. help
  155. Support for error detection and correction on the Intel
  156. 82860 chipset.
  157. config EDAC_R82600
  158. tristate "Radisys 82600 embedded chipset"
  159. depends on EDAC_MM_EDAC && PCI && X86_32
  160. help
  161. Support for error detection and correction on the Radisys
  162. 82600 embedded chipset.
  163. config EDAC_I5000
  164. tristate "Intel Greencreek/Blackford chipset"
  165. depends on EDAC_MM_EDAC && X86 && PCI
  166. help
  167. Support for error detection and correction the Intel
  168. Greekcreek/Blackford chipsets.
  169. config EDAC_I5100
  170. tristate "Intel San Clemente MCH"
  171. depends on EDAC_MM_EDAC && X86 && PCI
  172. help
  173. Support for error detection and correction the Intel
  174. San Clemente MCH.
  175. config EDAC_I7300
  176. tristate "Intel Clarksboro MCH"
  177. depends on EDAC_MM_EDAC && X86 && PCI
  178. help
  179. Support for error detection and correction the Intel
  180. Clarksboro MCH (Intel 7300 chipset).
  181. config EDAC_MPC85XX
  182. tristate "Freescale MPC83xx / MPC85xx"
  183. depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
  184. help
  185. Support for error detection and correction on the Freescale
  186. MPC8349, MPC8560, MPC8540, MPC8548
  187. config EDAC_MV64X60
  188. tristate "Marvell MV64x60"
  189. depends on EDAC_MM_EDAC && MV64X60
  190. help
  191. Support for error detection and correction on the Marvell
  192. MV64360 and MV64460 chipsets.
  193. config EDAC_PASEMI
  194. tristate "PA Semi PWRficient"
  195. depends on EDAC_MM_EDAC && PCI
  196. depends on PPC_PASEMI
  197. help
  198. Support for error detection and correction on PA Semi
  199. PWRficient.
  200. config EDAC_CELL
  201. tristate "Cell Broadband Engine memory controller"
  202. depends on EDAC_MM_EDAC && PPC_CELL_COMMON
  203. help
  204. Support for error detection and correction on the
  205. Cell Broadband Engine internal memory controller
  206. on platform without a hypervisor
  207. config EDAC_PPC4XX
  208. tristate "PPC4xx IBM DDR2 Memory Controller"
  209. depends on EDAC_MM_EDAC && 4xx
  210. help
  211. This enables support for EDAC on the ECC memory used
  212. with the IBM DDR2 memory controller found in various
  213. PowerPC 4xx embedded processors such as the 405EX[r],
  214. 440SP, 440SPe, 460EX, 460GT and 460SX.
  215. config EDAC_AMD8131
  216. tristate "AMD8131 HyperTransport PCI-X Tunnel"
  217. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  218. help
  219. Support for error detection and correction on the
  220. AMD8131 HyperTransport PCI-X Tunnel chip.
  221. Note, add more Kconfig dependency if it's adopted
  222. on some machine other than Maple.
  223. config EDAC_AMD8111
  224. tristate "AMD8111 HyperTransport I/O Hub"
  225. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  226. help
  227. Support for error detection and correction on the
  228. AMD8111 HyperTransport I/O Hub chip.
  229. Note, add more Kconfig dependency if it's adopted
  230. on some machine other than Maple.
  231. config EDAC_CPC925
  232. tristate "IBM CPC925 Memory Controller (PPC970FX)"
  233. depends on EDAC_MM_EDAC && PPC64
  234. help
  235. Support for error detection and correction on the
  236. IBM CPC925 Bridge and Memory Controller, which is
  237. a companion chip to the PowerPC 970 family of
  238. processors.
  239. config EDAC_TILE
  240. tristate "Tilera Memory Controller"
  241. depends on EDAC_MM_EDAC && TILE
  242. default y
  243. help
  244. Support for error detection and correction on the
  245. Tilera memory controller.
  246. endif # EDAC