book3s_32_mmu_host.c 12 KB

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  1. /*
  2. * Copyright (C) 2010 SUSE Linux Products GmbH. All rights reserved.
  3. *
  4. * Authors:
  5. * Alexander Graf <agraf@suse.de>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2, as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  19. */
  20. #include <linux/kvm_host.h>
  21. #include <asm/kvm_ppc.h>
  22. #include <asm/kvm_book3s.h>
  23. #include <asm/mmu-hash32.h>
  24. #include <asm/machdep.h>
  25. #include <asm/mmu_context.h>
  26. #include <asm/hw_irq.h>
  27. /* #define DEBUG_MMU */
  28. /* #define DEBUG_SR */
  29. #ifdef DEBUG_MMU
  30. #define dprintk_mmu(a, ...) printk(KERN_INFO a, __VA_ARGS__)
  31. #else
  32. #define dprintk_mmu(a, ...) do { } while(0)
  33. #endif
  34. #ifdef DEBUG_SR
  35. #define dprintk_sr(a, ...) printk(KERN_INFO a, __VA_ARGS__)
  36. #else
  37. #define dprintk_sr(a, ...) do { } while(0)
  38. #endif
  39. #if PAGE_SHIFT != 12
  40. #error Unknown page size
  41. #endif
  42. #ifdef CONFIG_SMP
  43. #error XXX need to grab mmu_hash_lock
  44. #endif
  45. #ifdef CONFIG_PTE_64BIT
  46. #error Only 32 bit pages are supported for now
  47. #endif
  48. static void invalidate_pte(struct kvm_vcpu *vcpu, struct hpte_cache *pte)
  49. {
  50. volatile u32 *pteg;
  51. dprintk_mmu("KVM: Flushing SPTE: 0x%llx (0x%llx) -> 0x%llx\n",
  52. pte->pte.eaddr, pte->pte.vpage, pte->host_va);
  53. pteg = (u32*)pte->slot;
  54. pteg[0] = 0;
  55. asm volatile ("sync");
  56. asm volatile ("tlbie %0" : : "r" (pte->pte.eaddr) : "memory");
  57. asm volatile ("sync");
  58. asm volatile ("tlbsync");
  59. pte->host_va = 0;
  60. if (pte->pte.may_write)
  61. kvm_release_pfn_dirty(pte->pfn);
  62. else
  63. kvm_release_pfn_clean(pte->pfn);
  64. }
  65. void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, ulong guest_ea, ulong ea_mask)
  66. {
  67. int i;
  68. dprintk_mmu("KVM: Flushing %d Shadow PTEs: 0x%x & 0x%x\n",
  69. vcpu->arch.hpte_cache_offset, guest_ea, ea_mask);
  70. BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
  71. guest_ea &= ea_mask;
  72. for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
  73. struct hpte_cache *pte;
  74. pte = &vcpu->arch.hpte_cache[i];
  75. if (!pte->host_va)
  76. continue;
  77. if ((pte->pte.eaddr & ea_mask) == guest_ea) {
  78. invalidate_pte(vcpu, pte);
  79. }
  80. }
  81. /* Doing a complete flush -> start from scratch */
  82. if (!ea_mask)
  83. vcpu->arch.hpte_cache_offset = 0;
  84. }
  85. void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 guest_vp, u64 vp_mask)
  86. {
  87. int i;
  88. dprintk_mmu("KVM: Flushing %d Shadow vPTEs: 0x%llx & 0x%llx\n",
  89. vcpu->arch.hpte_cache_offset, guest_vp, vp_mask);
  90. BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
  91. guest_vp &= vp_mask;
  92. for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
  93. struct hpte_cache *pte;
  94. pte = &vcpu->arch.hpte_cache[i];
  95. if (!pte->host_va)
  96. continue;
  97. if ((pte->pte.vpage & vp_mask) == guest_vp) {
  98. invalidate_pte(vcpu, pte);
  99. }
  100. }
  101. }
  102. void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, ulong pa_start, ulong pa_end)
  103. {
  104. int i;
  105. dprintk_mmu("KVM: Flushing %d Shadow pPTEs: 0x%llx & 0x%llx\n",
  106. vcpu->arch.hpte_cache_offset, pa_start, pa_end);
  107. BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
  108. for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
  109. struct hpte_cache *pte;
  110. pte = &vcpu->arch.hpte_cache[i];
  111. if (!pte->host_va)
  112. continue;
  113. if ((pte->pte.raddr >= pa_start) &&
  114. (pte->pte.raddr < pa_end)) {
  115. invalidate_pte(vcpu, pte);
  116. }
  117. }
  118. }
  119. struct kvmppc_pte *kvmppc_mmu_find_pte(struct kvm_vcpu *vcpu, u64 ea, bool data)
  120. {
  121. int i;
  122. u64 guest_vp;
  123. guest_vp = vcpu->arch.mmu.ea_to_vp(vcpu, ea, false);
  124. for (i=0; i<vcpu->arch.hpte_cache_offset; i++) {
  125. struct hpte_cache *pte;
  126. pte = &vcpu->arch.hpte_cache[i];
  127. if (!pte->host_va)
  128. continue;
  129. if (pte->pte.vpage == guest_vp)
  130. return &pte->pte;
  131. }
  132. return NULL;
  133. }
  134. static int kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu)
  135. {
  136. if (vcpu->arch.hpte_cache_offset == HPTEG_CACHE_NUM)
  137. kvmppc_mmu_pte_flush(vcpu, 0, 0);
  138. return vcpu->arch.hpte_cache_offset++;
  139. }
  140. /* We keep 512 gvsid->hvsid entries, mapping the guest ones to the array using
  141. * a hash, so we don't waste cycles on looping */
  142. static u16 kvmppc_sid_hash(struct kvm_vcpu *vcpu, u64 gvsid)
  143. {
  144. return (u16)(((gvsid >> (SID_MAP_BITS * 7)) & SID_MAP_MASK) ^
  145. ((gvsid >> (SID_MAP_BITS * 6)) & SID_MAP_MASK) ^
  146. ((gvsid >> (SID_MAP_BITS * 5)) & SID_MAP_MASK) ^
  147. ((gvsid >> (SID_MAP_BITS * 4)) & SID_MAP_MASK) ^
  148. ((gvsid >> (SID_MAP_BITS * 3)) & SID_MAP_MASK) ^
  149. ((gvsid >> (SID_MAP_BITS * 2)) & SID_MAP_MASK) ^
  150. ((gvsid >> (SID_MAP_BITS * 1)) & SID_MAP_MASK) ^
  151. ((gvsid >> (SID_MAP_BITS * 0)) & SID_MAP_MASK));
  152. }
  153. static struct kvmppc_sid_map *find_sid_vsid(struct kvm_vcpu *vcpu, u64 gvsid)
  154. {
  155. struct kvmppc_sid_map *map;
  156. u16 sid_map_mask;
  157. if (vcpu->arch.msr & MSR_PR)
  158. gvsid |= VSID_PR;
  159. sid_map_mask = kvmppc_sid_hash(vcpu, gvsid);
  160. map = &to_book3s(vcpu)->sid_map[sid_map_mask];
  161. if (map->guest_vsid == gvsid) {
  162. dprintk_sr("SR: Searching 0x%llx -> 0x%llx\n",
  163. gvsid, map->host_vsid);
  164. return map;
  165. }
  166. map = &to_book3s(vcpu)->sid_map[SID_MAP_MASK - sid_map_mask];
  167. if (map->guest_vsid == gvsid) {
  168. dprintk_sr("SR: Searching 0x%llx -> 0x%llx\n",
  169. gvsid, map->host_vsid);
  170. return map;
  171. }
  172. dprintk_sr("SR: Searching 0x%llx -> not found\n", gvsid);
  173. return NULL;
  174. }
  175. extern struct hash_pte *Hash;
  176. extern unsigned long _SDR1;
  177. static u32 *kvmppc_mmu_get_pteg(struct kvm_vcpu *vcpu, u32 vsid, u32 eaddr,
  178. bool primary)
  179. {
  180. u32 page, hash, htabmask;
  181. ulong pteg = (ulong)Hash;
  182. page = (eaddr & ~ESID_MASK) >> 12;
  183. hash = ((vsid ^ page) << 6);
  184. if (!primary)
  185. hash = ~hash;
  186. htabmask = ((_SDR1 & 0x1FF) << 16) | 0xFFC0;
  187. hash &= htabmask;
  188. pteg |= hash;
  189. dprintk_mmu("htab: %p | hash: %x | htabmask: %x | pteg: %lx\n",
  190. Hash, hash, htabmask, pteg);
  191. return (u32*)pteg;
  192. }
  193. extern char etext[];
  194. int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
  195. {
  196. pfn_t hpaddr;
  197. u64 va;
  198. u64 vsid;
  199. struct kvmppc_sid_map *map;
  200. volatile u32 *pteg;
  201. u32 eaddr = orig_pte->eaddr;
  202. u32 pteg0, pteg1;
  203. register int rr = 0;
  204. bool primary = false;
  205. bool evict = false;
  206. int hpte_id;
  207. struct hpte_cache *pte;
  208. /* Get host physical address for gpa */
  209. hpaddr = gfn_to_pfn(vcpu->kvm, orig_pte->raddr >> PAGE_SHIFT);
  210. if (kvm_is_error_hva(hpaddr)) {
  211. printk(KERN_INFO "Couldn't get guest page for gfn %lx!\n",
  212. orig_pte->eaddr);
  213. return -EINVAL;
  214. }
  215. hpaddr <<= PAGE_SHIFT;
  216. /* and write the mapping ea -> hpa into the pt */
  217. vcpu->arch.mmu.esid_to_vsid(vcpu, orig_pte->eaddr >> SID_SHIFT, &vsid);
  218. map = find_sid_vsid(vcpu, vsid);
  219. if (!map) {
  220. kvmppc_mmu_map_segment(vcpu, eaddr);
  221. map = find_sid_vsid(vcpu, vsid);
  222. }
  223. BUG_ON(!map);
  224. vsid = map->host_vsid;
  225. va = (vsid << SID_SHIFT) | (eaddr & ~ESID_MASK);
  226. next_pteg:
  227. if (rr == 16) {
  228. primary = !primary;
  229. evict = true;
  230. rr = 0;
  231. }
  232. pteg = kvmppc_mmu_get_pteg(vcpu, vsid, eaddr, primary);
  233. /* not evicting yet */
  234. if (!evict && (pteg[rr] & PTE_V)) {
  235. rr += 2;
  236. goto next_pteg;
  237. }
  238. dprintk_mmu("KVM: old PTEG: %p (%d)\n", pteg, rr);
  239. dprintk_mmu("KVM: %08x - %08x\n", pteg[0], pteg[1]);
  240. dprintk_mmu("KVM: %08x - %08x\n", pteg[2], pteg[3]);
  241. dprintk_mmu("KVM: %08x - %08x\n", pteg[4], pteg[5]);
  242. dprintk_mmu("KVM: %08x - %08x\n", pteg[6], pteg[7]);
  243. dprintk_mmu("KVM: %08x - %08x\n", pteg[8], pteg[9]);
  244. dprintk_mmu("KVM: %08x - %08x\n", pteg[10], pteg[11]);
  245. dprintk_mmu("KVM: %08x - %08x\n", pteg[12], pteg[13]);
  246. dprintk_mmu("KVM: %08x - %08x\n", pteg[14], pteg[15]);
  247. pteg0 = ((eaddr & 0x0fffffff) >> 22) | (vsid << 7) | PTE_V |
  248. (primary ? 0 : PTE_SEC);
  249. pteg1 = hpaddr | PTE_M | PTE_R | PTE_C;
  250. if (orig_pte->may_write) {
  251. pteg1 |= PP_RWRW;
  252. mark_page_dirty(vcpu->kvm, orig_pte->raddr >> PAGE_SHIFT);
  253. } else {
  254. pteg1 |= PP_RWRX;
  255. }
  256. local_irq_disable();
  257. if (pteg[rr]) {
  258. pteg[rr] = 0;
  259. asm volatile ("sync");
  260. }
  261. pteg[rr + 1] = pteg1;
  262. pteg[rr] = pteg0;
  263. asm volatile ("sync");
  264. local_irq_enable();
  265. dprintk_mmu("KVM: new PTEG: %p\n", pteg);
  266. dprintk_mmu("KVM: %08x - %08x\n", pteg[0], pteg[1]);
  267. dprintk_mmu("KVM: %08x - %08x\n", pteg[2], pteg[3]);
  268. dprintk_mmu("KVM: %08x - %08x\n", pteg[4], pteg[5]);
  269. dprintk_mmu("KVM: %08x - %08x\n", pteg[6], pteg[7]);
  270. dprintk_mmu("KVM: %08x - %08x\n", pteg[8], pteg[9]);
  271. dprintk_mmu("KVM: %08x - %08x\n", pteg[10], pteg[11]);
  272. dprintk_mmu("KVM: %08x - %08x\n", pteg[12], pteg[13]);
  273. dprintk_mmu("KVM: %08x - %08x\n", pteg[14], pteg[15]);
  274. /* Now tell our Shadow PTE code about the new page */
  275. hpte_id = kvmppc_mmu_hpte_cache_next(vcpu);
  276. pte = &vcpu->arch.hpte_cache[hpte_id];
  277. dprintk_mmu("KVM: %c%c Map 0x%llx: [%lx] 0x%llx (0x%llx) -> %lx\n",
  278. orig_pte->may_write ? 'w' : '-',
  279. orig_pte->may_execute ? 'x' : '-',
  280. orig_pte->eaddr, (ulong)pteg, va,
  281. orig_pte->vpage, hpaddr);
  282. pte->slot = (ulong)&pteg[rr];
  283. pte->host_va = va;
  284. pte->pte = *orig_pte;
  285. pte->pfn = hpaddr >> PAGE_SHIFT;
  286. return 0;
  287. }
  288. static struct kvmppc_sid_map *create_sid_map(struct kvm_vcpu *vcpu, u64 gvsid)
  289. {
  290. struct kvmppc_sid_map *map;
  291. struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
  292. u16 sid_map_mask;
  293. static int backwards_map = 0;
  294. if (vcpu->arch.msr & MSR_PR)
  295. gvsid |= VSID_PR;
  296. /* We might get collisions that trap in preceding order, so let's
  297. map them differently */
  298. sid_map_mask = kvmppc_sid_hash(vcpu, gvsid);
  299. if (backwards_map)
  300. sid_map_mask = SID_MAP_MASK - sid_map_mask;
  301. map = &to_book3s(vcpu)->sid_map[sid_map_mask];
  302. /* Make sure we're taking the other map next time */
  303. backwards_map = !backwards_map;
  304. /* Uh-oh ... out of mappings. Let's flush! */
  305. if (vcpu_book3s->vsid_next >= vcpu_book3s->vsid_max) {
  306. vcpu_book3s->vsid_next = vcpu_book3s->vsid_first;
  307. memset(vcpu_book3s->sid_map, 0,
  308. sizeof(struct kvmppc_sid_map) * SID_MAP_NUM);
  309. kvmppc_mmu_pte_flush(vcpu, 0, 0);
  310. kvmppc_mmu_flush_segments(vcpu);
  311. }
  312. map->host_vsid = vcpu_book3s->vsid_next;
  313. /* Would have to be 111 to be completely aligned with the rest of
  314. Linux, but that is just way too little space! */
  315. vcpu_book3s->vsid_next+=1;
  316. map->guest_vsid = gvsid;
  317. map->valid = true;
  318. return map;
  319. }
  320. int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr)
  321. {
  322. u32 esid = eaddr >> SID_SHIFT;
  323. u64 gvsid;
  324. u32 sr;
  325. struct kvmppc_sid_map *map;
  326. struct kvmppc_book3s_shadow_vcpu *svcpu = to_svcpu(vcpu);
  327. if (vcpu->arch.mmu.esid_to_vsid(vcpu, esid, &gvsid)) {
  328. /* Invalidate an entry */
  329. svcpu->sr[esid] = SR_INVALID;
  330. return -ENOENT;
  331. }
  332. map = find_sid_vsid(vcpu, gvsid);
  333. if (!map)
  334. map = create_sid_map(vcpu, gvsid);
  335. map->guest_esid = esid;
  336. sr = map->host_vsid | SR_KP;
  337. svcpu->sr[esid] = sr;
  338. dprintk_sr("MMU: mtsr %d, 0x%x\n", esid, sr);
  339. return 0;
  340. }
  341. void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu)
  342. {
  343. int i;
  344. struct kvmppc_book3s_shadow_vcpu *svcpu = to_svcpu(vcpu);
  345. dprintk_sr("MMU: flushing all segments (%d)\n", ARRAY_SIZE(svcpu->sr));
  346. for (i = 0; i < ARRAY_SIZE(svcpu->sr); i++)
  347. svcpu->sr[i] = SR_INVALID;
  348. }
  349. void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
  350. {
  351. kvmppc_mmu_pte_flush(vcpu, 0, 0);
  352. preempt_disable();
  353. __destroy_context(to_book3s(vcpu)->context_id);
  354. preempt_enable();
  355. }
  356. /* From mm/mmu_context_hash32.c */
  357. #define CTX_TO_VSID(ctx) (((ctx) * (897 * 16)) & 0xffffff)
  358. int kvmppc_mmu_init(struct kvm_vcpu *vcpu)
  359. {
  360. struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu);
  361. int err;
  362. err = __init_new_context();
  363. if (err < 0)
  364. return -1;
  365. vcpu3s->context_id = err;
  366. vcpu3s->vsid_max = CTX_TO_VSID(vcpu3s->context_id + 1) - 1;
  367. vcpu3s->vsid_first = CTX_TO_VSID(vcpu3s->context_id);
  368. #if 0 /* XXX still doesn't guarantee uniqueness */
  369. /* We could collide with the Linux vsid space because the vsid
  370. * wraps around at 24 bits. We're safe if we do our own space
  371. * though, so let's always set the highest bit. */
  372. vcpu3s->vsid_max |= 0x00800000;
  373. vcpu3s->vsid_first |= 0x00800000;
  374. #endif
  375. BUG_ON(vcpu3s->vsid_max < vcpu3s->vsid_first);
  376. vcpu3s->vsid_next = vcpu3s->vsid_first;
  377. return 0;
  378. }