setup.c 10 KB

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  1. /*
  2. * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/seq_file.h>
  9. #include <linux/fs.h>
  10. #include <linux/delay.h>
  11. #include <linux/root_dev.h>
  12. #include <linux/console.h>
  13. #include <linux/module.h>
  14. #include <linux/cpu.h>
  15. #include <linux/of_fdt.h>
  16. #include <asm/sections.h>
  17. #include <asm/arcregs.h>
  18. #include <asm/tlb.h>
  19. #include <asm/cache.h>
  20. #include <asm/setup.h>
  21. #include <asm/page.h>
  22. #include <asm/irq.h>
  23. #include <asm/arcregs.h>
  24. #include <asm/prom.h>
  25. #include <asm/unwind.h>
  26. #include <asm/clk.h>
  27. #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
  28. int running_on_hw = 1; /* vs. on ISS */
  29. char __initdata command_line[COMMAND_LINE_SIZE];
  30. struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
  31. struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
  32. void __init read_arc_build_cfg_regs(void)
  33. {
  34. struct bcr_perip uncached_space;
  35. struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
  36. FIX_PTR(cpu);
  37. READ_BCR(AUX_IDENTITY, cpu->core);
  38. cpu->timers = read_aux_reg(ARC_REG_TIMERS_BCR);
  39. cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
  40. if (cpu->vec_base == 0)
  41. cpu->vec_base = (unsigned int)_int_vec_base_lds;
  42. READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
  43. cpu->uncached_base = uncached_space.start << 24;
  44. cpu->extn.mul = read_aux_reg(ARC_REG_MUL_BCR);
  45. cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR);
  46. cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR);
  47. cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR);
  48. cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR);
  49. READ_BCR(ARC_REG_MAC_BCR, cpu->extn_mac_mul);
  50. cpu->extn.ext_arith = read_aux_reg(ARC_REG_EXTARITH_BCR);
  51. cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR);
  52. READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
  53. read_decode_mmu_bcr();
  54. read_decode_cache_bcr();
  55. READ_BCR(ARC_REG_FP_BCR, cpu->fp);
  56. READ_BCR(ARC_REG_DPFP_BCR, cpu->dpfp);
  57. }
  58. static const struct cpuinfo_data arc_cpu_tbl[] = {
  59. { {0x10, "ARCTangent A5"}, 0x1F},
  60. { {0x20, "ARC 600" }, 0x2F},
  61. { {0x30, "ARC 700" }, 0x33},
  62. { {0x34, "ARC 700 R4.10"}, 0x34},
  63. { {0x00, NULL } }
  64. };
  65. char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
  66. {
  67. int n = 0;
  68. struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
  69. struct bcr_identity *core = &cpu->core;
  70. const struct cpuinfo_data *tbl;
  71. int be = 0;
  72. #ifdef CONFIG_CPU_BIG_ENDIAN
  73. be = 1;
  74. #endif
  75. FIX_PTR(cpu);
  76. n += scnprintf(buf + n, len - n,
  77. "\nARC IDENTITY\t: Family [%#02x]"
  78. " Cpu-id [%#02x] Chip-id [%#4x]\n",
  79. core->family, core->cpu_id,
  80. core->chip_id);
  81. for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
  82. if ((core->family >= tbl->info.id) &&
  83. (core->family <= tbl->up_range)) {
  84. n += scnprintf(buf + n, len - n,
  85. "processor\t: %s %s\n",
  86. tbl->info.str,
  87. be ? "[Big Endian]" : "");
  88. break;
  89. }
  90. }
  91. if (tbl->info.id == 0)
  92. n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n");
  93. n += scnprintf(buf + n, len - n, "CPU speed\t: %u.%02u Mhz\n",
  94. (unsigned int)(arc_get_core_freq() / 1000000),
  95. (unsigned int)(arc_get_core_freq() / 10000) % 100);
  96. n += scnprintf(buf + n, len - n, "Timers\t\t: %s %s\n",
  97. (cpu->timers & 0x200) ? "TIMER1" : "",
  98. (cpu->timers & 0x100) ? "TIMER0" : "");
  99. n += scnprintf(buf + n, len - n, "Vect Tbl Base\t: %#x\n",
  100. cpu->vec_base);
  101. n += scnprintf(buf + n, len - n, "UNCACHED Base\t: %#x\n",
  102. cpu->uncached_base);
  103. return buf;
  104. }
  105. static const struct id_to_str mul_type_nm[] = {
  106. { 0x0, "N/A"},
  107. { 0x1, "32x32 (spl Result Reg)" },
  108. { 0x2, "32x32 (ANY Result Reg)" }
  109. };
  110. static const struct id_to_str mac_mul_nm[] = {
  111. {0x0, "N/A"},
  112. {0x1, "N/A"},
  113. {0x2, "Dual 16 x 16"},
  114. {0x3, "N/A"},
  115. {0x4, "32x16"},
  116. {0x5, "N/A"},
  117. {0x6, "Dual 16x16 and 32x16"}
  118. };
  119. char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
  120. {
  121. int n = 0;
  122. struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
  123. FIX_PTR(cpu);
  124. #define IS_AVAIL1(var, str) ((var) ? str : "")
  125. #define IS_AVAIL2(var, str) ((var == 0x2) ? str : "")
  126. #define IS_USED(var) ((var) ? "(in-use)" : "(not used)")
  127. n += scnprintf(buf + n, len - n,
  128. "Extn [700-Base]\t: %s %s %s %s %s %s\n",
  129. IS_AVAIL2(cpu->extn.norm, "norm,"),
  130. IS_AVAIL2(cpu->extn.barrel, "barrel-shift,"),
  131. IS_AVAIL1(cpu->extn.swap, "swap,"),
  132. IS_AVAIL2(cpu->extn.minmax, "minmax,"),
  133. IS_AVAIL1(cpu->extn.crc, "crc,"),
  134. IS_AVAIL2(cpu->extn.ext_arith, "ext-arith"));
  135. n += scnprintf(buf + n, len - n, "Extn [700-MPY]\t: %s",
  136. mul_type_nm[cpu->extn.mul].str);
  137. n += scnprintf(buf + n, len - n, " MAC MPY: %s\n",
  138. mac_mul_nm[cpu->extn_mac_mul.type].str);
  139. if (cpu->core.family == 0x34) {
  140. n += scnprintf(buf + n, len - n,
  141. "Extn [700-4.10]\t: LLOCK/SCOND %s, SWAPE %s, RTSC %s\n",
  142. IS_USED(__CONFIG_ARC_HAS_LLSC_VAL),
  143. IS_USED(__CONFIG_ARC_HAS_SWAPE_VAL),
  144. IS_USED(__CONFIG_ARC_HAS_RTSC_VAL));
  145. }
  146. n += scnprintf(buf + n, len - n, "Extn [CCM]\t: %s",
  147. !(cpu->dccm.sz || cpu->iccm.sz) ? "N/A" : "");
  148. if (cpu->dccm.sz)
  149. n += scnprintf(buf + n, len - n, "DCCM: @ %x, %d KB ",
  150. cpu->dccm.base_addr, TO_KB(cpu->dccm.sz));
  151. if (cpu->iccm.sz)
  152. n += scnprintf(buf + n, len - n, "ICCM: @ %x, %d KB",
  153. cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
  154. n += scnprintf(buf + n, len - n, "\nExtn [FPU]\t: %s",
  155. !(cpu->fp.ver || cpu->dpfp.ver) ? "N/A" : "");
  156. if (cpu->fp.ver)
  157. n += scnprintf(buf + n, len - n, "SP [v%d] %s",
  158. cpu->fp.ver, cpu->fp.fast ? "(fast)" : "");
  159. if (cpu->dpfp.ver)
  160. n += scnprintf(buf + n, len - n, "DP [v%d] %s",
  161. cpu->dpfp.ver, cpu->dpfp.fast ? "(fast)" : "");
  162. n += scnprintf(buf + n, len - n, "\n");
  163. #ifdef _ASM_GENERIC_UNISTD_H
  164. n += scnprintf(buf + n, len - n,
  165. "OS ABI [v2]\t: asm-generic/{unistd,stat,fcntl}\n");
  166. #endif
  167. return buf;
  168. }
  169. /*
  170. * Ensure that FP hardware and kernel config match
  171. * -If hardware contains DPFP, kernel needs to save/restore FPU state
  172. * across context switches
  173. * -If hardware lacks DPFP, but kernel configured to save FPU state then
  174. * kernel trying to access non-existant DPFP regs will crash
  175. *
  176. * We only check for Dbl precision Floating Point, because only DPFP
  177. * hardware has dedicated regs which need to be saved/restored on ctx-sw
  178. * (Single Precision uses core regs), thus kernel is kind of oblivious to it
  179. */
  180. void __init arc_chk_fpu(void)
  181. {
  182. struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
  183. if (cpu->dpfp.ver) {
  184. #ifndef CONFIG_ARC_FPU_SAVE_RESTORE
  185. pr_warn("DPFP support broken in this kernel...\n");
  186. #endif
  187. } else {
  188. #ifdef CONFIG_ARC_FPU_SAVE_RESTORE
  189. panic("H/w lacks DPFP support, apps won't work\n");
  190. #endif
  191. }
  192. }
  193. /*
  194. * Initialize and setup the processor core
  195. * This is called by all the CPUs thus should not do special case stuff
  196. * such as only for boot CPU etc
  197. */
  198. void __init setup_processor(void)
  199. {
  200. char str[512];
  201. int cpu_id = smp_processor_id();
  202. read_arc_build_cfg_regs();
  203. arc_init_IRQ();
  204. printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
  205. arc_mmu_init();
  206. arc_cache_init();
  207. printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
  208. #ifdef CONFIG_SMP
  209. printk(arc_platform_smp_cpuinfo());
  210. #endif
  211. arc_chk_fpu();
  212. }
  213. void __init __attribute__((weak)) arc_platform_early_init(void)
  214. {
  215. }
  216. void __init setup_arch(char **cmdline_p)
  217. {
  218. int rc;
  219. #ifdef CONFIG_CMDLINE_UBOOT
  220. /* Make sure that a whitespace is inserted before */
  221. strlcat(command_line, " ", sizeof(command_line));
  222. #endif
  223. /*
  224. * Append .config cmdline to base command line, which might already
  225. * contain u-boot "bootargs" (handled by head.S, if so configured)
  226. */
  227. strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line));
  228. /* Save unparsed command line copy for /proc/cmdline */
  229. strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
  230. *cmdline_p = command_line;
  231. rc = setup_machine_fdt(__dtb_start);
  232. /* To force early parsing of things like mem=xxx */
  233. parse_early_param();
  234. /* Platform/board specific: e.g. early console registration */
  235. arc_platform_early_init();
  236. setup_processor();
  237. #ifdef CONFIG_SMP
  238. smp_init_cpus();
  239. #endif
  240. setup_arch_memory();
  241. unflatten_device_tree();
  242. /* Can be issue if someone passes cmd line arg "ro"
  243. * But that is unlikely so keeping it as it is
  244. */
  245. root_mountflags &= ~MS_RDONLY;
  246. console_verbose();
  247. #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
  248. conswitchp = &dummy_con;
  249. #endif
  250. arc_unwind_init();
  251. arc_unwind_setup();
  252. }
  253. /*
  254. * Get CPU information for use by the procfs.
  255. */
  256. #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c)))
  257. #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p))
  258. static int show_cpuinfo(struct seq_file *m, void *v)
  259. {
  260. char *str;
  261. int cpu_id = ptr_to_cpu(v);
  262. str = (char *)__get_free_page(GFP_TEMPORARY);
  263. if (!str)
  264. goto done;
  265. seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
  266. seq_printf(m, "Bogo MIPS : \t%lu.%02lu\n",
  267. loops_per_jiffy / (500000 / HZ),
  268. (loops_per_jiffy / (5000 / HZ)) % 100);
  269. seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
  270. seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
  271. seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
  272. #ifdef CONFIG_SMP
  273. seq_printf(m, arc_platform_smp_cpuinfo());
  274. #endif
  275. free_page((unsigned long)str);
  276. done:
  277. seq_printf(m, "\n\n");
  278. return 0;
  279. }
  280. static void *c_start(struct seq_file *m, loff_t *pos)
  281. {
  282. /*
  283. * Callback returns cpu-id to iterator for show routine, NULL to stop.
  284. * However since NULL is also a valid cpu-id (0), we use a round-about
  285. * way to pass it w/o having to kmalloc/free a 2 byte string.
  286. * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
  287. */
  288. return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL;
  289. }
  290. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  291. {
  292. ++*pos;
  293. return c_start(m, pos);
  294. }
  295. static void c_stop(struct seq_file *m, void *v)
  296. {
  297. }
  298. const struct seq_operations cpuinfo_op = {
  299. .start = c_start,
  300. .next = c_next,
  301. .stop = c_stop,
  302. .show = show_cpuinfo
  303. };
  304. static DEFINE_PER_CPU(struct cpu, cpu_topology);
  305. static int __init topology_init(void)
  306. {
  307. int cpu;
  308. for_each_present_cpu(cpu)
  309. register_cpu(&per_cpu(cpu_topology, cpu), cpu);
  310. return 0;
  311. }
  312. subsys_initcall(topology_init);