async_tx.c 7.6 KB

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  1. /*
  2. * core routines for the asynchronous memory transfer/transform api
  3. *
  4. * Copyright © 2006, Intel Corporation.
  5. *
  6. * Dan Williams <dan.j.williams@intel.com>
  7. *
  8. * with architecture considerations by:
  9. * Neil Brown <neilb@suse.de>
  10. * Jeff Garzik <jeff@garzik.org>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms and conditions of the GNU General Public License,
  14. * version 2, as published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program; if not, write to the Free Software Foundation, Inc.,
  23. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  24. *
  25. */
  26. #include <linux/rculist.h>
  27. #include <linux/kernel.h>
  28. #include <linux/async_tx.h>
  29. #ifdef CONFIG_DMA_ENGINE
  30. static int __init async_tx_init(void)
  31. {
  32. async_dmaengine_get();
  33. printk(KERN_INFO "async_tx: api initialized (async)\n");
  34. return 0;
  35. }
  36. static void __exit async_tx_exit(void)
  37. {
  38. async_dmaengine_put();
  39. }
  40. module_init(async_tx_init);
  41. module_exit(async_tx_exit);
  42. /**
  43. * __async_tx_find_channel - find a channel to carry out the operation or let
  44. * the transaction execute synchronously
  45. * @submit: transaction dependency and submission modifiers
  46. * @tx_type: transaction type
  47. */
  48. struct dma_chan *
  49. __async_tx_find_channel(struct async_submit_ctl *submit,
  50. enum dma_transaction_type tx_type)
  51. {
  52. struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
  53. /* see if we can keep the chain on one channel */
  54. if (depend_tx &&
  55. dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
  56. return depend_tx->chan;
  57. return async_dma_find_channel(tx_type);
  58. }
  59. EXPORT_SYMBOL_GPL(__async_tx_find_channel);
  60. #endif
  61. /**
  62. * async_tx_channel_switch - queue an interrupt descriptor with a dependency
  63. * pre-attached.
  64. * @depend_tx: the operation that must finish before the new operation runs
  65. * @tx: the new operation
  66. */
  67. static void
  68. async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx,
  69. struct dma_async_tx_descriptor *tx)
  70. {
  71. struct dma_chan *chan;
  72. struct dma_device *device;
  73. struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
  74. /* first check to see if we can still append to depend_tx */
  75. spin_lock_bh(&depend_tx->lock);
  76. if (depend_tx->parent && depend_tx->chan == tx->chan) {
  77. tx->parent = depend_tx;
  78. depend_tx->next = tx;
  79. intr_tx = NULL;
  80. }
  81. spin_unlock_bh(&depend_tx->lock);
  82. if (!intr_tx)
  83. return;
  84. chan = depend_tx->chan;
  85. device = chan->device;
  86. /* see if we can schedule an interrupt
  87. * otherwise poll for completion
  88. */
  89. if (dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  90. intr_tx = device->device_prep_dma_interrupt(chan, 0);
  91. else
  92. intr_tx = NULL;
  93. if (intr_tx) {
  94. intr_tx->callback = NULL;
  95. intr_tx->callback_param = NULL;
  96. tx->parent = intr_tx;
  97. /* safe to set ->next outside the lock since we know we are
  98. * not submitted yet
  99. */
  100. intr_tx->next = tx;
  101. /* check if we need to append */
  102. spin_lock_bh(&depend_tx->lock);
  103. if (depend_tx->parent) {
  104. intr_tx->parent = depend_tx;
  105. depend_tx->next = intr_tx;
  106. async_tx_ack(intr_tx);
  107. intr_tx = NULL;
  108. }
  109. spin_unlock_bh(&depend_tx->lock);
  110. if (intr_tx) {
  111. intr_tx->parent = NULL;
  112. intr_tx->tx_submit(intr_tx);
  113. async_tx_ack(intr_tx);
  114. }
  115. } else {
  116. if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR)
  117. panic("%s: DMA_ERROR waiting for depend_tx\n",
  118. __func__);
  119. tx->tx_submit(tx);
  120. }
  121. }
  122. /**
  123. * submit_disposition - flags for routing an incoming operation
  124. * @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock
  125. * @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch
  126. * @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly
  127. *
  128. * while holding depend_tx->lock we must avoid submitting new operations
  129. * to prevent a circular locking dependency with drivers that already
  130. * hold a channel lock when calling async_tx_run_dependencies.
  131. */
  132. enum submit_disposition {
  133. ASYNC_TX_SUBMITTED,
  134. ASYNC_TX_CHANNEL_SWITCH,
  135. ASYNC_TX_DIRECT_SUBMIT,
  136. };
  137. void
  138. async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
  139. struct async_submit_ctl *submit)
  140. {
  141. struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
  142. tx->callback = submit->cb_fn;
  143. tx->callback_param = submit->cb_param;
  144. if (depend_tx) {
  145. enum submit_disposition s;
  146. /* sanity check the dependency chain:
  147. * 1/ if ack is already set then we cannot be sure
  148. * we are referring to the correct operation
  149. * 2/ dependencies are 1:1 i.e. two transactions can
  150. * not depend on the same parent
  151. */
  152. BUG_ON(async_tx_test_ack(depend_tx) || depend_tx->next ||
  153. tx->parent);
  154. /* the lock prevents async_tx_run_dependencies from missing
  155. * the setting of ->next when ->parent != NULL
  156. */
  157. spin_lock_bh(&depend_tx->lock);
  158. if (depend_tx->parent) {
  159. /* we have a parent so we can not submit directly
  160. * if we are staying on the same channel: append
  161. * else: channel switch
  162. */
  163. if (depend_tx->chan == chan) {
  164. tx->parent = depend_tx;
  165. depend_tx->next = tx;
  166. s = ASYNC_TX_SUBMITTED;
  167. } else
  168. s = ASYNC_TX_CHANNEL_SWITCH;
  169. } else {
  170. /* we do not have a parent so we may be able to submit
  171. * directly if we are staying on the same channel
  172. */
  173. if (depend_tx->chan == chan)
  174. s = ASYNC_TX_DIRECT_SUBMIT;
  175. else
  176. s = ASYNC_TX_CHANNEL_SWITCH;
  177. }
  178. spin_unlock_bh(&depend_tx->lock);
  179. switch (s) {
  180. case ASYNC_TX_SUBMITTED:
  181. break;
  182. case ASYNC_TX_CHANNEL_SWITCH:
  183. async_tx_channel_switch(depend_tx, tx);
  184. break;
  185. case ASYNC_TX_DIRECT_SUBMIT:
  186. tx->parent = NULL;
  187. tx->tx_submit(tx);
  188. break;
  189. }
  190. } else {
  191. tx->parent = NULL;
  192. tx->tx_submit(tx);
  193. }
  194. if (submit->flags & ASYNC_TX_ACK)
  195. async_tx_ack(tx);
  196. if (depend_tx)
  197. async_tx_ack(depend_tx);
  198. }
  199. EXPORT_SYMBOL_GPL(async_tx_submit);
  200. /**
  201. * async_trigger_callback - schedules the callback function to be run
  202. * @submit: submission and completion parameters
  203. *
  204. * honored flags: ASYNC_TX_ACK
  205. *
  206. * The callback is run after any dependent operations have completed.
  207. */
  208. struct dma_async_tx_descriptor *
  209. async_trigger_callback(struct async_submit_ctl *submit)
  210. {
  211. struct dma_chan *chan;
  212. struct dma_device *device;
  213. struct dma_async_tx_descriptor *tx;
  214. struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
  215. if (depend_tx) {
  216. chan = depend_tx->chan;
  217. device = chan->device;
  218. /* see if we can schedule an interrupt
  219. * otherwise poll for completion
  220. */
  221. if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  222. device = NULL;
  223. tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL;
  224. } else
  225. tx = NULL;
  226. if (tx) {
  227. pr_debug("%s: (async)\n", __func__);
  228. async_tx_submit(chan, tx, submit);
  229. } else {
  230. pr_debug("%s: (sync)\n", __func__);
  231. /* wait for any prerequisite operations */
  232. async_tx_quiesce(&submit->depend_tx);
  233. async_tx_sync_epilog(submit);
  234. }
  235. return tx;
  236. }
  237. EXPORT_SYMBOL_GPL(async_trigger_callback);
  238. /**
  239. * async_tx_quiesce - ensure tx is complete and freeable upon return
  240. * @tx - transaction to quiesce
  241. */
  242. void async_tx_quiesce(struct dma_async_tx_descriptor **tx)
  243. {
  244. if (*tx) {
  245. /* if ack is already set then we cannot be sure
  246. * we are referring to the correct operation
  247. */
  248. BUG_ON(async_tx_test_ack(*tx));
  249. if (dma_wait_for_async_tx(*tx) == DMA_ERROR)
  250. panic("DMA_ERROR waiting for transaction\n");
  251. async_tx_ack(*tx);
  252. *tx = NULL;
  253. }
  254. }
  255. EXPORT_SYMBOL_GPL(async_tx_quiesce);
  256. MODULE_AUTHOR("Intel Corporation");
  257. MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API");
  258. MODULE_LICENSE("GPL");