cnic.c 127 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x/bnx2x_reg.h"
  40. #include "bnx2x/bnx2x_fw_defs.h"
  41. #include "bnx2x/bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. static LIST_HEAD(cnic_dev_list);
  55. static LIST_HEAD(cnic_udev_list);
  56. static DEFINE_RWLOCK(cnic_dev_lock);
  57. static DEFINE_MUTEX(cnic_lock);
  58. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  59. static int cnic_service_bnx2(void *, void *);
  60. static int cnic_service_bnx2x(void *, void *);
  61. static int cnic_ctl(void *, struct cnic_ctl_info *);
  62. static struct cnic_ops cnic_bnx2_ops = {
  63. .cnic_owner = THIS_MODULE,
  64. .cnic_handler = cnic_service_bnx2,
  65. .cnic_ctl = cnic_ctl,
  66. };
  67. static struct cnic_ops cnic_bnx2x_ops = {
  68. .cnic_owner = THIS_MODULE,
  69. .cnic_handler = cnic_service_bnx2x,
  70. .cnic_ctl = cnic_ctl,
  71. };
  72. static struct workqueue_struct *cnic_wq;
  73. static void cnic_shutdown_rings(struct cnic_dev *);
  74. static void cnic_init_rings(struct cnic_dev *);
  75. static int cnic_cm_set_pg(struct cnic_sock *);
  76. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  77. {
  78. struct cnic_uio_dev *udev = uinfo->priv;
  79. struct cnic_dev *dev;
  80. if (!capable(CAP_NET_ADMIN))
  81. return -EPERM;
  82. if (udev->uio_dev != -1)
  83. return -EBUSY;
  84. rtnl_lock();
  85. dev = udev->dev;
  86. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  87. rtnl_unlock();
  88. return -ENODEV;
  89. }
  90. udev->uio_dev = iminor(inode);
  91. cnic_shutdown_rings(dev);
  92. cnic_init_rings(dev);
  93. rtnl_unlock();
  94. return 0;
  95. }
  96. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  97. {
  98. struct cnic_uio_dev *udev = uinfo->priv;
  99. udev->uio_dev = -1;
  100. return 0;
  101. }
  102. static inline void cnic_hold(struct cnic_dev *dev)
  103. {
  104. atomic_inc(&dev->ref_count);
  105. }
  106. static inline void cnic_put(struct cnic_dev *dev)
  107. {
  108. atomic_dec(&dev->ref_count);
  109. }
  110. static inline void csk_hold(struct cnic_sock *csk)
  111. {
  112. atomic_inc(&csk->ref_count);
  113. }
  114. static inline void csk_put(struct cnic_sock *csk)
  115. {
  116. atomic_dec(&csk->ref_count);
  117. }
  118. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  119. {
  120. struct cnic_dev *cdev;
  121. read_lock(&cnic_dev_lock);
  122. list_for_each_entry(cdev, &cnic_dev_list, list) {
  123. if (netdev == cdev->netdev) {
  124. cnic_hold(cdev);
  125. read_unlock(&cnic_dev_lock);
  126. return cdev;
  127. }
  128. }
  129. read_unlock(&cnic_dev_lock);
  130. return NULL;
  131. }
  132. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  133. {
  134. atomic_inc(&ulp_ops->ref_count);
  135. }
  136. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  137. {
  138. atomic_dec(&ulp_ops->ref_count);
  139. }
  140. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  141. {
  142. struct cnic_local *cp = dev->cnic_priv;
  143. struct cnic_eth_dev *ethdev = cp->ethdev;
  144. struct drv_ctl_info info;
  145. struct drv_ctl_io *io = &info.data.io;
  146. info.cmd = DRV_CTL_CTX_WR_CMD;
  147. io->cid_addr = cid_addr;
  148. io->offset = off;
  149. io->data = val;
  150. ethdev->drv_ctl(dev->netdev, &info);
  151. }
  152. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  153. {
  154. struct cnic_local *cp = dev->cnic_priv;
  155. struct cnic_eth_dev *ethdev = cp->ethdev;
  156. struct drv_ctl_info info;
  157. struct drv_ctl_io *io = &info.data.io;
  158. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  159. io->offset = off;
  160. io->dma_addr = addr;
  161. ethdev->drv_ctl(dev->netdev, &info);
  162. }
  163. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  164. {
  165. struct cnic_local *cp = dev->cnic_priv;
  166. struct cnic_eth_dev *ethdev = cp->ethdev;
  167. struct drv_ctl_info info;
  168. struct drv_ctl_l2_ring *ring = &info.data.ring;
  169. if (start)
  170. info.cmd = DRV_CTL_START_L2_CMD;
  171. else
  172. info.cmd = DRV_CTL_STOP_L2_CMD;
  173. ring->cid = cid;
  174. ring->client_id = cl_id;
  175. ethdev->drv_ctl(dev->netdev, &info);
  176. }
  177. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  178. {
  179. struct cnic_local *cp = dev->cnic_priv;
  180. struct cnic_eth_dev *ethdev = cp->ethdev;
  181. struct drv_ctl_info info;
  182. struct drv_ctl_io *io = &info.data.io;
  183. info.cmd = DRV_CTL_IO_WR_CMD;
  184. io->offset = off;
  185. io->data = val;
  186. ethdev->drv_ctl(dev->netdev, &info);
  187. }
  188. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  189. {
  190. struct cnic_local *cp = dev->cnic_priv;
  191. struct cnic_eth_dev *ethdev = cp->ethdev;
  192. struct drv_ctl_info info;
  193. struct drv_ctl_io *io = &info.data.io;
  194. info.cmd = DRV_CTL_IO_RD_CMD;
  195. io->offset = off;
  196. ethdev->drv_ctl(dev->netdev, &info);
  197. return io->data;
  198. }
  199. static int cnic_in_use(struct cnic_sock *csk)
  200. {
  201. return test_bit(SK_F_INUSE, &csk->flags);
  202. }
  203. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  204. {
  205. struct cnic_local *cp = dev->cnic_priv;
  206. struct cnic_eth_dev *ethdev = cp->ethdev;
  207. struct drv_ctl_info info;
  208. info.cmd = cmd;
  209. info.data.credit.credit_count = count;
  210. ethdev->drv_ctl(dev->netdev, &info);
  211. }
  212. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  213. {
  214. u32 i;
  215. for (i = 0; i < cp->max_cid_space; i++) {
  216. if (cp->ctx_tbl[i].cid == cid) {
  217. *l5_cid = i;
  218. return 0;
  219. }
  220. }
  221. return -EINVAL;
  222. }
  223. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  224. struct cnic_sock *csk)
  225. {
  226. struct iscsi_path path_req;
  227. char *buf = NULL;
  228. u16 len = 0;
  229. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  230. struct cnic_ulp_ops *ulp_ops;
  231. struct cnic_uio_dev *udev = cp->udev;
  232. if (!udev || udev->uio_dev == -1)
  233. return -ENODEV;
  234. if (csk) {
  235. len = sizeof(path_req);
  236. buf = (char *) &path_req;
  237. memset(&path_req, 0, len);
  238. msg_type = ISCSI_KEVENT_PATH_REQ;
  239. path_req.handle = (u64) csk->l5_cid;
  240. if (test_bit(SK_F_IPV6, &csk->flags)) {
  241. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  242. sizeof(struct in6_addr));
  243. path_req.ip_addr_len = 16;
  244. } else {
  245. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  246. sizeof(struct in_addr));
  247. path_req.ip_addr_len = 4;
  248. }
  249. path_req.vlan_id = csk->vlan_id;
  250. path_req.pmtu = csk->mtu;
  251. }
  252. rcu_read_lock();
  253. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  254. if (ulp_ops)
  255. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  256. rcu_read_unlock();
  257. return 0;
  258. }
  259. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  260. char *buf, u16 len)
  261. {
  262. int rc = -EINVAL;
  263. switch (msg_type) {
  264. case ISCSI_UEVENT_PATH_UPDATE: {
  265. struct cnic_local *cp;
  266. u32 l5_cid;
  267. struct cnic_sock *csk;
  268. struct iscsi_path *path_resp;
  269. if (len < sizeof(*path_resp))
  270. break;
  271. path_resp = (struct iscsi_path *) buf;
  272. cp = dev->cnic_priv;
  273. l5_cid = (u32) path_resp->handle;
  274. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  275. break;
  276. rcu_read_lock();
  277. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  278. rc = -ENODEV;
  279. rcu_read_unlock();
  280. break;
  281. }
  282. csk = &cp->csk_tbl[l5_cid];
  283. csk_hold(csk);
  284. if (cnic_in_use(csk)) {
  285. memcpy(csk->ha, path_resp->mac_addr, 6);
  286. if (test_bit(SK_F_IPV6, &csk->flags))
  287. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  288. sizeof(struct in6_addr));
  289. else
  290. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  291. sizeof(struct in_addr));
  292. if (is_valid_ether_addr(csk->ha))
  293. cnic_cm_set_pg(csk);
  294. }
  295. csk_put(csk);
  296. rcu_read_unlock();
  297. rc = 0;
  298. }
  299. }
  300. return rc;
  301. }
  302. static int cnic_offld_prep(struct cnic_sock *csk)
  303. {
  304. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  305. return 0;
  306. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  307. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  308. return 0;
  309. }
  310. return 1;
  311. }
  312. static int cnic_close_prep(struct cnic_sock *csk)
  313. {
  314. clear_bit(SK_F_CONNECT_START, &csk->flags);
  315. smp_mb__after_clear_bit();
  316. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  317. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  318. msleep(1);
  319. return 1;
  320. }
  321. return 0;
  322. }
  323. static int cnic_abort_prep(struct cnic_sock *csk)
  324. {
  325. clear_bit(SK_F_CONNECT_START, &csk->flags);
  326. smp_mb__after_clear_bit();
  327. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  328. msleep(1);
  329. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  330. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  331. return 1;
  332. }
  333. return 0;
  334. }
  335. static void cnic_uio_stop(void)
  336. {
  337. struct cnic_dev *dev;
  338. read_lock(&cnic_dev_lock);
  339. list_for_each_entry(dev, &cnic_dev_list, list) {
  340. struct cnic_local *cp = dev->cnic_priv;
  341. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  342. }
  343. read_unlock(&cnic_dev_lock);
  344. }
  345. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  346. {
  347. struct cnic_dev *dev;
  348. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  349. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  350. return -EINVAL;
  351. }
  352. mutex_lock(&cnic_lock);
  353. if (cnic_ulp_tbl[ulp_type]) {
  354. pr_err("%s: Type %d has already been registered\n",
  355. __func__, ulp_type);
  356. mutex_unlock(&cnic_lock);
  357. return -EBUSY;
  358. }
  359. read_lock(&cnic_dev_lock);
  360. list_for_each_entry(dev, &cnic_dev_list, list) {
  361. struct cnic_local *cp = dev->cnic_priv;
  362. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  363. }
  364. read_unlock(&cnic_dev_lock);
  365. atomic_set(&ulp_ops->ref_count, 0);
  366. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  367. mutex_unlock(&cnic_lock);
  368. /* Prevent race conditions with netdev_event */
  369. rtnl_lock();
  370. read_lock(&cnic_dev_lock);
  371. list_for_each_entry(dev, &cnic_dev_list, list) {
  372. struct cnic_local *cp = dev->cnic_priv;
  373. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  374. ulp_ops->cnic_init(dev);
  375. }
  376. read_unlock(&cnic_dev_lock);
  377. rtnl_unlock();
  378. return 0;
  379. }
  380. int cnic_unregister_driver(int ulp_type)
  381. {
  382. struct cnic_dev *dev;
  383. struct cnic_ulp_ops *ulp_ops;
  384. int i = 0;
  385. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  386. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  387. return -EINVAL;
  388. }
  389. mutex_lock(&cnic_lock);
  390. ulp_ops = cnic_ulp_tbl[ulp_type];
  391. if (!ulp_ops) {
  392. pr_err("%s: Type %d has not been registered\n",
  393. __func__, ulp_type);
  394. goto out_unlock;
  395. }
  396. read_lock(&cnic_dev_lock);
  397. list_for_each_entry(dev, &cnic_dev_list, list) {
  398. struct cnic_local *cp = dev->cnic_priv;
  399. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  400. pr_err("%s: Type %d still has devices registered\n",
  401. __func__, ulp_type);
  402. read_unlock(&cnic_dev_lock);
  403. goto out_unlock;
  404. }
  405. }
  406. read_unlock(&cnic_dev_lock);
  407. if (ulp_type == CNIC_ULP_ISCSI)
  408. cnic_uio_stop();
  409. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  410. mutex_unlock(&cnic_lock);
  411. synchronize_rcu();
  412. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  413. msleep(100);
  414. i++;
  415. }
  416. if (atomic_read(&ulp_ops->ref_count) != 0)
  417. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  418. return 0;
  419. out_unlock:
  420. mutex_unlock(&cnic_lock);
  421. return -EINVAL;
  422. }
  423. static int cnic_start_hw(struct cnic_dev *);
  424. static void cnic_stop_hw(struct cnic_dev *);
  425. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  426. void *ulp_ctx)
  427. {
  428. struct cnic_local *cp = dev->cnic_priv;
  429. struct cnic_ulp_ops *ulp_ops;
  430. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  431. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  432. return -EINVAL;
  433. }
  434. mutex_lock(&cnic_lock);
  435. if (cnic_ulp_tbl[ulp_type] == NULL) {
  436. pr_err("%s: Driver with type %d has not been registered\n",
  437. __func__, ulp_type);
  438. mutex_unlock(&cnic_lock);
  439. return -EAGAIN;
  440. }
  441. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  442. pr_err("%s: Type %d has already been registered to this device\n",
  443. __func__, ulp_type);
  444. mutex_unlock(&cnic_lock);
  445. return -EBUSY;
  446. }
  447. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  448. cp->ulp_handle[ulp_type] = ulp_ctx;
  449. ulp_ops = cnic_ulp_tbl[ulp_type];
  450. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  451. cnic_hold(dev);
  452. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  453. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  454. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  455. mutex_unlock(&cnic_lock);
  456. return 0;
  457. }
  458. EXPORT_SYMBOL(cnic_register_driver);
  459. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  460. {
  461. struct cnic_local *cp = dev->cnic_priv;
  462. int i = 0;
  463. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  464. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  465. return -EINVAL;
  466. }
  467. mutex_lock(&cnic_lock);
  468. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  469. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  470. cnic_put(dev);
  471. } else {
  472. pr_err("%s: device not registered to this ulp type %d\n",
  473. __func__, ulp_type);
  474. mutex_unlock(&cnic_lock);
  475. return -EINVAL;
  476. }
  477. mutex_unlock(&cnic_lock);
  478. synchronize_rcu();
  479. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  480. i < 20) {
  481. msleep(100);
  482. i++;
  483. }
  484. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  485. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  486. return 0;
  487. }
  488. EXPORT_SYMBOL(cnic_unregister_driver);
  489. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  490. {
  491. id_tbl->start = start_id;
  492. id_tbl->max = size;
  493. id_tbl->next = 0;
  494. spin_lock_init(&id_tbl->lock);
  495. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  496. if (!id_tbl->table)
  497. return -ENOMEM;
  498. return 0;
  499. }
  500. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  501. {
  502. kfree(id_tbl->table);
  503. id_tbl->table = NULL;
  504. }
  505. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  506. {
  507. int ret = -1;
  508. id -= id_tbl->start;
  509. if (id >= id_tbl->max)
  510. return ret;
  511. spin_lock(&id_tbl->lock);
  512. if (!test_bit(id, id_tbl->table)) {
  513. set_bit(id, id_tbl->table);
  514. ret = 0;
  515. }
  516. spin_unlock(&id_tbl->lock);
  517. return ret;
  518. }
  519. /* Returns -1 if not successful */
  520. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  521. {
  522. u32 id;
  523. spin_lock(&id_tbl->lock);
  524. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  525. if (id >= id_tbl->max) {
  526. id = -1;
  527. if (id_tbl->next != 0) {
  528. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  529. if (id >= id_tbl->next)
  530. id = -1;
  531. }
  532. }
  533. if (id < id_tbl->max) {
  534. set_bit(id, id_tbl->table);
  535. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  536. id += id_tbl->start;
  537. }
  538. spin_unlock(&id_tbl->lock);
  539. return id;
  540. }
  541. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  542. {
  543. if (id == -1)
  544. return;
  545. id -= id_tbl->start;
  546. if (id >= id_tbl->max)
  547. return;
  548. clear_bit(id, id_tbl->table);
  549. }
  550. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  551. {
  552. int i;
  553. if (!dma->pg_arr)
  554. return;
  555. for (i = 0; i < dma->num_pages; i++) {
  556. if (dma->pg_arr[i]) {
  557. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  558. dma->pg_arr[i], dma->pg_map_arr[i]);
  559. dma->pg_arr[i] = NULL;
  560. }
  561. }
  562. if (dma->pgtbl) {
  563. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  564. dma->pgtbl, dma->pgtbl_map);
  565. dma->pgtbl = NULL;
  566. }
  567. kfree(dma->pg_arr);
  568. dma->pg_arr = NULL;
  569. dma->num_pages = 0;
  570. }
  571. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  572. {
  573. int i;
  574. u32 *page_table = dma->pgtbl;
  575. for (i = 0; i < dma->num_pages; i++) {
  576. /* Each entry needs to be in big endian format. */
  577. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  578. page_table++;
  579. *page_table = (u32) dma->pg_map_arr[i];
  580. page_table++;
  581. }
  582. }
  583. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  584. {
  585. int i;
  586. u32 *page_table = dma->pgtbl;
  587. for (i = 0; i < dma->num_pages; i++) {
  588. /* Each entry needs to be in little endian format. */
  589. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  590. page_table++;
  591. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  592. page_table++;
  593. }
  594. }
  595. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  596. int pages, int use_pg_tbl)
  597. {
  598. int i, size;
  599. struct cnic_local *cp = dev->cnic_priv;
  600. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  601. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  602. if (dma->pg_arr == NULL)
  603. return -ENOMEM;
  604. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  605. dma->num_pages = pages;
  606. for (i = 0; i < pages; i++) {
  607. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  608. BCM_PAGE_SIZE,
  609. &dma->pg_map_arr[i],
  610. GFP_ATOMIC);
  611. if (dma->pg_arr[i] == NULL)
  612. goto error;
  613. }
  614. if (!use_pg_tbl)
  615. return 0;
  616. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  617. ~(BCM_PAGE_SIZE - 1);
  618. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  619. &dma->pgtbl_map, GFP_ATOMIC);
  620. if (dma->pgtbl == NULL)
  621. goto error;
  622. cp->setup_pgtbl(dev, dma);
  623. return 0;
  624. error:
  625. cnic_free_dma(dev, dma);
  626. return -ENOMEM;
  627. }
  628. static void cnic_free_context(struct cnic_dev *dev)
  629. {
  630. struct cnic_local *cp = dev->cnic_priv;
  631. int i;
  632. for (i = 0; i < cp->ctx_blks; i++) {
  633. if (cp->ctx_arr[i].ctx) {
  634. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  635. cp->ctx_arr[i].ctx,
  636. cp->ctx_arr[i].mapping);
  637. cp->ctx_arr[i].ctx = NULL;
  638. }
  639. }
  640. }
  641. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  642. {
  643. uio_unregister_device(&udev->cnic_uinfo);
  644. if (udev->l2_buf) {
  645. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  646. udev->l2_buf, udev->l2_buf_map);
  647. udev->l2_buf = NULL;
  648. }
  649. if (udev->l2_ring) {
  650. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  651. udev->l2_ring, udev->l2_ring_map);
  652. udev->l2_ring = NULL;
  653. }
  654. pci_dev_put(udev->pdev);
  655. kfree(udev);
  656. }
  657. static void cnic_free_uio(struct cnic_uio_dev *udev)
  658. {
  659. if (!udev)
  660. return;
  661. write_lock(&cnic_dev_lock);
  662. list_del_init(&udev->list);
  663. write_unlock(&cnic_dev_lock);
  664. __cnic_free_uio(udev);
  665. }
  666. static void cnic_free_resc(struct cnic_dev *dev)
  667. {
  668. struct cnic_local *cp = dev->cnic_priv;
  669. struct cnic_uio_dev *udev = cp->udev;
  670. if (udev) {
  671. udev->dev = NULL;
  672. cp->udev = NULL;
  673. }
  674. cnic_free_context(dev);
  675. kfree(cp->ctx_arr);
  676. cp->ctx_arr = NULL;
  677. cp->ctx_blks = 0;
  678. cnic_free_dma(dev, &cp->gbl_buf_info);
  679. cnic_free_dma(dev, &cp->conn_buf_info);
  680. cnic_free_dma(dev, &cp->kwq_info);
  681. cnic_free_dma(dev, &cp->kwq_16_data_info);
  682. cnic_free_dma(dev, &cp->kcq1.dma);
  683. kfree(cp->iscsi_tbl);
  684. cp->iscsi_tbl = NULL;
  685. kfree(cp->ctx_tbl);
  686. cp->ctx_tbl = NULL;
  687. cnic_free_id_tbl(&cp->cid_tbl);
  688. }
  689. static int cnic_alloc_context(struct cnic_dev *dev)
  690. {
  691. struct cnic_local *cp = dev->cnic_priv;
  692. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  693. int i, k, arr_size;
  694. cp->ctx_blk_size = BCM_PAGE_SIZE;
  695. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  696. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  697. sizeof(struct cnic_ctx);
  698. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  699. if (cp->ctx_arr == NULL)
  700. return -ENOMEM;
  701. k = 0;
  702. for (i = 0; i < 2; i++) {
  703. u32 j, reg, off, lo, hi;
  704. if (i == 0)
  705. off = BNX2_PG_CTX_MAP;
  706. else
  707. off = BNX2_ISCSI_CTX_MAP;
  708. reg = cnic_reg_rd_ind(dev, off);
  709. lo = reg >> 16;
  710. hi = reg & 0xffff;
  711. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  712. cp->ctx_arr[k].cid = j;
  713. }
  714. cp->ctx_blks = k;
  715. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  716. cp->ctx_blks = 0;
  717. return -ENOMEM;
  718. }
  719. for (i = 0; i < cp->ctx_blks; i++) {
  720. cp->ctx_arr[i].ctx =
  721. dma_alloc_coherent(&dev->pcidev->dev,
  722. BCM_PAGE_SIZE,
  723. &cp->ctx_arr[i].mapping,
  724. GFP_KERNEL);
  725. if (cp->ctx_arr[i].ctx == NULL)
  726. return -ENOMEM;
  727. }
  728. }
  729. return 0;
  730. }
  731. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  732. {
  733. int err, i, is_bnx2 = 0;
  734. struct kcqe **kcq;
  735. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  736. is_bnx2 = 1;
  737. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  738. if (err)
  739. return err;
  740. kcq = (struct kcqe **) info->dma.pg_arr;
  741. info->kcq = kcq;
  742. if (is_bnx2)
  743. return 0;
  744. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  745. struct bnx2x_bd_chain_next *next =
  746. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  747. int j = i + 1;
  748. if (j >= KCQ_PAGE_CNT)
  749. j = 0;
  750. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  751. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  752. }
  753. return 0;
  754. }
  755. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  756. {
  757. struct cnic_local *cp = dev->cnic_priv;
  758. struct cnic_uio_dev *udev;
  759. read_lock(&cnic_dev_lock);
  760. list_for_each_entry(udev, &cnic_udev_list, list) {
  761. if (udev->pdev == dev->pcidev) {
  762. udev->dev = dev;
  763. cp->udev = udev;
  764. read_unlock(&cnic_dev_lock);
  765. return 0;
  766. }
  767. }
  768. read_unlock(&cnic_dev_lock);
  769. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  770. if (!udev)
  771. return -ENOMEM;
  772. udev->uio_dev = -1;
  773. udev->dev = dev;
  774. udev->pdev = dev->pcidev;
  775. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  776. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  777. &udev->l2_ring_map,
  778. GFP_KERNEL | __GFP_COMP);
  779. if (!udev->l2_ring)
  780. goto err_udev;
  781. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  782. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  783. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  784. &udev->l2_buf_map,
  785. GFP_KERNEL | __GFP_COMP);
  786. if (!udev->l2_buf)
  787. goto err_dma;
  788. write_lock(&cnic_dev_lock);
  789. list_add(&udev->list, &cnic_udev_list);
  790. write_unlock(&cnic_dev_lock);
  791. pci_dev_get(udev->pdev);
  792. cp->udev = udev;
  793. return 0;
  794. err_dma:
  795. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  796. udev->l2_ring, udev->l2_ring_map);
  797. err_udev:
  798. kfree(udev);
  799. return -ENOMEM;
  800. }
  801. static int cnic_init_uio(struct cnic_dev *dev)
  802. {
  803. struct cnic_local *cp = dev->cnic_priv;
  804. struct cnic_uio_dev *udev = cp->udev;
  805. struct uio_info *uinfo;
  806. int ret = 0;
  807. if (!udev)
  808. return -ENOMEM;
  809. uinfo = &udev->cnic_uinfo;
  810. uinfo->mem[0].addr = dev->netdev->base_addr;
  811. uinfo->mem[0].internal_addr = dev->regview;
  812. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  813. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  814. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  815. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  816. PAGE_MASK;
  817. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  818. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  819. else
  820. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  821. uinfo->name = "bnx2_cnic";
  822. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  823. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  824. PAGE_MASK;
  825. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  826. uinfo->name = "bnx2x_cnic";
  827. }
  828. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  829. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  830. uinfo->mem[2].size = udev->l2_ring_size;
  831. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  832. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  833. uinfo->mem[3].size = udev->l2_buf_size;
  834. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  835. uinfo->version = CNIC_MODULE_VERSION;
  836. uinfo->irq = UIO_IRQ_CUSTOM;
  837. uinfo->open = cnic_uio_open;
  838. uinfo->release = cnic_uio_close;
  839. if (udev->uio_dev == -1) {
  840. if (!uinfo->priv) {
  841. uinfo->priv = udev;
  842. ret = uio_register_device(&udev->pdev->dev, uinfo);
  843. }
  844. } else {
  845. cnic_init_rings(dev);
  846. }
  847. return ret;
  848. }
  849. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  850. {
  851. struct cnic_local *cp = dev->cnic_priv;
  852. int ret;
  853. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  854. if (ret)
  855. goto error;
  856. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  857. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  858. if (ret)
  859. goto error;
  860. ret = cnic_alloc_context(dev);
  861. if (ret)
  862. goto error;
  863. ret = cnic_alloc_uio_rings(dev, 2);
  864. if (ret)
  865. goto error;
  866. ret = cnic_init_uio(dev);
  867. if (ret)
  868. goto error;
  869. return 0;
  870. error:
  871. cnic_free_resc(dev);
  872. return ret;
  873. }
  874. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  875. {
  876. struct cnic_local *cp = dev->cnic_priv;
  877. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  878. int total_mem, blks, i;
  879. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  880. blks = total_mem / ctx_blk_size;
  881. if (total_mem % ctx_blk_size)
  882. blks++;
  883. if (blks > cp->ethdev->ctx_tbl_len)
  884. return -ENOMEM;
  885. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  886. if (cp->ctx_arr == NULL)
  887. return -ENOMEM;
  888. cp->ctx_blks = blks;
  889. cp->ctx_blk_size = ctx_blk_size;
  890. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  891. cp->ctx_align = 0;
  892. else
  893. cp->ctx_align = ctx_blk_size;
  894. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  895. for (i = 0; i < blks; i++) {
  896. cp->ctx_arr[i].ctx =
  897. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  898. &cp->ctx_arr[i].mapping,
  899. GFP_KERNEL);
  900. if (cp->ctx_arr[i].ctx == NULL)
  901. return -ENOMEM;
  902. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  903. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  904. cnic_free_context(dev);
  905. cp->ctx_blk_size += cp->ctx_align;
  906. i = -1;
  907. continue;
  908. }
  909. }
  910. }
  911. return 0;
  912. }
  913. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  914. {
  915. struct cnic_local *cp = dev->cnic_priv;
  916. struct cnic_eth_dev *ethdev = cp->ethdev;
  917. u32 start_cid = ethdev->starting_cid;
  918. int i, j, n, ret, pages;
  919. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  920. cp->iro_arr = ethdev->iro_arr;
  921. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  922. cp->iscsi_start_cid = start_cid;
  923. if (start_cid < BNX2X_ISCSI_START_CID) {
  924. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  925. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  926. cp->max_cid_space += delta;
  927. }
  928. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  929. GFP_KERNEL);
  930. if (!cp->iscsi_tbl)
  931. goto error;
  932. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  933. cp->max_cid_space, GFP_KERNEL);
  934. if (!cp->ctx_tbl)
  935. goto error;
  936. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  937. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  938. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  939. }
  940. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  941. PAGE_SIZE;
  942. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  943. if (ret)
  944. return -ENOMEM;
  945. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  946. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  947. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  948. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  949. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  950. off;
  951. if ((i % n) == (n - 1))
  952. j++;
  953. }
  954. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  955. if (ret)
  956. goto error;
  957. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  958. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  959. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  960. if (ret)
  961. goto error;
  962. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  963. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  964. if (ret)
  965. goto error;
  966. ret = cnic_alloc_bnx2x_context(dev);
  967. if (ret)
  968. goto error;
  969. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  970. cp->l2_rx_ring_size = 15;
  971. ret = cnic_alloc_uio_rings(dev, 4);
  972. if (ret)
  973. goto error;
  974. ret = cnic_init_uio(dev);
  975. if (ret)
  976. goto error;
  977. return 0;
  978. error:
  979. cnic_free_resc(dev);
  980. return -ENOMEM;
  981. }
  982. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  983. {
  984. return cp->max_kwq_idx -
  985. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  986. }
  987. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  988. u32 num_wqes)
  989. {
  990. struct cnic_local *cp = dev->cnic_priv;
  991. struct kwqe *prod_qe;
  992. u16 prod, sw_prod, i;
  993. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  994. return -EAGAIN; /* bnx2 is down */
  995. spin_lock_bh(&cp->cnic_ulp_lock);
  996. if (num_wqes > cnic_kwq_avail(cp) &&
  997. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  998. spin_unlock_bh(&cp->cnic_ulp_lock);
  999. return -EAGAIN;
  1000. }
  1001. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1002. prod = cp->kwq_prod_idx;
  1003. sw_prod = prod & MAX_KWQ_IDX;
  1004. for (i = 0; i < num_wqes; i++) {
  1005. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1006. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1007. prod++;
  1008. sw_prod = prod & MAX_KWQ_IDX;
  1009. }
  1010. cp->kwq_prod_idx = prod;
  1011. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1012. spin_unlock_bh(&cp->cnic_ulp_lock);
  1013. return 0;
  1014. }
  1015. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1016. union l5cm_specific_data *l5_data)
  1017. {
  1018. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1019. dma_addr_t map;
  1020. map = ctx->kwqe_data_mapping;
  1021. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1022. l5_data->phy_address.hi = (u64) map >> 32;
  1023. return ctx->kwqe_data;
  1024. }
  1025. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1026. u32 type, union l5cm_specific_data *l5_data)
  1027. {
  1028. struct cnic_local *cp = dev->cnic_priv;
  1029. struct l5cm_spe kwqe;
  1030. struct kwqe_16 *kwq[1];
  1031. int ret;
  1032. kwqe.hdr.conn_and_cmd_data =
  1033. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1034. BNX2X_HW_CID(cp, cid)));
  1035. kwqe.hdr.type = cpu_to_le16(type);
  1036. kwqe.hdr.reserved1 = 0;
  1037. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1038. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1039. kwq[0] = (struct kwqe_16 *) &kwqe;
  1040. spin_lock_bh(&cp->cnic_ulp_lock);
  1041. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1042. spin_unlock_bh(&cp->cnic_ulp_lock);
  1043. if (ret == 1)
  1044. return 0;
  1045. return -EBUSY;
  1046. }
  1047. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1048. struct kcqe *cqes[], u32 num_cqes)
  1049. {
  1050. struct cnic_local *cp = dev->cnic_priv;
  1051. struct cnic_ulp_ops *ulp_ops;
  1052. rcu_read_lock();
  1053. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1054. if (likely(ulp_ops)) {
  1055. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1056. cqes, num_cqes);
  1057. }
  1058. rcu_read_unlock();
  1059. }
  1060. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1061. {
  1062. struct cnic_local *cp = dev->cnic_priv;
  1063. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1064. int hq_bds, pages;
  1065. u32 pfid = cp->pfid;
  1066. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1067. cp->num_ccells = req1->num_ccells_per_conn;
  1068. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1069. cp->num_iscsi_tasks;
  1070. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1071. BNX2X_ISCSI_R2TQE_SIZE;
  1072. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1073. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1074. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1075. cp->num_cqs = req1->num_cqs;
  1076. if (!dev->max_iscsi_conn)
  1077. return 0;
  1078. /* init Tstorm RAM */
  1079. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1080. req1->rq_num_wqes);
  1081. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1082. PAGE_SIZE);
  1083. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1084. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1085. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1086. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1087. req1->num_tasks_per_conn);
  1088. /* init Ustorm RAM */
  1089. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1090. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1091. req1->rq_buffer_size);
  1092. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1093. PAGE_SIZE);
  1094. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1095. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1096. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1097. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1098. req1->num_tasks_per_conn);
  1099. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1100. req1->rq_num_wqes);
  1101. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1102. req1->cq_num_wqes);
  1103. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1104. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1105. /* init Xstorm RAM */
  1106. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1107. PAGE_SIZE);
  1108. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1109. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1110. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1111. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1112. req1->num_tasks_per_conn);
  1113. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1114. hq_bds);
  1115. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1116. req1->num_tasks_per_conn);
  1117. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1118. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1119. /* init Cstorm RAM */
  1120. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1121. PAGE_SIZE);
  1122. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1123. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1124. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1125. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1126. req1->num_tasks_per_conn);
  1127. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1128. req1->cq_num_wqes);
  1129. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1130. hq_bds);
  1131. return 0;
  1132. }
  1133. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1134. {
  1135. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1136. struct cnic_local *cp = dev->cnic_priv;
  1137. u32 pfid = cp->pfid;
  1138. struct iscsi_kcqe kcqe;
  1139. struct kcqe *cqes[1];
  1140. memset(&kcqe, 0, sizeof(kcqe));
  1141. if (!dev->max_iscsi_conn) {
  1142. kcqe.completion_status =
  1143. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1144. goto done;
  1145. }
  1146. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1147. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1148. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1149. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1150. req2->error_bit_map[1]);
  1151. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1152. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1153. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1154. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1155. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1156. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1157. req2->error_bit_map[1]);
  1158. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1159. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1160. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1161. done:
  1162. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1163. cqes[0] = (struct kcqe *) &kcqe;
  1164. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1165. return 0;
  1166. }
  1167. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1168. {
  1169. struct cnic_local *cp = dev->cnic_priv;
  1170. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1171. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1172. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1173. cnic_free_dma(dev, &iscsi->hq_info);
  1174. cnic_free_dma(dev, &iscsi->r2tq_info);
  1175. cnic_free_dma(dev, &iscsi->task_array_info);
  1176. }
  1177. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1178. ctx->cid = 0;
  1179. }
  1180. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1181. {
  1182. u32 cid;
  1183. int ret, pages;
  1184. struct cnic_local *cp = dev->cnic_priv;
  1185. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1186. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1187. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1188. if (cid == -1) {
  1189. ret = -ENOMEM;
  1190. goto error;
  1191. }
  1192. ctx->cid = cid;
  1193. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1194. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1195. if (ret)
  1196. goto error;
  1197. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1198. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1199. if (ret)
  1200. goto error;
  1201. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1202. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1203. if (ret)
  1204. goto error;
  1205. return 0;
  1206. error:
  1207. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1208. return ret;
  1209. }
  1210. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1211. struct regpair *ctx_addr)
  1212. {
  1213. struct cnic_local *cp = dev->cnic_priv;
  1214. struct cnic_eth_dev *ethdev = cp->ethdev;
  1215. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1216. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1217. unsigned long align_off = 0;
  1218. dma_addr_t ctx_map;
  1219. void *ctx;
  1220. if (cp->ctx_align) {
  1221. unsigned long mask = cp->ctx_align - 1;
  1222. if (cp->ctx_arr[blk].mapping & mask)
  1223. align_off = cp->ctx_align -
  1224. (cp->ctx_arr[blk].mapping & mask);
  1225. }
  1226. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1227. (off * BNX2X_CONTEXT_MEM_SIZE);
  1228. ctx = cp->ctx_arr[blk].ctx + align_off +
  1229. (off * BNX2X_CONTEXT_MEM_SIZE);
  1230. if (init)
  1231. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1232. ctx_addr->lo = ctx_map & 0xffffffff;
  1233. ctx_addr->hi = (u64) ctx_map >> 32;
  1234. return ctx;
  1235. }
  1236. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1237. u32 num)
  1238. {
  1239. struct cnic_local *cp = dev->cnic_priv;
  1240. struct iscsi_kwqe_conn_offload1 *req1 =
  1241. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1242. struct iscsi_kwqe_conn_offload2 *req2 =
  1243. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1244. struct iscsi_kwqe_conn_offload3 *req3;
  1245. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1246. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1247. u32 cid = ctx->cid;
  1248. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1249. struct iscsi_context *ictx;
  1250. struct regpair context_addr;
  1251. int i, j, n = 2, n_max;
  1252. ctx->ctx_flags = 0;
  1253. if (!req2->num_additional_wqes)
  1254. return -EINVAL;
  1255. n_max = req2->num_additional_wqes + 2;
  1256. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1257. if (ictx == NULL)
  1258. return -ENOMEM;
  1259. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1260. ictx->xstorm_ag_context.hq_prod = 1;
  1261. ictx->xstorm_st_context.iscsi.first_burst_length =
  1262. ISCSI_DEF_FIRST_BURST_LEN;
  1263. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1264. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1265. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1266. req1->sq_page_table_addr_lo;
  1267. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1268. req1->sq_page_table_addr_hi;
  1269. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1270. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1271. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1272. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1273. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1274. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1275. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1276. iscsi->hq_info.pgtbl[0];
  1277. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1278. iscsi->hq_info.pgtbl[1];
  1279. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1280. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1281. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1282. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1283. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1284. iscsi->r2tq_info.pgtbl[0];
  1285. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1286. iscsi->r2tq_info.pgtbl[1];
  1287. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1288. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1289. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1290. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1291. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1292. BNX2X_ISCSI_PBL_NOT_CACHED;
  1293. ictx->xstorm_st_context.iscsi.flags.flags |=
  1294. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1295. ictx->xstorm_st_context.iscsi.flags.flags |=
  1296. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1297. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1298. /* TSTORM requires the base address of RQ DB & not PTE */
  1299. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1300. req2->rq_page_table_addr_lo & PAGE_MASK;
  1301. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1302. req2->rq_page_table_addr_hi;
  1303. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1304. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1305. ictx->tstorm_st_context.tcp.flags2 |=
  1306. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1307. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1308. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1309. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1310. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1311. req2->rq_page_table_addr_lo;
  1312. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1313. req2->rq_page_table_addr_hi;
  1314. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1315. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1316. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1317. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1318. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1319. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1320. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1321. iscsi->r2tq_info.pgtbl[0];
  1322. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1323. iscsi->r2tq_info.pgtbl[1];
  1324. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1325. req1->cq_page_table_addr_lo;
  1326. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1327. req1->cq_page_table_addr_hi;
  1328. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1329. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1330. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1331. ictx->ustorm_st_context.task_pbe_cache_index =
  1332. BNX2X_ISCSI_PBL_NOT_CACHED;
  1333. ictx->ustorm_st_context.task_pdu_cache_index =
  1334. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1335. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1336. if (j == 3) {
  1337. if (n >= n_max)
  1338. break;
  1339. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1340. j = 0;
  1341. }
  1342. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1343. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1344. req3->qp_first_pte[j].hi;
  1345. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1346. req3->qp_first_pte[j].lo;
  1347. }
  1348. ictx->ustorm_st_context.task_pbl_base.lo =
  1349. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1350. ictx->ustorm_st_context.task_pbl_base.hi =
  1351. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1352. ictx->ustorm_st_context.tce_phy_addr.lo =
  1353. iscsi->task_array_info.pgtbl[0];
  1354. ictx->ustorm_st_context.tce_phy_addr.hi =
  1355. iscsi->task_array_info.pgtbl[1];
  1356. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1357. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1358. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1359. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1360. ISCSI_DEF_MAX_BURST_LEN;
  1361. ictx->ustorm_st_context.negotiated_rx |=
  1362. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1363. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1364. ictx->cstorm_st_context.hq_pbl_base.lo =
  1365. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1366. ictx->cstorm_st_context.hq_pbl_base.hi =
  1367. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1368. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1369. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1370. ictx->cstorm_st_context.task_pbl_base.lo =
  1371. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1372. ictx->cstorm_st_context.task_pbl_base.hi =
  1373. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1374. /* CSTORM and USTORM initialization is different, CSTORM requires
  1375. * CQ DB base & not PTE addr */
  1376. ictx->cstorm_st_context.cq_db_base.lo =
  1377. req1->cq_page_table_addr_lo & PAGE_MASK;
  1378. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1379. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1380. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1381. for (i = 0; i < cp->num_cqs; i++) {
  1382. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1383. ISCSI_INITIAL_SN;
  1384. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1385. ISCSI_INITIAL_SN;
  1386. }
  1387. ictx->xstorm_ag_context.cdu_reserved =
  1388. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1389. ISCSI_CONNECTION_TYPE);
  1390. ictx->ustorm_ag_context.cdu_usage =
  1391. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1392. ISCSI_CONNECTION_TYPE);
  1393. return 0;
  1394. }
  1395. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1396. u32 num, int *work)
  1397. {
  1398. struct iscsi_kwqe_conn_offload1 *req1;
  1399. struct iscsi_kwqe_conn_offload2 *req2;
  1400. struct cnic_local *cp = dev->cnic_priv;
  1401. struct cnic_context *ctx;
  1402. struct iscsi_kcqe kcqe;
  1403. struct kcqe *cqes[1];
  1404. u32 l5_cid;
  1405. int ret = 0;
  1406. if (num < 2) {
  1407. *work = num;
  1408. return -EINVAL;
  1409. }
  1410. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1411. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1412. if ((num - 2) < req2->num_additional_wqes) {
  1413. *work = num;
  1414. return -EINVAL;
  1415. }
  1416. *work = 2 + req2->num_additional_wqes;;
  1417. l5_cid = req1->iscsi_conn_id;
  1418. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1419. return -EINVAL;
  1420. memset(&kcqe, 0, sizeof(kcqe));
  1421. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1422. kcqe.iscsi_conn_id = l5_cid;
  1423. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1424. ctx = &cp->ctx_tbl[l5_cid];
  1425. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1426. kcqe.completion_status =
  1427. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1428. goto done;
  1429. }
  1430. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1431. atomic_dec(&cp->iscsi_conn);
  1432. goto done;
  1433. }
  1434. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1435. if (ret) {
  1436. atomic_dec(&cp->iscsi_conn);
  1437. ret = 0;
  1438. goto done;
  1439. }
  1440. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1441. if (ret < 0) {
  1442. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1443. atomic_dec(&cp->iscsi_conn);
  1444. goto done;
  1445. }
  1446. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1447. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1448. done:
  1449. cqes[0] = (struct kcqe *) &kcqe;
  1450. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1451. return ret;
  1452. }
  1453. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1454. {
  1455. struct cnic_local *cp = dev->cnic_priv;
  1456. struct iscsi_kwqe_conn_update *req =
  1457. (struct iscsi_kwqe_conn_update *) kwqe;
  1458. void *data;
  1459. union l5cm_specific_data l5_data;
  1460. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1461. int ret;
  1462. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1463. return -EINVAL;
  1464. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1465. if (!data)
  1466. return -ENOMEM;
  1467. memcpy(data, kwqe, sizeof(struct kwqe));
  1468. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1469. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1470. return ret;
  1471. }
  1472. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1473. {
  1474. struct cnic_local *cp = dev->cnic_priv;
  1475. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1476. union l5cm_specific_data l5_data;
  1477. int ret;
  1478. u32 hw_cid, type;
  1479. init_waitqueue_head(&ctx->waitq);
  1480. ctx->wait_cond = 0;
  1481. memset(&l5_data, 0, sizeof(l5_data));
  1482. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1483. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  1484. & SPE_HDR_CONN_TYPE;
  1485. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1486. SPE_HDR_FUNCTION_ID);
  1487. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1488. hw_cid, type, &l5_data);
  1489. if (ret == 0)
  1490. wait_event(ctx->waitq, ctx->wait_cond);
  1491. return ret;
  1492. }
  1493. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1494. {
  1495. struct cnic_local *cp = dev->cnic_priv;
  1496. struct iscsi_kwqe_conn_destroy *req =
  1497. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1498. u32 l5_cid = req->reserved0;
  1499. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1500. int ret = 0;
  1501. struct iscsi_kcqe kcqe;
  1502. struct kcqe *cqes[1];
  1503. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1504. goto skip_cfc_delete;
  1505. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1506. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1507. if (delta > (2 * HZ))
  1508. delta = 0;
  1509. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1510. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1511. goto destroy_reply;
  1512. }
  1513. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1514. skip_cfc_delete:
  1515. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1516. atomic_dec(&cp->iscsi_conn);
  1517. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1518. destroy_reply:
  1519. memset(&kcqe, 0, sizeof(kcqe));
  1520. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1521. kcqe.iscsi_conn_id = l5_cid;
  1522. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1523. kcqe.iscsi_conn_context_id = req->context_id;
  1524. cqes[0] = (struct kcqe *) &kcqe;
  1525. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1526. return ret;
  1527. }
  1528. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1529. struct l4_kwq_connect_req1 *kwqe1,
  1530. struct l4_kwq_connect_req3 *kwqe3,
  1531. struct l5cm_active_conn_buffer *conn_buf)
  1532. {
  1533. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1534. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1535. &conn_buf->xstorm_conn_buffer;
  1536. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1537. &conn_buf->tstorm_conn_buffer;
  1538. struct regpair context_addr;
  1539. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1540. struct in6_addr src_ip, dst_ip;
  1541. int i;
  1542. u32 *addrp;
  1543. addrp = (u32 *) &conn_addr->local_ip_addr;
  1544. for (i = 0; i < 4; i++, addrp++)
  1545. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1546. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1547. for (i = 0; i < 4; i++, addrp++)
  1548. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1549. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1550. xstorm_buf->context_addr.hi = context_addr.hi;
  1551. xstorm_buf->context_addr.lo = context_addr.lo;
  1552. xstorm_buf->mss = 0xffff;
  1553. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1554. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1555. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1556. xstorm_buf->pseudo_header_checksum =
  1557. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1558. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1559. tstorm_buf->params |=
  1560. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1561. if (kwqe3->ka_timeout) {
  1562. tstorm_buf->ka_enable = 1;
  1563. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1564. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1565. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1566. }
  1567. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1568. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1569. tstorm_buf->max_rt_time = 0xffffffff;
  1570. }
  1571. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1572. {
  1573. struct cnic_local *cp = dev->cnic_priv;
  1574. u32 pfid = cp->pfid;
  1575. u8 *mac = dev->mac_addr;
  1576. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1577. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1578. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1579. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1580. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1581. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1582. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1583. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1584. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1585. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1586. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1587. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1588. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1589. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1590. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1591. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1592. mac[4]);
  1593. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1594. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1595. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1596. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1597. mac[2]);
  1598. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1599. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1600. mac[1]);
  1601. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1602. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1603. mac[0]);
  1604. }
  1605. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1606. {
  1607. struct cnic_local *cp = dev->cnic_priv;
  1608. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1609. u16 tstorm_flags = 0;
  1610. if (tcp_ts) {
  1611. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1612. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1613. }
  1614. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1615. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1616. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1617. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1618. }
  1619. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1620. u32 num, int *work)
  1621. {
  1622. struct cnic_local *cp = dev->cnic_priv;
  1623. struct l4_kwq_connect_req1 *kwqe1 =
  1624. (struct l4_kwq_connect_req1 *) wqes[0];
  1625. struct l4_kwq_connect_req3 *kwqe3;
  1626. struct l5cm_active_conn_buffer *conn_buf;
  1627. struct l5cm_conn_addr_params *conn_addr;
  1628. union l5cm_specific_data l5_data;
  1629. u32 l5_cid = kwqe1->pg_cid;
  1630. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1631. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1632. int ret;
  1633. if (num < 2) {
  1634. *work = num;
  1635. return -EINVAL;
  1636. }
  1637. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1638. *work = 3;
  1639. else
  1640. *work = 2;
  1641. if (num < *work) {
  1642. *work = num;
  1643. return -EINVAL;
  1644. }
  1645. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1646. netdev_err(dev->netdev, "conn_buf size too big\n");
  1647. return -ENOMEM;
  1648. }
  1649. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1650. if (!conn_buf)
  1651. return -ENOMEM;
  1652. memset(conn_buf, 0, sizeof(*conn_buf));
  1653. conn_addr = &conn_buf->conn_addr_buf;
  1654. conn_addr->remote_addr_0 = csk->ha[0];
  1655. conn_addr->remote_addr_1 = csk->ha[1];
  1656. conn_addr->remote_addr_2 = csk->ha[2];
  1657. conn_addr->remote_addr_3 = csk->ha[3];
  1658. conn_addr->remote_addr_4 = csk->ha[4];
  1659. conn_addr->remote_addr_5 = csk->ha[5];
  1660. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1661. struct l4_kwq_connect_req2 *kwqe2 =
  1662. (struct l4_kwq_connect_req2 *) wqes[1];
  1663. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1664. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1665. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1666. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1667. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1668. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1669. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1670. }
  1671. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1672. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1673. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1674. conn_addr->local_tcp_port = kwqe1->src_port;
  1675. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1676. conn_addr->pmtu = kwqe3->pmtu;
  1677. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1678. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1679. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1680. cnic_bnx2x_set_tcp_timestamp(dev,
  1681. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1682. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1683. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1684. if (!ret)
  1685. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1686. return ret;
  1687. }
  1688. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1689. {
  1690. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1691. union l5cm_specific_data l5_data;
  1692. int ret;
  1693. memset(&l5_data, 0, sizeof(l5_data));
  1694. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1695. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1696. return ret;
  1697. }
  1698. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1699. {
  1700. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1701. union l5cm_specific_data l5_data;
  1702. int ret;
  1703. memset(&l5_data, 0, sizeof(l5_data));
  1704. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1705. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1706. return ret;
  1707. }
  1708. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1709. {
  1710. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1711. struct l4_kcq kcqe;
  1712. struct kcqe *cqes[1];
  1713. memset(&kcqe, 0, sizeof(kcqe));
  1714. kcqe.pg_host_opaque = req->host_opaque;
  1715. kcqe.pg_cid = req->host_opaque;
  1716. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1717. cqes[0] = (struct kcqe *) &kcqe;
  1718. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1719. return 0;
  1720. }
  1721. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1722. {
  1723. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1724. struct l4_kcq kcqe;
  1725. struct kcqe *cqes[1];
  1726. memset(&kcqe, 0, sizeof(kcqe));
  1727. kcqe.pg_host_opaque = req->pg_host_opaque;
  1728. kcqe.pg_cid = req->pg_cid;
  1729. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1730. cqes[0] = (struct kcqe *) &kcqe;
  1731. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1732. return 0;
  1733. }
  1734. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1735. u32 num_wqes)
  1736. {
  1737. int i, work, ret;
  1738. u32 opcode;
  1739. struct kwqe *kwqe;
  1740. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1741. return -EAGAIN; /* bnx2 is down */
  1742. for (i = 0; i < num_wqes; ) {
  1743. kwqe = wqes[i];
  1744. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1745. work = 1;
  1746. switch (opcode) {
  1747. case ISCSI_KWQE_OPCODE_INIT1:
  1748. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1749. break;
  1750. case ISCSI_KWQE_OPCODE_INIT2:
  1751. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1752. break;
  1753. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1754. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1755. num_wqes - i, &work);
  1756. break;
  1757. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1758. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1759. break;
  1760. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1761. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1762. break;
  1763. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1764. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1765. &work);
  1766. break;
  1767. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1768. ret = cnic_bnx2x_close(dev, kwqe);
  1769. break;
  1770. case L4_KWQE_OPCODE_VALUE_RESET:
  1771. ret = cnic_bnx2x_reset(dev, kwqe);
  1772. break;
  1773. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1774. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1775. break;
  1776. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1777. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1778. break;
  1779. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1780. ret = 0;
  1781. break;
  1782. default:
  1783. ret = 0;
  1784. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  1785. opcode);
  1786. break;
  1787. }
  1788. if (ret < 0)
  1789. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  1790. opcode);
  1791. i += work;
  1792. }
  1793. return 0;
  1794. }
  1795. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1796. {
  1797. struct cnic_local *cp = dev->cnic_priv;
  1798. int i, j, comp = 0;
  1799. i = 0;
  1800. j = 1;
  1801. while (num_cqes) {
  1802. struct cnic_ulp_ops *ulp_ops;
  1803. int ulp_type;
  1804. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1805. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1806. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1807. comp++;
  1808. while (j < num_cqes) {
  1809. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1810. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1811. break;
  1812. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1813. comp++;
  1814. j++;
  1815. }
  1816. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1817. ulp_type = CNIC_ULP_RDMA;
  1818. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1819. ulp_type = CNIC_ULP_ISCSI;
  1820. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1821. ulp_type = CNIC_ULP_L4;
  1822. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1823. goto end;
  1824. else {
  1825. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  1826. kcqe_op_flag);
  1827. goto end;
  1828. }
  1829. rcu_read_lock();
  1830. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1831. if (likely(ulp_ops)) {
  1832. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1833. cp->completed_kcq + i, j);
  1834. }
  1835. rcu_read_unlock();
  1836. end:
  1837. num_cqes -= j;
  1838. i += j;
  1839. j = 1;
  1840. }
  1841. if (unlikely(comp))
  1842. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  1843. }
  1844. static u16 cnic_bnx2_next_idx(u16 idx)
  1845. {
  1846. return idx + 1;
  1847. }
  1848. static u16 cnic_bnx2_hw_idx(u16 idx)
  1849. {
  1850. return idx;
  1851. }
  1852. static u16 cnic_bnx2x_next_idx(u16 idx)
  1853. {
  1854. idx++;
  1855. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1856. idx++;
  1857. return idx;
  1858. }
  1859. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1860. {
  1861. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1862. idx++;
  1863. return idx;
  1864. }
  1865. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  1866. {
  1867. struct cnic_local *cp = dev->cnic_priv;
  1868. u16 i, ri, hw_prod, last;
  1869. struct kcqe *kcqe;
  1870. int kcqe_cnt = 0, last_cnt = 0;
  1871. i = ri = last = info->sw_prod_idx;
  1872. ri &= MAX_KCQ_IDX;
  1873. hw_prod = *info->hw_prod_idx_ptr;
  1874. hw_prod = cp->hw_idx(hw_prod);
  1875. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1876. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1877. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1878. i = cp->next_idx(i);
  1879. ri = i & MAX_KCQ_IDX;
  1880. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1881. last_cnt = kcqe_cnt;
  1882. last = i;
  1883. }
  1884. }
  1885. info->sw_prod_idx = last;
  1886. return last_cnt;
  1887. }
  1888. static int cnic_l2_completion(struct cnic_local *cp)
  1889. {
  1890. u16 hw_cons, sw_cons;
  1891. struct cnic_uio_dev *udev = cp->udev;
  1892. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  1893. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  1894. u32 cmd;
  1895. int comp = 0;
  1896. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  1897. return 0;
  1898. hw_cons = *cp->rx_cons_ptr;
  1899. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  1900. hw_cons++;
  1901. sw_cons = cp->rx_cons;
  1902. while (sw_cons != hw_cons) {
  1903. u8 cqe_fp_flags;
  1904. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  1905. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  1906. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  1907. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  1908. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  1909. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  1910. cmd == RAMROD_CMD_ID_ETH_HALT)
  1911. comp++;
  1912. }
  1913. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  1914. }
  1915. return comp;
  1916. }
  1917. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1918. {
  1919. u16 rx_cons, tx_cons;
  1920. int comp = 0;
  1921. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  1922. return;
  1923. rx_cons = *cp->rx_cons_ptr;
  1924. tx_cons = *cp->tx_cons_ptr;
  1925. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1926. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  1927. comp = cnic_l2_completion(cp);
  1928. cp->tx_cons = tx_cons;
  1929. cp->rx_cons = rx_cons;
  1930. if (cp->udev)
  1931. uio_event_notify(&cp->udev->cnic_uinfo);
  1932. }
  1933. if (comp)
  1934. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  1935. }
  1936. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  1937. {
  1938. struct cnic_local *cp = dev->cnic_priv;
  1939. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1940. int kcqe_cnt;
  1941. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1942. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  1943. service_kcqes(dev, kcqe_cnt);
  1944. /* Tell compiler that status_blk fields can change. */
  1945. barrier();
  1946. if (status_idx != *cp->kcq1.status_idx_ptr) {
  1947. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1948. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1949. } else
  1950. break;
  1951. }
  1952. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  1953. cnic_chk_pkt_rings(cp);
  1954. return status_idx;
  1955. }
  1956. static int cnic_service_bnx2(void *data, void *status_blk)
  1957. {
  1958. struct cnic_dev *dev = data;
  1959. struct cnic_local *cp = dev->cnic_priv;
  1960. u32 status_idx = *cp->kcq1.status_idx_ptr;
  1961. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1962. return status_idx;
  1963. return cnic_service_bnx2_queues(dev);
  1964. }
  1965. static void cnic_service_bnx2_msix(unsigned long data)
  1966. {
  1967. struct cnic_dev *dev = (struct cnic_dev *) data;
  1968. struct cnic_local *cp = dev->cnic_priv;
  1969. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  1970. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1971. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1972. }
  1973. static void cnic_doirq(struct cnic_dev *dev)
  1974. {
  1975. struct cnic_local *cp = dev->cnic_priv;
  1976. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  1977. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  1978. prefetch(cp->status_blk.gen);
  1979. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1980. tasklet_schedule(&cp->cnic_irq_task);
  1981. }
  1982. }
  1983. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1984. {
  1985. struct cnic_dev *dev = dev_instance;
  1986. struct cnic_local *cp = dev->cnic_priv;
  1987. if (cp->ack_int)
  1988. cp->ack_int(dev);
  1989. cnic_doirq(dev);
  1990. return IRQ_HANDLED;
  1991. }
  1992. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1993. u16 index, u8 op, u8 update)
  1994. {
  1995. struct cnic_local *cp = dev->cnic_priv;
  1996. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1997. COMMAND_REG_INT_ACK);
  1998. struct igu_ack_register igu_ack;
  1999. igu_ack.status_block_index = index;
  2000. igu_ack.sb_id_and_flags =
  2001. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2002. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2003. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2004. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2005. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2006. }
  2007. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2008. u16 index, u8 op, u8 update)
  2009. {
  2010. struct igu_regular cmd_data;
  2011. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2012. cmd_data.sb_id_and_flags =
  2013. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2014. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2015. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2016. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2017. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2018. }
  2019. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2020. {
  2021. struct cnic_local *cp = dev->cnic_priv;
  2022. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2023. IGU_INT_DISABLE, 0);
  2024. }
  2025. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2026. {
  2027. struct cnic_local *cp = dev->cnic_priv;
  2028. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2029. IGU_INT_DISABLE, 0);
  2030. }
  2031. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2032. {
  2033. u32 last_status = *info->status_idx_ptr;
  2034. int kcqe_cnt;
  2035. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2036. service_kcqes(dev, kcqe_cnt);
  2037. /* Tell compiler that sblk fields can change. */
  2038. barrier();
  2039. if (last_status == *info->status_idx_ptr)
  2040. break;
  2041. last_status = *info->status_idx_ptr;
  2042. }
  2043. return last_status;
  2044. }
  2045. static void cnic_service_bnx2x_bh(unsigned long data)
  2046. {
  2047. struct cnic_dev *dev = (struct cnic_dev *) data;
  2048. struct cnic_local *cp = dev->cnic_priv;
  2049. u32 status_idx;
  2050. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2051. return;
  2052. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2053. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2054. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  2055. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2056. status_idx, IGU_INT_ENABLE, 1);
  2057. else
  2058. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2059. status_idx, IGU_INT_ENABLE, 1);
  2060. }
  2061. static int cnic_service_bnx2x(void *data, void *status_blk)
  2062. {
  2063. struct cnic_dev *dev = data;
  2064. struct cnic_local *cp = dev->cnic_priv;
  2065. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2066. cnic_doirq(dev);
  2067. cnic_chk_pkt_rings(cp);
  2068. return 0;
  2069. }
  2070. static void cnic_ulp_stop(struct cnic_dev *dev)
  2071. {
  2072. struct cnic_local *cp = dev->cnic_priv;
  2073. int if_type;
  2074. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2075. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2076. struct cnic_ulp_ops *ulp_ops;
  2077. mutex_lock(&cnic_lock);
  2078. ulp_ops = cp->ulp_ops[if_type];
  2079. if (!ulp_ops) {
  2080. mutex_unlock(&cnic_lock);
  2081. continue;
  2082. }
  2083. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2084. mutex_unlock(&cnic_lock);
  2085. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2086. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2087. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2088. }
  2089. }
  2090. static void cnic_ulp_start(struct cnic_dev *dev)
  2091. {
  2092. struct cnic_local *cp = dev->cnic_priv;
  2093. int if_type;
  2094. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2095. struct cnic_ulp_ops *ulp_ops;
  2096. mutex_lock(&cnic_lock);
  2097. ulp_ops = cp->ulp_ops[if_type];
  2098. if (!ulp_ops || !ulp_ops->cnic_start) {
  2099. mutex_unlock(&cnic_lock);
  2100. continue;
  2101. }
  2102. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2103. mutex_unlock(&cnic_lock);
  2104. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2105. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2106. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2107. }
  2108. }
  2109. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2110. {
  2111. struct cnic_dev *dev = data;
  2112. switch (info->cmd) {
  2113. case CNIC_CTL_STOP_CMD:
  2114. cnic_hold(dev);
  2115. cnic_ulp_stop(dev);
  2116. cnic_stop_hw(dev);
  2117. cnic_put(dev);
  2118. break;
  2119. case CNIC_CTL_START_CMD:
  2120. cnic_hold(dev);
  2121. if (!cnic_start_hw(dev))
  2122. cnic_ulp_start(dev);
  2123. cnic_put(dev);
  2124. break;
  2125. case CNIC_CTL_COMPLETION_CMD: {
  2126. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2127. u32 l5_cid;
  2128. struct cnic_local *cp = dev->cnic_priv;
  2129. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2130. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2131. ctx->wait_cond = 1;
  2132. wake_up(&ctx->waitq);
  2133. }
  2134. break;
  2135. }
  2136. default:
  2137. return -EINVAL;
  2138. }
  2139. return 0;
  2140. }
  2141. static void cnic_ulp_init(struct cnic_dev *dev)
  2142. {
  2143. int i;
  2144. struct cnic_local *cp = dev->cnic_priv;
  2145. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2146. struct cnic_ulp_ops *ulp_ops;
  2147. mutex_lock(&cnic_lock);
  2148. ulp_ops = cnic_ulp_tbl[i];
  2149. if (!ulp_ops || !ulp_ops->cnic_init) {
  2150. mutex_unlock(&cnic_lock);
  2151. continue;
  2152. }
  2153. ulp_get(ulp_ops);
  2154. mutex_unlock(&cnic_lock);
  2155. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2156. ulp_ops->cnic_init(dev);
  2157. ulp_put(ulp_ops);
  2158. }
  2159. }
  2160. static void cnic_ulp_exit(struct cnic_dev *dev)
  2161. {
  2162. int i;
  2163. struct cnic_local *cp = dev->cnic_priv;
  2164. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2165. struct cnic_ulp_ops *ulp_ops;
  2166. mutex_lock(&cnic_lock);
  2167. ulp_ops = cnic_ulp_tbl[i];
  2168. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2169. mutex_unlock(&cnic_lock);
  2170. continue;
  2171. }
  2172. ulp_get(ulp_ops);
  2173. mutex_unlock(&cnic_lock);
  2174. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2175. ulp_ops->cnic_exit(dev);
  2176. ulp_put(ulp_ops);
  2177. }
  2178. }
  2179. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2180. {
  2181. struct cnic_dev *dev = csk->dev;
  2182. struct l4_kwq_offload_pg *l4kwqe;
  2183. struct kwqe *wqes[1];
  2184. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2185. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2186. wqes[0] = (struct kwqe *) l4kwqe;
  2187. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2188. l4kwqe->flags =
  2189. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2190. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2191. l4kwqe->da0 = csk->ha[0];
  2192. l4kwqe->da1 = csk->ha[1];
  2193. l4kwqe->da2 = csk->ha[2];
  2194. l4kwqe->da3 = csk->ha[3];
  2195. l4kwqe->da4 = csk->ha[4];
  2196. l4kwqe->da5 = csk->ha[5];
  2197. l4kwqe->sa0 = dev->mac_addr[0];
  2198. l4kwqe->sa1 = dev->mac_addr[1];
  2199. l4kwqe->sa2 = dev->mac_addr[2];
  2200. l4kwqe->sa3 = dev->mac_addr[3];
  2201. l4kwqe->sa4 = dev->mac_addr[4];
  2202. l4kwqe->sa5 = dev->mac_addr[5];
  2203. l4kwqe->etype = ETH_P_IP;
  2204. l4kwqe->ipid_start = DEF_IPID_START;
  2205. l4kwqe->host_opaque = csk->l5_cid;
  2206. if (csk->vlan_id) {
  2207. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2208. l4kwqe->vlan_tag = csk->vlan_id;
  2209. l4kwqe->l2hdr_nbytes += 4;
  2210. }
  2211. return dev->submit_kwqes(dev, wqes, 1);
  2212. }
  2213. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2214. {
  2215. struct cnic_dev *dev = csk->dev;
  2216. struct l4_kwq_update_pg *l4kwqe;
  2217. struct kwqe *wqes[1];
  2218. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2219. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2220. wqes[0] = (struct kwqe *) l4kwqe;
  2221. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2222. l4kwqe->flags =
  2223. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2224. l4kwqe->pg_cid = csk->pg_cid;
  2225. l4kwqe->da0 = csk->ha[0];
  2226. l4kwqe->da1 = csk->ha[1];
  2227. l4kwqe->da2 = csk->ha[2];
  2228. l4kwqe->da3 = csk->ha[3];
  2229. l4kwqe->da4 = csk->ha[4];
  2230. l4kwqe->da5 = csk->ha[5];
  2231. l4kwqe->pg_host_opaque = csk->l5_cid;
  2232. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2233. return dev->submit_kwqes(dev, wqes, 1);
  2234. }
  2235. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2236. {
  2237. struct cnic_dev *dev = csk->dev;
  2238. struct l4_kwq_upload *l4kwqe;
  2239. struct kwqe *wqes[1];
  2240. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2241. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2242. wqes[0] = (struct kwqe *) l4kwqe;
  2243. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2244. l4kwqe->flags =
  2245. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2246. l4kwqe->cid = csk->pg_cid;
  2247. return dev->submit_kwqes(dev, wqes, 1);
  2248. }
  2249. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2250. {
  2251. struct cnic_dev *dev = csk->dev;
  2252. struct l4_kwq_connect_req1 *l4kwqe1;
  2253. struct l4_kwq_connect_req2 *l4kwqe2;
  2254. struct l4_kwq_connect_req3 *l4kwqe3;
  2255. struct kwqe *wqes[3];
  2256. u8 tcp_flags = 0;
  2257. int num_wqes = 2;
  2258. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2259. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2260. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2261. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2262. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2263. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2264. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2265. l4kwqe3->flags =
  2266. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2267. l4kwqe3->ka_timeout = csk->ka_timeout;
  2268. l4kwqe3->ka_interval = csk->ka_interval;
  2269. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2270. l4kwqe3->tos = csk->tos;
  2271. l4kwqe3->ttl = csk->ttl;
  2272. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2273. l4kwqe3->pmtu = csk->mtu;
  2274. l4kwqe3->rcv_buf = csk->rcv_buf;
  2275. l4kwqe3->snd_buf = csk->snd_buf;
  2276. l4kwqe3->seed = csk->seed;
  2277. wqes[0] = (struct kwqe *) l4kwqe1;
  2278. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2279. wqes[1] = (struct kwqe *) l4kwqe2;
  2280. wqes[2] = (struct kwqe *) l4kwqe3;
  2281. num_wqes = 3;
  2282. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2283. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2284. l4kwqe2->flags =
  2285. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2286. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2287. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2288. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2289. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2290. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2291. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2292. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2293. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2294. sizeof(struct tcphdr);
  2295. } else {
  2296. wqes[1] = (struct kwqe *) l4kwqe3;
  2297. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2298. sizeof(struct tcphdr);
  2299. }
  2300. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2301. l4kwqe1->flags =
  2302. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2303. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2304. l4kwqe1->cid = csk->cid;
  2305. l4kwqe1->pg_cid = csk->pg_cid;
  2306. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2307. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2308. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2309. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2310. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2311. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2312. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2313. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2314. if (csk->tcp_flags & SK_TCP_NAGLE)
  2315. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2316. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2317. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2318. if (csk->tcp_flags & SK_TCP_SACK)
  2319. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2320. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2321. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2322. l4kwqe1->tcp_flags = tcp_flags;
  2323. return dev->submit_kwqes(dev, wqes, num_wqes);
  2324. }
  2325. static int cnic_cm_close_req(struct cnic_sock *csk)
  2326. {
  2327. struct cnic_dev *dev = csk->dev;
  2328. struct l4_kwq_close_req *l4kwqe;
  2329. struct kwqe *wqes[1];
  2330. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2331. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2332. wqes[0] = (struct kwqe *) l4kwqe;
  2333. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2334. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2335. l4kwqe->cid = csk->cid;
  2336. return dev->submit_kwqes(dev, wqes, 1);
  2337. }
  2338. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2339. {
  2340. struct cnic_dev *dev = csk->dev;
  2341. struct l4_kwq_reset_req *l4kwqe;
  2342. struct kwqe *wqes[1];
  2343. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2344. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2345. wqes[0] = (struct kwqe *) l4kwqe;
  2346. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2347. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2348. l4kwqe->cid = csk->cid;
  2349. return dev->submit_kwqes(dev, wqes, 1);
  2350. }
  2351. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2352. u32 l5_cid, struct cnic_sock **csk, void *context)
  2353. {
  2354. struct cnic_local *cp = dev->cnic_priv;
  2355. struct cnic_sock *csk1;
  2356. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2357. return -EINVAL;
  2358. if (cp->ctx_tbl) {
  2359. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2360. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2361. return -EAGAIN;
  2362. }
  2363. csk1 = &cp->csk_tbl[l5_cid];
  2364. if (atomic_read(&csk1->ref_count))
  2365. return -EAGAIN;
  2366. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2367. return -EBUSY;
  2368. csk1->dev = dev;
  2369. csk1->cid = cid;
  2370. csk1->l5_cid = l5_cid;
  2371. csk1->ulp_type = ulp_type;
  2372. csk1->context = context;
  2373. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2374. csk1->ka_interval = DEF_KA_INTERVAL;
  2375. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2376. csk1->tos = DEF_TOS;
  2377. csk1->ttl = DEF_TTL;
  2378. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2379. csk1->rcv_buf = DEF_RCV_BUF;
  2380. csk1->snd_buf = DEF_SND_BUF;
  2381. csk1->seed = DEF_SEED;
  2382. *csk = csk1;
  2383. return 0;
  2384. }
  2385. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2386. {
  2387. if (csk->src_port) {
  2388. struct cnic_dev *dev = csk->dev;
  2389. struct cnic_local *cp = dev->cnic_priv;
  2390. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  2391. csk->src_port = 0;
  2392. }
  2393. }
  2394. static void cnic_close_conn(struct cnic_sock *csk)
  2395. {
  2396. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2397. cnic_cm_upload_pg(csk);
  2398. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2399. }
  2400. cnic_cm_cleanup(csk);
  2401. }
  2402. static int cnic_cm_destroy(struct cnic_sock *csk)
  2403. {
  2404. if (!cnic_in_use(csk))
  2405. return -EINVAL;
  2406. csk_hold(csk);
  2407. clear_bit(SK_F_INUSE, &csk->flags);
  2408. smp_mb__after_clear_bit();
  2409. while (atomic_read(&csk->ref_count) != 1)
  2410. msleep(1);
  2411. cnic_cm_cleanup(csk);
  2412. csk->flags = 0;
  2413. csk_put(csk);
  2414. return 0;
  2415. }
  2416. static inline u16 cnic_get_vlan(struct net_device *dev,
  2417. struct net_device **vlan_dev)
  2418. {
  2419. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2420. *vlan_dev = vlan_dev_real_dev(dev);
  2421. return vlan_dev_vlan_id(dev);
  2422. }
  2423. *vlan_dev = dev;
  2424. return 0;
  2425. }
  2426. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2427. struct dst_entry **dst)
  2428. {
  2429. #if defined(CONFIG_INET)
  2430. struct flowi fl;
  2431. int err;
  2432. struct rtable *rt;
  2433. memset(&fl, 0, sizeof(fl));
  2434. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2435. err = ip_route_output_key(&init_net, &rt, &fl);
  2436. if (!err)
  2437. *dst = &rt->dst;
  2438. return err;
  2439. #else
  2440. return -ENETUNREACH;
  2441. #endif
  2442. }
  2443. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2444. struct dst_entry **dst)
  2445. {
  2446. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2447. struct flowi fl;
  2448. memset(&fl, 0, sizeof(fl));
  2449. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2450. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2451. fl.oif = dst_addr->sin6_scope_id;
  2452. *dst = ip6_route_output(&init_net, NULL, &fl);
  2453. if (*dst)
  2454. return 0;
  2455. #endif
  2456. return -ENETUNREACH;
  2457. }
  2458. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2459. int ulp_type)
  2460. {
  2461. struct cnic_dev *dev = NULL;
  2462. struct dst_entry *dst;
  2463. struct net_device *netdev = NULL;
  2464. int err = -ENETUNREACH;
  2465. if (dst_addr->sin_family == AF_INET)
  2466. err = cnic_get_v4_route(dst_addr, &dst);
  2467. else if (dst_addr->sin_family == AF_INET6) {
  2468. struct sockaddr_in6 *dst_addr6 =
  2469. (struct sockaddr_in6 *) dst_addr;
  2470. err = cnic_get_v6_route(dst_addr6, &dst);
  2471. } else
  2472. return NULL;
  2473. if (err)
  2474. return NULL;
  2475. if (!dst->dev)
  2476. goto done;
  2477. cnic_get_vlan(dst->dev, &netdev);
  2478. dev = cnic_from_netdev(netdev);
  2479. done:
  2480. dst_release(dst);
  2481. if (dev)
  2482. cnic_put(dev);
  2483. return dev;
  2484. }
  2485. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2486. {
  2487. struct cnic_dev *dev = csk->dev;
  2488. struct cnic_local *cp = dev->cnic_priv;
  2489. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2490. }
  2491. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2492. {
  2493. struct cnic_dev *dev = csk->dev;
  2494. struct cnic_local *cp = dev->cnic_priv;
  2495. int is_v6, rc = 0;
  2496. struct dst_entry *dst = NULL;
  2497. struct net_device *realdev;
  2498. u32 local_port;
  2499. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2500. saddr->remote.v6.sin6_family == AF_INET6)
  2501. is_v6 = 1;
  2502. else if (saddr->local.v4.sin_family == AF_INET &&
  2503. saddr->remote.v4.sin_family == AF_INET)
  2504. is_v6 = 0;
  2505. else
  2506. return -EINVAL;
  2507. clear_bit(SK_F_IPV6, &csk->flags);
  2508. if (is_v6) {
  2509. set_bit(SK_F_IPV6, &csk->flags);
  2510. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2511. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2512. sizeof(struct in6_addr));
  2513. csk->dst_port = saddr->remote.v6.sin6_port;
  2514. local_port = saddr->local.v6.sin6_port;
  2515. } else {
  2516. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2517. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2518. csk->dst_port = saddr->remote.v4.sin_port;
  2519. local_port = saddr->local.v4.sin_port;
  2520. }
  2521. csk->vlan_id = 0;
  2522. csk->mtu = dev->netdev->mtu;
  2523. if (dst && dst->dev) {
  2524. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2525. if (realdev == dev->netdev) {
  2526. csk->vlan_id = vlan;
  2527. csk->mtu = dst_mtu(dst);
  2528. }
  2529. }
  2530. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  2531. local_port < CNIC_LOCAL_PORT_MAX) {
  2532. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  2533. local_port = 0;
  2534. } else
  2535. local_port = 0;
  2536. if (!local_port) {
  2537. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  2538. if (local_port == -1) {
  2539. rc = -ENOMEM;
  2540. goto err_out;
  2541. }
  2542. }
  2543. csk->src_port = local_port;
  2544. err_out:
  2545. dst_release(dst);
  2546. return rc;
  2547. }
  2548. static void cnic_init_csk_state(struct cnic_sock *csk)
  2549. {
  2550. csk->state = 0;
  2551. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2552. clear_bit(SK_F_CLOSING, &csk->flags);
  2553. }
  2554. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2555. {
  2556. int err = 0;
  2557. if (!cnic_in_use(csk))
  2558. return -EINVAL;
  2559. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2560. return -EINVAL;
  2561. cnic_init_csk_state(csk);
  2562. err = cnic_get_route(csk, saddr);
  2563. if (err)
  2564. goto err_out;
  2565. err = cnic_resolve_addr(csk, saddr);
  2566. if (!err)
  2567. return 0;
  2568. err_out:
  2569. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2570. return err;
  2571. }
  2572. static int cnic_cm_abort(struct cnic_sock *csk)
  2573. {
  2574. struct cnic_local *cp = csk->dev->cnic_priv;
  2575. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2576. if (!cnic_in_use(csk))
  2577. return -EINVAL;
  2578. if (cnic_abort_prep(csk))
  2579. return cnic_cm_abort_req(csk);
  2580. /* Getting here means that we haven't started connect, or
  2581. * connect was not successful.
  2582. */
  2583. cp->close_conn(csk, opcode);
  2584. if (csk->state != opcode)
  2585. return -EALREADY;
  2586. return 0;
  2587. }
  2588. static int cnic_cm_close(struct cnic_sock *csk)
  2589. {
  2590. if (!cnic_in_use(csk))
  2591. return -EINVAL;
  2592. if (cnic_close_prep(csk)) {
  2593. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2594. return cnic_cm_close_req(csk);
  2595. } else {
  2596. return -EALREADY;
  2597. }
  2598. return 0;
  2599. }
  2600. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2601. u8 opcode)
  2602. {
  2603. struct cnic_ulp_ops *ulp_ops;
  2604. int ulp_type = csk->ulp_type;
  2605. rcu_read_lock();
  2606. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2607. if (ulp_ops) {
  2608. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2609. ulp_ops->cm_connect_complete(csk);
  2610. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2611. ulp_ops->cm_close_complete(csk);
  2612. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2613. ulp_ops->cm_remote_abort(csk);
  2614. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2615. ulp_ops->cm_abort_complete(csk);
  2616. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2617. ulp_ops->cm_remote_close(csk);
  2618. }
  2619. rcu_read_unlock();
  2620. }
  2621. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2622. {
  2623. if (cnic_offld_prep(csk)) {
  2624. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2625. cnic_cm_update_pg(csk);
  2626. else
  2627. cnic_cm_offload_pg(csk);
  2628. }
  2629. return 0;
  2630. }
  2631. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2632. {
  2633. struct cnic_local *cp = dev->cnic_priv;
  2634. u32 l5_cid = kcqe->pg_host_opaque;
  2635. u8 opcode = kcqe->op_code;
  2636. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2637. csk_hold(csk);
  2638. if (!cnic_in_use(csk))
  2639. goto done;
  2640. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2641. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2642. goto done;
  2643. }
  2644. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  2645. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  2646. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2647. cnic_cm_upcall(cp, csk,
  2648. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2649. goto done;
  2650. }
  2651. csk->pg_cid = kcqe->pg_cid;
  2652. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2653. cnic_cm_conn_req(csk);
  2654. done:
  2655. csk_put(csk);
  2656. }
  2657. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2658. {
  2659. struct cnic_local *cp = dev->cnic_priv;
  2660. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2661. u8 opcode = l4kcqe->op_code;
  2662. u32 l5_cid;
  2663. struct cnic_sock *csk;
  2664. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2665. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2666. cnic_cm_process_offld_pg(dev, l4kcqe);
  2667. return;
  2668. }
  2669. l5_cid = l4kcqe->conn_id;
  2670. if (opcode & 0x80)
  2671. l5_cid = l4kcqe->cid;
  2672. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2673. return;
  2674. csk = &cp->csk_tbl[l5_cid];
  2675. csk_hold(csk);
  2676. if (!cnic_in_use(csk)) {
  2677. csk_put(csk);
  2678. return;
  2679. }
  2680. switch (opcode) {
  2681. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  2682. if (l4kcqe->status != 0) {
  2683. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2684. cnic_cm_upcall(cp, csk,
  2685. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2686. }
  2687. break;
  2688. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2689. if (l4kcqe->status == 0)
  2690. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2691. smp_mb__before_clear_bit();
  2692. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2693. cnic_cm_upcall(cp, csk, opcode);
  2694. break;
  2695. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2696. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2697. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2698. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2699. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2700. cp->close_conn(csk, opcode);
  2701. break;
  2702. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2703. cnic_cm_upcall(cp, csk, opcode);
  2704. break;
  2705. }
  2706. csk_put(csk);
  2707. }
  2708. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2709. {
  2710. struct cnic_dev *dev = data;
  2711. int i;
  2712. for (i = 0; i < num; i++)
  2713. cnic_cm_process_kcqe(dev, kcqe[i]);
  2714. }
  2715. static struct cnic_ulp_ops cm_ulp_ops = {
  2716. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2717. };
  2718. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2719. {
  2720. struct cnic_local *cp = dev->cnic_priv;
  2721. kfree(cp->csk_tbl);
  2722. cp->csk_tbl = NULL;
  2723. cnic_free_id_tbl(&cp->csk_port_tbl);
  2724. }
  2725. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2726. {
  2727. struct cnic_local *cp = dev->cnic_priv;
  2728. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2729. GFP_KERNEL);
  2730. if (!cp->csk_tbl)
  2731. return -ENOMEM;
  2732. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2733. CNIC_LOCAL_PORT_MIN)) {
  2734. cnic_cm_free_mem(dev);
  2735. return -ENOMEM;
  2736. }
  2737. return 0;
  2738. }
  2739. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2740. {
  2741. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  2742. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  2743. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  2744. csk->state = opcode;
  2745. }
  2746. /* 1. If event opcode matches the expected event in csk->state
  2747. * 2. If the expected event is CLOSE_COMP, we accept any event
  2748. * 3. If the expected event is 0, meaning the connection was never
  2749. * never established, we accept the opcode from cm_abort.
  2750. */
  2751. if (opcode == csk->state || csk->state == 0 ||
  2752. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  2753. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  2754. if (csk->state == 0)
  2755. csk->state = opcode;
  2756. return 1;
  2757. }
  2758. }
  2759. return 0;
  2760. }
  2761. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2762. {
  2763. struct cnic_dev *dev = csk->dev;
  2764. struct cnic_local *cp = dev->cnic_priv;
  2765. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  2766. cnic_cm_upcall(cp, csk, opcode);
  2767. return;
  2768. }
  2769. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2770. cnic_close_conn(csk);
  2771. csk->state = opcode;
  2772. cnic_cm_upcall(cp, csk, opcode);
  2773. }
  2774. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2775. {
  2776. }
  2777. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2778. {
  2779. u32 seed;
  2780. get_random_bytes(&seed, 4);
  2781. cnic_ctx_wr(dev, 45, 0, seed);
  2782. return 0;
  2783. }
  2784. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2785. {
  2786. struct cnic_dev *dev = csk->dev;
  2787. struct cnic_local *cp = dev->cnic_priv;
  2788. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2789. union l5cm_specific_data l5_data;
  2790. u32 cmd = 0;
  2791. int close_complete = 0;
  2792. switch (opcode) {
  2793. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2794. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2795. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2796. if (cnic_ready_to_close(csk, opcode)) {
  2797. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2798. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2799. else
  2800. close_complete = 1;
  2801. }
  2802. break;
  2803. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2804. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2805. break;
  2806. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2807. close_complete = 1;
  2808. break;
  2809. }
  2810. if (cmd) {
  2811. memset(&l5_data, 0, sizeof(l5_data));
  2812. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2813. &l5_data);
  2814. } else if (close_complete) {
  2815. ctx->timestamp = jiffies;
  2816. cnic_close_conn(csk);
  2817. cnic_cm_upcall(cp, csk, csk->state);
  2818. }
  2819. }
  2820. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2821. {
  2822. struct cnic_local *cp = dev->cnic_priv;
  2823. int i;
  2824. if (!cp->ctx_tbl)
  2825. return;
  2826. if (!netif_running(dev->netdev))
  2827. return;
  2828. for (i = 0; i < cp->max_cid_space; i++) {
  2829. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2830. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2831. msleep(10);
  2832. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2833. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2834. ctx->cid);
  2835. }
  2836. cancel_delayed_work(&cp->delete_task);
  2837. flush_workqueue(cnic_wq);
  2838. if (atomic_read(&cp->iscsi_conn) != 0)
  2839. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  2840. atomic_read(&cp->iscsi_conn));
  2841. }
  2842. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2843. {
  2844. struct cnic_local *cp = dev->cnic_priv;
  2845. u32 pfid = cp->pfid;
  2846. u32 port = CNIC_PORT(cp);
  2847. cnic_init_bnx2x_mac(dev);
  2848. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2849. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2850. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  2851. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2852. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  2853. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2854. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  2855. DEF_MAX_DA_COUNT);
  2856. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2857. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  2858. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2859. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  2860. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2861. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  2862. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2863. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  2864. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  2865. DEF_MAX_CWND);
  2866. return 0;
  2867. }
  2868. static void cnic_delete_task(struct work_struct *work)
  2869. {
  2870. struct cnic_local *cp;
  2871. struct cnic_dev *dev;
  2872. u32 i;
  2873. int need_resched = 0;
  2874. cp = container_of(work, struct cnic_local, delete_task.work);
  2875. dev = cp->dev;
  2876. for (i = 0; i < cp->max_cid_space; i++) {
  2877. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2878. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  2879. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2880. continue;
  2881. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  2882. need_resched = 1;
  2883. continue;
  2884. }
  2885. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2886. continue;
  2887. cnic_bnx2x_destroy_ramrod(dev, i);
  2888. cnic_free_bnx2x_conn_resc(dev, i);
  2889. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  2890. atomic_dec(&cp->iscsi_conn);
  2891. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  2892. }
  2893. if (need_resched)
  2894. queue_delayed_work(cnic_wq, &cp->delete_task,
  2895. msecs_to_jiffies(10));
  2896. }
  2897. static int cnic_cm_open(struct cnic_dev *dev)
  2898. {
  2899. struct cnic_local *cp = dev->cnic_priv;
  2900. int err;
  2901. err = cnic_cm_alloc_mem(dev);
  2902. if (err)
  2903. return err;
  2904. err = cp->start_cm(dev);
  2905. if (err)
  2906. goto err_out;
  2907. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  2908. dev->cm_create = cnic_cm_create;
  2909. dev->cm_destroy = cnic_cm_destroy;
  2910. dev->cm_connect = cnic_cm_connect;
  2911. dev->cm_abort = cnic_cm_abort;
  2912. dev->cm_close = cnic_cm_close;
  2913. dev->cm_select_dev = cnic_cm_select_dev;
  2914. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2915. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2916. return 0;
  2917. err_out:
  2918. cnic_cm_free_mem(dev);
  2919. return err;
  2920. }
  2921. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2922. {
  2923. struct cnic_local *cp = dev->cnic_priv;
  2924. int i;
  2925. cp->stop_cm(dev);
  2926. if (!cp->csk_tbl)
  2927. return 0;
  2928. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2929. struct cnic_sock *csk = &cp->csk_tbl[i];
  2930. clear_bit(SK_F_INUSE, &csk->flags);
  2931. cnic_cm_cleanup(csk);
  2932. }
  2933. cnic_cm_free_mem(dev);
  2934. return 0;
  2935. }
  2936. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2937. {
  2938. u32 cid_addr;
  2939. int i;
  2940. cid_addr = GET_CID_ADDR(cid);
  2941. for (i = 0; i < CTX_SIZE; i += 4)
  2942. cnic_ctx_wr(dev, cid_addr, i, 0);
  2943. }
  2944. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2945. {
  2946. struct cnic_local *cp = dev->cnic_priv;
  2947. int ret = 0, i;
  2948. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2949. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2950. return 0;
  2951. for (i = 0; i < cp->ctx_blks; i++) {
  2952. int j;
  2953. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2954. u32 val;
  2955. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2956. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2957. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2958. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2959. (u64) cp->ctx_arr[i].mapping >> 32);
  2960. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2961. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2962. for (j = 0; j < 10; j++) {
  2963. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2964. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2965. break;
  2966. udelay(5);
  2967. }
  2968. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2969. ret = -EBUSY;
  2970. break;
  2971. }
  2972. }
  2973. return ret;
  2974. }
  2975. static void cnic_free_irq(struct cnic_dev *dev)
  2976. {
  2977. struct cnic_local *cp = dev->cnic_priv;
  2978. struct cnic_eth_dev *ethdev = cp->ethdev;
  2979. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2980. cp->disable_int_sync(dev);
  2981. tasklet_kill(&cp->cnic_irq_task);
  2982. free_irq(ethdev->irq_arr[0].vector, dev);
  2983. }
  2984. }
  2985. static int cnic_request_irq(struct cnic_dev *dev)
  2986. {
  2987. struct cnic_local *cp = dev->cnic_priv;
  2988. struct cnic_eth_dev *ethdev = cp->ethdev;
  2989. int err;
  2990. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  2991. if (err)
  2992. tasklet_disable(&cp->cnic_irq_task);
  2993. return err;
  2994. }
  2995. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2996. {
  2997. struct cnic_local *cp = dev->cnic_priv;
  2998. struct cnic_eth_dev *ethdev = cp->ethdev;
  2999. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3000. int err, i = 0;
  3001. int sblk_num = cp->status_blk_num;
  3002. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3003. BNX2_HC_SB_CONFIG_1;
  3004. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3005. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3006. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3007. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3008. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3009. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3010. (unsigned long) dev);
  3011. err = cnic_request_irq(dev);
  3012. if (err)
  3013. return err;
  3014. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3015. i < 10) {
  3016. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3017. 1 << (11 + sblk_num));
  3018. udelay(10);
  3019. i++;
  3020. barrier();
  3021. }
  3022. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3023. cnic_free_irq(dev);
  3024. goto failed;
  3025. }
  3026. } else {
  3027. struct status_block *sblk = cp->status_blk.gen;
  3028. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3029. int i = 0;
  3030. while (sblk->status_completion_producer_index && i < 10) {
  3031. CNIC_WR(dev, BNX2_HC_COMMAND,
  3032. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3033. udelay(10);
  3034. i++;
  3035. barrier();
  3036. }
  3037. if (sblk->status_completion_producer_index)
  3038. goto failed;
  3039. }
  3040. return 0;
  3041. failed:
  3042. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3043. return -EBUSY;
  3044. }
  3045. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3046. {
  3047. struct cnic_local *cp = dev->cnic_priv;
  3048. struct cnic_eth_dev *ethdev = cp->ethdev;
  3049. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3050. return;
  3051. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3052. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3053. }
  3054. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3055. {
  3056. struct cnic_local *cp = dev->cnic_priv;
  3057. struct cnic_eth_dev *ethdev = cp->ethdev;
  3058. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3059. return;
  3060. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3061. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3062. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3063. synchronize_irq(ethdev->irq_arr[0].vector);
  3064. }
  3065. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3066. {
  3067. struct cnic_local *cp = dev->cnic_priv;
  3068. struct cnic_eth_dev *ethdev = cp->ethdev;
  3069. struct cnic_uio_dev *udev = cp->udev;
  3070. u32 cid_addr, tx_cid, sb_id;
  3071. u32 val, offset0, offset1, offset2, offset3;
  3072. int i;
  3073. struct tx_bd *txbd;
  3074. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3075. struct status_block *s_blk = cp->status_blk.gen;
  3076. sb_id = cp->status_blk_num;
  3077. tx_cid = 20;
  3078. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3079. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3080. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3081. tx_cid = TX_TSS_CID + sb_id - 1;
  3082. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3083. (TX_TSS_CID << 7));
  3084. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3085. }
  3086. cp->tx_cons = *cp->tx_cons_ptr;
  3087. cid_addr = GET_CID_ADDR(tx_cid);
  3088. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3089. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3090. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3091. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3092. offset0 = BNX2_L2CTX_TYPE_XI;
  3093. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3094. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3095. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3096. } else {
  3097. cnic_init_context(dev, tx_cid);
  3098. cnic_init_context(dev, tx_cid + 1);
  3099. offset0 = BNX2_L2CTX_TYPE;
  3100. offset1 = BNX2_L2CTX_CMD_TYPE;
  3101. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3102. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3103. }
  3104. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3105. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3106. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3107. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3108. txbd = (struct tx_bd *) udev->l2_ring;
  3109. buf_map = udev->l2_buf_map;
  3110. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3111. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3112. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3113. }
  3114. val = (u64) ring_map >> 32;
  3115. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3116. txbd->tx_bd_haddr_hi = val;
  3117. val = (u64) ring_map & 0xffffffff;
  3118. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3119. txbd->tx_bd_haddr_lo = val;
  3120. }
  3121. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3122. {
  3123. struct cnic_local *cp = dev->cnic_priv;
  3124. struct cnic_eth_dev *ethdev = cp->ethdev;
  3125. struct cnic_uio_dev *udev = cp->udev;
  3126. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3127. int i;
  3128. struct rx_bd *rxbd;
  3129. struct status_block *s_blk = cp->status_blk.gen;
  3130. dma_addr_t ring_map = udev->l2_ring_map;
  3131. sb_id = cp->status_blk_num;
  3132. cnic_init_context(dev, 2);
  3133. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3134. coal_reg = BNX2_HC_COMMAND;
  3135. coal_val = CNIC_RD(dev, coal_reg);
  3136. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3137. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3138. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3139. coal_reg = BNX2_HC_COALESCE_NOW;
  3140. coal_val = 1 << (11 + sb_id);
  3141. }
  3142. i = 0;
  3143. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3144. CNIC_WR(dev, coal_reg, coal_val);
  3145. udelay(10);
  3146. i++;
  3147. barrier();
  3148. }
  3149. cp->rx_cons = *cp->rx_cons_ptr;
  3150. cid_addr = GET_CID_ADDR(2);
  3151. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3152. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3153. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3154. if (sb_id == 0)
  3155. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3156. else
  3157. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3158. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3159. rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
  3160. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3161. dma_addr_t buf_map;
  3162. int n = (i % cp->l2_rx_ring_size) + 1;
  3163. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3164. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3165. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3166. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3167. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3168. }
  3169. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3170. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3171. rxbd->rx_bd_haddr_hi = val;
  3172. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3173. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3174. rxbd->rx_bd_haddr_lo = val;
  3175. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3176. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3177. }
  3178. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3179. {
  3180. struct kwqe *wqes[1], l2kwqe;
  3181. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3182. wqes[0] = &l2kwqe;
  3183. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  3184. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3185. KWQE_OPCODE_SHIFT) | 2;
  3186. dev->submit_kwqes(dev, wqes, 1);
  3187. }
  3188. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3189. {
  3190. struct cnic_local *cp = dev->cnic_priv;
  3191. u32 val;
  3192. val = cp->func << 2;
  3193. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3194. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3195. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3196. dev->mac_addr[0] = (u8) (val >> 8);
  3197. dev->mac_addr[1] = (u8) val;
  3198. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3199. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3200. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3201. dev->mac_addr[2] = (u8) (val >> 24);
  3202. dev->mac_addr[3] = (u8) (val >> 16);
  3203. dev->mac_addr[4] = (u8) (val >> 8);
  3204. dev->mac_addr[5] = (u8) val;
  3205. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3206. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3207. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3208. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3209. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3210. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3211. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3212. }
  3213. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3214. {
  3215. struct cnic_local *cp = dev->cnic_priv;
  3216. struct cnic_eth_dev *ethdev = cp->ethdev;
  3217. struct status_block *sblk = cp->status_blk.gen;
  3218. u32 val, kcq_cid_addr, kwq_cid_addr;
  3219. int err;
  3220. cnic_set_bnx2_mac(dev);
  3221. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3222. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3223. if (BCM_PAGE_BITS > 12)
  3224. val |= (12 - 8) << 4;
  3225. else
  3226. val |= (BCM_PAGE_BITS - 8) << 4;
  3227. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3228. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3229. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3230. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3231. err = cnic_setup_5709_context(dev, 1);
  3232. if (err)
  3233. return err;
  3234. cnic_init_context(dev, KWQ_CID);
  3235. cnic_init_context(dev, KCQ_CID);
  3236. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3237. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3238. cp->max_kwq_idx = MAX_KWQ_IDX;
  3239. cp->kwq_prod_idx = 0;
  3240. cp->kwq_con_idx = 0;
  3241. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3242. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3243. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3244. else
  3245. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3246. /* Initialize the kernel work queue context. */
  3247. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3248. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3249. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3250. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3251. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3252. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3253. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3254. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3255. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3256. val = (u32) cp->kwq_info.pgtbl_map;
  3257. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3258. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3259. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3260. cp->kcq1.sw_prod_idx = 0;
  3261. cp->kcq1.hw_prod_idx_ptr =
  3262. (u16 *) &sblk->status_completion_producer_index;
  3263. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3264. /* Initialize the kernel complete queue context. */
  3265. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3266. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3267. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3268. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3269. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3270. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3271. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3272. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3273. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3274. val = (u32) cp->kcq1.dma.pgtbl_map;
  3275. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3276. cp->int_num = 0;
  3277. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3278. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3279. u32 sb_id = cp->status_blk_num;
  3280. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3281. cp->kcq1.hw_prod_idx_ptr =
  3282. (u16 *) &msblk->status_completion_producer_index;
  3283. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3284. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3285. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3286. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3287. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3288. }
  3289. /* Enable Commnad Scheduler notification when we write to the
  3290. * host producer index of the kernel contexts. */
  3291. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3292. /* Enable Command Scheduler notification when we write to either
  3293. * the Send Queue or Receive Queue producer indexes of the kernel
  3294. * bypass contexts. */
  3295. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3296. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3297. /* Notify COM when the driver post an application buffer. */
  3298. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3299. /* Set the CP and COM doorbells. These two processors polls the
  3300. * doorbell for a non zero value before running. This must be done
  3301. * after setting up the kernel queue contexts. */
  3302. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3303. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3304. cnic_init_bnx2_tx_ring(dev);
  3305. cnic_init_bnx2_rx_ring(dev);
  3306. err = cnic_init_bnx2_irq(dev);
  3307. if (err) {
  3308. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3309. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3310. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3311. return err;
  3312. }
  3313. return 0;
  3314. }
  3315. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3316. {
  3317. struct cnic_local *cp = dev->cnic_priv;
  3318. struct cnic_eth_dev *ethdev = cp->ethdev;
  3319. u32 start_offset = ethdev->ctx_tbl_offset;
  3320. int i;
  3321. for (i = 0; i < cp->ctx_blks; i++) {
  3322. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3323. dma_addr_t map = ctx->mapping;
  3324. if (cp->ctx_align) {
  3325. unsigned long mask = cp->ctx_align - 1;
  3326. map = (map + mask) & ~mask;
  3327. }
  3328. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3329. }
  3330. }
  3331. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3332. {
  3333. struct cnic_local *cp = dev->cnic_priv;
  3334. struct cnic_eth_dev *ethdev = cp->ethdev;
  3335. int err = 0;
  3336. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3337. (unsigned long) dev);
  3338. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3339. err = cnic_request_irq(dev);
  3340. return err;
  3341. }
  3342. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3343. u16 sb_id, u8 sb_index,
  3344. u8 disable)
  3345. {
  3346. u32 addr = BAR_CSTRORM_INTMEM +
  3347. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3348. offsetof(struct hc_status_block_data_e1x, index_data) +
  3349. sizeof(struct hc_index_data)*sb_index +
  3350. offsetof(struct hc_index_data, flags);
  3351. u16 flags = CNIC_RD16(dev, addr);
  3352. /* clear and set */
  3353. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3354. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3355. HC_INDEX_DATA_HC_ENABLED);
  3356. CNIC_WR16(dev, addr, flags);
  3357. }
  3358. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3359. {
  3360. struct cnic_local *cp = dev->cnic_priv;
  3361. u8 sb_id = cp->status_blk_num;
  3362. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3363. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3364. offsetof(struct hc_status_block_data_e1x, index_data) +
  3365. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3366. offsetof(struct hc_index_data, timeout), 64 / 12);
  3367. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3368. }
  3369. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3370. {
  3371. }
  3372. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3373. struct client_init_ramrod_data *data)
  3374. {
  3375. struct cnic_local *cp = dev->cnic_priv;
  3376. struct cnic_uio_dev *udev = cp->udev;
  3377. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3378. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3379. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3380. int port = CNIC_PORT(cp);
  3381. int i;
  3382. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3383. u32 val;
  3384. memset(txbd, 0, BCM_PAGE_SIZE);
  3385. buf_map = udev->l2_buf_map;
  3386. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3387. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3388. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3389. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3390. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3391. reg_bd->addr_hi = start_bd->addr_hi;
  3392. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3393. start_bd->nbytes = cpu_to_le16(0x10);
  3394. start_bd->nbd = cpu_to_le16(3);
  3395. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3396. start_bd->general_data = (UNICAST_ADDRESS <<
  3397. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3398. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3399. }
  3400. val = (u64) ring_map >> 32;
  3401. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3402. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3403. val = (u64) ring_map & 0xffffffff;
  3404. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3405. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3406. /* Other ramrod params */
  3407. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3408. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3409. /* reset xstorm per client statistics */
  3410. if (cli < MAX_STAT_COUNTER_ID) {
  3411. val = BAR_XSTRORM_INTMEM +
  3412. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3413. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3414. CNIC_WR(dev, val + i * 4, 0);
  3415. }
  3416. cp->tx_cons_ptr =
  3417. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3418. }
  3419. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3420. struct client_init_ramrod_data *data)
  3421. {
  3422. struct cnic_local *cp = dev->cnic_priv;
  3423. struct cnic_uio_dev *udev = cp->udev;
  3424. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3425. BCM_PAGE_SIZE);
  3426. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3427. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3428. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3429. int i;
  3430. int port = CNIC_PORT(cp);
  3431. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3432. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3433. u32 val;
  3434. dma_addr_t ring_map = udev->l2_ring_map;
  3435. /* General data */
  3436. data->general.client_id = cli;
  3437. data->general.statistics_en_flg = 1;
  3438. data->general.statistics_counter_id = cli;
  3439. data->general.activate_flg = 1;
  3440. data->general.sp_client_id = cli;
  3441. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3442. dma_addr_t buf_map;
  3443. int n = (i % cp->l2_rx_ring_size) + 1;
  3444. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3445. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3446. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3447. }
  3448. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3449. rxbd->addr_hi = cpu_to_le32(val);
  3450. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3451. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3452. rxbd->addr_lo = cpu_to_le32(val);
  3453. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3454. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3455. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3456. rxcqe->addr_hi = cpu_to_le32(val);
  3457. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3458. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3459. rxcqe->addr_lo = cpu_to_le32(val);
  3460. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3461. /* Other ramrod params */
  3462. data->rx.client_qzone_id = cl_qzone_id;
  3463. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3464. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3465. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3466. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3467. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3468. data->rx.outer_vlan_removal_enable_flg = 1;
  3469. /* reset tstorm and ustorm per client statistics */
  3470. if (cli < MAX_STAT_COUNTER_ID) {
  3471. val = BAR_TSTRORM_INTMEM +
  3472. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3473. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3474. CNIC_WR(dev, val + i * 4, 0);
  3475. val = BAR_USTRORM_INTMEM +
  3476. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3477. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3478. CNIC_WR(dev, val + i * 4, 0);
  3479. }
  3480. cp->rx_cons_ptr =
  3481. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3482. }
  3483. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3484. {
  3485. struct cnic_local *cp = dev->cnic_priv;
  3486. u32 base, base2, addr, val;
  3487. int port = CNIC_PORT(cp);
  3488. dev->max_iscsi_conn = 0;
  3489. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3490. if (base == 0)
  3491. return;
  3492. base2 = CNIC_RD(dev, (CNIC_PATH(cp) ? MISC_REG_GENERIC_CR_1 :
  3493. MISC_REG_GENERIC_CR_0));
  3494. addr = BNX2X_SHMEM_ADDR(base,
  3495. dev_info.port_hw_config[port].iscsi_mac_upper);
  3496. val = CNIC_RD(dev, addr);
  3497. dev->mac_addr[0] = (u8) (val >> 8);
  3498. dev->mac_addr[1] = (u8) val;
  3499. addr = BNX2X_SHMEM_ADDR(base,
  3500. dev_info.port_hw_config[port].iscsi_mac_lower);
  3501. val = CNIC_RD(dev, addr);
  3502. dev->mac_addr[2] = (u8) (val >> 24);
  3503. dev->mac_addr[3] = (u8) (val >> 16);
  3504. dev->mac_addr[4] = (u8) (val >> 8);
  3505. dev->mac_addr[5] = (u8) val;
  3506. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3507. val = CNIC_RD(dev, addr);
  3508. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3509. u16 val16;
  3510. addr = BNX2X_SHMEM_ADDR(base,
  3511. drv_lic_key[port].max_iscsi_init_conn);
  3512. val16 = CNIC_RD16(dev, addr);
  3513. if (val16)
  3514. val16 ^= 0x1e1e;
  3515. dev->max_iscsi_conn = val16;
  3516. }
  3517. if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3518. int func = CNIC_FUNC(cp);
  3519. u32 mf_cfg_addr;
  3520. if (BNX2X_SHMEM2_HAS(base2, mf_cfg_addr))
  3521. mf_cfg_addr = CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base2,
  3522. mf_cfg_addr));
  3523. else
  3524. mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
  3525. addr = mf_cfg_addr +
  3526. offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
  3527. val = CNIC_RD(dev, addr);
  3528. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3529. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3530. addr = mf_cfg_addr +
  3531. offsetof(struct mf_cfg,
  3532. func_mf_config[func].config);
  3533. val = CNIC_RD(dev, addr);
  3534. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3535. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3536. dev->max_iscsi_conn = 0;
  3537. }
  3538. }
  3539. }
  3540. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3541. {
  3542. struct cnic_local *cp = dev->cnic_priv;
  3543. struct cnic_eth_dev *ethdev = cp->ethdev;
  3544. int func = CNIC_FUNC(cp), ret, i;
  3545. u32 pfid;
  3546. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3547. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  3548. if (!(val & 1))
  3549. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  3550. else
  3551. val = (val >> 1) & 1;
  3552. if (val)
  3553. cp->pfid = func >> 1;
  3554. else
  3555. cp->pfid = func & 0x6;
  3556. } else {
  3557. cp->pfid = func;
  3558. }
  3559. pfid = cp->pfid;
  3560. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3561. cp->iscsi_start_cid);
  3562. if (ret)
  3563. return -ENOMEM;
  3564. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  3565. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3566. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3567. cp->kcq1.sw_prod_idx = 0;
  3568. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3569. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3570. cp->kcq1.hw_prod_idx_ptr =
  3571. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3572. cp->kcq1.status_idx_ptr =
  3573. &sb->sb.running_index[SM_RX_ID];
  3574. } else {
  3575. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3576. cp->kcq1.hw_prod_idx_ptr =
  3577. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3578. cp->kcq1.status_idx_ptr =
  3579. &sb->sb.running_index[SM_RX_ID];
  3580. }
  3581. cnic_get_bnx2x_iscsi_info(dev);
  3582. /* Only 1 EQ */
  3583. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3584. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3585. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  3586. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3587. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  3588. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3589. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3590. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  3591. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  3592. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3593. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  3594. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  3595. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3596. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  3597. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  3598. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3599. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  3600. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3601. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  3602. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3603. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  3604. HC_INDEX_ISCSI_EQ_CONS);
  3605. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3606. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3607. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  3608. cp->conn_buf_info.pgtbl[2 * i]);
  3609. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3610. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  3611. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3612. }
  3613. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3614. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  3615. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3616. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3617. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  3618. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3619. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3620. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  3621. cnic_setup_bnx2x_context(dev);
  3622. ret = cnic_init_bnx2x_irq(dev);
  3623. if (ret)
  3624. return ret;
  3625. return 0;
  3626. }
  3627. static void cnic_init_rings(struct cnic_dev *dev)
  3628. {
  3629. struct cnic_local *cp = dev->cnic_priv;
  3630. struct cnic_uio_dev *udev = cp->udev;
  3631. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3632. return;
  3633. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3634. cnic_init_bnx2_tx_ring(dev);
  3635. cnic_init_bnx2_rx_ring(dev);
  3636. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3637. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3638. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3639. u32 cl_qzone_id, type;
  3640. struct client_init_ramrod_data *data;
  3641. union l5cm_specific_data l5_data;
  3642. struct ustorm_eth_rx_producers rx_prods = {0};
  3643. u32 off, i;
  3644. rx_prods.bd_prod = 0;
  3645. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3646. barrier();
  3647. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3648. off = BAR_USTRORM_INTMEM +
  3649. (BNX2X_CHIP_IS_E2(cp->chip_id) ?
  3650. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  3651. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  3652. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3653. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  3654. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3655. data = udev->l2_buf;
  3656. memset(data, 0, sizeof(*data));
  3657. cnic_init_bnx2x_tx_ring(dev, data);
  3658. cnic_init_bnx2x_rx_ring(dev, data);
  3659. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  3660. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  3661. type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3662. & SPE_HDR_CONN_TYPE;
  3663. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3664. SPE_HDR_FUNCTION_ID);
  3665. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3666. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3667. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3668. i = 0;
  3669. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3670. ++i < 10)
  3671. msleep(1);
  3672. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3673. netdev_err(dev->netdev,
  3674. "iSCSI CLIENT_SETUP did not complete\n");
  3675. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3676. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3677. }
  3678. }
  3679. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3680. {
  3681. struct cnic_local *cp = dev->cnic_priv;
  3682. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3683. return;
  3684. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3685. cnic_shutdown_bnx2_rx_ring(dev);
  3686. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3687. struct cnic_local *cp = dev->cnic_priv;
  3688. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3689. union l5cm_specific_data l5_data;
  3690. int i;
  3691. u32 type;
  3692. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3693. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3694. l5_data.phy_address.lo = cli;
  3695. l5_data.phy_address.hi = 0;
  3696. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  3697. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3698. i = 0;
  3699. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3700. ++i < 10)
  3701. msleep(1);
  3702. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3703. netdev_err(dev->netdev,
  3704. "iSCSI CLIENT_HALT did not complete\n");
  3705. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3706. memset(&l5_data, 0, sizeof(l5_data));
  3707. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3708. & SPE_HDR_CONN_TYPE;
  3709. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3710. SPE_HDR_FUNCTION_ID);
  3711. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  3712. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3713. msleep(10);
  3714. }
  3715. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3716. }
  3717. static int cnic_register_netdev(struct cnic_dev *dev)
  3718. {
  3719. struct cnic_local *cp = dev->cnic_priv;
  3720. struct cnic_eth_dev *ethdev = cp->ethdev;
  3721. int err;
  3722. if (!ethdev)
  3723. return -ENODEV;
  3724. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3725. return 0;
  3726. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3727. if (err)
  3728. netdev_err(dev->netdev, "register_cnic failed\n");
  3729. return err;
  3730. }
  3731. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3732. {
  3733. struct cnic_local *cp = dev->cnic_priv;
  3734. struct cnic_eth_dev *ethdev = cp->ethdev;
  3735. if (!ethdev)
  3736. return;
  3737. ethdev->drv_unregister_cnic(dev->netdev);
  3738. }
  3739. static int cnic_start_hw(struct cnic_dev *dev)
  3740. {
  3741. struct cnic_local *cp = dev->cnic_priv;
  3742. struct cnic_eth_dev *ethdev = cp->ethdev;
  3743. int err;
  3744. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3745. return -EALREADY;
  3746. dev->regview = ethdev->io_base;
  3747. pci_dev_get(dev->pcidev);
  3748. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3749. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  3750. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3751. err = cp->alloc_resc(dev);
  3752. if (err) {
  3753. netdev_err(dev->netdev, "allocate resource failure\n");
  3754. goto err1;
  3755. }
  3756. err = cp->start_hw(dev);
  3757. if (err)
  3758. goto err1;
  3759. err = cnic_cm_open(dev);
  3760. if (err)
  3761. goto err1;
  3762. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3763. cp->enable_int(dev);
  3764. return 0;
  3765. err1:
  3766. cp->free_resc(dev);
  3767. pci_dev_put(dev->pcidev);
  3768. return err;
  3769. }
  3770. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3771. {
  3772. cnic_disable_bnx2_int_sync(dev);
  3773. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3774. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3775. cnic_init_context(dev, KWQ_CID);
  3776. cnic_init_context(dev, KCQ_CID);
  3777. cnic_setup_5709_context(dev, 0);
  3778. cnic_free_irq(dev);
  3779. cnic_free_resc(dev);
  3780. }
  3781. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3782. {
  3783. struct cnic_local *cp = dev->cnic_priv;
  3784. cnic_free_irq(dev);
  3785. *cp->kcq1.hw_prod_idx_ptr = 0;
  3786. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3787. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  3788. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  3789. cnic_free_resc(dev);
  3790. }
  3791. static void cnic_stop_hw(struct cnic_dev *dev)
  3792. {
  3793. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3794. struct cnic_local *cp = dev->cnic_priv;
  3795. int i = 0;
  3796. /* Need to wait for the ring shutdown event to complete
  3797. * before clearing the CNIC_UP flag.
  3798. */
  3799. while (cp->udev->uio_dev != -1 && i < 15) {
  3800. msleep(100);
  3801. i++;
  3802. }
  3803. cnic_shutdown_rings(dev);
  3804. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3805. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3806. synchronize_rcu();
  3807. cnic_cm_shutdown(dev);
  3808. cp->stop_hw(dev);
  3809. pci_dev_put(dev->pcidev);
  3810. }
  3811. }
  3812. static void cnic_free_dev(struct cnic_dev *dev)
  3813. {
  3814. int i = 0;
  3815. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3816. msleep(100);
  3817. i++;
  3818. }
  3819. if (atomic_read(&dev->ref_count) != 0)
  3820. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  3821. netdev_info(dev->netdev, "Removed CNIC device\n");
  3822. dev_put(dev->netdev);
  3823. kfree(dev);
  3824. }
  3825. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3826. struct pci_dev *pdev)
  3827. {
  3828. struct cnic_dev *cdev;
  3829. struct cnic_local *cp;
  3830. int alloc_size;
  3831. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3832. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3833. if (cdev == NULL) {
  3834. netdev_err(dev, "allocate dev struct failure\n");
  3835. return NULL;
  3836. }
  3837. cdev->netdev = dev;
  3838. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3839. cdev->register_device = cnic_register_device;
  3840. cdev->unregister_device = cnic_unregister_device;
  3841. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3842. cp = cdev->cnic_priv;
  3843. cp->dev = cdev;
  3844. cp->l2_single_buf_size = 0x400;
  3845. cp->l2_rx_ring_size = 3;
  3846. spin_lock_init(&cp->cnic_ulp_lock);
  3847. netdev_info(dev, "Added CNIC device\n");
  3848. return cdev;
  3849. }
  3850. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3851. {
  3852. struct pci_dev *pdev;
  3853. struct cnic_dev *cdev;
  3854. struct cnic_local *cp;
  3855. struct cnic_eth_dev *ethdev = NULL;
  3856. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3857. probe = symbol_get(bnx2_cnic_probe);
  3858. if (probe) {
  3859. ethdev = (*probe)(dev);
  3860. symbol_put(bnx2_cnic_probe);
  3861. }
  3862. if (!ethdev)
  3863. return NULL;
  3864. pdev = ethdev->pdev;
  3865. if (!pdev)
  3866. return NULL;
  3867. dev_hold(dev);
  3868. pci_dev_get(pdev);
  3869. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3870. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3871. u8 rev;
  3872. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3873. if (rev < 0x10) {
  3874. pci_dev_put(pdev);
  3875. goto cnic_err;
  3876. }
  3877. }
  3878. pci_dev_put(pdev);
  3879. cdev = cnic_alloc_dev(dev, pdev);
  3880. if (cdev == NULL)
  3881. goto cnic_err;
  3882. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3883. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3884. cp = cdev->cnic_priv;
  3885. cp->ethdev = ethdev;
  3886. cdev->pcidev = pdev;
  3887. cp->chip_id = ethdev->chip_id;
  3888. cp->cnic_ops = &cnic_bnx2_ops;
  3889. cp->start_hw = cnic_start_bnx2_hw;
  3890. cp->stop_hw = cnic_stop_bnx2_hw;
  3891. cp->setup_pgtbl = cnic_setup_page_tbl;
  3892. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3893. cp->free_resc = cnic_free_resc;
  3894. cp->start_cm = cnic_cm_init_bnx2_hw;
  3895. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3896. cp->enable_int = cnic_enable_bnx2_int;
  3897. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3898. cp->close_conn = cnic_close_bnx2_conn;
  3899. cp->next_idx = cnic_bnx2_next_idx;
  3900. cp->hw_idx = cnic_bnx2_hw_idx;
  3901. return cdev;
  3902. cnic_err:
  3903. dev_put(dev);
  3904. return NULL;
  3905. }
  3906. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3907. {
  3908. struct pci_dev *pdev;
  3909. struct cnic_dev *cdev;
  3910. struct cnic_local *cp;
  3911. struct cnic_eth_dev *ethdev = NULL;
  3912. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3913. probe = symbol_get(bnx2x_cnic_probe);
  3914. if (probe) {
  3915. ethdev = (*probe)(dev);
  3916. symbol_put(bnx2x_cnic_probe);
  3917. }
  3918. if (!ethdev)
  3919. return NULL;
  3920. pdev = ethdev->pdev;
  3921. if (!pdev)
  3922. return NULL;
  3923. dev_hold(dev);
  3924. cdev = cnic_alloc_dev(dev, pdev);
  3925. if (cdev == NULL) {
  3926. dev_put(dev);
  3927. return NULL;
  3928. }
  3929. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3930. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3931. cp = cdev->cnic_priv;
  3932. cp->ethdev = ethdev;
  3933. cdev->pcidev = pdev;
  3934. cp->chip_id = ethdev->chip_id;
  3935. cp->cnic_ops = &cnic_bnx2x_ops;
  3936. cp->start_hw = cnic_start_bnx2x_hw;
  3937. cp->stop_hw = cnic_stop_bnx2x_hw;
  3938. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3939. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3940. cp->free_resc = cnic_free_resc;
  3941. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3942. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3943. cp->enable_int = cnic_enable_bnx2x_int;
  3944. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3945. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  3946. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  3947. else
  3948. cp->ack_int = cnic_ack_bnx2x_msix;
  3949. cp->close_conn = cnic_close_bnx2x_conn;
  3950. cp->next_idx = cnic_bnx2x_next_idx;
  3951. cp->hw_idx = cnic_bnx2x_hw_idx;
  3952. return cdev;
  3953. }
  3954. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3955. {
  3956. struct ethtool_drvinfo drvinfo;
  3957. struct cnic_dev *cdev = NULL;
  3958. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3959. memset(&drvinfo, 0, sizeof(drvinfo));
  3960. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3961. if (!strcmp(drvinfo.driver, "bnx2"))
  3962. cdev = init_bnx2_cnic(dev);
  3963. if (!strcmp(drvinfo.driver, "bnx2x"))
  3964. cdev = init_bnx2x_cnic(dev);
  3965. if (cdev) {
  3966. write_lock(&cnic_dev_lock);
  3967. list_add(&cdev->list, &cnic_dev_list);
  3968. write_unlock(&cnic_dev_lock);
  3969. }
  3970. }
  3971. return cdev;
  3972. }
  3973. /**
  3974. * netdev event handler
  3975. */
  3976. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3977. void *ptr)
  3978. {
  3979. struct net_device *netdev = ptr;
  3980. struct cnic_dev *dev;
  3981. int if_type;
  3982. int new_dev = 0;
  3983. dev = cnic_from_netdev(netdev);
  3984. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3985. /* Check for the hot-plug device */
  3986. dev = is_cnic_dev(netdev);
  3987. if (dev) {
  3988. new_dev = 1;
  3989. cnic_hold(dev);
  3990. }
  3991. }
  3992. if (dev) {
  3993. struct cnic_local *cp = dev->cnic_priv;
  3994. if (new_dev)
  3995. cnic_ulp_init(dev);
  3996. else if (event == NETDEV_UNREGISTER)
  3997. cnic_ulp_exit(dev);
  3998. if (event == NETDEV_UP) {
  3999. if (cnic_register_netdev(dev) != 0) {
  4000. cnic_put(dev);
  4001. goto done;
  4002. }
  4003. if (!cnic_start_hw(dev))
  4004. cnic_ulp_start(dev);
  4005. }
  4006. rcu_read_lock();
  4007. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4008. struct cnic_ulp_ops *ulp_ops;
  4009. void *ctx;
  4010. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4011. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4012. continue;
  4013. ctx = cp->ulp_handle[if_type];
  4014. ulp_ops->indicate_netevent(ctx, event);
  4015. }
  4016. rcu_read_unlock();
  4017. if (event == NETDEV_GOING_DOWN) {
  4018. cnic_ulp_stop(dev);
  4019. cnic_stop_hw(dev);
  4020. cnic_unregister_netdev(dev);
  4021. } else if (event == NETDEV_UNREGISTER) {
  4022. write_lock(&cnic_dev_lock);
  4023. list_del_init(&dev->list);
  4024. write_unlock(&cnic_dev_lock);
  4025. cnic_put(dev);
  4026. cnic_free_dev(dev);
  4027. goto done;
  4028. }
  4029. cnic_put(dev);
  4030. }
  4031. done:
  4032. return NOTIFY_DONE;
  4033. }
  4034. static struct notifier_block cnic_netdev_notifier = {
  4035. .notifier_call = cnic_netdev_event
  4036. };
  4037. static void cnic_release(void)
  4038. {
  4039. struct cnic_dev *dev;
  4040. struct cnic_uio_dev *udev;
  4041. while (!list_empty(&cnic_dev_list)) {
  4042. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4043. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4044. cnic_ulp_stop(dev);
  4045. cnic_stop_hw(dev);
  4046. }
  4047. cnic_ulp_exit(dev);
  4048. cnic_unregister_netdev(dev);
  4049. list_del_init(&dev->list);
  4050. cnic_free_dev(dev);
  4051. }
  4052. while (!list_empty(&cnic_udev_list)) {
  4053. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4054. list);
  4055. cnic_free_uio(udev);
  4056. }
  4057. }
  4058. static int __init cnic_init(void)
  4059. {
  4060. int rc = 0;
  4061. pr_info("%s", version);
  4062. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4063. if (rc) {
  4064. cnic_release();
  4065. return rc;
  4066. }
  4067. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4068. if (!cnic_wq) {
  4069. cnic_release();
  4070. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4071. return -ENOMEM;
  4072. }
  4073. return 0;
  4074. }
  4075. static void __exit cnic_exit(void)
  4076. {
  4077. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4078. cnic_release();
  4079. destroy_workqueue(cnic_wq);
  4080. }
  4081. module_init(cnic_init);
  4082. module_exit(cnic_exit);