gdth.c 200 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.4.x, 2.6.x supported *
  31. * *
  32. * $Log: gdth.c,v $
  33. * Revision 1.74 2006/04/10 13:44:47 achim
  34. * Community changes for 2.6.x
  35. * Kernel 2.2.x no longer supported
  36. * scsi_request interface removed, thanks to Christoph Hellwig
  37. *
  38. * Revision 1.73 2004/03/31 13:33:03 achim
  39. * Special command 0xfd implemented to detect 64-bit DMA support
  40. *
  41. * Revision 1.72 2004/03/17 08:56:04 achim
  42. * 64-bit DMA only enabled if FW >= x.43
  43. *
  44. * Revision 1.71 2004/03/05 15:51:29 achim
  45. * Screen service: separate message buffer, bugfixes
  46. *
  47. * Revision 1.70 2004/02/27 12:19:07 achim
  48. * Bugfix: Reset bit in config (0xfe) call removed
  49. *
  50. * Revision 1.69 2004/02/20 09:50:24 achim
  51. * Compatibility changes for kernels < 2.4.20
  52. * Bugfix screen service command size
  53. * pci_set_dma_mask() error handling added
  54. *
  55. * Revision 1.68 2004/02/19 15:46:54 achim
  56. * 64-bit DMA bugfixes
  57. * Drive size bugfix for drives > 1TB
  58. *
  59. * Revision 1.67 2004/01/14 13:11:57 achim
  60. * Tool access over /proc no longer supported
  61. * Bugfixes IOCTLs
  62. *
  63. * Revision 1.66 2003/12/19 15:04:06 achim
  64. * Bugfixes support for drives > 2TB
  65. *
  66. * Revision 1.65 2003/12/15 11:21:56 achim
  67. * 64-bit DMA support added
  68. * Support for drives > 2 TB implemented
  69. * Kernels 2.2.x, 2.4.x, 2.6.x supported
  70. *
  71. * Revision 1.64 2003/09/17 08:30:26 achim
  72. * EISA/ISA controller scan disabled
  73. * Command line switch probe_eisa_isa added
  74. *
  75. * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
  76. * Minor cleanups in gdth_ioctl.
  77. *
  78. * Revision 1.62 2003/02/27 15:01:59 achim
  79. * Dynamic DMA mapping implemented
  80. * New (character device) IOCTL interface added
  81. * Other controller related changes made
  82. *
  83. * Revision 1.61 2002/11/08 13:09:52 boji
  84. * Added support for XSCALE based RAID Controllers
  85. * Fixed SCREENSERVICE initialization in SMP cases
  86. * Added checks for gdth_polling before GDTH_HA_LOCK
  87. *
  88. * Revision 1.60 2002/02/05 09:35:22 achim
  89. * MODULE_LICENSE only if kernel >= 2.4.11
  90. *
  91. * Revision 1.59 2002/01/30 09:46:33 achim
  92. * Small changes
  93. *
  94. * Revision 1.58 2002/01/29 15:30:02 achim
  95. * Set default value of shared_access to Y
  96. * New status S_CACHE_RESERV for clustering added
  97. *
  98. * Revision 1.57 2001/08/21 11:16:35 achim
  99. * Bugfix free_irq()
  100. *
  101. * Revision 1.56 2001/08/09 11:19:39 achim
  102. * Scsi_Host_Template changes
  103. *
  104. * Revision 1.55 2001/08/09 10:11:28 achim
  105. * Command HOST_UNFREEZE_IO before cache service init.
  106. *
  107. * Revision 1.54 2001/07/20 13:48:12 achim
  108. * Expand: gdth_analyse_hdrive() removed
  109. *
  110. * Revision 1.53 2001/07/17 09:52:49 achim
  111. * Small OEM related change
  112. *
  113. * Revision 1.52 2001/06/19 15:06:20 achim
  114. * New host command GDT_UNFREEZE_IO added
  115. *
  116. * Revision 1.51 2001/05/22 06:42:37 achim
  117. * PCI: Subdevice ID added
  118. *
  119. * Revision 1.50 2001/05/17 13:42:16 achim
  120. * Support for Intel Storage RAID Controllers added
  121. *
  122. * Revision 1.50 2001/05/17 12:12:34 achim
  123. * Support for Intel Storage RAID Controllers added
  124. *
  125. * Revision 1.49 2001/03/15 15:07:17 achim
  126. * New __setup interface for boot command line options added
  127. *
  128. * Revision 1.48 2001/02/06 12:36:28 achim
  129. * Bugfix Cluster protocol
  130. *
  131. * Revision 1.47 2001/01/10 14:42:06 achim
  132. * New switch shared_access added
  133. *
  134. * Revision 1.46 2001/01/09 08:11:35 achim
  135. * gdth_command() removed
  136. * meaning of Scsi_Pointer members changed
  137. *
  138. * Revision 1.45 2000/11/16 12:02:24 achim
  139. * Changes for kernel 2.4
  140. *
  141. * Revision 1.44 2000/10/11 08:44:10 achim
  142. * Clustering changes: New flag media_changed added
  143. *
  144. * Revision 1.43 2000/09/20 12:59:01 achim
  145. * DPMEM remap functions for all PCI controller types implemented
  146. * Small changes for ia64 platform
  147. *
  148. * Revision 1.42 2000/07/20 09:04:50 achim
  149. * Small changes for kernel 2.4
  150. *
  151. * Revision 1.41 2000/07/04 14:11:11 achim
  152. * gdth_analyse_hdrive() added to rescan drives after online expansion
  153. *
  154. * Revision 1.40 2000/06/27 11:24:16 achim
  155. * Changes Clustering, Screenservice
  156. *
  157. * Revision 1.39 2000/06/15 13:09:04 achim
  158. * Changes for gdth_do_cmd()
  159. *
  160. * Revision 1.38 2000/06/15 12:08:43 achim
  161. * Bugfix gdth_sync_event(), service SCREENSERVICE
  162. * Data direction for command 0xc2 changed to DOU
  163. *
  164. * Revision 1.37 2000/05/25 13:50:10 achim
  165. * New driver parameter virt_ctr added
  166. *
  167. * Revision 1.36 2000/05/04 08:50:46 achim
  168. * Event buffer now in gdth_ha_str
  169. *
  170. * Revision 1.35 2000/03/03 10:44:08 achim
  171. * New event_string only valid for the RP controller family
  172. *
  173. * Revision 1.34 2000/03/02 14:55:29 achim
  174. * New mechanism for async. event handling implemented
  175. *
  176. * Revision 1.33 2000/02/21 15:37:37 achim
  177. * Bugfix Alpha platform + DPMEM above 4GB
  178. *
  179. * Revision 1.32 2000/02/14 16:17:37 achim
  180. * Bugfix sense_buffer[] + raw devices
  181. *
  182. * Revision 1.31 2000/02/10 10:29:00 achim
  183. * Delete sense_buffer[0], if command OK
  184. *
  185. * Revision 1.30 1999/11/02 13:42:39 achim
  186. * ARRAY_DRV_LIST2 implemented
  187. * Now 255 log. and 100 host drives supported
  188. *
  189. * Revision 1.29 1999/10/05 13:28:47 achim
  190. * GDT_CLUST_RESET added
  191. *
  192. * Revision 1.28 1999/08/12 13:44:54 achim
  193. * MOUNTALL removed
  194. * Cluster drives -> removeable drives
  195. *
  196. * Revision 1.27 1999/06/22 07:22:38 achim
  197. * Small changes
  198. *
  199. * Revision 1.26 1999/06/10 16:09:12 achim
  200. * Cluster Host Drive support: Bugfixes
  201. *
  202. * Revision 1.25 1999/06/01 16:03:56 achim
  203. * gdth_init_pci(): Manipulate config. space to start RP controller
  204. *
  205. * Revision 1.24 1999/05/26 11:53:06 achim
  206. * Cluster Host Drive support added
  207. *
  208. * Revision 1.23 1999/03/26 09:12:31 achim
  209. * Default value for hdr_channel set to 0
  210. *
  211. * Revision 1.22 1999/03/22 16:27:16 achim
  212. * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
  213. *
  214. * Revision 1.21 1999/03/16 13:40:34 achim
  215. * Problems with reserved drives solved
  216. * gdth_eh_bus_reset() implemented
  217. *
  218. * Revision 1.20 1999/03/10 09:08:13 achim
  219. * Bugfix: Corrections in gdth_direction_tab[] made
  220. * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
  221. *
  222. * Revision 1.19 1999/03/05 14:38:16 achim
  223. * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
  224. * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
  225. * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
  226. * with BIOS disabled and memory test set to Intensive
  227. * Enhanced /proc support
  228. *
  229. * Revision 1.18 1999/02/24 09:54:33 achim
  230. * Command line parameter hdr_channel implemented
  231. * Bugfix for EISA controllers + Linux 2.2.x
  232. *
  233. * Revision 1.17 1998/12/17 15:58:11 achim
  234. * Command line parameters implemented
  235. * Changes for Alpha platforms
  236. * PCI controller scan changed
  237. * SMP support improved (spin_lock_irqsave(),...)
  238. * New async. events, new scan/reserve commands included
  239. *
  240. * Revision 1.16 1998/09/28 16:08:46 achim
  241. * GDT_PCIMPR: DPMEM remapping, if required
  242. * mdelay() added
  243. *
  244. * Revision 1.15 1998/06/03 14:54:06 achim
  245. * gdth_delay(), gdth_flush() implemented
  246. * Bugfix: gdth_release() changed
  247. *
  248. * Revision 1.14 1998/05/22 10:01:17 achim
  249. * mj: pcibios_strerror() removed
  250. * Improved SMP support (if version >= 2.1.95)
  251. * gdth_halt(): halt_called flag added (if version < 2.1)
  252. *
  253. * Revision 1.13 1998/04/16 09:14:57 achim
  254. * Reserve drives (for raw service) implemented
  255. * New error handling code enabled
  256. * Get controller name from board_info() IOCTL
  257. * Final round of PCI device driver patches by Martin Mares
  258. *
  259. * Revision 1.12 1998/03/03 09:32:37 achim
  260. * Fibre channel controller support added
  261. *
  262. * Revision 1.11 1998/01/27 16:19:14 achim
  263. * SA_SHIRQ added
  264. * add_timer()/del_timer() instead of GDTH_TIMER
  265. * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
  266. * New error handling included
  267. *
  268. * Revision 1.10 1997/10/31 12:29:57 achim
  269. * Read heads/sectors from host drive
  270. *
  271. * Revision 1.9 1997/09/04 10:07:25 achim
  272. * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
  273. * register_reboot_notifier() to get a notify on shutown used
  274. *
  275. * Revision 1.8 1997/04/02 12:14:30 achim
  276. * Version 1.00 (see gdth.h), tested with kernel 2.0.29
  277. *
  278. * Revision 1.7 1997/03/12 13:33:37 achim
  279. * gdth_reset() changed, new async. events
  280. *
  281. * Revision 1.6 1997/03/04 14:01:11 achim
  282. * Shutdown routine gdth_halt() implemented
  283. *
  284. * Revision 1.5 1997/02/21 09:08:36 achim
  285. * New controller included (RP, RP1, RP2 series)
  286. * IOCTL interface implemented
  287. *
  288. * Revision 1.4 1996/07/05 12:48:55 achim
  289. * Function gdth_bios_param() implemented
  290. * New constant GDTH_MAXC_P_L inserted
  291. * GDT_WRITE_THR, GDT_EXT_INFO implemented
  292. * Function gdth_reset() changed
  293. *
  294. * Revision 1.3 1996/05/10 09:04:41 achim
  295. * Small changes for Linux 1.2.13
  296. *
  297. * Revision 1.2 1996/05/09 12:45:27 achim
  298. * Loadable module support implemented
  299. * /proc support corrections made
  300. *
  301. * Revision 1.1 1996/04/11 07:35:57 achim
  302. * Initial revision
  303. *
  304. ************************************************************************/
  305. /* All GDT Disk Array Controllers are fully supported by this driver.
  306. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  307. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  308. * list of all controller types.
  309. *
  310. * If you have one or more GDT3000/3020 EISA controllers with
  311. * controller BIOS disabled, you have to set the IRQ values with the
  312. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  313. * the IRQ values for the EISA controllers.
  314. *
  315. * After the optional list of IRQ values, other possible
  316. * command line options are:
  317. * disable:Y disable driver
  318. * disable:N enable driver
  319. * reserve_mode:0 reserve no drives for the raw service
  320. * reserve_mode:1 reserve all not init., removable drives
  321. * reserve_mode:2 reserve all not init. drives
  322. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  323. * h- controller no., b- channel no.,
  324. * t- target ID, l- LUN
  325. * reverse_scan:Y reverse scan order for PCI controllers
  326. * reverse_scan:N scan PCI controllers like BIOS
  327. * max_ids:x x - target ID count per channel (1..MAXID)
  328. * rescan:Y rescan all channels/IDs
  329. * rescan:N use all devices found until now
  330. * virt_ctr:Y map every channel to a virtual controller
  331. * virt_ctr:N use multi channel support
  332. * hdr_channel:x x - number of virtual bus for host drives
  333. * shared_access:Y disable driver reserve/release protocol to
  334. * access a shared resource from several nodes,
  335. * appropriate controller firmware required
  336. * shared_access:N enable driver reserve/release protocol
  337. * probe_eisa_isa:Y scan for EISA/ISA controllers
  338. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  339. * force_dma32:Y use only 32 bit DMA mode
  340. * force_dma32:N use 64 bit DMA mode, if supported
  341. *
  342. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  343. * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
  344. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  345. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  346. *
  347. * When loading the gdth driver as a module, the same options are available.
  348. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  349. * options changes slightly. You must replace all ',' between options
  350. * with ' ' and all ':' with '=' and you must use
  351. * '1' in place of 'Y' and '0' in place of 'N'.
  352. *
  353. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  354. * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
  355. * probe_eisa_isa=0 force_dma32=0"
  356. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  357. */
  358. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  359. * ptr: Chaining
  360. * this_residual: Command priority
  361. * buffer: phys. DMA sense buffer
  362. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  363. * buffers_residual: Timeout value
  364. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  365. * Message: Additional info (gdth_do_cmd()), DMA direction
  366. * have_data_in: Flag for gdth_wait_completion()
  367. * sent_command: Opcode special command
  368. * phase: Service/parameter/return code special command
  369. */
  370. /* interrupt coalescing */
  371. /* #define INT_COAL */
  372. /* statistics */
  373. #define GDTH_STATISTICS
  374. #include <linux/module.h>
  375. #include <linux/version.h>
  376. #include <linux/kernel.h>
  377. #include <linux/types.h>
  378. #include <linux/pci.h>
  379. #include <linux/string.h>
  380. #include <linux/ctype.h>
  381. #include <linux/ioport.h>
  382. #include <linux/delay.h>
  383. #include <linux/interrupt.h>
  384. #include <linux/in.h>
  385. #include <linux/proc_fs.h>
  386. #include <linux/time.h>
  387. #include <linux/timer.h>
  388. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
  389. #include <linux/dma-mapping.h>
  390. #else
  391. #define DMA_32BIT_MASK 0x00000000ffffffffULL
  392. #define DMA_64BIT_MASK 0xffffffffffffffffULL
  393. #endif
  394. #ifdef GDTH_RTC
  395. #include <linux/mc146818rtc.h>
  396. #endif
  397. #include <linux/reboot.h>
  398. #include <asm/dma.h>
  399. #include <asm/system.h>
  400. #include <asm/io.h>
  401. #include <asm/uaccess.h>
  402. #include <linux/spinlock.h>
  403. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  404. #include <linux/blkdev.h>
  405. #else
  406. #include <linux/blk.h>
  407. #include "sd.h"
  408. #endif
  409. #include "scsi.h"
  410. #include <scsi/scsi_host.h>
  411. #include "gdth_kcompat.h"
  412. #include "gdth.h"
  413. static void gdth_delay(int milliseconds);
  414. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  415. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  416. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
  417. static int gdth_async_event(int hanum);
  418. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  419. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
  420. static void gdth_next(int hanum);
  421. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
  422. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
  423. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  424. ushort idx, gdth_evt_data *evt);
  425. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  426. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  427. gdth_evt_str *estr);
  428. static void gdth_clear_events(void);
  429. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  430. char *buffer,ushort count);
  431. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
  432. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
  433. static int gdth_search_eisa(ushort eisa_adr);
  434. static int gdth_search_pci(gdth_pci_str *pcistr);
  435. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  436. ushort vendor, ushort dev);
  437. static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
  438. static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
  439. static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
  440. static void gdth_enable_int(int hanum);
  441. static int gdth_get_status(unchar *pIStatus,int irq);
  442. static int gdth_test_busy(int hanum);
  443. static int gdth_get_cmd_index(int hanum);
  444. static void gdth_release_event(int hanum);
  445. static int gdth_wait(int hanum,int index,ulong32 time);
  446. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  447. ulong64 p2,ulong64 p3);
  448. static int gdth_search_drives(int hanum);
  449. static int gdth_analyse_hdrive(int hanum, ushort hdrive);
  450. static const char *gdth_ctr_name(int hanum);
  451. static int gdth_open(struct inode *inode, struct file *filep);
  452. static int gdth_close(struct inode *inode, struct file *filep);
  453. static int gdth_ioctl(struct inode *inode, struct file *filep,
  454. unsigned int cmd, unsigned long arg);
  455. static void gdth_flush(int hanum);
  456. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  457. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  458. static void gdth_scsi_done(struct scsi_cmnd *scp);
  459. #ifdef CONFIG_ISA
  460. static int gdth_isa_probe_one(struct scsi_host_template *, ulong32);
  461. #endif
  462. #ifdef DEBUG_GDTH
  463. static unchar DebugState = DEBUG_GDTH;
  464. #ifdef __SERIAL__
  465. #define MAX_SERBUF 160
  466. static void ser_init(void);
  467. static void ser_puts(char *str);
  468. static void ser_putc(char c);
  469. static int ser_printk(const char *fmt, ...);
  470. static char strbuf[MAX_SERBUF+1];
  471. #ifdef __COM2__
  472. #define COM_BASE 0x2f8
  473. #else
  474. #define COM_BASE 0x3f8
  475. #endif
  476. static void ser_init()
  477. {
  478. unsigned port=COM_BASE;
  479. outb(0x80,port+3);
  480. outb(0,port+1);
  481. /* 19200 Baud, if 9600: outb(12,port) */
  482. outb(6, port);
  483. outb(3,port+3);
  484. outb(0,port+1);
  485. /*
  486. ser_putc('I');
  487. ser_putc(' ');
  488. */
  489. }
  490. static void ser_puts(char *str)
  491. {
  492. char *ptr;
  493. ser_init();
  494. for (ptr=str;*ptr;++ptr)
  495. ser_putc(*ptr);
  496. }
  497. static void ser_putc(char c)
  498. {
  499. unsigned port=COM_BASE;
  500. while ((inb(port+5) & 0x20)==0);
  501. outb(c,port);
  502. if (c==0x0a)
  503. {
  504. while ((inb(port+5) & 0x20)==0);
  505. outb(0x0d,port);
  506. }
  507. }
  508. static int ser_printk(const char *fmt, ...)
  509. {
  510. va_list args;
  511. int i;
  512. va_start(args,fmt);
  513. i = vsprintf(strbuf,fmt,args);
  514. ser_puts(strbuf);
  515. va_end(args);
  516. return i;
  517. }
  518. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  519. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  520. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  521. #else /* !__SERIAL__ */
  522. #define TRACE(a) {if (DebugState==1) {printk a;}}
  523. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  524. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  525. #endif
  526. #else /* !DEBUG */
  527. #define TRACE(a)
  528. #define TRACE2(a)
  529. #define TRACE3(a)
  530. #endif
  531. #ifdef GDTH_STATISTICS
  532. static ulong32 max_rq=0, max_index=0, max_sg=0;
  533. #ifdef INT_COAL
  534. static ulong32 max_int_coal=0;
  535. #endif
  536. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  537. static struct timer_list gdth_timer;
  538. #endif
  539. #define PTR2USHORT(a) (ushort)(ulong)(a)
  540. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  541. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  542. #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
  543. #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
  544. #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
  545. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  546. #define gdth_readb(addr) readb(addr)
  547. #define gdth_readw(addr) readw(addr)
  548. #define gdth_readl(addr) readl(addr)
  549. #define gdth_writeb(b,addr) writeb((b),(addr))
  550. #define gdth_writew(b,addr) writew((b),(addr))
  551. #define gdth_writel(b,addr) writel((b),(addr))
  552. #ifdef CONFIG_ISA
  553. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  554. #endif
  555. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  556. static unchar gdth_polling; /* polling if TRUE */
  557. static unchar gdth_from_wait = FALSE; /* gdth_wait() */
  558. static int wait_index,wait_hanum; /* gdth_wait() */
  559. static int gdth_ctr_count = 0; /* controller count */
  560. static int gdth_ctr_vcount = 0; /* virt. ctr. count */
  561. static int gdth_ctr_released = 0; /* gdth_release() */
  562. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  563. static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
  564. static unchar gdth_write_through = FALSE; /* write through */
  565. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  566. static int elastidx;
  567. static int eoldidx;
  568. static int major;
  569. #define DIN 1 /* IN data direction */
  570. #define DOU 2 /* OUT data direction */
  571. #define DNO DIN /* no data transfer */
  572. #define DUN DIN /* unknown data direction */
  573. static unchar gdth_direction_tab[0x100] = {
  574. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  575. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  576. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  577. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  578. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  579. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  580. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  581. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  582. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  583. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  584. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  585. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  586. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  587. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  588. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  589. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  590. };
  591. /* LILO and modprobe/insmod parameters */
  592. /* IRQ list for GDT3000/3020 EISA controllers */
  593. static int irq[MAXHA] __initdata =
  594. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  595. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  596. /* disable driver flag */
  597. static int disable __initdata = 0;
  598. /* reserve flag */
  599. static int reserve_mode = 1;
  600. /* reserve list */
  601. static int reserve_list[MAX_RES_ARGS] =
  602. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  603. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  604. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  605. /* scan order for PCI controllers */
  606. static int reverse_scan = 0;
  607. /* virtual channel for the host drives */
  608. static int hdr_channel = 0;
  609. /* max. IDs per channel */
  610. static int max_ids = MAXID;
  611. /* rescan all IDs */
  612. static int rescan = 0;
  613. /* map channels to virtual controllers */
  614. static int virt_ctr = 0;
  615. /* shared access */
  616. static int shared_access = 1;
  617. /* enable support for EISA and ISA controllers */
  618. static int probe_eisa_isa = 0;
  619. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  620. static int force_dma32 = 0;
  621. /* parameters for modprobe/insmod */
  622. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
  623. module_param_array(irq, int, NULL, 0);
  624. module_param(disable, int, 0);
  625. module_param(reserve_mode, int, 0);
  626. module_param_array(reserve_list, int, NULL, 0);
  627. module_param(reverse_scan, int, 0);
  628. module_param(hdr_channel, int, 0);
  629. module_param(max_ids, int, 0);
  630. module_param(rescan, int, 0);
  631. module_param(virt_ctr, int, 0);
  632. module_param(shared_access, int, 0);
  633. module_param(probe_eisa_isa, int, 0);
  634. module_param(force_dma32, int, 0);
  635. #else
  636. MODULE_PARM(irq, "i");
  637. MODULE_PARM(disable, "i");
  638. MODULE_PARM(reserve_mode, "i");
  639. MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
  640. MODULE_PARM(reverse_scan, "i");
  641. MODULE_PARM(hdr_channel, "i");
  642. MODULE_PARM(max_ids, "i");
  643. MODULE_PARM(rescan, "i");
  644. MODULE_PARM(virt_ctr, "i");
  645. MODULE_PARM(shared_access, "i");
  646. MODULE_PARM(probe_eisa_isa, "i");
  647. MODULE_PARM(force_dma32, "i");
  648. #endif
  649. MODULE_AUTHOR("Achim Leubner");
  650. MODULE_LICENSE("GPL");
  651. /* ioctl interface */
  652. static const struct file_operations gdth_fops = {
  653. .ioctl = gdth_ioctl,
  654. .open = gdth_open,
  655. .release = gdth_close,
  656. };
  657. #define GDTH_MAGIC 0xc2e7c389 /* I got it from /dev/urandom */
  658. #define IS_GDTH_INTERNAL_CMD(scp) (scp->underflow == GDTH_MAGIC)
  659. #include "gdth_proc.h"
  660. #include "gdth_proc.c"
  661. /* notifier block to get a notify on system shutdown/halt/reboot */
  662. static struct notifier_block gdth_notifier = {
  663. gdth_halt, NULL, 0
  664. };
  665. static int notifier_disabled = 0;
  666. static void gdth_delay(int milliseconds)
  667. {
  668. if (milliseconds == 0) {
  669. udelay(1);
  670. } else {
  671. mdelay(milliseconds);
  672. }
  673. }
  674. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  675. static void gdth_scsi_done(struct scsi_cmnd *scp)
  676. {
  677. TRACE2(("gdth_scsi_done()\n"));
  678. if (IS_GDTH_INTERNAL_CMD(scp))
  679. complete((struct completion *)scp->request);
  680. else
  681. scp->scsi_done(scp);
  682. }
  683. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  684. int timeout, u32 *info)
  685. {
  686. Scsi_Cmnd *scp;
  687. DECLARE_COMPLETION_ONSTACK(wait);
  688. int rval;
  689. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  690. if (!scp)
  691. return -ENOMEM;
  692. scp->device = sdev;
  693. /* use request field to save the ptr. to completion struct. */
  694. scp->request = (struct request *)&wait;
  695. scp->timeout_per_command = timeout*HZ;
  696. scp->request_buffer = gdtcmd;
  697. scp->cmd_len = 12;
  698. memcpy(scp->cmnd, cmnd, 12);
  699. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  700. scp->underflow = GDTH_MAGIC;
  701. gdth_queuecommand(scp, NULL);
  702. wait_for_completion(&wait);
  703. rval = scp->SCp.Status;
  704. if (info)
  705. *info = scp->SCp.Message;
  706. kfree(scp);
  707. return rval;
  708. }
  709. #else
  710. static void gdth_scsi_done(Scsi_Cmnd *scp)
  711. {
  712. TRACE2(("gdth_scsi_done()\n"));
  713. scp->request.rq_status = RQ_SCSI_DONE;
  714. if (scp->request.waiting)
  715. complete(scp->request.waiting);
  716. }
  717. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  718. int timeout, u32 *info)
  719. {
  720. Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
  721. unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
  722. DECLARE_COMPLETION_ONSTACK(wait);
  723. int rval;
  724. if (!scp)
  725. return -ENOMEM;
  726. scp->cmd_len = 12;
  727. scp->use_sg = 0;
  728. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  729. scp->request.rq_status = RQ_SCSI_BUSY;
  730. scp->request.waiting = &wait;
  731. scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
  732. wait_for_completion(&wait);
  733. rval = scp->SCp.Status;
  734. if (info)
  735. *info = scp->SCp.Message;
  736. scsi_release_command(scp);
  737. return rval;
  738. }
  739. #endif
  740. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  741. int timeout, u32 *info)
  742. {
  743. struct scsi_device *sdev = scsi_get_host_dev(shost);
  744. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  745. scsi_free_host_dev(sdev);
  746. return rval;
  747. }
  748. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  749. {
  750. *cyls = size /HEADS/SECS;
  751. if (*cyls <= MAXCYLS) {
  752. *heads = HEADS;
  753. *secs = SECS;
  754. } else { /* too high for 64*32 */
  755. *cyls = size /MEDHEADS/MEDSECS;
  756. if (*cyls <= MAXCYLS) {
  757. *heads = MEDHEADS;
  758. *secs = MEDSECS;
  759. } else { /* too high for 127*63 */
  760. *cyls = size /BIGHEADS/BIGSECS;
  761. *heads = BIGHEADS;
  762. *secs = BIGSECS;
  763. }
  764. }
  765. }
  766. /* controller search and initialization functions */
  767. static int __init gdth_search_eisa(ushort eisa_adr)
  768. {
  769. ulong32 id;
  770. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  771. id = inl(eisa_adr+ID0REG);
  772. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  773. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  774. return 0; /* not EISA configured */
  775. return 1;
  776. }
  777. if (id == GDT3_ID) /* GDT3000 */
  778. return 1;
  779. return 0;
  780. }
  781. #ifdef CONFIG_ISA
  782. static int __init gdth_search_isa(ulong32 bios_adr)
  783. {
  784. void __iomem *addr;
  785. ulong32 id;
  786. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  787. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  788. id = gdth_readl(addr);
  789. iounmap(addr);
  790. if (id == GDT2_ID) /* GDT2000 */
  791. return 1;
  792. }
  793. return 0;
  794. }
  795. #endif /* CONFIG_ISA */
  796. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  797. {
  798. ushort device, cnt;
  799. TRACE(("gdth_search_pci()\n"));
  800. cnt = 0;
  801. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  802. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  803. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  804. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  805. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  806. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  807. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  808. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  809. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  810. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  811. PCI_DEVICE_ID_INTEL_SRC);
  812. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  813. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  814. return cnt;
  815. }
  816. /* Vortex only makes RAID controllers.
  817. * We do not really want to specify all 550 ids here, so wildcard match.
  818. */
  819. static struct pci_device_id gdthtable[] __maybe_unused = {
  820. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  821. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  822. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  823. {0}
  824. };
  825. MODULE_DEVICE_TABLE(pci,gdthtable);
  826. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  827. ushort vendor, ushort device)
  828. {
  829. ulong base0, base1, base2;
  830. struct pci_dev *pdev;
  831. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  832. *cnt, vendor, device));
  833. pdev = NULL;
  834. while ((pdev = pci_find_device(vendor, device, pdev))
  835. != NULL) {
  836. if (pci_enable_device(pdev))
  837. continue;
  838. if (*cnt >= MAXHA)
  839. return;
  840. /* GDT PCI controller found, resources are already in pdev */
  841. pcistr[*cnt].pdev = pdev;
  842. pcistr[*cnt].irq = pdev->irq;
  843. base0 = pci_resource_flags(pdev, 0);
  844. base1 = pci_resource_flags(pdev, 1);
  845. base2 = pci_resource_flags(pdev, 2);
  846. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  847. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  848. if (!(base0 & IORESOURCE_MEM))
  849. continue;
  850. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  851. } else { /* GDT6110, GDT6120, .. */
  852. if (!(base0 & IORESOURCE_MEM) ||
  853. !(base2 & IORESOURCE_MEM) ||
  854. !(base1 & IORESOURCE_IO))
  855. continue;
  856. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  857. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  858. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  859. }
  860. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  861. pcistr[*cnt].pdev->bus->number,
  862. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  863. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  864. (*cnt)++;
  865. }
  866. }
  867. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  868. {
  869. gdth_pci_str temp;
  870. int i, changed;
  871. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  872. if (cnt == 0)
  873. return;
  874. do {
  875. changed = FALSE;
  876. for (i = 0; i < cnt-1; ++i) {
  877. if (!reverse_scan) {
  878. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  879. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  880. PCI_SLOT(pcistr[i].pdev->devfn) >
  881. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  882. temp = pcistr[i];
  883. pcistr[i] = pcistr[i+1];
  884. pcistr[i+1] = temp;
  885. changed = TRUE;
  886. }
  887. } else {
  888. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  889. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  890. PCI_SLOT(pcistr[i].pdev->devfn) <
  891. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  892. temp = pcistr[i];
  893. pcistr[i] = pcistr[i+1];
  894. pcistr[i+1] = temp;
  895. changed = TRUE;
  896. }
  897. }
  898. }
  899. } while (changed);
  900. }
  901. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  902. {
  903. ulong32 retries,id;
  904. unchar prot_ver,eisacf,i,irq_found;
  905. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  906. /* disable board interrupts, deinitialize services */
  907. outb(0xff,eisa_adr+EDOORREG);
  908. outb(0x00,eisa_adr+EDENABREG);
  909. outb(0x00,eisa_adr+EINTENABREG);
  910. outb(0xff,eisa_adr+LDOORREG);
  911. retries = INIT_RETRIES;
  912. gdth_delay(20);
  913. while (inb(eisa_adr+EDOORREG) != 0xff) {
  914. if (--retries == 0) {
  915. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  916. return 0;
  917. }
  918. gdth_delay(1);
  919. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  920. }
  921. prot_ver = inb(eisa_adr+MAILBOXREG);
  922. outb(0xff,eisa_adr+EDOORREG);
  923. if (prot_ver != PROTOCOL_VERSION) {
  924. printk("GDT-EISA: Illegal protocol version\n");
  925. return 0;
  926. }
  927. ha->bmic = eisa_adr;
  928. ha->brd_phys = (ulong32)eisa_adr >> 12;
  929. outl(0,eisa_adr+MAILBOXREG);
  930. outl(0,eisa_adr+MAILBOXREG+4);
  931. outl(0,eisa_adr+MAILBOXREG+8);
  932. outl(0,eisa_adr+MAILBOXREG+12);
  933. /* detect IRQ */
  934. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  935. ha->oem_id = OEM_ID_ICP;
  936. ha->type = GDT_EISA;
  937. ha->stype = id;
  938. outl(1,eisa_adr+MAILBOXREG+8);
  939. outb(0xfe,eisa_adr+LDOORREG);
  940. retries = INIT_RETRIES;
  941. gdth_delay(20);
  942. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  943. if (--retries == 0) {
  944. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  945. return 0;
  946. }
  947. gdth_delay(1);
  948. }
  949. ha->irq = inb(eisa_adr+MAILBOXREG);
  950. outb(0xff,eisa_adr+EDOORREG);
  951. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  952. /* check the result */
  953. if (ha->irq == 0) {
  954. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  955. for (i = 0, irq_found = FALSE;
  956. i < MAXHA && irq[i] != 0xff; ++i) {
  957. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  958. irq_found = TRUE;
  959. break;
  960. }
  961. }
  962. if (irq_found) {
  963. ha->irq = irq[i];
  964. irq[i] = 0;
  965. printk("GDT-EISA: Can not detect controller IRQ,\n");
  966. printk("Use IRQ setting from command line (IRQ = %d)\n",
  967. ha->irq);
  968. } else {
  969. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  970. printk("the controller BIOS or use command line parameters\n");
  971. return 0;
  972. }
  973. }
  974. } else {
  975. eisacf = inb(eisa_adr+EISAREG) & 7;
  976. if (eisacf > 4) /* level triggered */
  977. eisacf -= 4;
  978. ha->irq = gdth_irq_tab[eisacf];
  979. ha->oem_id = OEM_ID_ICP;
  980. ha->type = GDT_EISA;
  981. ha->stype = id;
  982. }
  983. ha->dma64_support = 0;
  984. return 1;
  985. }
  986. #ifdef CONFIG_ISA
  987. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  988. {
  989. register gdt2_dpram_str __iomem *dp2_ptr;
  990. int i;
  991. unchar irq_drq,prot_ver;
  992. ulong32 retries;
  993. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  994. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  995. if (ha->brd == NULL) {
  996. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  997. return 0;
  998. }
  999. dp2_ptr = ha->brd;
  1000. gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  1001. /* reset interface area */
  1002. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  1003. if (gdth_readl(&dp2_ptr->u) != 0) {
  1004. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  1005. iounmap(ha->brd);
  1006. return 0;
  1007. }
  1008. /* disable board interrupts, read DRQ and IRQ */
  1009. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1010. gdth_writeb(0x00, &dp2_ptr->io.irqen);
  1011. gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
  1012. gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  1013. irq_drq = gdth_readb(&dp2_ptr->io.rq);
  1014. for (i=0; i<3; ++i) {
  1015. if ((irq_drq & 1)==0)
  1016. break;
  1017. irq_drq >>= 1;
  1018. }
  1019. ha->drq = gdth_drq_tab[i];
  1020. irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
  1021. for (i=1; i<5; ++i) {
  1022. if ((irq_drq & 1)==0)
  1023. break;
  1024. irq_drq >>= 1;
  1025. }
  1026. ha->irq = gdth_irq_tab[i];
  1027. /* deinitialize services */
  1028. gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  1029. gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  1030. gdth_writeb(0, &dp2_ptr->io.event);
  1031. retries = INIT_RETRIES;
  1032. gdth_delay(20);
  1033. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  1034. if (--retries == 0) {
  1035. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  1036. iounmap(ha->brd);
  1037. return 0;
  1038. }
  1039. gdth_delay(1);
  1040. }
  1041. prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
  1042. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1043. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1044. if (prot_ver != PROTOCOL_VERSION) {
  1045. printk("GDT-ISA: Illegal protocol version\n");
  1046. iounmap(ha->brd);
  1047. return 0;
  1048. }
  1049. ha->oem_id = OEM_ID_ICP;
  1050. ha->type = GDT_ISA;
  1051. ha->ic_all_size = sizeof(dp2_ptr->u);
  1052. ha->stype= GDT2_ID;
  1053. ha->brd_phys = bios_adr >> 4;
  1054. /* special request to controller BIOS */
  1055. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  1056. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  1057. gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  1058. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  1059. gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  1060. gdth_writeb(0, &dp2_ptr->io.event);
  1061. retries = INIT_RETRIES;
  1062. gdth_delay(20);
  1063. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  1064. if (--retries == 0) {
  1065. printk("GDT-ISA: Initialization error\n");
  1066. iounmap(ha->brd);
  1067. return 0;
  1068. }
  1069. gdth_delay(1);
  1070. }
  1071. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1072. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1073. ha->dma64_support = 0;
  1074. return 1;
  1075. }
  1076. #endif /* CONFIG_ISA */
  1077. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  1078. {
  1079. register gdt6_dpram_str __iomem *dp6_ptr;
  1080. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1081. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1082. ulong32 retries;
  1083. unchar prot_ver;
  1084. ushort command;
  1085. int i, found = FALSE;
  1086. TRACE(("gdth_init_pci()\n"));
  1087. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  1088. ha->oem_id = OEM_ID_INTEL;
  1089. else
  1090. ha->oem_id = OEM_ID_ICP;
  1091. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  1092. ha->stype = (ulong32)pcistr->pdev->device;
  1093. ha->irq = pcistr->irq;
  1094. ha->pdev = pcistr->pdev;
  1095. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  1096. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1097. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  1098. if (ha->brd == NULL) {
  1099. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1100. return 0;
  1101. }
  1102. /* check and reset interface area */
  1103. dp6_ptr = ha->brd;
  1104. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1105. if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  1106. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1107. pcistr->dpmem);
  1108. found = FALSE;
  1109. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1110. iounmap(ha->brd);
  1111. ha->brd = ioremap(i, sizeof(ushort));
  1112. if (ha->brd == NULL) {
  1113. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1114. return 0;
  1115. }
  1116. if (gdth_readw(ha->brd) != 0xffff) {
  1117. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  1118. continue;
  1119. }
  1120. iounmap(ha->brd);
  1121. pci_write_config_dword(pcistr->pdev,
  1122. PCI_BASE_ADDRESS_0, i);
  1123. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  1124. if (ha->brd == NULL) {
  1125. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1126. return 0;
  1127. }
  1128. dp6_ptr = ha->brd;
  1129. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1130. if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  1131. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1132. found = TRUE;
  1133. break;
  1134. }
  1135. }
  1136. if (!found) {
  1137. printk("GDT-PCI: No free address found!\n");
  1138. iounmap(ha->brd);
  1139. return 0;
  1140. }
  1141. }
  1142. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  1143. if (gdth_readl(&dp6_ptr->u) != 0) {
  1144. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1145. iounmap(ha->brd);
  1146. return 0;
  1147. }
  1148. /* disable board interrupts, deinit services */
  1149. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1150. gdth_writeb(0x00, &dp6_ptr->io.irqen);
  1151. gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
  1152. gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  1153. gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  1154. gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  1155. gdth_writeb(0, &dp6_ptr->io.event);
  1156. retries = INIT_RETRIES;
  1157. gdth_delay(20);
  1158. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  1159. if (--retries == 0) {
  1160. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1161. iounmap(ha->brd);
  1162. return 0;
  1163. }
  1164. gdth_delay(1);
  1165. }
  1166. prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
  1167. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1168. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1169. if (prot_ver != PROTOCOL_VERSION) {
  1170. printk("GDT-PCI: Illegal protocol version\n");
  1171. iounmap(ha->brd);
  1172. return 0;
  1173. }
  1174. ha->type = GDT_PCI;
  1175. ha->ic_all_size = sizeof(dp6_ptr->u);
  1176. /* special command to controller BIOS */
  1177. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  1178. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  1179. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  1180. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  1181. gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  1182. gdth_writeb(0, &dp6_ptr->io.event);
  1183. retries = INIT_RETRIES;
  1184. gdth_delay(20);
  1185. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  1186. if (--retries == 0) {
  1187. printk("GDT-PCI: Initialization error\n");
  1188. iounmap(ha->brd);
  1189. return 0;
  1190. }
  1191. gdth_delay(1);
  1192. }
  1193. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1194. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1195. ha->dma64_support = 0;
  1196. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  1197. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  1198. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  1199. pcistr->dpmem,ha->irq));
  1200. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  1201. if (ha->brd == NULL) {
  1202. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1203. iounmap(ha->brd);
  1204. return 0;
  1205. }
  1206. /* check and reset interface area */
  1207. dp6c_ptr = ha->brd;
  1208. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1209. if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  1210. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1211. pcistr->dpmem);
  1212. found = FALSE;
  1213. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1214. iounmap(ha->brd);
  1215. ha->brd = ioremap(i, sizeof(ushort));
  1216. if (ha->brd == NULL) {
  1217. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1218. return 0;
  1219. }
  1220. if (gdth_readw(ha->brd) != 0xffff) {
  1221. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  1222. continue;
  1223. }
  1224. iounmap(ha->brd);
  1225. pci_write_config_dword(pcistr->pdev,
  1226. PCI_BASE_ADDRESS_2, i);
  1227. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  1228. if (ha->brd == NULL) {
  1229. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1230. return 0;
  1231. }
  1232. dp6c_ptr = ha->brd;
  1233. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1234. if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  1235. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1236. found = TRUE;
  1237. break;
  1238. }
  1239. }
  1240. if (!found) {
  1241. printk("GDT-PCI: No free address found!\n");
  1242. iounmap(ha->brd);
  1243. return 0;
  1244. }
  1245. }
  1246. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  1247. if (gdth_readl(&dp6c_ptr->u) != 0) {
  1248. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1249. iounmap(ha->brd);
  1250. return 0;
  1251. }
  1252. /* disable board interrupts, deinit services */
  1253. outb(0x00,PTR2USHORT(&ha->plx->control1));
  1254. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  1255. gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  1256. gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  1257. gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  1258. gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1259. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1260. retries = INIT_RETRIES;
  1261. gdth_delay(20);
  1262. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  1263. if (--retries == 0) {
  1264. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1265. iounmap(ha->brd);
  1266. return 0;
  1267. }
  1268. gdth_delay(1);
  1269. }
  1270. prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
  1271. gdth_writeb(0, &dp6c_ptr->u.ic.Status);
  1272. if (prot_ver != PROTOCOL_VERSION) {
  1273. printk("GDT-PCI: Illegal protocol version\n");
  1274. iounmap(ha->brd);
  1275. return 0;
  1276. }
  1277. ha->type = GDT_PCINEW;
  1278. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1279. /* special command to controller BIOS */
  1280. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1281. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1282. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1283. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1284. gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1285. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1286. retries = INIT_RETRIES;
  1287. gdth_delay(20);
  1288. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1289. if (--retries == 0) {
  1290. printk("GDT-PCI: Initialization error\n");
  1291. iounmap(ha->brd);
  1292. return 0;
  1293. }
  1294. gdth_delay(1);
  1295. }
  1296. gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
  1297. ha->dma64_support = 0;
  1298. } else { /* MPR */
  1299. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1300. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1301. if (ha->brd == NULL) {
  1302. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1303. return 0;
  1304. }
  1305. /* manipulate config. space to enable DPMEM, start RP controller */
  1306. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1307. command |= 6;
  1308. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1309. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1310. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1311. i = 0xFEFF0001UL;
  1312. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1313. gdth_delay(1);
  1314. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1315. pci_resource_start(pcistr->pdev, 8));
  1316. dp6m_ptr = ha->brd;
  1317. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1318. * Aditional check needed for Xscale based RAID controllers */
  1319. while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1320. gdth_delay(1);
  1321. /* check and reset interface area */
  1322. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1323. if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1324. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1325. pcistr->dpmem);
  1326. found = FALSE;
  1327. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1328. iounmap(ha->brd);
  1329. ha->brd = ioremap(i, sizeof(ushort));
  1330. if (ha->brd == NULL) {
  1331. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1332. return 0;
  1333. }
  1334. if (gdth_readw(ha->brd) != 0xffff) {
  1335. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1336. continue;
  1337. }
  1338. iounmap(ha->brd);
  1339. pci_write_config_dword(pcistr->pdev,
  1340. PCI_BASE_ADDRESS_0, i);
  1341. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1342. if (ha->brd == NULL) {
  1343. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1344. return 0;
  1345. }
  1346. dp6m_ptr = ha->brd;
  1347. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1348. if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1349. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1350. found = TRUE;
  1351. break;
  1352. }
  1353. }
  1354. if (!found) {
  1355. printk("GDT-PCI: No free address found!\n");
  1356. iounmap(ha->brd);
  1357. return 0;
  1358. }
  1359. }
  1360. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1361. /* disable board interrupts, deinit services */
  1362. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1363. &dp6m_ptr->i960r.edoor_en_reg);
  1364. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1365. gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1366. gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1367. gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1368. gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1369. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1370. retries = INIT_RETRIES;
  1371. gdth_delay(20);
  1372. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1373. if (--retries == 0) {
  1374. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1375. iounmap(ha->brd);
  1376. return 0;
  1377. }
  1378. gdth_delay(1);
  1379. }
  1380. prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
  1381. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1382. if (prot_ver != PROTOCOL_VERSION) {
  1383. printk("GDT-PCI: Illegal protocol version\n");
  1384. iounmap(ha->brd);
  1385. return 0;
  1386. }
  1387. ha->type = GDT_PCIMPR;
  1388. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1389. /* special command to controller BIOS */
  1390. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1391. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1392. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1393. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1394. gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1395. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1396. retries = INIT_RETRIES;
  1397. gdth_delay(20);
  1398. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1399. if (--retries == 0) {
  1400. printk("GDT-PCI: Initialization error\n");
  1401. iounmap(ha->brd);
  1402. return 0;
  1403. }
  1404. gdth_delay(1);
  1405. }
  1406. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1407. /* read FW version to detect 64-bit DMA support */
  1408. gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1409. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1410. retries = INIT_RETRIES;
  1411. gdth_delay(20);
  1412. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1413. if (--retries == 0) {
  1414. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1415. iounmap(ha->brd);
  1416. return 0;
  1417. }
  1418. gdth_delay(1);
  1419. }
  1420. prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1421. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1422. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1423. ha->dma64_support = 0;
  1424. else
  1425. ha->dma64_support = 1;
  1426. }
  1427. return 1;
  1428. }
  1429. /* controller protocol functions */
  1430. static void __init gdth_enable_int(int hanum)
  1431. {
  1432. gdth_ha_str *ha;
  1433. ulong flags;
  1434. gdt2_dpram_str __iomem *dp2_ptr;
  1435. gdt6_dpram_str __iomem *dp6_ptr;
  1436. gdt6m_dpram_str __iomem *dp6m_ptr;
  1437. TRACE(("gdth_enable_int() hanum %d\n",hanum));
  1438. ha = HADATA(gdth_ctr_tab[hanum]);
  1439. spin_lock_irqsave(&ha->smp_lock, flags);
  1440. if (ha->type == GDT_EISA) {
  1441. outb(0xff, ha->bmic + EDOORREG);
  1442. outb(0xff, ha->bmic + EDENABREG);
  1443. outb(0x01, ha->bmic + EINTENABREG);
  1444. } else if (ha->type == GDT_ISA) {
  1445. dp2_ptr = ha->brd;
  1446. gdth_writeb(1, &dp2_ptr->io.irqdel);
  1447. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1448. gdth_writeb(1, &dp2_ptr->io.irqen);
  1449. } else if (ha->type == GDT_PCI) {
  1450. dp6_ptr = ha->brd;
  1451. gdth_writeb(1, &dp6_ptr->io.irqdel);
  1452. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1453. gdth_writeb(1, &dp6_ptr->io.irqen);
  1454. } else if (ha->type == GDT_PCINEW) {
  1455. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1456. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1457. } else if (ha->type == GDT_PCIMPR) {
  1458. dp6m_ptr = ha->brd;
  1459. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1460. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1461. &dp6m_ptr->i960r.edoor_en_reg);
  1462. }
  1463. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1464. }
  1465. static int gdth_get_status(unchar *pIStatus,int irq)
  1466. {
  1467. register gdth_ha_str *ha;
  1468. int i;
  1469. TRACE(("gdth_get_status() irq %d ctr_count %d\n",
  1470. irq,gdth_ctr_count));
  1471. *pIStatus = 0;
  1472. for (i=0; i<gdth_ctr_count; ++i) {
  1473. ha = HADATA(gdth_ctr_tab[i]);
  1474. if (ha->irq != (unchar)irq) /* check IRQ */
  1475. continue;
  1476. if (ha->type == GDT_EISA)
  1477. *pIStatus = inb((ushort)ha->bmic + EDOORREG);
  1478. else if (ha->type == GDT_ISA)
  1479. *pIStatus =
  1480. gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1481. else if (ha->type == GDT_PCI)
  1482. *pIStatus =
  1483. gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1484. else if (ha->type == GDT_PCINEW)
  1485. *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1486. else if (ha->type == GDT_PCIMPR)
  1487. *pIStatus =
  1488. gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1489. if (*pIStatus)
  1490. return i; /* board found */
  1491. }
  1492. return -1;
  1493. }
  1494. static int gdth_test_busy(int hanum)
  1495. {
  1496. register gdth_ha_str *ha;
  1497. register int gdtsema0 = 0;
  1498. TRACE(("gdth_test_busy() hanum %d\n",hanum));
  1499. ha = HADATA(gdth_ctr_tab[hanum]);
  1500. if (ha->type == GDT_EISA)
  1501. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1502. else if (ha->type == GDT_ISA)
  1503. gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1504. else if (ha->type == GDT_PCI)
  1505. gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1506. else if (ha->type == GDT_PCINEW)
  1507. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1508. else if (ha->type == GDT_PCIMPR)
  1509. gdtsema0 =
  1510. (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1511. return (gdtsema0 & 1);
  1512. }
  1513. static int gdth_get_cmd_index(int hanum)
  1514. {
  1515. register gdth_ha_str *ha;
  1516. int i;
  1517. TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
  1518. ha = HADATA(gdth_ctr_tab[hanum]);
  1519. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1520. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1521. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1522. ha->cmd_tab[i].service = ha->pccb->Service;
  1523. ha->pccb->CommandIndex = (ulong32)i+2;
  1524. return (i+2);
  1525. }
  1526. }
  1527. return 0;
  1528. }
  1529. static void gdth_set_sema0(int hanum)
  1530. {
  1531. register gdth_ha_str *ha;
  1532. TRACE(("gdth_set_sema0() hanum %d\n",hanum));
  1533. ha = HADATA(gdth_ctr_tab[hanum]);
  1534. if (ha->type == GDT_EISA) {
  1535. outb(1, ha->bmic + SEMA0REG);
  1536. } else if (ha->type == GDT_ISA) {
  1537. gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1538. } else if (ha->type == GDT_PCI) {
  1539. gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1540. } else if (ha->type == GDT_PCINEW) {
  1541. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1542. } else if (ha->type == GDT_PCIMPR) {
  1543. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1544. }
  1545. }
  1546. static void gdth_copy_command(int hanum)
  1547. {
  1548. register gdth_ha_str *ha;
  1549. register gdth_cmd_str *cmd_ptr;
  1550. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1551. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1552. gdt6_dpram_str __iomem *dp6_ptr;
  1553. gdt2_dpram_str __iomem *dp2_ptr;
  1554. ushort cp_count,dp_offset,cmd_no;
  1555. TRACE(("gdth_copy_command() hanum %d\n",hanum));
  1556. ha = HADATA(gdth_ctr_tab[hanum]);
  1557. cp_count = ha->cmd_len;
  1558. dp_offset= ha->cmd_offs_dpmem;
  1559. cmd_no = ha->cmd_cnt;
  1560. cmd_ptr = ha->pccb;
  1561. ++ha->cmd_cnt;
  1562. if (ha->type == GDT_EISA)
  1563. return; /* no DPMEM, no copy */
  1564. /* set cpcount dword aligned */
  1565. if (cp_count & 3)
  1566. cp_count += (4 - (cp_count & 3));
  1567. ha->cmd_offs_dpmem += cp_count;
  1568. /* set offset and service, copy command to DPMEM */
  1569. if (ha->type == GDT_ISA) {
  1570. dp2_ptr = ha->brd;
  1571. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1572. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1573. gdth_writew((ushort)cmd_ptr->Service,
  1574. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1575. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1576. } else if (ha->type == GDT_PCI) {
  1577. dp6_ptr = ha->brd;
  1578. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1579. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1580. gdth_writew((ushort)cmd_ptr->Service,
  1581. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1582. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1583. } else if (ha->type == GDT_PCINEW) {
  1584. dp6c_ptr = ha->brd;
  1585. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1586. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1587. gdth_writew((ushort)cmd_ptr->Service,
  1588. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1589. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1590. } else if (ha->type == GDT_PCIMPR) {
  1591. dp6m_ptr = ha->brd;
  1592. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1593. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1594. gdth_writew((ushort)cmd_ptr->Service,
  1595. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1596. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1597. }
  1598. }
  1599. static void gdth_release_event(int hanum)
  1600. {
  1601. register gdth_ha_str *ha;
  1602. TRACE(("gdth_release_event() hanum %d\n",hanum));
  1603. ha = HADATA(gdth_ctr_tab[hanum]);
  1604. #ifdef GDTH_STATISTICS
  1605. {
  1606. ulong32 i,j;
  1607. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1608. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1609. ++i;
  1610. }
  1611. if (max_index < i) {
  1612. max_index = i;
  1613. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1614. }
  1615. }
  1616. #endif
  1617. if (ha->pccb->OpCode == GDT_INIT)
  1618. ha->pccb->Service |= 0x80;
  1619. if (ha->type == GDT_EISA) {
  1620. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1621. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1622. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1623. } else if (ha->type == GDT_ISA) {
  1624. gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1625. } else if (ha->type == GDT_PCI) {
  1626. gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1627. } else if (ha->type == GDT_PCINEW) {
  1628. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1629. } else if (ha->type == GDT_PCIMPR) {
  1630. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1631. }
  1632. }
  1633. static int gdth_wait(int hanum,int index,ulong32 time)
  1634. {
  1635. gdth_ha_str *ha;
  1636. int answer_found = FALSE;
  1637. TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
  1638. ha = HADATA(gdth_ctr_tab[hanum]);
  1639. if (index == 0)
  1640. return 1; /* no wait required */
  1641. gdth_from_wait = TRUE;
  1642. do {
  1643. gdth_interrupt((int)ha->irq,ha);
  1644. if (wait_hanum==hanum && wait_index==index) {
  1645. answer_found = TRUE;
  1646. break;
  1647. }
  1648. gdth_delay(1);
  1649. } while (--time);
  1650. gdth_from_wait = FALSE;
  1651. while (gdth_test_busy(hanum))
  1652. gdth_delay(0);
  1653. return (answer_found);
  1654. }
  1655. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  1656. ulong64 p2,ulong64 p3)
  1657. {
  1658. register gdth_ha_str *ha;
  1659. register gdth_cmd_str *cmd_ptr;
  1660. int retries,index;
  1661. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1662. ha = HADATA(gdth_ctr_tab[hanum]);
  1663. cmd_ptr = ha->pccb;
  1664. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1665. /* make command */
  1666. for (retries = INIT_RETRIES;;) {
  1667. cmd_ptr->Service = service;
  1668. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1669. if (!(index=gdth_get_cmd_index(hanum))) {
  1670. TRACE(("GDT: No free command index found\n"));
  1671. return 0;
  1672. }
  1673. gdth_set_sema0(hanum);
  1674. cmd_ptr->OpCode = opcode;
  1675. cmd_ptr->BoardNode = LOCALBOARD;
  1676. if (service == CACHESERVICE) {
  1677. if (opcode == GDT_IOCTL) {
  1678. cmd_ptr->u.ioctl.subfunc = p1;
  1679. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1680. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1681. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1682. } else {
  1683. if (ha->cache_feat & GDT_64BIT) {
  1684. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1685. cmd_ptr->u.cache64.BlockNo = p2;
  1686. } else {
  1687. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1688. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1689. }
  1690. }
  1691. } else if (service == SCSIRAWSERVICE) {
  1692. if (ha->raw_feat & GDT_64BIT) {
  1693. cmd_ptr->u.raw64.direction = p1;
  1694. cmd_ptr->u.raw64.bus = (unchar)p2;
  1695. cmd_ptr->u.raw64.target = (unchar)p3;
  1696. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1697. } else {
  1698. cmd_ptr->u.raw.direction = p1;
  1699. cmd_ptr->u.raw.bus = (unchar)p2;
  1700. cmd_ptr->u.raw.target = (unchar)p3;
  1701. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1702. }
  1703. } else if (service == SCREENSERVICE) {
  1704. if (opcode == GDT_REALTIME) {
  1705. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1706. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1707. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1708. }
  1709. }
  1710. ha->cmd_len = sizeof(gdth_cmd_str);
  1711. ha->cmd_offs_dpmem = 0;
  1712. ha->cmd_cnt = 0;
  1713. gdth_copy_command(hanum);
  1714. gdth_release_event(hanum);
  1715. gdth_delay(20);
  1716. if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
  1717. printk("GDT: Initialization error (timeout service %d)\n",service);
  1718. return 0;
  1719. }
  1720. if (ha->status != S_BSY || --retries == 0)
  1721. break;
  1722. gdth_delay(1);
  1723. }
  1724. return (ha->status != S_OK ? 0:1);
  1725. }
  1726. /* search for devices */
  1727. static int __init gdth_search_drives(int hanum)
  1728. {
  1729. register gdth_ha_str *ha;
  1730. ushort cdev_cnt, i;
  1731. int ok;
  1732. ulong32 bus_no, drv_cnt, drv_no, j;
  1733. gdth_getch_str *chn;
  1734. gdth_drlist_str *drl;
  1735. gdth_iochan_str *ioc;
  1736. gdth_raw_iochan_str *iocr;
  1737. gdth_arcdl_str *alst;
  1738. gdth_alist_str *alst2;
  1739. gdth_oem_str_ioctl *oemstr;
  1740. #ifdef INT_COAL
  1741. gdth_perf_modes *pmod;
  1742. #endif
  1743. #ifdef GDTH_RTC
  1744. unchar rtc[12];
  1745. ulong flags;
  1746. #endif
  1747. TRACE(("gdth_search_drives() hanum %d\n",hanum));
  1748. ha = HADATA(gdth_ctr_tab[hanum]);
  1749. ok = 0;
  1750. /* initialize controller services, at first: screen service */
  1751. ha->screen_feat = 0;
  1752. if (!force_dma32) {
  1753. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
  1754. if (ok)
  1755. ha->screen_feat = GDT_64BIT;
  1756. }
  1757. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1758. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
  1759. if (!ok) {
  1760. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1761. hanum, ha->status);
  1762. return 0;
  1763. }
  1764. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1765. #ifdef GDTH_RTC
  1766. /* read realtime clock info, send to controller */
  1767. /* 1. wait for the falling edge of update flag */
  1768. spin_lock_irqsave(&rtc_lock, flags);
  1769. for (j = 0; j < 1000000; ++j)
  1770. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1771. break;
  1772. for (j = 0; j < 1000000; ++j)
  1773. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1774. break;
  1775. /* 2. read info */
  1776. do {
  1777. for (j = 0; j < 12; ++j)
  1778. rtc[j] = CMOS_READ(j);
  1779. } while (rtc[0] != CMOS_READ(0));
  1780. spin_unlock_irqrestore(&rtc_lock, flags);
  1781. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1782. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1783. /* 3. send to controller firmware */
  1784. gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
  1785. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1786. #endif
  1787. /* unfreeze all IOs */
  1788. gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
  1789. /* initialize cache service */
  1790. ha->cache_feat = 0;
  1791. if (!force_dma32) {
  1792. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
  1793. if (ok)
  1794. ha->cache_feat = GDT_64BIT;
  1795. }
  1796. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1797. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
  1798. if (!ok) {
  1799. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1800. hanum, ha->status);
  1801. return 0;
  1802. }
  1803. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1804. cdev_cnt = (ushort)ha->info;
  1805. ha->fw_vers = ha->service;
  1806. #ifdef INT_COAL
  1807. if (ha->type == GDT_PCIMPR) {
  1808. /* set perf. modes */
  1809. pmod = (gdth_perf_modes *)ha->pscratch;
  1810. pmod->version = 1;
  1811. pmod->st_mode = 1; /* enable one status buffer */
  1812. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1813. pmod->st_buff_indx1 = COALINDEX;
  1814. pmod->st_buff_addr2 = 0;
  1815. pmod->st_buff_u_addr2 = 0;
  1816. pmod->st_buff_indx2 = 0;
  1817. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1818. pmod->cmd_mode = 0; // disable all cmd buffers
  1819. pmod->cmd_buff_addr1 = 0;
  1820. pmod->cmd_buff_u_addr1 = 0;
  1821. pmod->cmd_buff_indx1 = 0;
  1822. pmod->cmd_buff_addr2 = 0;
  1823. pmod->cmd_buff_u_addr2 = 0;
  1824. pmod->cmd_buff_indx2 = 0;
  1825. pmod->cmd_buff_size = 0;
  1826. pmod->reserved1 = 0;
  1827. pmod->reserved2 = 0;
  1828. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
  1829. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1830. printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
  1831. }
  1832. }
  1833. #endif
  1834. /* detect number of buses - try new IOCTL */
  1835. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1836. iocr->hdr.version = 0xffffffff;
  1837. iocr->hdr.list_entries = MAXBUS;
  1838. iocr->hdr.first_chan = 0;
  1839. iocr->hdr.last_chan = MAXBUS-1;
  1840. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1841. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
  1842. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1843. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1844. ha->bus_cnt = iocr->hdr.chan_count;
  1845. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1846. if (iocr->list[bus_no].proc_id < MAXID)
  1847. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1848. else
  1849. ha->bus_id[bus_no] = 0xff;
  1850. }
  1851. } else {
  1852. /* old method */
  1853. chn = (gdth_getch_str *)ha->pscratch;
  1854. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1855. chn->channel_no = bus_no;
  1856. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1857. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1858. IO_CHANNEL | INVALID_CHANNEL,
  1859. sizeof(gdth_getch_str))) {
  1860. if (bus_no == 0) {
  1861. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1862. hanum, ha->status);
  1863. return 0;
  1864. }
  1865. break;
  1866. }
  1867. if (chn->siop_id < MAXID)
  1868. ha->bus_id[bus_no] = chn->siop_id;
  1869. else
  1870. ha->bus_id[bus_no] = 0xff;
  1871. }
  1872. ha->bus_cnt = (unchar)bus_no;
  1873. }
  1874. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1875. /* read cache configuration */
  1876. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
  1877. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1878. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1879. hanum, ha->status);
  1880. return 0;
  1881. }
  1882. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1883. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1884. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1885. ha->cpar.write_back,ha->cpar.block_size));
  1886. /* read board info and features */
  1887. ha->more_proc = FALSE;
  1888. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
  1889. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1890. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1891. sizeof(gdth_binfo_str));
  1892. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
  1893. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1894. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1895. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1896. ha->more_proc = TRUE;
  1897. }
  1898. } else {
  1899. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1900. strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
  1901. }
  1902. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1903. /* read more informations */
  1904. if (ha->more_proc) {
  1905. /* physical drives, channel addresses */
  1906. ioc = (gdth_iochan_str *)ha->pscratch;
  1907. ioc->hdr.version = 0xffffffff;
  1908. ioc->hdr.list_entries = MAXBUS;
  1909. ioc->hdr.first_chan = 0;
  1910. ioc->hdr.last_chan = MAXBUS-1;
  1911. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1912. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
  1913. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1914. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1915. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1916. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1917. }
  1918. } else {
  1919. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1920. ha->raw[bus_no].address = IO_CHANNEL;
  1921. ha->raw[bus_no].local_no = bus_no;
  1922. }
  1923. }
  1924. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1925. chn = (gdth_getch_str *)ha->pscratch;
  1926. chn->channel_no = ha->raw[bus_no].local_no;
  1927. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1928. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1929. ha->raw[bus_no].address | INVALID_CHANNEL,
  1930. sizeof(gdth_getch_str))) {
  1931. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1932. TRACE2(("Channel %d: %d phys. drives\n",
  1933. bus_no,chn->drive_cnt));
  1934. }
  1935. if (ha->raw[bus_no].pdev_cnt > 0) {
  1936. drl = (gdth_drlist_str *)ha->pscratch;
  1937. drl->sc_no = ha->raw[bus_no].local_no;
  1938. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1939. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1940. SCSI_DR_LIST | L_CTRL_PATTERN,
  1941. ha->raw[bus_no].address | INVALID_CHANNEL,
  1942. sizeof(gdth_drlist_str))) {
  1943. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1944. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1945. } else {
  1946. ha->raw[bus_no].pdev_cnt = 0;
  1947. }
  1948. }
  1949. }
  1950. /* logical drives */
  1951. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
  1952. INVALID_CHANNEL,sizeof(ulong32))) {
  1953. drv_cnt = *(ulong32 *)ha->pscratch;
  1954. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
  1955. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1956. for (j = 0; j < drv_cnt; ++j) {
  1957. drv_no = ((ulong32 *)ha->pscratch)[j];
  1958. if (drv_no < MAX_LDRIVES) {
  1959. ha->hdr[drv_no].is_logdrv = TRUE;
  1960. TRACE2(("Drive %d is log. drive\n",drv_no));
  1961. }
  1962. }
  1963. }
  1964. alst = (gdth_arcdl_str *)ha->pscratch;
  1965. alst->entries_avail = MAX_LDRIVES;
  1966. alst->first_entry = 0;
  1967. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1968. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1969. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1970. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1971. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1972. for (j = 0; j < alst->entries_init; ++j) {
  1973. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1974. ha->hdr[j].is_master = alst->list[j].is_master;
  1975. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1976. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1977. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1978. }
  1979. } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1980. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1981. 0, 35 * sizeof(gdth_alist_str))) {
  1982. for (j = 0; j < 35; ++j) {
  1983. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1984. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1985. ha->hdr[j].is_master = alst2->is_master;
  1986. ha->hdr[j].is_parity = alst2->is_parity;
  1987. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1988. ha->hdr[j].master_no = alst2->cd_handle;
  1989. }
  1990. }
  1991. }
  1992. }
  1993. /* initialize raw service */
  1994. ha->raw_feat = 0;
  1995. if (!force_dma32) {
  1996. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
  1997. if (ok)
  1998. ha->raw_feat = GDT_64BIT;
  1999. }
  2000. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  2001. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
  2002. if (!ok) {
  2003. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  2004. hanum, ha->status);
  2005. return 0;
  2006. }
  2007. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  2008. /* set/get features raw service (scatter/gather) */
  2009. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
  2010. 0,0)) {
  2011. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  2012. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
  2013. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  2014. ha->info));
  2015. ha->raw_feat |= (ushort)ha->info;
  2016. }
  2017. }
  2018. /* set/get features cache service (equal to raw service) */
  2019. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
  2020. SCATTER_GATHER,0)) {
  2021. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  2022. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
  2023. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  2024. ha->info));
  2025. ha->cache_feat |= (ushort)ha->info;
  2026. }
  2027. }
  2028. /* reserve drives for raw service */
  2029. if (reserve_mode != 0) {
  2030. gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
  2031. reserve_mode == 1 ? 1 : 3, 0, 0);
  2032. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  2033. ha->status));
  2034. }
  2035. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  2036. if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
  2037. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  2038. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  2039. reserve_list[i], reserve_list[i+1],
  2040. reserve_list[i+2], reserve_list[i+3]));
  2041. if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
  2042. reserve_list[i+1], reserve_list[i+2] |
  2043. (reserve_list[i+3] << 8))) {
  2044. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  2045. hanum, ha->status);
  2046. }
  2047. }
  2048. }
  2049. /* Determine OEM string using IOCTL */
  2050. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  2051. oemstr->params.ctl_version = 0x01;
  2052. oemstr->params.buffer_size = sizeof(oemstr->text);
  2053. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  2054. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  2055. sizeof(gdth_oem_str_ioctl))) {
  2056. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  2057. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  2058. hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
  2059. /* Save the Host Drive inquiry data */
  2060. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2061. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  2062. sizeof(ha->oem_name));
  2063. #else
  2064. strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
  2065. ha->oem_name[7] = '\0';
  2066. #endif
  2067. } else {
  2068. /* Old method, based on PCI ID */
  2069. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  2070. printk("GDT-HA %d: Name: %s\n",
  2071. hanum,ha->binfo.type_string);
  2072. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2073. if (ha->oem_id == OEM_ID_INTEL)
  2074. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  2075. else
  2076. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  2077. #else
  2078. if (ha->oem_id == OEM_ID_INTEL)
  2079. strcpy(ha->oem_name,"Intel ");
  2080. else
  2081. strcpy(ha->oem_name,"ICP ");
  2082. #endif
  2083. }
  2084. /* scanning for host drives */
  2085. for (i = 0; i < cdev_cnt; ++i)
  2086. gdth_analyse_hdrive(hanum,i);
  2087. TRACE(("gdth_search_drives() OK\n"));
  2088. return 1;
  2089. }
  2090. static int gdth_analyse_hdrive(int hanum,ushort hdrive)
  2091. {
  2092. register gdth_ha_str *ha;
  2093. ulong32 drv_cyls;
  2094. int drv_hds, drv_secs;
  2095. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
  2096. if (hdrive >= MAX_HDRIVES)
  2097. return 0;
  2098. ha = HADATA(gdth_ctr_tab[hanum]);
  2099. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
  2100. return 0;
  2101. ha->hdr[hdrive].present = TRUE;
  2102. ha->hdr[hdrive].size = ha->info;
  2103. /* evaluate mapping (sectors per head, heads per cylinder) */
  2104. ha->hdr[hdrive].size &= ~SECS32;
  2105. if (ha->info2 == 0) {
  2106. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  2107. } else {
  2108. drv_hds = ha->info2 & 0xff;
  2109. drv_secs = (ha->info2 >> 8) & 0xff;
  2110. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  2111. }
  2112. ha->hdr[hdrive].heads = (unchar)drv_hds;
  2113. ha->hdr[hdrive].secs = (unchar)drv_secs;
  2114. /* round size */
  2115. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  2116. if (ha->cache_feat & GDT_64BIT) {
  2117. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
  2118. && ha->info2 != 0) {
  2119. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  2120. }
  2121. }
  2122. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  2123. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  2124. /* get informations about device */
  2125. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
  2126. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  2127. hdrive,ha->info));
  2128. ha->hdr[hdrive].devtype = (ushort)ha->info;
  2129. }
  2130. /* cluster info */
  2131. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
  2132. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  2133. hdrive,ha->info));
  2134. if (!shared_access)
  2135. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  2136. }
  2137. /* R/W attributes */
  2138. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
  2139. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  2140. hdrive,ha->info));
  2141. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  2142. }
  2143. return 1;
  2144. }
  2145. /* command queueing/sending functions */
  2146. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
  2147. {
  2148. register gdth_ha_str *ha;
  2149. register Scsi_Cmnd *pscp;
  2150. register Scsi_Cmnd *nscp;
  2151. ulong flags;
  2152. unchar b, t;
  2153. TRACE(("gdth_putq() priority %d\n",priority));
  2154. ha = HADATA(gdth_ctr_tab[hanum]);
  2155. spin_lock_irqsave(&ha->smp_lock, flags);
  2156. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  2157. scp->SCp.this_residual = (int)priority;
  2158. b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
  2159. t = scp->device->id;
  2160. if (priority >= DEFAULT_PRI) {
  2161. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2162. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  2163. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  2164. scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
  2165. }
  2166. }
  2167. }
  2168. if (ha->req_first==NULL) {
  2169. ha->req_first = scp; /* queue was empty */
  2170. scp->SCp.ptr = NULL;
  2171. } else { /* queue not empty */
  2172. pscp = ha->req_first;
  2173. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2174. /* priority: 0-highest,..,0xff-lowest */
  2175. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  2176. pscp = nscp;
  2177. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2178. }
  2179. pscp->SCp.ptr = (char *)scp;
  2180. scp->SCp.ptr = (char *)nscp;
  2181. }
  2182. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2183. #ifdef GDTH_STATISTICS
  2184. flags = 0;
  2185. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  2186. ++flags;
  2187. if (max_rq < flags) {
  2188. max_rq = flags;
  2189. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  2190. }
  2191. #endif
  2192. }
  2193. static void gdth_next(int hanum)
  2194. {
  2195. register gdth_ha_str *ha;
  2196. register Scsi_Cmnd *pscp;
  2197. register Scsi_Cmnd *nscp;
  2198. unchar b, t, l, firsttime;
  2199. unchar this_cmd, next_cmd;
  2200. ulong flags = 0;
  2201. int cmd_index;
  2202. TRACE(("gdth_next() hanum %d\n",hanum));
  2203. ha = HADATA(gdth_ctr_tab[hanum]);
  2204. if (!gdth_polling)
  2205. spin_lock_irqsave(&ha->smp_lock, flags);
  2206. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  2207. this_cmd = firsttime = TRUE;
  2208. next_cmd = gdth_polling ? FALSE:TRUE;
  2209. cmd_index = 0;
  2210. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  2211. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  2212. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2213. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  2214. b = virt_ctr ?
  2215. NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
  2216. t = nscp->device->id;
  2217. l = nscp->device->lun;
  2218. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  2219. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2220. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  2221. continue;
  2222. }
  2223. } else
  2224. b = t = l = 0;
  2225. if (firsttime) {
  2226. if (gdth_test_busy(hanum)) { /* controller busy ? */
  2227. TRACE(("gdth_next() controller %d busy !\n",hanum));
  2228. if (!gdth_polling) {
  2229. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2230. return;
  2231. }
  2232. while (gdth_test_busy(hanum))
  2233. gdth_delay(1);
  2234. }
  2235. firsttime = FALSE;
  2236. }
  2237. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  2238. if (nscp->SCp.phase == -1) {
  2239. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  2240. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  2241. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  2242. b, t, l));
  2243. /* TEST_UNIT_READY -> set scan mode */
  2244. if ((ha->scan_mode & 0x0f) == 0) {
  2245. if (b == 0 && t == 0 && l == 0) {
  2246. ha->scan_mode |= 1;
  2247. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2248. }
  2249. } else if ((ha->scan_mode & 0x0f) == 1) {
  2250. if (b == 0 && ((t == 0 && l == 1) ||
  2251. (t == 1 && l == 0))) {
  2252. nscp->SCp.sent_command = GDT_SCAN_START;
  2253. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  2254. | SCSIRAWSERVICE;
  2255. ha->scan_mode = 0x12;
  2256. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  2257. ha->scan_mode));
  2258. } else {
  2259. ha->scan_mode &= 0x10;
  2260. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2261. }
  2262. } else if (ha->scan_mode == 0x12) {
  2263. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  2264. nscp->SCp.phase = SCSIRAWSERVICE;
  2265. nscp->SCp.sent_command = GDT_SCAN_END;
  2266. ha->scan_mode &= 0x10;
  2267. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  2268. ha->scan_mode));
  2269. }
  2270. }
  2271. }
  2272. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  2273. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  2274. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  2275. /* always GDT_CLUST_INFO! */
  2276. nscp->SCp.sent_command = GDT_CLUST_INFO;
  2277. }
  2278. }
  2279. }
  2280. if (nscp->SCp.sent_command != -1) {
  2281. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  2282. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2283. this_cmd = FALSE;
  2284. next_cmd = FALSE;
  2285. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  2286. if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2287. this_cmd = FALSE;
  2288. next_cmd = FALSE;
  2289. } else {
  2290. memset((char*)nscp->sense_buffer,0,16);
  2291. nscp->sense_buffer[0] = 0x70;
  2292. nscp->sense_buffer[2] = NOT_READY;
  2293. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2294. if (!nscp->SCp.have_data_in)
  2295. nscp->SCp.have_data_in++;
  2296. else
  2297. gdth_scsi_done(nscp);
  2298. }
  2299. } else if (IS_GDTH_INTERNAL_CMD(nscp)) {
  2300. if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
  2301. this_cmd = FALSE;
  2302. next_cmd = FALSE;
  2303. } else if (b != ha->virt_bus) {
  2304. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  2305. !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2306. this_cmd = FALSE;
  2307. else
  2308. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  2309. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2310. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2311. nscp->cmnd[0], b, t, l));
  2312. nscp->result = DID_BAD_TARGET << 16;
  2313. if (!nscp->SCp.have_data_in)
  2314. nscp->SCp.have_data_in++;
  2315. else
  2316. gdth_scsi_done(nscp);
  2317. } else {
  2318. switch (nscp->cmnd[0]) {
  2319. case TEST_UNIT_READY:
  2320. case INQUIRY:
  2321. case REQUEST_SENSE:
  2322. case READ_CAPACITY:
  2323. case VERIFY:
  2324. case START_STOP:
  2325. case MODE_SENSE:
  2326. case SERVICE_ACTION_IN:
  2327. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2328. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2329. nscp->cmnd[4],nscp->cmnd[5]));
  2330. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2331. /* return UNIT_ATTENTION */
  2332. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2333. nscp->cmnd[0], t));
  2334. ha->hdr[t].media_changed = FALSE;
  2335. memset((char*)nscp->sense_buffer,0,16);
  2336. nscp->sense_buffer[0] = 0x70;
  2337. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2338. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2339. if (!nscp->SCp.have_data_in)
  2340. nscp->SCp.have_data_in++;
  2341. else
  2342. gdth_scsi_done(nscp);
  2343. } else if (gdth_internal_cache_cmd(hanum, nscp))
  2344. gdth_scsi_done(nscp);
  2345. break;
  2346. case ALLOW_MEDIUM_REMOVAL:
  2347. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2348. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2349. nscp->cmnd[4],nscp->cmnd[5]));
  2350. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2351. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2352. nscp->result = DID_OK << 16;
  2353. nscp->sense_buffer[0] = 0;
  2354. if (!nscp->SCp.have_data_in)
  2355. nscp->SCp.have_data_in++;
  2356. else
  2357. gdth_scsi_done(nscp);
  2358. } else {
  2359. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2360. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2361. nscp->cmnd[4],nscp->cmnd[3]));
  2362. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2363. this_cmd = FALSE;
  2364. }
  2365. break;
  2366. case RESERVE:
  2367. case RELEASE:
  2368. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2369. "RESERVE" : "RELEASE"));
  2370. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2371. this_cmd = FALSE;
  2372. break;
  2373. case READ_6:
  2374. case WRITE_6:
  2375. case READ_10:
  2376. case WRITE_10:
  2377. case READ_16:
  2378. case WRITE_16:
  2379. if (ha->hdr[t].media_changed) {
  2380. /* return UNIT_ATTENTION */
  2381. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2382. nscp->cmnd[0], t));
  2383. ha->hdr[t].media_changed = FALSE;
  2384. memset((char*)nscp->sense_buffer,0,16);
  2385. nscp->sense_buffer[0] = 0x70;
  2386. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2387. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2388. if (!nscp->SCp.have_data_in)
  2389. nscp->SCp.have_data_in++;
  2390. else
  2391. gdth_scsi_done(nscp);
  2392. } else if (!(cmd_index=gdth_fill_cache_cmd(hanum, nscp, t)))
  2393. this_cmd = FALSE;
  2394. break;
  2395. default:
  2396. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2397. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2398. nscp->cmnd[4],nscp->cmnd[5]));
  2399. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2400. hanum, nscp->cmnd[0]);
  2401. nscp->result = DID_ABORT << 16;
  2402. if (!nscp->SCp.have_data_in)
  2403. nscp->SCp.have_data_in++;
  2404. else
  2405. gdth_scsi_done(nscp);
  2406. break;
  2407. }
  2408. }
  2409. if (!this_cmd)
  2410. break;
  2411. if (nscp == ha->req_first)
  2412. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2413. else
  2414. pscp->SCp.ptr = nscp->SCp.ptr;
  2415. if (!next_cmd)
  2416. break;
  2417. }
  2418. if (ha->cmd_cnt > 0) {
  2419. gdth_release_event(hanum);
  2420. }
  2421. if (!gdth_polling)
  2422. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2423. if (gdth_polling && ha->cmd_cnt > 0) {
  2424. if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
  2425. printk("GDT-HA %d: Command %d timed out !\n",
  2426. hanum,cmd_index);
  2427. }
  2428. }
  2429. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  2430. char *buffer,ushort count)
  2431. {
  2432. ushort cpcount,i;
  2433. ushort cpsum,cpnow;
  2434. struct scatterlist *sl;
  2435. gdth_ha_str *ha;
  2436. char *address;
  2437. cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
  2438. ha = HADATA(gdth_ctr_tab[hanum]);
  2439. if (scp->use_sg) {
  2440. sl = (struct scatterlist *)scp->request_buffer;
  2441. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2442. unsigned long flags;
  2443. cpnow = (ushort)sl->length;
  2444. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2445. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2446. if (cpsum+cpnow > cpcount)
  2447. cpnow = cpcount - cpsum;
  2448. cpsum += cpnow;
  2449. if (!sl->page) {
  2450. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2451. hanum);
  2452. return;
  2453. }
  2454. local_irq_save(flags);
  2455. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2456. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2457. memcpy(address,buffer,cpnow);
  2458. flush_dcache_page(sl->page);
  2459. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2460. #else
  2461. address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
  2462. memcpy(address,buffer,cpnow);
  2463. flush_dcache_page(sl->page);
  2464. kunmap_atomic(address, KM_BH_IRQ);
  2465. #endif
  2466. local_irq_restore(flags);
  2467. if (cpsum == cpcount)
  2468. break;
  2469. buffer += cpnow;
  2470. }
  2471. } else {
  2472. TRACE(("copy_internal() count %d\n",cpcount));
  2473. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2474. }
  2475. }
  2476. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
  2477. {
  2478. register gdth_ha_str *ha;
  2479. unchar t;
  2480. gdth_inq_data inq;
  2481. gdth_rdcap_data rdc;
  2482. gdth_sense_data sd;
  2483. gdth_modep_data mpd;
  2484. ha = HADATA(gdth_ctr_tab[hanum]);
  2485. t = scp->device->id;
  2486. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2487. scp->cmnd[0],t));
  2488. scp->result = DID_OK << 16;
  2489. scp->sense_buffer[0] = 0;
  2490. switch (scp->cmnd[0]) {
  2491. case TEST_UNIT_READY:
  2492. case VERIFY:
  2493. case START_STOP:
  2494. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2495. break;
  2496. case INQUIRY:
  2497. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2498. t,ha->hdr[t].devtype));
  2499. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2500. /* you can here set all disks to removable, if you want to do
  2501. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2502. inq.modif_rmb = 0x00;
  2503. if ((ha->hdr[t].devtype & 1) ||
  2504. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2505. inq.modif_rmb = 0x80;
  2506. inq.version = 2;
  2507. inq.resp_aenc = 2;
  2508. inq.add_length= 32;
  2509. strcpy(inq.vendor,ha->oem_name);
  2510. sprintf(inq.product,"Host Drive #%02d",t);
  2511. strcpy(inq.revision," ");
  2512. gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
  2513. break;
  2514. case REQUEST_SENSE:
  2515. TRACE2(("Request sense hdrive %d\n",t));
  2516. sd.errorcode = 0x70;
  2517. sd.segno = 0x00;
  2518. sd.key = NO_SENSE;
  2519. sd.info = 0;
  2520. sd.add_length= 0;
  2521. gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
  2522. break;
  2523. case MODE_SENSE:
  2524. TRACE2(("Mode sense hdrive %d\n",t));
  2525. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2526. mpd.hd.data_length = sizeof(gdth_modep_data);
  2527. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2528. mpd.hd.bd_length = sizeof(mpd.bd);
  2529. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2530. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2531. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2532. gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
  2533. break;
  2534. case READ_CAPACITY:
  2535. TRACE2(("Read capacity hdrive %d\n",t));
  2536. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2537. rdc.last_block_no = 0xffffffff;
  2538. else
  2539. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2540. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2541. gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
  2542. break;
  2543. case SERVICE_ACTION_IN:
  2544. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2545. (ha->cache_feat & GDT_64BIT)) {
  2546. gdth_rdcap16_data rdc16;
  2547. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2548. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2549. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2550. gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
  2551. } else {
  2552. scp->result = DID_ABORT << 16;
  2553. }
  2554. break;
  2555. default:
  2556. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2557. break;
  2558. }
  2559. if (!scp->SCp.have_data_in)
  2560. scp->SCp.have_data_in++;
  2561. else
  2562. return 1;
  2563. return 0;
  2564. }
  2565. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
  2566. {
  2567. register gdth_ha_str *ha;
  2568. register gdth_cmd_str *cmdp;
  2569. struct scatterlist *sl;
  2570. ulong32 cnt, blockcnt;
  2571. ulong64 no, blockno;
  2572. dma_addr_t phys_addr;
  2573. int i, cmd_index, read_write, sgcnt, mode64;
  2574. struct page *page;
  2575. ulong offset;
  2576. ha = HADATA(gdth_ctr_tab[hanum]);
  2577. cmdp = ha->pccb;
  2578. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2579. scp->cmnd[0],scp->cmd_len,hdrive));
  2580. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2581. return 0;
  2582. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2583. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2584. not required, should not occur due to error return on
  2585. READ_CAPACITY_16 */
  2586. cmdp->Service = CACHESERVICE;
  2587. cmdp->RequestBuffer = scp;
  2588. /* search free command index */
  2589. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2590. TRACE(("GDT: No free command index found\n"));
  2591. return 0;
  2592. }
  2593. /* if it's the first command, set command semaphore */
  2594. if (ha->cmd_cnt == 0)
  2595. gdth_set_sema0(hanum);
  2596. /* fill command */
  2597. read_write = 0;
  2598. if (scp->SCp.sent_command != -1)
  2599. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2600. else if (scp->cmnd[0] == RESERVE)
  2601. cmdp->OpCode = GDT_RESERVE_DRV;
  2602. else if (scp->cmnd[0] == RELEASE)
  2603. cmdp->OpCode = GDT_RELEASE_DRV;
  2604. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2605. if (scp->cmnd[4] & 1) /* prevent ? */
  2606. cmdp->OpCode = GDT_MOUNT;
  2607. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2608. cmdp->OpCode = GDT_UNMOUNT;
  2609. else
  2610. cmdp->OpCode = GDT_FLUSH;
  2611. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2612. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2613. ) {
  2614. read_write = 1;
  2615. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2616. (ha->cache_feat & GDT_WR_THROUGH)))
  2617. cmdp->OpCode = GDT_WRITE_THR;
  2618. else
  2619. cmdp->OpCode = GDT_WRITE;
  2620. } else {
  2621. read_write = 2;
  2622. cmdp->OpCode = GDT_READ;
  2623. }
  2624. cmdp->BoardNode = LOCALBOARD;
  2625. if (mode64) {
  2626. cmdp->u.cache64.DeviceNo = hdrive;
  2627. cmdp->u.cache64.BlockNo = 1;
  2628. cmdp->u.cache64.sg_canz = 0;
  2629. } else {
  2630. cmdp->u.cache.DeviceNo = hdrive;
  2631. cmdp->u.cache.BlockNo = 1;
  2632. cmdp->u.cache.sg_canz = 0;
  2633. }
  2634. if (read_write) {
  2635. if (scp->cmd_len == 16) {
  2636. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2637. blockno = be64_to_cpu(no);
  2638. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2639. blockcnt = be32_to_cpu(cnt);
  2640. } else if (scp->cmd_len == 10) {
  2641. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2642. blockno = be32_to_cpu(no);
  2643. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2644. blockcnt = be16_to_cpu(cnt);
  2645. } else {
  2646. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2647. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2648. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2649. }
  2650. if (mode64) {
  2651. cmdp->u.cache64.BlockNo = blockno;
  2652. cmdp->u.cache64.BlockCnt = blockcnt;
  2653. } else {
  2654. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2655. cmdp->u.cache.BlockCnt = blockcnt;
  2656. }
  2657. if (scp->use_sg) {
  2658. sl = (struct scatterlist *)scp->request_buffer;
  2659. sgcnt = scp->use_sg;
  2660. scp->SCp.Status = GDTH_MAP_SG;
  2661. scp->SCp.Message = (read_write == 1 ?
  2662. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2663. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2664. if (mode64) {
  2665. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2666. cmdp->u.cache64.sg_canz = sgcnt;
  2667. for (i=0; i<sgcnt; ++i,++sl) {
  2668. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2669. #ifdef GDTH_DMA_STATISTICS
  2670. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2671. ha->dma64_cnt++;
  2672. else
  2673. ha->dma32_cnt++;
  2674. #endif
  2675. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2676. }
  2677. } else {
  2678. cmdp->u.cache.DestAddr= 0xffffffff;
  2679. cmdp->u.cache.sg_canz = sgcnt;
  2680. for (i=0; i<sgcnt; ++i,++sl) {
  2681. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2682. #ifdef GDTH_DMA_STATISTICS
  2683. ha->dma32_cnt++;
  2684. #endif
  2685. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2686. }
  2687. }
  2688. #ifdef GDTH_STATISTICS
  2689. if (max_sg < (ulong32)sgcnt) {
  2690. max_sg = (ulong32)sgcnt;
  2691. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2692. }
  2693. #endif
  2694. } else if (scp->request_bufflen) {
  2695. scp->SCp.Status = GDTH_MAP_SINGLE;
  2696. scp->SCp.Message = (read_write == 1 ?
  2697. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2698. page = virt_to_page(scp->request_buffer);
  2699. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2700. phys_addr = pci_map_page(ha->pdev,page,offset,
  2701. scp->request_bufflen,scp->SCp.Message);
  2702. scp->SCp.dma_handle = phys_addr;
  2703. if (mode64) {
  2704. if (ha->cache_feat & SCATTER_GATHER) {
  2705. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2706. cmdp->u.cache64.sg_canz = 1;
  2707. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2708. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2709. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2710. } else {
  2711. cmdp->u.cache64.DestAddr = phys_addr;
  2712. cmdp->u.cache64.sg_canz= 0;
  2713. }
  2714. } else {
  2715. if (ha->cache_feat & SCATTER_GATHER) {
  2716. cmdp->u.cache.DestAddr = 0xffffffff;
  2717. cmdp->u.cache.sg_canz = 1;
  2718. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2719. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2720. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2721. } else {
  2722. cmdp->u.cache.DestAddr = phys_addr;
  2723. cmdp->u.cache.sg_canz= 0;
  2724. }
  2725. }
  2726. }
  2727. }
  2728. /* evaluate command size, check space */
  2729. if (mode64) {
  2730. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2731. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2732. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2733. cmdp->u.cache64.sg_lst[0].sg_len));
  2734. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2735. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2736. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2737. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2738. } else {
  2739. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2740. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2741. cmdp->u.cache.sg_lst[0].sg_ptr,
  2742. cmdp->u.cache.sg_lst[0].sg_len));
  2743. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2744. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2745. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2746. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2747. }
  2748. if (ha->cmd_len & 3)
  2749. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2750. if (ha->cmd_cnt > 0) {
  2751. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2752. ha->ic_all_size) {
  2753. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2754. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2755. return 0;
  2756. }
  2757. }
  2758. /* copy command */
  2759. gdth_copy_command(hanum);
  2760. return cmd_index;
  2761. }
  2762. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
  2763. {
  2764. register gdth_ha_str *ha;
  2765. register gdth_cmd_str *cmdp;
  2766. struct scatterlist *sl;
  2767. ushort i;
  2768. dma_addr_t phys_addr, sense_paddr;
  2769. int cmd_index, sgcnt, mode64;
  2770. unchar t,l;
  2771. struct page *page;
  2772. ulong offset;
  2773. ha = HADATA(gdth_ctr_tab[hanum]);
  2774. t = scp->device->id;
  2775. l = scp->device->lun;
  2776. cmdp = ha->pccb;
  2777. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2778. scp->cmnd[0],b,t,l));
  2779. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2780. return 0;
  2781. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2782. cmdp->Service = SCSIRAWSERVICE;
  2783. cmdp->RequestBuffer = scp;
  2784. /* search free command index */
  2785. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2786. TRACE(("GDT: No free command index found\n"));
  2787. return 0;
  2788. }
  2789. /* if it's the first command, set command semaphore */
  2790. if (ha->cmd_cnt == 0)
  2791. gdth_set_sema0(hanum);
  2792. /* fill command */
  2793. if (scp->SCp.sent_command != -1) {
  2794. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2795. cmdp->BoardNode = LOCALBOARD;
  2796. if (mode64) {
  2797. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2798. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2799. cmdp->OpCode, cmdp->u.raw64.direction));
  2800. /* evaluate command size */
  2801. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2802. } else {
  2803. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2804. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2805. cmdp->OpCode, cmdp->u.raw.direction));
  2806. /* evaluate command size */
  2807. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2808. }
  2809. } else {
  2810. page = virt_to_page(scp->sense_buffer);
  2811. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2812. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2813. 16,PCI_DMA_FROMDEVICE);
  2814. *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
  2815. /* high part, if 64bit */
  2816. *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
  2817. cmdp->OpCode = GDT_WRITE; /* always */
  2818. cmdp->BoardNode = LOCALBOARD;
  2819. if (mode64) {
  2820. cmdp->u.raw64.reserved = 0;
  2821. cmdp->u.raw64.mdisc_time = 0;
  2822. cmdp->u.raw64.mcon_time = 0;
  2823. cmdp->u.raw64.clen = scp->cmd_len;
  2824. cmdp->u.raw64.target = t;
  2825. cmdp->u.raw64.lun = l;
  2826. cmdp->u.raw64.bus = b;
  2827. cmdp->u.raw64.priority = 0;
  2828. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2829. cmdp->u.raw64.sense_len = 16;
  2830. cmdp->u.raw64.sense_data = sense_paddr;
  2831. cmdp->u.raw64.direction =
  2832. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2833. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2834. cmdp->u.raw64.sg_ranz = 0;
  2835. } else {
  2836. cmdp->u.raw.reserved = 0;
  2837. cmdp->u.raw.mdisc_time = 0;
  2838. cmdp->u.raw.mcon_time = 0;
  2839. cmdp->u.raw.clen = scp->cmd_len;
  2840. cmdp->u.raw.target = t;
  2841. cmdp->u.raw.lun = l;
  2842. cmdp->u.raw.bus = b;
  2843. cmdp->u.raw.priority = 0;
  2844. cmdp->u.raw.link_p = 0;
  2845. cmdp->u.raw.sdlen = scp->request_bufflen;
  2846. cmdp->u.raw.sense_len = 16;
  2847. cmdp->u.raw.sense_data = sense_paddr;
  2848. cmdp->u.raw.direction =
  2849. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2850. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2851. cmdp->u.raw.sg_ranz = 0;
  2852. }
  2853. if (scp->use_sg) {
  2854. sl = (struct scatterlist *)scp->request_buffer;
  2855. sgcnt = scp->use_sg;
  2856. scp->SCp.Status = GDTH_MAP_SG;
  2857. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2858. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2859. if (mode64) {
  2860. cmdp->u.raw64.sdata = (ulong64)-1;
  2861. cmdp->u.raw64.sg_ranz = sgcnt;
  2862. for (i=0; i<sgcnt; ++i,++sl) {
  2863. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2864. #ifdef GDTH_DMA_STATISTICS
  2865. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2866. ha->dma64_cnt++;
  2867. else
  2868. ha->dma32_cnt++;
  2869. #endif
  2870. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2871. }
  2872. } else {
  2873. cmdp->u.raw.sdata = 0xffffffff;
  2874. cmdp->u.raw.sg_ranz = sgcnt;
  2875. for (i=0; i<sgcnt; ++i,++sl) {
  2876. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2877. #ifdef GDTH_DMA_STATISTICS
  2878. ha->dma32_cnt++;
  2879. #endif
  2880. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2881. }
  2882. }
  2883. #ifdef GDTH_STATISTICS
  2884. if (max_sg < sgcnt) {
  2885. max_sg = sgcnt;
  2886. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2887. }
  2888. #endif
  2889. } else if (scp->request_bufflen) {
  2890. scp->SCp.Status = GDTH_MAP_SINGLE;
  2891. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2892. page = virt_to_page(scp->request_buffer);
  2893. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2894. phys_addr = pci_map_page(ha->pdev,page,offset,
  2895. scp->request_bufflen,scp->SCp.Message);
  2896. scp->SCp.dma_handle = phys_addr;
  2897. if (mode64) {
  2898. if (ha->raw_feat & SCATTER_GATHER) {
  2899. cmdp->u.raw64.sdata = (ulong64)-1;
  2900. cmdp->u.raw64.sg_ranz= 1;
  2901. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2902. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2903. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2904. } else {
  2905. cmdp->u.raw64.sdata = phys_addr;
  2906. cmdp->u.raw64.sg_ranz= 0;
  2907. }
  2908. } else {
  2909. if (ha->raw_feat & SCATTER_GATHER) {
  2910. cmdp->u.raw.sdata = 0xffffffff;
  2911. cmdp->u.raw.sg_ranz= 1;
  2912. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2913. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2914. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2915. } else {
  2916. cmdp->u.raw.sdata = phys_addr;
  2917. cmdp->u.raw.sg_ranz= 0;
  2918. }
  2919. }
  2920. }
  2921. if (mode64) {
  2922. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2923. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2924. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2925. cmdp->u.raw64.sg_lst[0].sg_len));
  2926. /* evaluate command size */
  2927. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2928. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2929. } else {
  2930. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2931. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2932. cmdp->u.raw.sg_lst[0].sg_ptr,
  2933. cmdp->u.raw.sg_lst[0].sg_len));
  2934. /* evaluate command size */
  2935. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2936. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2937. }
  2938. }
  2939. /* check space */
  2940. if (ha->cmd_len & 3)
  2941. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2942. if (ha->cmd_cnt > 0) {
  2943. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2944. ha->ic_all_size) {
  2945. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2946. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2947. return 0;
  2948. }
  2949. }
  2950. /* copy command */
  2951. gdth_copy_command(hanum);
  2952. return cmd_index;
  2953. }
  2954. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
  2955. {
  2956. register gdth_ha_str *ha;
  2957. register gdth_cmd_str *cmdp;
  2958. int cmd_index;
  2959. ha = HADATA(gdth_ctr_tab[hanum]);
  2960. cmdp= ha->pccb;
  2961. TRACE2(("gdth_special_cmd(): "));
  2962. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2963. return 0;
  2964. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2965. cmdp->RequestBuffer = scp;
  2966. /* search free command index */
  2967. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2968. TRACE(("GDT: No free command index found\n"));
  2969. return 0;
  2970. }
  2971. /* if it's the first command, set command semaphore */
  2972. if (ha->cmd_cnt == 0)
  2973. gdth_set_sema0(hanum);
  2974. /* evaluate command size, check space */
  2975. if (cmdp->OpCode == GDT_IOCTL) {
  2976. TRACE2(("IOCTL\n"));
  2977. ha->cmd_len =
  2978. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2979. } else if (cmdp->Service == CACHESERVICE) {
  2980. TRACE2(("cache command %d\n",cmdp->OpCode));
  2981. if (ha->cache_feat & GDT_64BIT)
  2982. ha->cmd_len =
  2983. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2984. else
  2985. ha->cmd_len =
  2986. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2987. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2988. TRACE2(("raw command %d\n",cmdp->OpCode));
  2989. if (ha->raw_feat & GDT_64BIT)
  2990. ha->cmd_len =
  2991. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2992. else
  2993. ha->cmd_len =
  2994. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2995. }
  2996. if (ha->cmd_len & 3)
  2997. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2998. if (ha->cmd_cnt > 0) {
  2999. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  3000. ha->ic_all_size) {
  3001. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  3002. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  3003. return 0;
  3004. }
  3005. }
  3006. /* copy command */
  3007. gdth_copy_command(hanum);
  3008. return cmd_index;
  3009. }
  3010. /* Controller event handling functions */
  3011. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  3012. ushort idx, gdth_evt_data *evt)
  3013. {
  3014. gdth_evt_str *e;
  3015. struct timeval tv;
  3016. /* no GDTH_LOCK_HA() ! */
  3017. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  3018. if (source == 0) /* no source -> no event */
  3019. return NULL;
  3020. if (ebuffer[elastidx].event_source == source &&
  3021. ebuffer[elastidx].event_idx == idx &&
  3022. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  3023. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  3024. (char *)&evt->eu, evt->size)) ||
  3025. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  3026. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  3027. (char *)&evt->event_string)))) {
  3028. e = &ebuffer[elastidx];
  3029. do_gettimeofday(&tv);
  3030. e->last_stamp = tv.tv_sec;
  3031. ++e->same_count;
  3032. } else {
  3033. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  3034. ++elastidx;
  3035. if (elastidx == MAX_EVENTS)
  3036. elastidx = 0;
  3037. if (elastidx == eoldidx) { /* reached mark ? */
  3038. ++eoldidx;
  3039. if (eoldidx == MAX_EVENTS)
  3040. eoldidx = 0;
  3041. }
  3042. }
  3043. e = &ebuffer[elastidx];
  3044. e->event_source = source;
  3045. e->event_idx = idx;
  3046. do_gettimeofday(&tv);
  3047. e->first_stamp = e->last_stamp = tv.tv_sec;
  3048. e->same_count = 1;
  3049. e->event_data = *evt;
  3050. e->application = 0;
  3051. }
  3052. return e;
  3053. }
  3054. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  3055. {
  3056. gdth_evt_str *e;
  3057. int eindex;
  3058. ulong flags;
  3059. TRACE2(("gdth_read_event() handle %d\n", handle));
  3060. spin_lock_irqsave(&ha->smp_lock, flags);
  3061. if (handle == -1)
  3062. eindex = eoldidx;
  3063. else
  3064. eindex = handle;
  3065. estr->event_source = 0;
  3066. if (eindex >= MAX_EVENTS) {
  3067. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3068. return eindex;
  3069. }
  3070. e = &ebuffer[eindex];
  3071. if (e->event_source != 0) {
  3072. if (eindex != elastidx) {
  3073. if (++eindex == MAX_EVENTS)
  3074. eindex = 0;
  3075. } else {
  3076. eindex = -1;
  3077. }
  3078. memcpy(estr, e, sizeof(gdth_evt_str));
  3079. }
  3080. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3081. return eindex;
  3082. }
  3083. static void gdth_readapp_event(gdth_ha_str *ha,
  3084. unchar application, gdth_evt_str *estr)
  3085. {
  3086. gdth_evt_str *e;
  3087. int eindex;
  3088. ulong flags;
  3089. unchar found = FALSE;
  3090. TRACE2(("gdth_readapp_event() app. %d\n", application));
  3091. spin_lock_irqsave(&ha->smp_lock, flags);
  3092. eindex = eoldidx;
  3093. for (;;) {
  3094. e = &ebuffer[eindex];
  3095. if (e->event_source == 0)
  3096. break;
  3097. if ((e->application & application) == 0) {
  3098. e->application |= application;
  3099. found = TRUE;
  3100. break;
  3101. }
  3102. if (eindex == elastidx)
  3103. break;
  3104. if (++eindex == MAX_EVENTS)
  3105. eindex = 0;
  3106. }
  3107. if (found)
  3108. memcpy(estr, e, sizeof(gdth_evt_str));
  3109. else
  3110. estr->event_source = 0;
  3111. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3112. }
  3113. static void gdth_clear_events(void)
  3114. {
  3115. TRACE(("gdth_clear_events()"));
  3116. eoldidx = elastidx = 0;
  3117. ebuffer[0].event_source = 0;
  3118. }
  3119. /* SCSI interface functions */
  3120. static irqreturn_t gdth_interrupt(int irq,void *dev_id)
  3121. {
  3122. gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
  3123. register gdth_ha_str *ha;
  3124. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  3125. gdt6_dpram_str __iomem *dp6_ptr;
  3126. gdt2_dpram_str __iomem *dp2_ptr;
  3127. Scsi_Cmnd *scp;
  3128. int hanum, rval, i;
  3129. unchar IStatus;
  3130. ushort Service;
  3131. ulong flags = 0;
  3132. #ifdef INT_COAL
  3133. int coalesced = FALSE;
  3134. int next = FALSE;
  3135. gdth_coal_status *pcs = NULL;
  3136. int act_int_coal = 0;
  3137. #endif
  3138. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  3139. /* if polling and not from gdth_wait() -> return */
  3140. if (gdth_polling) {
  3141. if (!gdth_from_wait) {
  3142. return IRQ_HANDLED;
  3143. }
  3144. }
  3145. if (!gdth_polling)
  3146. spin_lock_irqsave(&ha2->smp_lock, flags);
  3147. wait_index = 0;
  3148. /* search controller */
  3149. if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
  3150. /* spurious interrupt */
  3151. if (!gdth_polling)
  3152. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3153. return IRQ_HANDLED;
  3154. }
  3155. ha = HADATA(gdth_ctr_tab[hanum]);
  3156. #ifdef GDTH_STATISTICS
  3157. ++act_ints;
  3158. #endif
  3159. #ifdef INT_COAL
  3160. /* See if the fw is returning coalesced status */
  3161. if (IStatus == COALINDEX) {
  3162. /* Coalesced status. Setup the initial status
  3163. buffer pointer and flags */
  3164. pcs = ha->coal_stat;
  3165. coalesced = TRUE;
  3166. next = TRUE;
  3167. }
  3168. do {
  3169. if (coalesced) {
  3170. /* For coalesced requests all status
  3171. information is found in the status buffer */
  3172. IStatus = (unchar)(pcs->status & 0xff);
  3173. }
  3174. #endif
  3175. if (ha->type == GDT_EISA) {
  3176. if (IStatus & 0x80) { /* error flag */
  3177. IStatus &= ~0x80;
  3178. ha->status = inw(ha->bmic + MAILBOXREG+8);
  3179. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3180. } else /* no error */
  3181. ha->status = S_OK;
  3182. ha->info = inl(ha->bmic + MAILBOXREG+12);
  3183. ha->service = inw(ha->bmic + MAILBOXREG+10);
  3184. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  3185. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  3186. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  3187. } else if (ha->type == GDT_ISA) {
  3188. dp2_ptr = ha->brd;
  3189. if (IStatus & 0x80) { /* error flag */
  3190. IStatus &= ~0x80;
  3191. ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
  3192. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3193. } else /* no error */
  3194. ha->status = S_OK;
  3195. ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
  3196. ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
  3197. ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
  3198. gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  3199. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  3200. gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  3201. } else if (ha->type == GDT_PCI) {
  3202. dp6_ptr = ha->brd;
  3203. if (IStatus & 0x80) { /* error flag */
  3204. IStatus &= ~0x80;
  3205. ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
  3206. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3207. } else /* no error */
  3208. ha->status = S_OK;
  3209. ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
  3210. ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
  3211. ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
  3212. gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  3213. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  3214. gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  3215. } else if (ha->type == GDT_PCINEW) {
  3216. if (IStatus & 0x80) { /* error flag */
  3217. IStatus &= ~0x80;
  3218. ha->status = inw(PTR2USHORT(&ha->plx->status));
  3219. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3220. } else
  3221. ha->status = S_OK;
  3222. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  3223. ha->service = inw(PTR2USHORT(&ha->plx->service));
  3224. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  3225. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  3226. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  3227. } else if (ha->type == GDT_PCIMPR) {
  3228. dp6m_ptr = ha->brd;
  3229. if (IStatus & 0x80) { /* error flag */
  3230. IStatus &= ~0x80;
  3231. #ifdef INT_COAL
  3232. if (coalesced)
  3233. ha->status = pcs->ext_status & 0xffff;
  3234. else
  3235. #endif
  3236. ha->status = gdth_readw(&dp6m_ptr->i960r.status);
  3237. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3238. } else /* no error */
  3239. ha->status = S_OK;
  3240. #ifdef INT_COAL
  3241. /* get information */
  3242. if (coalesced) {
  3243. ha->info = pcs->info0;
  3244. ha->info2 = pcs->info1;
  3245. ha->service = (pcs->ext_status >> 16) & 0xffff;
  3246. } else
  3247. #endif
  3248. {
  3249. ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
  3250. ha->service = gdth_readw(&dp6m_ptr->i960r.service);
  3251. ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
  3252. }
  3253. /* event string */
  3254. if (IStatus == ASYNCINDEX) {
  3255. if (ha->service != SCREENSERVICE &&
  3256. (ha->fw_vers & 0xff) >= 0x1a) {
  3257. ha->dvr.severity = gdth_readb
  3258. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  3259. for (i = 0; i < 256; ++i) {
  3260. ha->dvr.event_string[i] = gdth_readb
  3261. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  3262. if (ha->dvr.event_string[i] == 0)
  3263. break;
  3264. }
  3265. }
  3266. }
  3267. #ifdef INT_COAL
  3268. /* Make sure that non coalesced interrupts get cleared
  3269. before being handled by gdth_async_event/gdth_sync_event */
  3270. if (!coalesced)
  3271. #endif
  3272. {
  3273. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3274. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3275. }
  3276. } else {
  3277. TRACE2(("gdth_interrupt() unknown controller type\n"));
  3278. if (!gdth_polling)
  3279. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3280. return IRQ_HANDLED;
  3281. }
  3282. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  3283. IStatus,ha->status,ha->info));
  3284. if (gdth_from_wait) {
  3285. wait_hanum = hanum;
  3286. wait_index = (int)IStatus;
  3287. }
  3288. if (IStatus == ASYNCINDEX) {
  3289. TRACE2(("gdth_interrupt() async. event\n"));
  3290. gdth_async_event(hanum);
  3291. if (!gdth_polling)
  3292. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3293. gdth_next(hanum);
  3294. return IRQ_HANDLED;
  3295. }
  3296. if (IStatus == SPEZINDEX) {
  3297. TRACE2(("Service unknown or not initialized !\n"));
  3298. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3299. ha->dvr.eu.driver.ionode = hanum;
  3300. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  3301. if (!gdth_polling)
  3302. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3303. return IRQ_HANDLED;
  3304. }
  3305. scp = ha->cmd_tab[IStatus-2].cmnd;
  3306. Service = ha->cmd_tab[IStatus-2].service;
  3307. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  3308. if (scp == UNUSED_CMND) {
  3309. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  3310. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3311. ha->dvr.eu.driver.ionode = hanum;
  3312. ha->dvr.eu.driver.index = IStatus;
  3313. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  3314. if (!gdth_polling)
  3315. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3316. return IRQ_HANDLED;
  3317. }
  3318. if (scp == INTERNAL_CMND) {
  3319. TRACE(("gdth_interrupt() answer to internal command\n"));
  3320. if (!gdth_polling)
  3321. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3322. return IRQ_HANDLED;
  3323. }
  3324. TRACE(("gdth_interrupt() sync. status\n"));
  3325. rval = gdth_sync_event(hanum,Service,IStatus,scp);
  3326. if (!gdth_polling)
  3327. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3328. if (rval == 2) {
  3329. gdth_putq(hanum,scp,scp->SCp.this_residual);
  3330. } else if (rval == 1) {
  3331. gdth_scsi_done(scp);
  3332. }
  3333. #ifdef INT_COAL
  3334. if (coalesced) {
  3335. /* go to the next status in the status buffer */
  3336. ++pcs;
  3337. #ifdef GDTH_STATISTICS
  3338. ++act_int_coal;
  3339. if (act_int_coal > max_int_coal) {
  3340. max_int_coal = act_int_coal;
  3341. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  3342. }
  3343. #endif
  3344. /* see if there is another status */
  3345. if (pcs->status == 0)
  3346. /* Stop the coalesce loop */
  3347. next = FALSE;
  3348. }
  3349. } while (next);
  3350. /* coalescing only for new GDT_PCIMPR controllers available */
  3351. if (ha->type == GDT_PCIMPR && coalesced) {
  3352. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3353. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3354. }
  3355. #endif
  3356. gdth_next(hanum);
  3357. return IRQ_HANDLED;
  3358. }
  3359. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
  3360. {
  3361. register gdth_ha_str *ha;
  3362. gdth_msg_str *msg;
  3363. gdth_cmd_str *cmdp;
  3364. unchar b, t;
  3365. ha = HADATA(gdth_ctr_tab[hanum]);
  3366. cmdp = ha->pccb;
  3367. TRACE(("gdth_sync_event() serv %d status %d\n",
  3368. service,ha->status));
  3369. if (service == SCREENSERVICE) {
  3370. msg = ha->pmsg;
  3371. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3372. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3373. if (msg->msg_len > MSGLEN+1)
  3374. msg->msg_len = MSGLEN+1;
  3375. if (msg->msg_len)
  3376. if (!(msg->msg_answer && msg->msg_ext)) {
  3377. msg->msg_text[msg->msg_len] = '\0';
  3378. printk("%s",msg->msg_text);
  3379. }
  3380. if (msg->msg_ext && !msg->msg_answer) {
  3381. while (gdth_test_busy(hanum))
  3382. gdth_delay(0);
  3383. cmdp->Service = SCREENSERVICE;
  3384. cmdp->RequestBuffer = SCREEN_CMND;
  3385. gdth_get_cmd_index(hanum);
  3386. gdth_set_sema0(hanum);
  3387. cmdp->OpCode = GDT_READ;
  3388. cmdp->BoardNode = LOCALBOARD;
  3389. cmdp->u.screen.reserved = 0;
  3390. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3391. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3392. ha->cmd_offs_dpmem = 0;
  3393. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3394. + sizeof(ulong64);
  3395. ha->cmd_cnt = 0;
  3396. gdth_copy_command(hanum);
  3397. gdth_release_event(hanum);
  3398. return 0;
  3399. }
  3400. if (msg->msg_answer && msg->msg_alen) {
  3401. /* default answers (getchar() not possible) */
  3402. if (msg->msg_alen == 1) {
  3403. msg->msg_alen = 0;
  3404. msg->msg_len = 1;
  3405. msg->msg_text[0] = 0;
  3406. } else {
  3407. msg->msg_alen -= 2;
  3408. msg->msg_len = 2;
  3409. msg->msg_text[0] = 1;
  3410. msg->msg_text[1] = 0;
  3411. }
  3412. msg->msg_ext = 0;
  3413. msg->msg_answer = 0;
  3414. while (gdth_test_busy(hanum))
  3415. gdth_delay(0);
  3416. cmdp->Service = SCREENSERVICE;
  3417. cmdp->RequestBuffer = SCREEN_CMND;
  3418. gdth_get_cmd_index(hanum);
  3419. gdth_set_sema0(hanum);
  3420. cmdp->OpCode = GDT_WRITE;
  3421. cmdp->BoardNode = LOCALBOARD;
  3422. cmdp->u.screen.reserved = 0;
  3423. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3424. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3425. ha->cmd_offs_dpmem = 0;
  3426. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3427. + sizeof(ulong64);
  3428. ha->cmd_cnt = 0;
  3429. gdth_copy_command(hanum);
  3430. gdth_release_event(hanum);
  3431. return 0;
  3432. }
  3433. printk("\n");
  3434. } else {
  3435. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  3436. t = scp->device->id;
  3437. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3438. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3439. }
  3440. /* cache or raw service */
  3441. if (ha->status == S_BSY) {
  3442. TRACE2(("Controller busy -> retry !\n"));
  3443. if (scp->SCp.sent_command == GDT_MOUNT)
  3444. scp->SCp.sent_command = GDT_CLUST_INFO;
  3445. /* retry */
  3446. return 2;
  3447. }
  3448. if (scp->SCp.Status == GDTH_MAP_SG)
  3449. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3450. scp->use_sg,scp->SCp.Message);
  3451. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3452. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3453. scp->request_bufflen,scp->SCp.Message);
  3454. if (scp->SCp.buffer) {
  3455. dma_addr_t addr;
  3456. addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
  3457. if (scp->host_scribble)
  3458. addr += (dma_addr_t)
  3459. ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
  3460. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3461. }
  3462. if (ha->status == S_OK) {
  3463. scp->SCp.Status = S_OK;
  3464. scp->SCp.Message = ha->info;
  3465. if (scp->SCp.sent_command != -1) {
  3466. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3467. scp->SCp.sent_command));
  3468. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3469. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3470. ha->hdr[t].cluster_type = (unchar)ha->info;
  3471. if (!(ha->hdr[t].cluster_type &
  3472. CLUSTER_MOUNTED)) {
  3473. /* NOT MOUNTED -> MOUNT */
  3474. scp->SCp.sent_command = GDT_MOUNT;
  3475. if (ha->hdr[t].cluster_type &
  3476. CLUSTER_RESERVED) {
  3477. /* cluster drive RESERVED (on the other node) */
  3478. scp->SCp.phase = -2; /* reservation conflict */
  3479. }
  3480. } else {
  3481. scp->SCp.sent_command = -1;
  3482. }
  3483. } else {
  3484. if (scp->SCp.sent_command == GDT_MOUNT) {
  3485. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3486. ha->hdr[t].media_changed = TRUE;
  3487. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3488. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3489. ha->hdr[t].media_changed = TRUE;
  3490. }
  3491. scp->SCp.sent_command = -1;
  3492. }
  3493. /* retry */
  3494. scp->SCp.this_residual = HIGH_PRI;
  3495. return 2;
  3496. } else {
  3497. /* RESERVE/RELEASE ? */
  3498. if (scp->cmnd[0] == RESERVE) {
  3499. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3500. } else if (scp->cmnd[0] == RELEASE) {
  3501. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3502. }
  3503. scp->result = DID_OK << 16;
  3504. scp->sense_buffer[0] = 0;
  3505. }
  3506. } else {
  3507. scp->SCp.Status = ha->status;
  3508. scp->SCp.Message = ha->info;
  3509. if (scp->SCp.sent_command != -1) {
  3510. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3511. scp->SCp.sent_command, ha->status));
  3512. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3513. scp->SCp.sent_command == GDT_SCAN_END) {
  3514. scp->SCp.sent_command = -1;
  3515. /* retry */
  3516. scp->SCp.this_residual = HIGH_PRI;
  3517. return 2;
  3518. }
  3519. memset((char*)scp->sense_buffer,0,16);
  3520. scp->sense_buffer[0] = 0x70;
  3521. scp->sense_buffer[2] = NOT_READY;
  3522. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3523. } else if (service == CACHESERVICE) {
  3524. if (ha->status == S_CACHE_UNKNOWN &&
  3525. (ha->hdr[t].cluster_type &
  3526. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3527. /* bus reset -> force GDT_CLUST_INFO */
  3528. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3529. }
  3530. memset((char*)scp->sense_buffer,0,16);
  3531. if (ha->status == (ushort)S_CACHE_RESERV) {
  3532. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3533. } else {
  3534. scp->sense_buffer[0] = 0x70;
  3535. scp->sense_buffer[2] = NOT_READY;
  3536. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3537. }
  3538. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  3539. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3540. ha->dvr.eu.sync.ionode = hanum;
  3541. ha->dvr.eu.sync.service = service;
  3542. ha->dvr.eu.sync.status = ha->status;
  3543. ha->dvr.eu.sync.info = ha->info;
  3544. ha->dvr.eu.sync.hostdrive = t;
  3545. if (ha->status >= 0x8000)
  3546. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3547. else
  3548. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3549. }
  3550. } else {
  3551. /* sense buffer filled from controller firmware (DMA) */
  3552. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3553. scp->result = DID_BAD_TARGET << 16;
  3554. } else {
  3555. scp->result = (DID_OK << 16) | ha->info;
  3556. }
  3557. }
  3558. }
  3559. if (!scp->SCp.have_data_in)
  3560. scp->SCp.have_data_in++;
  3561. else
  3562. return 1;
  3563. }
  3564. return 0;
  3565. }
  3566. static char *async_cache_tab[] = {
  3567. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3568. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3569. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3570. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3571. /* 2*/ "\005\000\002\006\004"
  3572. "GDT HA %u, Host Drive %lu not ready",
  3573. /* 3*/ "\005\000\002\006\004"
  3574. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3575. /* 4*/ "\005\000\002\006\004"
  3576. "GDT HA %u, mirror update on Host Drive %lu failed",
  3577. /* 5*/ "\005\000\002\006\004"
  3578. "GDT HA %u, Mirror Drive %lu failed",
  3579. /* 6*/ "\005\000\002\006\004"
  3580. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3581. /* 7*/ "\005\000\002\006\004"
  3582. "GDT HA %u, Host Drive %lu write protected",
  3583. /* 8*/ "\005\000\002\006\004"
  3584. "GDT HA %u, media changed in Host Drive %lu",
  3585. /* 9*/ "\005\000\002\006\004"
  3586. "GDT HA %u, Host Drive %lu is offline",
  3587. /*10*/ "\005\000\002\006\004"
  3588. "GDT HA %u, media change of Mirror Drive %lu",
  3589. /*11*/ "\005\000\002\006\004"
  3590. "GDT HA %u, Mirror Drive %lu is write protected",
  3591. /*12*/ "\005\000\002\006\004"
  3592. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3593. /*13*/ "\007\000\002\006\002\010\002"
  3594. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3595. /*14*/ "\005\000\002\006\002"
  3596. "GDT HA %u, Array Drive %u: FAIL state entered",
  3597. /*15*/ "\005\000\002\006\002"
  3598. "GDT HA %u, Array Drive %u: error",
  3599. /*16*/ "\007\000\002\006\002\010\002"
  3600. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3601. /*17*/ "\005\000\002\006\002"
  3602. "GDT HA %u, Array Drive %u: parity build failed",
  3603. /*18*/ "\005\000\002\006\002"
  3604. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3605. /*19*/ "\005\000\002\010\002"
  3606. "GDT HA %u, Test of Hot Fix %u failed",
  3607. /*20*/ "\005\000\002\006\002"
  3608. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3609. /*21*/ "\005\000\002\006\002"
  3610. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3611. /*22*/ "\007\000\002\006\002\010\002"
  3612. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3613. /*23*/ "\005\000\002\006\002"
  3614. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3615. /*24*/ "\005\000\002\010\002"
  3616. "GDT HA %u, mirror update on Cache Drive %u completed",
  3617. /*25*/ "\005\000\002\010\002"
  3618. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3619. /*26*/ "\005\000\002\006\002"
  3620. "GDT HA %u, Array Drive %u: drive rebuild started",
  3621. /*27*/ "\005\000\002\012\001"
  3622. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3623. /*28*/ "\005\000\002\012\001"
  3624. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3625. /*29*/ "\007\000\002\012\001\013\001"
  3626. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3627. /*30*/ "\007\000\002\012\001\013\001"
  3628. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3629. /*31*/ "\007\000\002\012\001\013\001"
  3630. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3631. /*32*/ "\007\000\002\012\001\013\001"
  3632. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3633. /*33*/ "\007\000\002\012\001\013\001"
  3634. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3635. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3636. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3637. /*35*/ "\007\000\002\012\001\013\001"
  3638. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3639. /*36*/ "\007\000\002\012\001\013\001"
  3640. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3641. /*37*/ "\007\000\002\012\001\006\004"
  3642. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3643. /*38*/ "\007\000\002\012\001\013\001"
  3644. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3645. /*39*/ "\007\000\002\012\001\013\001"
  3646. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3647. /*40*/ "\007\000\002\012\001\013\001"
  3648. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3649. /*41*/ "\007\000\002\012\001\013\001"
  3650. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3651. /*42*/ "\005\000\002\006\002"
  3652. "GDT HA %u, Array Drive %u: drive build started",
  3653. /*43*/ "\003\000\002"
  3654. "GDT HA %u, DRAM parity error detected",
  3655. /*44*/ "\005\000\002\006\002"
  3656. "GDT HA %u, Mirror Drive %u: update started",
  3657. /*45*/ "\007\000\002\006\002\010\002"
  3658. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3659. /*46*/ "\005\000\002\006\002"
  3660. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3661. /*47*/ "\005\000\002\006\002"
  3662. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3663. /*48*/ "\005\000\002\006\002"
  3664. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3665. /*49*/ "\005\000\002\006\002"
  3666. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3667. /*50*/ "\007\000\002\012\001\013\001"
  3668. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3669. /*51*/ "\005\000\002\006\002"
  3670. "GDT HA %u, Array Drive %u: expand started",
  3671. /*52*/ "\005\000\002\006\002"
  3672. "GDT HA %u, Array Drive %u: expand finished successfully",
  3673. /*53*/ "\005\000\002\006\002"
  3674. "GDT HA %u, Array Drive %u: expand failed",
  3675. /*54*/ "\003\000\002"
  3676. "GDT HA %u, CPU temperature critical",
  3677. /*55*/ "\003\000\002"
  3678. "GDT HA %u, CPU temperature OK",
  3679. /*56*/ "\005\000\002\006\004"
  3680. "GDT HA %u, Host drive %lu created",
  3681. /*57*/ "\005\000\002\006\002"
  3682. "GDT HA %u, Array Drive %u: expand restarted",
  3683. /*58*/ "\005\000\002\006\002"
  3684. "GDT HA %u, Array Drive %u: expand stopped",
  3685. /*59*/ "\005\000\002\010\002"
  3686. "GDT HA %u, Mirror Drive %u: drive build quited",
  3687. /*60*/ "\005\000\002\006\002"
  3688. "GDT HA %u, Array Drive %u: parity build quited",
  3689. /*61*/ "\005\000\002\006\002"
  3690. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3691. /*62*/ "\005\000\002\006\002"
  3692. "GDT HA %u, Array Drive %u: parity verify started",
  3693. /*63*/ "\005\000\002\006\002"
  3694. "GDT HA %u, Array Drive %u: parity verify done",
  3695. /*64*/ "\005\000\002\006\002"
  3696. "GDT HA %u, Array Drive %u: parity verify failed",
  3697. /*65*/ "\005\000\002\006\002"
  3698. "GDT HA %u, Array Drive %u: parity error detected",
  3699. /*66*/ "\005\000\002\006\002"
  3700. "GDT HA %u, Array Drive %u: parity verify quited",
  3701. /*67*/ "\005\000\002\006\002"
  3702. "GDT HA %u, Host Drive %u reserved",
  3703. /*68*/ "\005\000\002\006\002"
  3704. "GDT HA %u, Host Drive %u mounted and released",
  3705. /*69*/ "\005\000\002\006\002"
  3706. "GDT HA %u, Host Drive %u released",
  3707. /*70*/ "\003\000\002"
  3708. "GDT HA %u, DRAM error detected and corrected with ECC",
  3709. /*71*/ "\003\000\002"
  3710. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3711. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3712. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3713. /*73*/ "\005\000\002\006\002"
  3714. "GDT HA %u, Host drive %u resetted locally",
  3715. /*74*/ "\005\000\002\006\002"
  3716. "GDT HA %u, Host drive %u resetted remotely",
  3717. /*75*/ "\003\000\002"
  3718. "GDT HA %u, async. status 75 unknown",
  3719. };
  3720. static int gdth_async_event(int hanum)
  3721. {
  3722. gdth_ha_str *ha;
  3723. gdth_cmd_str *cmdp;
  3724. int cmd_index;
  3725. ha = HADATA(gdth_ctr_tab[hanum]);
  3726. cmdp= ha->pccb;
  3727. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3728. hanum,ha->service));
  3729. if (ha->service == SCREENSERVICE) {
  3730. if (ha->status == MSG_REQUEST) {
  3731. while (gdth_test_busy(hanum))
  3732. gdth_delay(0);
  3733. cmdp->Service = SCREENSERVICE;
  3734. cmdp->RequestBuffer = SCREEN_CMND;
  3735. cmd_index = gdth_get_cmd_index(hanum);
  3736. gdth_set_sema0(hanum);
  3737. cmdp->OpCode = GDT_READ;
  3738. cmdp->BoardNode = LOCALBOARD;
  3739. cmdp->u.screen.reserved = 0;
  3740. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3741. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3742. ha->cmd_offs_dpmem = 0;
  3743. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3744. + sizeof(ulong64);
  3745. ha->cmd_cnt = 0;
  3746. gdth_copy_command(hanum);
  3747. if (ha->type == GDT_EISA)
  3748. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3749. else if (ha->type == GDT_ISA)
  3750. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3751. else
  3752. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3753. (ushort)((ha->brd_phys>>3)&0x1f));
  3754. gdth_release_event(hanum);
  3755. }
  3756. } else {
  3757. if (ha->type == GDT_PCIMPR &&
  3758. (ha->fw_vers & 0xff) >= 0x1a) {
  3759. ha->dvr.size = 0;
  3760. ha->dvr.eu.async.ionode = hanum;
  3761. ha->dvr.eu.async.status = ha->status;
  3762. /* severity and event_string already set! */
  3763. } else {
  3764. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3765. ha->dvr.eu.async.ionode = hanum;
  3766. ha->dvr.eu.async.service = ha->service;
  3767. ha->dvr.eu.async.status = ha->status;
  3768. ha->dvr.eu.async.info = ha->info;
  3769. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3770. }
  3771. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3772. gdth_log_event( &ha->dvr, NULL );
  3773. /* new host drive from expand? */
  3774. if (ha->service == CACHESERVICE && ha->status == 56) {
  3775. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3776. (ushort)ha->info));
  3777. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3778. }
  3779. }
  3780. return 1;
  3781. }
  3782. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3783. {
  3784. gdth_stackframe stack;
  3785. char *f = NULL;
  3786. int i,j;
  3787. TRACE2(("gdth_log_event()\n"));
  3788. if (dvr->size == 0) {
  3789. if (buffer == NULL) {
  3790. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3791. } else {
  3792. sprintf(buffer,"Adapter %d: %s\n",
  3793. dvr->eu.async.ionode,dvr->event_string);
  3794. }
  3795. } else if (dvr->eu.async.service == CACHESERVICE &&
  3796. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3797. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3798. dvr->eu.async.status));
  3799. f = async_cache_tab[dvr->eu.async.status];
  3800. /* i: parameter to push, j: stack element to fill */
  3801. for (j=0,i=1; i < f[0]; i+=2) {
  3802. switch (f[i+1]) {
  3803. case 4:
  3804. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3805. break;
  3806. case 2:
  3807. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3808. break;
  3809. case 1:
  3810. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3811. break;
  3812. default:
  3813. break;
  3814. }
  3815. }
  3816. if (buffer == NULL) {
  3817. printk(&f[(int)f[0]],stack);
  3818. printk("\n");
  3819. } else {
  3820. sprintf(buffer,&f[(int)f[0]],stack);
  3821. }
  3822. } else {
  3823. if (buffer == NULL) {
  3824. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3825. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3826. } else {
  3827. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3828. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3829. }
  3830. }
  3831. }
  3832. #ifdef GDTH_STATISTICS
  3833. static void gdth_timeout(ulong data)
  3834. {
  3835. ulong32 i;
  3836. Scsi_Cmnd *nscp;
  3837. gdth_ha_str *ha;
  3838. ulong flags;
  3839. int hanum = 0;
  3840. ha = HADATA(gdth_ctr_tab[hanum]);
  3841. spin_lock_irqsave(&ha->smp_lock, flags);
  3842. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3843. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3844. ++act_stats;
  3845. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3846. ++act_rq;
  3847. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3848. act_ints, act_ios, act_stats, act_rq));
  3849. act_ints = act_ios = 0;
  3850. gdth_timer.expires = jiffies + 30 * HZ;
  3851. add_timer(&gdth_timer);
  3852. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3853. }
  3854. #endif
  3855. static void __init internal_setup(char *str,int *ints)
  3856. {
  3857. int i, argc;
  3858. char *cur_str, *argv;
  3859. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3860. str ? str:"NULL", ints ? ints[0]:0));
  3861. /* read irq[] from ints[] */
  3862. if (ints) {
  3863. argc = ints[0];
  3864. if (argc > 0) {
  3865. if (argc > MAXHA)
  3866. argc = MAXHA;
  3867. for (i = 0; i < argc; ++i)
  3868. irq[i] = ints[i+1];
  3869. }
  3870. }
  3871. /* analyse string */
  3872. argv = str;
  3873. while (argv && (cur_str = strchr(argv, ':'))) {
  3874. int val = 0, c = *++cur_str;
  3875. if (c == 'n' || c == 'N')
  3876. val = 0;
  3877. else if (c == 'y' || c == 'Y')
  3878. val = 1;
  3879. else
  3880. val = (int)simple_strtoul(cur_str, NULL, 0);
  3881. if (!strncmp(argv, "disable:", 8))
  3882. disable = val;
  3883. else if (!strncmp(argv, "reserve_mode:", 13))
  3884. reserve_mode = val;
  3885. else if (!strncmp(argv, "reverse_scan:", 13))
  3886. reverse_scan = val;
  3887. else if (!strncmp(argv, "hdr_channel:", 12))
  3888. hdr_channel = val;
  3889. else if (!strncmp(argv, "max_ids:", 8))
  3890. max_ids = val;
  3891. else if (!strncmp(argv, "rescan:", 7))
  3892. rescan = val;
  3893. else if (!strncmp(argv, "virt_ctr:", 9))
  3894. virt_ctr = val;
  3895. else if (!strncmp(argv, "shared_access:", 14))
  3896. shared_access = val;
  3897. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3898. probe_eisa_isa = val;
  3899. else if (!strncmp(argv, "reserve_list:", 13)) {
  3900. reserve_list[0] = val;
  3901. for (i = 1; i < MAX_RES_ARGS; i++) {
  3902. cur_str = strchr(cur_str, ',');
  3903. if (!cur_str)
  3904. break;
  3905. if (!isdigit((int)*++cur_str)) {
  3906. --cur_str;
  3907. break;
  3908. }
  3909. reserve_list[i] =
  3910. (int)simple_strtoul(cur_str, NULL, 0);
  3911. }
  3912. if (!cur_str)
  3913. break;
  3914. argv = ++cur_str;
  3915. continue;
  3916. }
  3917. if ((argv = strchr(argv, ',')))
  3918. ++argv;
  3919. }
  3920. }
  3921. int __init option_setup(char *str)
  3922. {
  3923. int ints[MAXHA];
  3924. char *cur = str;
  3925. int i = 1;
  3926. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3927. while (cur && isdigit(*cur) && i <= MAXHA) {
  3928. ints[i++] = simple_strtoul(cur, NULL, 0);
  3929. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3930. }
  3931. ints[0] = i - 1;
  3932. internal_setup(cur, ints);
  3933. return 1;
  3934. }
  3935. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  3936. static int __init gdth_detect(struct scsi_host_template *shtp)
  3937. #else
  3938. static int __init gdth_detect(Scsi_Host_Template *shtp)
  3939. #endif
  3940. {
  3941. struct Scsi_Host *shp;
  3942. gdth_pci_str pcistr[MAXHA];
  3943. gdth_ha_str *ha;
  3944. ushort eisa_slot;
  3945. int i,hanum,cnt,ctr,err;
  3946. unchar b;
  3947. #ifdef DEBUG_GDTH
  3948. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3949. DebugState);
  3950. printk(" Destination of debugging information: ");
  3951. #ifdef __SERIAL__
  3952. #ifdef __COM2__
  3953. printk("Serial port COM2\n");
  3954. #else
  3955. printk("Serial port COM1\n");
  3956. #endif
  3957. #else
  3958. printk("Console\n");
  3959. #endif
  3960. gdth_delay(3000);
  3961. #endif
  3962. TRACE(("gdth_detect()\n"));
  3963. if (disable) {
  3964. printk("GDT-HA: Controller driver disabled from command line !\n");
  3965. return 0;
  3966. }
  3967. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
  3968. /* initializations */
  3969. gdth_polling = TRUE; b = 0;
  3970. gdth_clear_events();
  3971. /* As default we do not probe for EISA or ISA controllers */
  3972. if (probe_eisa_isa) {
  3973. /* scanning for controllers, at first: ISA controller */
  3974. #ifdef CONFIG_ISA
  3975. ulong32 isa_bios;
  3976. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  3977. isa_bios += 0x8000UL) {
  3978. if (gdth_ctr_count >= MAXHA)
  3979. break;
  3980. gdth_isa_probe_one(shtp, isa_bios);
  3981. }
  3982. #endif
  3983. for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
  3984. dma_addr_t scratch_dma_handle;
  3985. scratch_dma_handle = 0;
  3986. if (gdth_ctr_count >= MAXHA)
  3987. break;
  3988. if (gdth_search_eisa(eisa_slot)) { /* controller found */
  3989. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  3990. if (shp == NULL)
  3991. continue;
  3992. ha = HADATA(shp);
  3993. if (!gdth_init_eisa(eisa_slot,ha)) {
  3994. scsi_unregister(shp);
  3995. continue;
  3996. }
  3997. /* controller found and initialized */
  3998. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  3999. eisa_slot>>12,ha->irq);
  4000. if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
  4001. printk("GDT-EISA: Unable to allocate IRQ\n");
  4002. scsi_unregister(shp);
  4003. continue;
  4004. }
  4005. shp->unchecked_isa_dma = 0;
  4006. shp->irq = ha->irq;
  4007. shp->dma_channel = 0xff;
  4008. hanum = gdth_ctr_count;
  4009. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4010. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4011. NUMDATA(shp)->hanum = (ushort)hanum;
  4012. NUMDATA(shp)->busnum= 0;
  4013. TRACE2(("EISA detect Bus 0: hanum %d\n",
  4014. NUMDATA(shp)->hanum));
  4015. ha->pccb = CMDDATA(shp);
  4016. ha->ccb_phys = 0L;
  4017. ha->pdev = NULL;
  4018. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4019. &scratch_dma_handle);
  4020. ha->scratch_phys = scratch_dma_handle;
  4021. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4022. &scratch_dma_handle);
  4023. ha->msg_phys = scratch_dma_handle;
  4024. #ifdef INT_COAL
  4025. ha->coal_stat = (gdth_coal_status *)
  4026. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4027. MAXOFFSETS, &scratch_dma_handle);
  4028. ha->coal_stat_phys = scratch_dma_handle;
  4029. #endif
  4030. ha->ccb_phys =
  4031. pci_map_single(ha->pdev,ha->pccb,
  4032. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4033. ha->scratch_busy = FALSE;
  4034. ha->req_first = NULL;
  4035. ha->tid_cnt = MAX_HDRIVES;
  4036. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4037. ha->tid_cnt = max_ids;
  4038. for (i=0; i<GDTH_MAXCMDS; ++i)
  4039. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4040. ha->scan_mode = rescan ? 0x10 : 0;
  4041. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4042. !gdth_search_drives(hanum)) {
  4043. printk("GDT-EISA: Error during device scan\n");
  4044. --gdth_ctr_count;
  4045. --gdth_ctr_vcount;
  4046. #ifdef INT_COAL
  4047. if (ha->coal_stat)
  4048. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4049. MAXOFFSETS, ha->coal_stat,
  4050. ha->coal_stat_phys);
  4051. #endif
  4052. if (ha->pscratch)
  4053. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4054. ha->pscratch, ha->scratch_phys);
  4055. if (ha->pmsg)
  4056. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4057. ha->pmsg, ha->msg_phys);
  4058. if (ha->ccb_phys)
  4059. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4060. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4061. free_irq(ha->irq,ha);
  4062. scsi_unregister(shp);
  4063. continue;
  4064. }
  4065. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4066. hdr_channel = ha->bus_cnt;
  4067. ha->virt_bus = hdr_channel;
  4068. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  4069. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4070. shp->highmem_io = 0;
  4071. #endif
  4072. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4073. shp->max_cmd_len = 16;
  4074. shp->max_id = ha->tid_cnt;
  4075. shp->max_lun = MAXLUN;
  4076. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4077. if (virt_ctr) {
  4078. virt_ctr = 1;
  4079. /* register addit. SCSI channels as virtual controllers */
  4080. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4081. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4082. shp->unchecked_isa_dma = 0;
  4083. shp->irq = ha->irq;
  4084. shp->dma_channel = 0xff;
  4085. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4086. NUMDATA(shp)->hanum = (ushort)hanum;
  4087. NUMDATA(shp)->busnum = b;
  4088. }
  4089. }
  4090. spin_lock_init(&ha->smp_lock);
  4091. gdth_enable_int(hanum);
  4092. }
  4093. }
  4094. }
  4095. /* scanning for PCI controllers */
  4096. cnt = gdth_search_pci(pcistr);
  4097. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  4098. gdth_sort_pci(pcistr,cnt);
  4099. for (ctr = 0; ctr < cnt; ++ctr) {
  4100. dma_addr_t scratch_dma_handle;
  4101. scratch_dma_handle = 0;
  4102. if (gdth_ctr_count >= MAXHA)
  4103. break;
  4104. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4105. if (shp == NULL)
  4106. continue;
  4107. ha = HADATA(shp);
  4108. if (!gdth_init_pci(&pcistr[ctr],ha)) {
  4109. scsi_unregister(shp);
  4110. continue;
  4111. }
  4112. /* controller found and initialized */
  4113. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4114. pcistr[ctr].pdev->bus->number,
  4115. PCI_SLOT(pcistr[ctr].pdev->devfn), ha->irq);
  4116. if (request_irq(ha->irq, gdth_interrupt,
  4117. IRQF_DISABLED|IRQF_SHARED, "gdth", ha))
  4118. {
  4119. printk("GDT-PCI: Unable to allocate IRQ\n");
  4120. scsi_unregister(shp);
  4121. continue;
  4122. }
  4123. shp->unchecked_isa_dma = 0;
  4124. shp->irq = ha->irq;
  4125. shp->dma_channel = 0xff;
  4126. hanum = gdth_ctr_count;
  4127. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4128. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4129. NUMDATA(shp)->hanum = (ushort)hanum;
  4130. NUMDATA(shp)->busnum= 0;
  4131. ha->pccb = CMDDATA(shp);
  4132. ha->ccb_phys = 0L;
  4133. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4134. &scratch_dma_handle);
  4135. ha->scratch_phys = scratch_dma_handle;
  4136. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4137. &scratch_dma_handle);
  4138. ha->msg_phys = scratch_dma_handle;
  4139. #ifdef INT_COAL
  4140. ha->coal_stat = (gdth_coal_status *)
  4141. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4142. MAXOFFSETS, &scratch_dma_handle);
  4143. ha->coal_stat_phys = scratch_dma_handle;
  4144. #endif
  4145. ha->scratch_busy = FALSE;
  4146. ha->req_first = NULL;
  4147. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4148. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4149. ha->tid_cnt = max_ids;
  4150. for (i=0; i<GDTH_MAXCMDS; ++i)
  4151. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4152. ha->scan_mode = rescan ? 0x10 : 0;
  4153. err = FALSE;
  4154. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4155. !gdth_search_drives(hanum)) {
  4156. err = TRUE;
  4157. } else {
  4158. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4159. hdr_channel = ha->bus_cnt;
  4160. ha->virt_bus = hdr_channel;
  4161. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4162. scsi_set_pci_device(shp, pcistr[ctr].pdev);
  4163. #endif
  4164. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
  4165. /* 64-bit DMA only supported from FW >= x.43 */
  4166. (!ha->dma64_support)) {
  4167. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4168. printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
  4169. err = TRUE;
  4170. }
  4171. } else {
  4172. shp->max_cmd_len = 16;
  4173. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4174. printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
  4175. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4176. printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
  4177. err = TRUE;
  4178. }
  4179. }
  4180. }
  4181. if (err) {
  4182. printk("GDT-PCI %d: Error during device scan\n", hanum);
  4183. --gdth_ctr_count;
  4184. --gdth_ctr_vcount;
  4185. #ifdef INT_COAL
  4186. if (ha->coal_stat)
  4187. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4188. MAXOFFSETS, ha->coal_stat,
  4189. ha->coal_stat_phys);
  4190. #endif
  4191. if (ha->pscratch)
  4192. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4193. ha->pscratch, ha->scratch_phys);
  4194. if (ha->pmsg)
  4195. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4196. ha->pmsg, ha->msg_phys);
  4197. free_irq(ha->irq,ha);
  4198. scsi_unregister(shp);
  4199. continue;
  4200. }
  4201. shp->max_id = ha->tid_cnt;
  4202. shp->max_lun = MAXLUN;
  4203. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4204. if (virt_ctr) {
  4205. virt_ctr = 1;
  4206. /* register addit. SCSI channels as virtual controllers */
  4207. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4208. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4209. shp->unchecked_isa_dma = 0;
  4210. shp->irq = ha->irq;
  4211. shp->dma_channel = 0xff;
  4212. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4213. NUMDATA(shp)->hanum = (ushort)hanum;
  4214. NUMDATA(shp)->busnum = b;
  4215. }
  4216. }
  4217. spin_lock_init(&ha->smp_lock);
  4218. gdth_enable_int(hanum);
  4219. }
  4220. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  4221. if (gdth_ctr_count > 0) {
  4222. #ifdef GDTH_STATISTICS
  4223. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4224. init_timer(&gdth_timer);
  4225. gdth_timer.expires = jiffies + HZ;
  4226. gdth_timer.data = 0L;
  4227. gdth_timer.function = gdth_timeout;
  4228. add_timer(&gdth_timer);
  4229. #endif
  4230. major = register_chrdev(0,"gdth",&gdth_fops);
  4231. notifier_disabled = 0;
  4232. register_reboot_notifier(&gdth_notifier);
  4233. }
  4234. gdth_polling = FALSE;
  4235. return gdth_ctr_vcount;
  4236. }
  4237. static int gdth_release(struct Scsi_Host *shp)
  4238. {
  4239. int hanum;
  4240. gdth_ha_str *ha;
  4241. TRACE2(("gdth_release()\n"));
  4242. if (NUMDATA(shp)->busnum == 0) {
  4243. hanum = NUMDATA(shp)->hanum;
  4244. ha = HADATA(gdth_ctr_tab[hanum]);
  4245. if (ha->sdev) {
  4246. scsi_free_host_dev(ha->sdev);
  4247. ha->sdev = NULL;
  4248. }
  4249. gdth_flush(hanum);
  4250. if (shp->irq) {
  4251. free_irq(shp->irq,ha);
  4252. }
  4253. #ifdef CONFIG_ISA
  4254. if (shp->dma_channel != 0xff) {
  4255. free_dma(shp->dma_channel);
  4256. }
  4257. #endif
  4258. #ifdef INT_COAL
  4259. if (ha->coal_stat)
  4260. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4261. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4262. #endif
  4263. if (ha->pscratch)
  4264. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4265. ha->pscratch, ha->scratch_phys);
  4266. if (ha->pmsg)
  4267. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4268. ha->pmsg, ha->msg_phys);
  4269. if (ha->ccb_phys)
  4270. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4271. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4272. gdth_ctr_released++;
  4273. TRACE2(("gdth_release(): HA %d of %d\n",
  4274. gdth_ctr_released, gdth_ctr_count));
  4275. if (gdth_ctr_released == gdth_ctr_count) {
  4276. #ifdef GDTH_STATISTICS
  4277. del_timer(&gdth_timer);
  4278. #endif
  4279. unregister_chrdev(major,"gdth");
  4280. unregister_reboot_notifier(&gdth_notifier);
  4281. }
  4282. }
  4283. scsi_unregister(shp);
  4284. return 0;
  4285. }
  4286. static const char *gdth_ctr_name(int hanum)
  4287. {
  4288. gdth_ha_str *ha;
  4289. TRACE2(("gdth_ctr_name()\n"));
  4290. ha = HADATA(gdth_ctr_tab[hanum]);
  4291. if (ha->type == GDT_EISA) {
  4292. switch (ha->stype) {
  4293. case GDT3_ID:
  4294. return("GDT3000/3020");
  4295. case GDT3A_ID:
  4296. return("GDT3000A/3020A/3050A");
  4297. case GDT3B_ID:
  4298. return("GDT3000B/3010A");
  4299. }
  4300. } else if (ha->type == GDT_ISA) {
  4301. return("GDT2000/2020");
  4302. } else if (ha->type == GDT_PCI) {
  4303. switch (ha->pdev->device) {
  4304. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  4305. return("GDT6000/6020/6050");
  4306. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  4307. return("GDT6000B/6010");
  4308. }
  4309. }
  4310. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  4311. return("");
  4312. }
  4313. static const char *gdth_info(struct Scsi_Host *shp)
  4314. {
  4315. int hanum;
  4316. gdth_ha_str *ha;
  4317. TRACE2(("gdth_info()\n"));
  4318. hanum = NUMDATA(shp)->hanum;
  4319. ha = HADATA(gdth_ctr_tab[hanum]);
  4320. return ((const char *)ha->binfo.type_string);
  4321. }
  4322. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  4323. {
  4324. int i, hanum;
  4325. gdth_ha_str *ha;
  4326. ulong flags;
  4327. Scsi_Cmnd *cmnd;
  4328. unchar b;
  4329. TRACE2(("gdth_eh_bus_reset()\n"));
  4330. hanum = NUMDATA(scp->device->host)->hanum;
  4331. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  4332. ha = HADATA(gdth_ctr_tab[hanum]);
  4333. /* clear command tab */
  4334. spin_lock_irqsave(&ha->smp_lock, flags);
  4335. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  4336. cmnd = ha->cmd_tab[i].cmnd;
  4337. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  4338. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4339. }
  4340. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4341. if (b == ha->virt_bus) {
  4342. /* host drives */
  4343. for (i = 0; i < MAX_HDRIVES; ++i) {
  4344. if (ha->hdr[i].present) {
  4345. spin_lock_irqsave(&ha->smp_lock, flags);
  4346. gdth_polling = TRUE;
  4347. while (gdth_test_busy(hanum))
  4348. gdth_delay(0);
  4349. if (gdth_internal_cmd(hanum, CACHESERVICE,
  4350. GDT_CLUST_RESET, i, 0, 0))
  4351. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  4352. gdth_polling = FALSE;
  4353. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4354. }
  4355. }
  4356. } else {
  4357. /* raw devices */
  4358. spin_lock_irqsave(&ha->smp_lock, flags);
  4359. for (i = 0; i < MAXID; ++i)
  4360. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  4361. gdth_polling = TRUE;
  4362. while (gdth_test_busy(hanum))
  4363. gdth_delay(0);
  4364. gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
  4365. BUS_L2P(ha,b), 0, 0);
  4366. gdth_polling = FALSE;
  4367. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4368. }
  4369. return SUCCESS;
  4370. }
  4371. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4372. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  4373. #else
  4374. static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
  4375. #endif
  4376. {
  4377. unchar b, t;
  4378. int hanum;
  4379. gdth_ha_str *ha;
  4380. struct scsi_device *sd;
  4381. unsigned capacity;
  4382. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4383. sd = sdev;
  4384. capacity = cap;
  4385. #else
  4386. sd = disk->device;
  4387. capacity = disk->capacity;
  4388. #endif
  4389. hanum = NUMDATA(sd->host)->hanum;
  4390. b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
  4391. t = sd->id;
  4392. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
  4393. ha = HADATA(gdth_ctr_tab[hanum]);
  4394. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  4395. /* raw device or host drive without mapping information */
  4396. TRACE2(("Evaluate mapping\n"));
  4397. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  4398. } else {
  4399. ip[0] = ha->hdr[t].heads;
  4400. ip[1] = ha->hdr[t].secs;
  4401. ip[2] = capacity / ip[0] / ip[1];
  4402. }
  4403. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  4404. ip[0],ip[1],ip[2]));
  4405. return 0;
  4406. }
  4407. static int gdth_queuecommand(struct scsi_cmnd *scp,
  4408. void (*done)(struct scsi_cmnd *))
  4409. {
  4410. int hanum;
  4411. int priority;
  4412. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  4413. scp->scsi_done = done;
  4414. scp->SCp.have_data_in = 1;
  4415. scp->SCp.phase = -1;
  4416. scp->SCp.sent_command = -1;
  4417. scp->SCp.Status = GDTH_MAP_NONE;
  4418. scp->SCp.buffer = (struct scatterlist *)NULL;
  4419. hanum = NUMDATA(scp->device->host)->hanum;
  4420. #ifdef GDTH_STATISTICS
  4421. ++act_ios;
  4422. #endif
  4423. priority = DEFAULT_PRI;
  4424. if (IS_GDTH_INTERNAL_CMD(scp))
  4425. priority = scp->SCp.this_residual;
  4426. else
  4427. gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
  4428. gdth_putq( hanum, scp, priority );
  4429. gdth_next( hanum );
  4430. return 0;
  4431. }
  4432. static int gdth_open(struct inode *inode, struct file *filep)
  4433. {
  4434. gdth_ha_str *ha;
  4435. int i;
  4436. for (i = 0; i < gdth_ctr_count; i++) {
  4437. ha = HADATA(gdth_ctr_tab[i]);
  4438. if (!ha->sdev)
  4439. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  4440. }
  4441. TRACE(("gdth_open()\n"));
  4442. return 0;
  4443. }
  4444. static int gdth_close(struct inode *inode, struct file *filep)
  4445. {
  4446. TRACE(("gdth_close()\n"));
  4447. return 0;
  4448. }
  4449. static int ioc_event(void __user *arg)
  4450. {
  4451. gdth_ioctl_event evt;
  4452. gdth_ha_str *ha;
  4453. ulong flags;
  4454. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  4455. evt.ionode >= gdth_ctr_count)
  4456. return -EFAULT;
  4457. ha = HADATA(gdth_ctr_tab[evt.ionode]);
  4458. if (evt.erase == 0xff) {
  4459. if (evt.event.event_source == ES_TEST)
  4460. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  4461. else if (evt.event.event_source == ES_DRIVER)
  4462. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  4463. else if (evt.event.event_source == ES_SYNC)
  4464. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  4465. else
  4466. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  4467. spin_lock_irqsave(&ha->smp_lock, flags);
  4468. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  4469. &evt.event.event_data);
  4470. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4471. } else if (evt.erase == 0xfe) {
  4472. gdth_clear_events();
  4473. } else if (evt.erase == 0) {
  4474. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  4475. } else {
  4476. gdth_readapp_event(ha, evt.erase, &evt.event);
  4477. }
  4478. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  4479. return -EFAULT;
  4480. return 0;
  4481. }
  4482. static int ioc_lockdrv(void __user *arg)
  4483. {
  4484. gdth_ioctl_lockdrv ldrv;
  4485. unchar i, j;
  4486. ulong flags;
  4487. gdth_ha_str *ha;
  4488. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  4489. ldrv.ionode >= gdth_ctr_count)
  4490. return -EFAULT;
  4491. ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
  4492. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  4493. j = ldrv.drives[i];
  4494. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  4495. continue;
  4496. if (ldrv.lock) {
  4497. spin_lock_irqsave(&ha->smp_lock, flags);
  4498. ha->hdr[j].lock = 1;
  4499. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4500. gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
  4501. gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
  4502. } else {
  4503. spin_lock_irqsave(&ha->smp_lock, flags);
  4504. ha->hdr[j].lock = 0;
  4505. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4506. gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
  4507. gdth_next(ldrv.ionode);
  4508. }
  4509. }
  4510. return 0;
  4511. }
  4512. static int ioc_resetdrv(void __user *arg, char *cmnd)
  4513. {
  4514. gdth_ioctl_reset res;
  4515. gdth_cmd_str cmd;
  4516. int hanum;
  4517. gdth_ha_str *ha;
  4518. int rval;
  4519. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  4520. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  4521. return -EFAULT;
  4522. hanum = res.ionode;
  4523. ha = HADATA(gdth_ctr_tab[hanum]);
  4524. if (!ha->hdr[res.number].present)
  4525. return 0;
  4526. memset(&cmd, 0, sizeof(gdth_cmd_str));
  4527. cmd.Service = CACHESERVICE;
  4528. cmd.OpCode = GDT_CLUST_RESET;
  4529. if (ha->cache_feat & GDT_64BIT)
  4530. cmd.u.cache64.DeviceNo = res.number;
  4531. else
  4532. cmd.u.cache.DeviceNo = res.number;
  4533. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  4534. if (rval < 0)
  4535. return rval;
  4536. res.status = rval;
  4537. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  4538. return -EFAULT;
  4539. return 0;
  4540. }
  4541. static int ioc_general(void __user *arg, char *cmnd)
  4542. {
  4543. gdth_ioctl_general gen;
  4544. char *buf = NULL;
  4545. ulong64 paddr;
  4546. int hanum;
  4547. gdth_ha_str *ha;
  4548. int rval;
  4549. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  4550. gen.ionode >= gdth_ctr_count)
  4551. return -EFAULT;
  4552. hanum = gen.ionode;
  4553. ha = HADATA(gdth_ctr_tab[hanum]);
  4554. if (gen.data_len + gen.sense_len != 0) {
  4555. if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
  4556. FALSE, &paddr)))
  4557. return -EFAULT;
  4558. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  4559. gen.data_len + gen.sense_len)) {
  4560. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4561. return -EFAULT;
  4562. }
  4563. if (gen.command.OpCode == GDT_IOCTL) {
  4564. gen.command.u.ioctl.p_param = paddr;
  4565. } else if (gen.command.Service == CACHESERVICE) {
  4566. if (ha->cache_feat & GDT_64BIT) {
  4567. /* copy elements from 32-bit IOCTL structure */
  4568. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  4569. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  4570. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  4571. /* addresses */
  4572. if (ha->cache_feat & SCATTER_GATHER) {
  4573. gen.command.u.cache64.DestAddr = (ulong64)-1;
  4574. gen.command.u.cache64.sg_canz = 1;
  4575. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  4576. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  4577. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  4578. } else {
  4579. gen.command.u.cache64.DestAddr = paddr;
  4580. gen.command.u.cache64.sg_canz = 0;
  4581. }
  4582. } else {
  4583. if (ha->cache_feat & SCATTER_GATHER) {
  4584. gen.command.u.cache.DestAddr = 0xffffffff;
  4585. gen.command.u.cache.sg_canz = 1;
  4586. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  4587. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  4588. gen.command.u.cache.sg_lst[1].sg_len = 0;
  4589. } else {
  4590. gen.command.u.cache.DestAddr = paddr;
  4591. gen.command.u.cache.sg_canz = 0;
  4592. }
  4593. }
  4594. } else if (gen.command.Service == SCSIRAWSERVICE) {
  4595. if (ha->raw_feat & GDT_64BIT) {
  4596. /* copy elements from 32-bit IOCTL structure */
  4597. char cmd[16];
  4598. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  4599. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  4600. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  4601. gen.command.u.raw64.target = gen.command.u.raw.target;
  4602. memcpy(cmd, gen.command.u.raw.cmd, 16);
  4603. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  4604. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  4605. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  4606. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  4607. /* addresses */
  4608. if (ha->raw_feat & SCATTER_GATHER) {
  4609. gen.command.u.raw64.sdata = (ulong64)-1;
  4610. gen.command.u.raw64.sg_ranz = 1;
  4611. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  4612. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  4613. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  4614. } else {
  4615. gen.command.u.raw64.sdata = paddr;
  4616. gen.command.u.raw64.sg_ranz = 0;
  4617. }
  4618. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  4619. } else {
  4620. if (ha->raw_feat & SCATTER_GATHER) {
  4621. gen.command.u.raw.sdata = 0xffffffff;
  4622. gen.command.u.raw.sg_ranz = 1;
  4623. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  4624. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  4625. gen.command.u.raw.sg_lst[1].sg_len = 0;
  4626. } else {
  4627. gen.command.u.raw.sdata = paddr;
  4628. gen.command.u.raw.sg_ranz = 0;
  4629. }
  4630. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  4631. }
  4632. } else {
  4633. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4634. return -EFAULT;
  4635. }
  4636. }
  4637. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  4638. if (rval < 0)
  4639. return rval;
  4640. gen.status = rval;
  4641. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  4642. gen.data_len + gen.sense_len)) {
  4643. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4644. return -EFAULT;
  4645. }
  4646. if (copy_to_user(arg, &gen,
  4647. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  4648. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4649. return -EFAULT;
  4650. }
  4651. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4652. return 0;
  4653. }
  4654. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4655. {
  4656. gdth_ioctl_rescan *rsc;
  4657. gdth_cmd_str *cmd;
  4658. gdth_ha_str *ha;
  4659. unchar i;
  4660. int hanum, rc = -ENOMEM;
  4661. u32 cluster_type = 0;
  4662. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4663. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4664. if (!rsc || !cmd)
  4665. goto free_fail;
  4666. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4667. rsc->ionode >= gdth_ctr_count) {
  4668. rc = -EFAULT;
  4669. goto free_fail;
  4670. }
  4671. hanum = rsc->ionode;
  4672. ha = HADATA(gdth_ctr_tab[hanum]);
  4673. memset(cmd, 0, sizeof(gdth_cmd_str));
  4674. for (i = 0; i < MAX_HDRIVES; ++i) {
  4675. if (!ha->hdr[i].present) {
  4676. rsc->hdr_list[i].bus = 0xff;
  4677. continue;
  4678. }
  4679. rsc->hdr_list[i].bus = ha->virt_bus;
  4680. rsc->hdr_list[i].target = i;
  4681. rsc->hdr_list[i].lun = 0;
  4682. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4683. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4684. cmd->Service = CACHESERVICE;
  4685. cmd->OpCode = GDT_CLUST_INFO;
  4686. if (ha->cache_feat & GDT_64BIT)
  4687. cmd->u.cache64.DeviceNo = i;
  4688. else
  4689. cmd->u.cache.DeviceNo = i;
  4690. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  4691. rsc->hdr_list[i].cluster_type = cluster_type;
  4692. }
  4693. }
  4694. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4695. rc = -EFAULT;
  4696. else
  4697. rc = 0;
  4698. free_fail:
  4699. kfree(rsc);
  4700. kfree(cmd);
  4701. return rc;
  4702. }
  4703. static int ioc_rescan(void __user *arg, char *cmnd)
  4704. {
  4705. gdth_ioctl_rescan *rsc;
  4706. gdth_cmd_str *cmd;
  4707. ushort i, status, hdr_cnt;
  4708. ulong32 info;
  4709. int hanum, cyls, hds, secs;
  4710. int rc = -ENOMEM;
  4711. ulong flags;
  4712. gdth_ha_str *ha;
  4713. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4714. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4715. if (!cmd || !rsc)
  4716. goto free_fail;
  4717. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4718. rsc->ionode >= gdth_ctr_count) {
  4719. rc = -EFAULT;
  4720. goto free_fail;
  4721. }
  4722. hanum = rsc->ionode;
  4723. ha = HADATA(gdth_ctr_tab[hanum]);
  4724. memset(cmd, 0, sizeof(gdth_cmd_str));
  4725. if (rsc->flag == 0) {
  4726. /* old method: re-init. cache service */
  4727. cmd->Service = CACHESERVICE;
  4728. if (ha->cache_feat & GDT_64BIT) {
  4729. cmd->OpCode = GDT_X_INIT_HOST;
  4730. cmd->u.cache64.DeviceNo = LINUX_OS;
  4731. } else {
  4732. cmd->OpCode = GDT_INIT;
  4733. cmd->u.cache.DeviceNo = LINUX_OS;
  4734. }
  4735. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4736. i = 0;
  4737. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4738. } else {
  4739. i = rsc->hdr_no;
  4740. hdr_cnt = i + 1;
  4741. }
  4742. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4743. cmd->Service = CACHESERVICE;
  4744. cmd->OpCode = GDT_INFO;
  4745. if (ha->cache_feat & GDT_64BIT)
  4746. cmd->u.cache64.DeviceNo = i;
  4747. else
  4748. cmd->u.cache.DeviceNo = i;
  4749. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4750. spin_lock_irqsave(&ha->smp_lock, flags);
  4751. rsc->hdr_list[i].bus = ha->virt_bus;
  4752. rsc->hdr_list[i].target = i;
  4753. rsc->hdr_list[i].lun = 0;
  4754. if (status != S_OK) {
  4755. ha->hdr[i].present = FALSE;
  4756. } else {
  4757. ha->hdr[i].present = TRUE;
  4758. ha->hdr[i].size = info;
  4759. /* evaluate mapping */
  4760. ha->hdr[i].size &= ~SECS32;
  4761. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4762. ha->hdr[i].heads = hds;
  4763. ha->hdr[i].secs = secs;
  4764. /* round size */
  4765. ha->hdr[i].size = cyls * hds * secs;
  4766. }
  4767. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4768. if (status != S_OK)
  4769. continue;
  4770. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4771. /* but we need ha->info2, not yet stored in scp->SCp */
  4772. /* devtype, cluster info, R/W attribs */
  4773. cmd->Service = CACHESERVICE;
  4774. cmd->OpCode = GDT_DEVTYPE;
  4775. if (ha->cache_feat & GDT_64BIT)
  4776. cmd->u.cache64.DeviceNo = i;
  4777. else
  4778. cmd->u.cache.DeviceNo = i;
  4779. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4780. spin_lock_irqsave(&ha->smp_lock, flags);
  4781. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4782. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4783. cmd->Service = CACHESERVICE;
  4784. cmd->OpCode = GDT_CLUST_INFO;
  4785. if (ha->cache_feat & GDT_64BIT)
  4786. cmd->u.cache64.DeviceNo = i;
  4787. else
  4788. cmd->u.cache.DeviceNo = i;
  4789. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4790. spin_lock_irqsave(&ha->smp_lock, flags);
  4791. ha->hdr[i].cluster_type =
  4792. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4793. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4794. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4795. cmd->Service = CACHESERVICE;
  4796. cmd->OpCode = GDT_RW_ATTRIBS;
  4797. if (ha->cache_feat & GDT_64BIT)
  4798. cmd->u.cache64.DeviceNo = i;
  4799. else
  4800. cmd->u.cache.DeviceNo = i;
  4801. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4802. spin_lock_irqsave(&ha->smp_lock, flags);
  4803. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4804. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4805. }
  4806. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4807. rc = -EFAULT;
  4808. else
  4809. rc = 0;
  4810. free_fail:
  4811. kfree(rsc);
  4812. kfree(cmd);
  4813. return rc;
  4814. }
  4815. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4816. unsigned int cmd, unsigned long arg)
  4817. {
  4818. gdth_ha_str *ha;
  4819. Scsi_Cmnd *scp;
  4820. ulong flags;
  4821. char cmnd[MAX_COMMAND_SIZE];
  4822. void __user *argp = (void __user *)arg;
  4823. memset(cmnd, 0xff, 12);
  4824. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4825. switch (cmd) {
  4826. case GDTIOCTL_CTRCNT:
  4827. {
  4828. int cnt = gdth_ctr_count;
  4829. if (put_user(cnt, (int __user *)argp))
  4830. return -EFAULT;
  4831. break;
  4832. }
  4833. case GDTIOCTL_DRVERS:
  4834. {
  4835. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4836. if (put_user(ver, (int __user *)argp))
  4837. return -EFAULT;
  4838. break;
  4839. }
  4840. case GDTIOCTL_OSVERS:
  4841. {
  4842. gdth_ioctl_osvers osv;
  4843. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4844. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4845. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4846. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4847. return -EFAULT;
  4848. break;
  4849. }
  4850. case GDTIOCTL_CTRTYPE:
  4851. {
  4852. gdth_ioctl_ctrtype ctrt;
  4853. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4854. ctrt.ionode >= gdth_ctr_count)
  4855. return -EFAULT;
  4856. ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
  4857. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4858. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4859. } else {
  4860. if (ha->type != GDT_PCIMPR) {
  4861. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4862. } else {
  4863. ctrt.type =
  4864. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4865. if (ha->stype >= 0x300)
  4866. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4867. else
  4868. ctrt.ext_type = 0x6000 | ha->stype;
  4869. }
  4870. ctrt.device_id = ha->pdev->device;
  4871. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4872. }
  4873. ctrt.info = ha->brd_phys;
  4874. ctrt.oem_id = ha->oem_id;
  4875. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4876. return -EFAULT;
  4877. break;
  4878. }
  4879. case GDTIOCTL_GENERAL:
  4880. return ioc_general(argp, cmnd);
  4881. case GDTIOCTL_EVENT:
  4882. return ioc_event(argp);
  4883. case GDTIOCTL_LOCKDRV:
  4884. return ioc_lockdrv(argp);
  4885. case GDTIOCTL_LOCKCHN:
  4886. {
  4887. gdth_ioctl_lockchn lchn;
  4888. unchar i, j;
  4889. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4890. lchn.ionode >= gdth_ctr_count)
  4891. return -EFAULT;
  4892. ha = HADATA(gdth_ctr_tab[lchn.ionode]);
  4893. i = lchn.channel;
  4894. if (i < ha->bus_cnt) {
  4895. if (lchn.lock) {
  4896. spin_lock_irqsave(&ha->smp_lock, flags);
  4897. ha->raw[i].lock = 1;
  4898. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4899. for (j = 0; j < ha->tid_cnt; ++j) {
  4900. gdth_wait_completion(lchn.ionode, i, j);
  4901. gdth_stop_timeout(lchn.ionode, i, j);
  4902. }
  4903. } else {
  4904. spin_lock_irqsave(&ha->smp_lock, flags);
  4905. ha->raw[i].lock = 0;
  4906. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4907. for (j = 0; j < ha->tid_cnt; ++j) {
  4908. gdth_start_timeout(lchn.ionode, i, j);
  4909. gdth_next(lchn.ionode);
  4910. }
  4911. }
  4912. }
  4913. break;
  4914. }
  4915. case GDTIOCTL_RESCAN:
  4916. return ioc_rescan(argp, cmnd);
  4917. case GDTIOCTL_HDRLIST:
  4918. return ioc_hdrlist(argp, cmnd);
  4919. case GDTIOCTL_RESET_BUS:
  4920. {
  4921. gdth_ioctl_reset res;
  4922. int hanum, rval;
  4923. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4924. res.ionode >= gdth_ctr_count)
  4925. return -EFAULT;
  4926. hanum = res.ionode;
  4927. ha = HADATA(gdth_ctr_tab[hanum]);
  4928. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4929. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4930. if (!scp)
  4931. return -ENOMEM;
  4932. scp->device = ha->sdev;
  4933. scp->cmd_len = 12;
  4934. scp->use_sg = 0;
  4935. scp->device->channel = virt_ctr ? 0 : res.number;
  4936. rval = gdth_eh_bus_reset(scp);
  4937. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4938. kfree(scp);
  4939. #else
  4940. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4941. if (!scp)
  4942. return -ENOMEM;
  4943. scp->cmd_len = 12;
  4944. scp->use_sg = 0;
  4945. scp->channel = virt_ctr ? 0 : res.number;
  4946. rval = gdth_eh_bus_reset(scp);
  4947. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4948. scsi_release_command(scp);
  4949. #endif
  4950. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4951. return -EFAULT;
  4952. break;
  4953. }
  4954. case GDTIOCTL_RESET_DRV:
  4955. return ioc_resetdrv(argp, cmnd);
  4956. default:
  4957. break;
  4958. }
  4959. return 0;
  4960. }
  4961. /* flush routine */
  4962. static void gdth_flush(int hanum)
  4963. {
  4964. int i;
  4965. gdth_ha_str *ha;
  4966. gdth_cmd_str gdtcmd;
  4967. char cmnd[MAX_COMMAND_SIZE];
  4968. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4969. TRACE2(("gdth_flush() hanum %d\n",hanum));
  4970. ha = HADATA(gdth_ctr_tab[hanum]);
  4971. for (i = 0; i < MAX_HDRIVES; ++i) {
  4972. if (ha->hdr[i].present) {
  4973. gdtcmd.BoardNode = LOCALBOARD;
  4974. gdtcmd.Service = CACHESERVICE;
  4975. gdtcmd.OpCode = GDT_FLUSH;
  4976. if (ha->cache_feat & GDT_64BIT) {
  4977. gdtcmd.u.cache64.DeviceNo = i;
  4978. gdtcmd.u.cache64.BlockNo = 1;
  4979. gdtcmd.u.cache64.sg_canz = 0;
  4980. } else {
  4981. gdtcmd.u.cache.DeviceNo = i;
  4982. gdtcmd.u.cache.BlockNo = 1;
  4983. gdtcmd.u.cache.sg_canz = 0;
  4984. }
  4985. TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
  4986. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
  4987. }
  4988. }
  4989. }
  4990. /* shutdown routine */
  4991. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4992. {
  4993. int hanum;
  4994. #ifndef __alpha__
  4995. gdth_cmd_str gdtcmd;
  4996. char cmnd[MAX_COMMAND_SIZE];
  4997. #endif
  4998. if (notifier_disabled)
  4999. return NOTIFY_OK;
  5000. TRACE2(("gdth_halt() event %d\n",(int)event));
  5001. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  5002. return NOTIFY_DONE;
  5003. notifier_disabled = 1;
  5004. printk("GDT-HA: Flushing all host drives .. ");
  5005. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  5006. gdth_flush(hanum);
  5007. #ifndef __alpha__
  5008. /* controller reset */
  5009. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5010. gdtcmd.BoardNode = LOCALBOARD;
  5011. gdtcmd.Service = CACHESERVICE;
  5012. gdtcmd.OpCode = GDT_RESET;
  5013. TRACE2(("gdth_halt(): reset controller %d\n", hanum));
  5014. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
  5015. #endif
  5016. }
  5017. printk("Done.\n");
  5018. #ifdef GDTH_STATISTICS
  5019. del_timer(&gdth_timer);
  5020. #endif
  5021. return NOTIFY_OK;
  5022. }
  5023. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5024. /* configure lun */
  5025. static int gdth_slave_configure(struct scsi_device *sdev)
  5026. {
  5027. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  5028. sdev->skip_ms_page_3f = 1;
  5029. sdev->skip_ms_page_8 = 1;
  5030. return 0;
  5031. }
  5032. #endif
  5033. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5034. static struct scsi_host_template driver_template = {
  5035. #else
  5036. static Scsi_Host_Template driver_template = {
  5037. #endif
  5038. .proc_name = "gdth",
  5039. .proc_info = gdth_proc_info,
  5040. .name = "GDT SCSI Disk Array Controller",
  5041. .detect = gdth_detect,
  5042. .release = gdth_release,
  5043. .info = gdth_info,
  5044. .queuecommand = gdth_queuecommand,
  5045. .eh_bus_reset_handler = gdth_eh_bus_reset,
  5046. .bios_param = gdth_bios_param,
  5047. .can_queue = GDTH_MAXCMDS,
  5048. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5049. .slave_configure = gdth_slave_configure,
  5050. #endif
  5051. .this_id = -1,
  5052. .sg_tablesize = GDTH_MAXSG,
  5053. .cmd_per_lun = GDTH_MAXC_P_L,
  5054. .unchecked_isa_dma = 1,
  5055. .use_clustering = ENABLE_CLUSTERING,
  5056. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  5057. .use_new_eh_code = 1,
  5058. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
  5059. .highmem_io = 1,
  5060. #endif
  5061. #endif
  5062. };
  5063. #ifdef CONFIG_ISA
  5064. static int gdth_isa_probe_one(struct scsi_host_template *shtp, ulong32 isa_bios)
  5065. {
  5066. struct Scsi_Host *shp;
  5067. gdth_ha_str *ha;
  5068. dma_addr_t scratch_dma_handle = 0;
  5069. int error, hanum, i;
  5070. u8 b;
  5071. if (!gdth_search_isa(isa_bios))
  5072. return -ENXIO;
  5073. shp = scsi_register(shtp, sizeof(gdth_ext_str));
  5074. if (!shp)
  5075. return -ENOMEM;
  5076. ha = HADATA(shp);
  5077. error = -ENODEV;
  5078. if (!gdth_init_isa(isa_bios,ha))
  5079. goto out_host_put;
  5080. /* controller found and initialized */
  5081. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  5082. isa_bios, ha->irq, ha->drq);
  5083. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  5084. if (error) {
  5085. printk("GDT-ISA: Unable to allocate IRQ\n");
  5086. goto out_host_put;
  5087. }
  5088. error = request_dma(ha->drq, "gdth");
  5089. if (error) {
  5090. printk("GDT-ISA: Unable to allocate DMA channel\n");
  5091. goto out_free_irq;
  5092. }
  5093. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  5094. enable_dma(ha->drq);
  5095. shp->unchecked_isa_dma = 1;
  5096. shp->irq = ha->irq;
  5097. shp->dma_channel = ha->drq;
  5098. hanum = gdth_ctr_count;
  5099. gdth_ctr_tab[gdth_ctr_count++] = shp;
  5100. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  5101. NUMDATA(shp)->hanum = (ushort)hanum;
  5102. NUMDATA(shp)->busnum= 0;
  5103. ha->pccb = CMDDATA(shp);
  5104. ha->ccb_phys = 0L;
  5105. ha->pdev = NULL;
  5106. error = -ENOMEM;
  5107. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  5108. &scratch_dma_handle);
  5109. if (!ha->pscratch)
  5110. goto out_dec_counters;
  5111. ha->scratch_phys = scratch_dma_handle;
  5112. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  5113. &scratch_dma_handle);
  5114. if (!ha->pmsg)
  5115. goto out_free_pscratch;
  5116. ha->msg_phys = scratch_dma_handle;
  5117. #ifdef INT_COAL
  5118. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  5119. sizeof(gdth_coal_status) * MAXOFFSETS,
  5120. &scratch_dma_handle);
  5121. if (!ha->coal_stat)
  5122. goto out_free_pmsg;
  5123. ha->coal_stat_phys = scratch_dma_handle;
  5124. #endif
  5125. ha->scratch_busy = FALSE;
  5126. ha->req_first = NULL;
  5127. ha->tid_cnt = MAX_HDRIVES;
  5128. if (max_ids > 0 && max_ids < ha->tid_cnt)
  5129. ha->tid_cnt = max_ids;
  5130. for (i = 0; i < GDTH_MAXCMDS; ++i)
  5131. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  5132. ha->scan_mode = rescan ? 0x10 : 0;
  5133. error = -ENODEV;
  5134. if (!gdth_search_drives(hanum)) {
  5135. printk("GDT-ISA: Error during device scan\n");
  5136. goto out_free_coal_stat;
  5137. }
  5138. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  5139. hdr_channel = ha->bus_cnt;
  5140. ha->virt_bus = hdr_channel;
  5141. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  5142. shp->max_cmd_len = 16;
  5143. shp->max_id = ha->tid_cnt;
  5144. shp->max_lun = MAXLUN;
  5145. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  5146. if (virt_ctr) {
  5147. virt_ctr = 1;
  5148. /* register addit. SCSI channels as virtual controllers */
  5149. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  5150. shp = scsi_register(shtp,sizeof(gdth_num_str));
  5151. shp->unchecked_isa_dma = 1;
  5152. shp->irq = ha->irq;
  5153. shp->dma_channel = ha->drq;
  5154. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  5155. NUMDATA(shp)->hanum = (ushort)hanum;
  5156. NUMDATA(shp)->busnum = b;
  5157. }
  5158. }
  5159. spin_lock_init(&ha->smp_lock);
  5160. gdth_enable_int(hanum);
  5161. return 0;
  5162. out_free_coal_stat:
  5163. #ifdef INT_COAL
  5164. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  5165. ha->coal_stat, ha->coal_stat_phys);
  5166. out_free_pmsg:
  5167. #endif
  5168. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  5169. ha->pmsg, ha->msg_phys);
  5170. out_free_pscratch:
  5171. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  5172. ha->pscratch, ha->scratch_phys);
  5173. out_dec_counters:
  5174. gdth_ctr_count--;
  5175. gdth_ctr_vcount--;
  5176. out_free_irq:
  5177. free_irq(ha->irq, ha);
  5178. out_host_put:
  5179. scsi_unregister(shp);
  5180. return error;
  5181. }
  5182. #endif /* CONFIG_ISA */
  5183. #include "scsi_module.c"
  5184. #ifndef MODULE
  5185. __setup("gdth=", option_setup);
  5186. #endif