gpio-mxc.c 13 KB

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  1. /*
  2. * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
  3. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  4. *
  5. * Based on code from Freescale,
  6. * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/io.h>
  24. #include <linux/irq.h>
  25. #include <linux/gpio.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/slab.h>
  28. #include <linux/basic_mmio_gpio.h>
  29. #include <linux/of.h>
  30. #include <linux/of_device.h>
  31. #include <linux/module.h>
  32. #include <asm-generic/bug.h>
  33. #include <asm/mach/irq.h>
  34. #define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
  35. enum mxc_gpio_hwtype {
  36. IMX1_GPIO, /* runs on i.mx1 */
  37. IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
  38. IMX31_GPIO, /* runs on i.mx31 */
  39. IMX35_GPIO, /* runs on all other i.mx */
  40. };
  41. /* device type dependent stuff */
  42. struct mxc_gpio_hwdata {
  43. unsigned dr_reg;
  44. unsigned gdir_reg;
  45. unsigned psr_reg;
  46. unsigned icr1_reg;
  47. unsigned icr2_reg;
  48. unsigned imr_reg;
  49. unsigned isr_reg;
  50. int edge_sel_reg;
  51. unsigned low_level;
  52. unsigned high_level;
  53. unsigned rise_edge;
  54. unsigned fall_edge;
  55. };
  56. struct mxc_gpio_port {
  57. struct list_head node;
  58. void __iomem *base;
  59. int irq;
  60. int irq_high;
  61. int virtual_irq_start;
  62. struct bgpio_chip bgc;
  63. u32 both_edges;
  64. };
  65. static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
  66. .dr_reg = 0x1c,
  67. .gdir_reg = 0x00,
  68. .psr_reg = 0x24,
  69. .icr1_reg = 0x28,
  70. .icr2_reg = 0x2c,
  71. .imr_reg = 0x30,
  72. .isr_reg = 0x34,
  73. .edge_sel_reg = -EINVAL,
  74. .low_level = 0x03,
  75. .high_level = 0x02,
  76. .rise_edge = 0x00,
  77. .fall_edge = 0x01,
  78. };
  79. static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
  80. .dr_reg = 0x00,
  81. .gdir_reg = 0x04,
  82. .psr_reg = 0x08,
  83. .icr1_reg = 0x0c,
  84. .icr2_reg = 0x10,
  85. .imr_reg = 0x14,
  86. .isr_reg = 0x18,
  87. .edge_sel_reg = -EINVAL,
  88. .low_level = 0x00,
  89. .high_level = 0x01,
  90. .rise_edge = 0x02,
  91. .fall_edge = 0x03,
  92. };
  93. static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
  94. .dr_reg = 0x00,
  95. .gdir_reg = 0x04,
  96. .psr_reg = 0x08,
  97. .icr1_reg = 0x0c,
  98. .icr2_reg = 0x10,
  99. .imr_reg = 0x14,
  100. .isr_reg = 0x18,
  101. .edge_sel_reg = 0x1c,
  102. .low_level = 0x00,
  103. .high_level = 0x01,
  104. .rise_edge = 0x02,
  105. .fall_edge = 0x03,
  106. };
  107. static enum mxc_gpio_hwtype mxc_gpio_hwtype;
  108. static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
  109. #define GPIO_DR (mxc_gpio_hwdata->dr_reg)
  110. #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
  111. #define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
  112. #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
  113. #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
  114. #define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
  115. #define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
  116. #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
  117. #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
  118. #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
  119. #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
  120. #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
  121. #define GPIO_INT_BOTH_EDGES 0x4
  122. static struct platform_device_id mxc_gpio_devtype[] = {
  123. {
  124. .name = "imx1-gpio",
  125. .driver_data = IMX1_GPIO,
  126. }, {
  127. .name = "imx21-gpio",
  128. .driver_data = IMX21_GPIO,
  129. }, {
  130. .name = "imx31-gpio",
  131. .driver_data = IMX31_GPIO,
  132. }, {
  133. .name = "imx35-gpio",
  134. .driver_data = IMX35_GPIO,
  135. }, {
  136. /* sentinel */
  137. }
  138. };
  139. static const struct of_device_id mxc_gpio_dt_ids[] = {
  140. { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
  141. { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
  142. { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
  143. { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
  144. { /* sentinel */ }
  145. };
  146. /*
  147. * MX2 has one interrupt *for all* gpio ports. The list is used
  148. * to save the references to all ports, so that mx2_gpio_irq_handler
  149. * can walk through all interrupt status registers.
  150. */
  151. static LIST_HEAD(mxc_gpio_ports);
  152. /* Note: This driver assumes 32 GPIOs are handled in one register */
  153. static int gpio_set_irq_type(struct irq_data *d, u32 type)
  154. {
  155. u32 gpio = irq_to_gpio(d->irq);
  156. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  157. struct mxc_gpio_port *port = gc->private;
  158. u32 bit, val;
  159. int edge;
  160. void __iomem *reg = port->base;
  161. port->both_edges &= ~(1 << (gpio & 31));
  162. switch (type) {
  163. case IRQ_TYPE_EDGE_RISING:
  164. edge = GPIO_INT_RISE_EDGE;
  165. break;
  166. case IRQ_TYPE_EDGE_FALLING:
  167. edge = GPIO_INT_FALL_EDGE;
  168. break;
  169. case IRQ_TYPE_EDGE_BOTH:
  170. if (GPIO_EDGE_SEL >= 0) {
  171. edge = GPIO_INT_BOTH_EDGES;
  172. } else {
  173. val = gpio_get_value(gpio);
  174. if (val) {
  175. edge = GPIO_INT_LOW_LEV;
  176. pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
  177. } else {
  178. edge = GPIO_INT_HIGH_LEV;
  179. pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
  180. }
  181. port->both_edges |= 1 << (gpio & 31);
  182. }
  183. break;
  184. case IRQ_TYPE_LEVEL_LOW:
  185. edge = GPIO_INT_LOW_LEV;
  186. break;
  187. case IRQ_TYPE_LEVEL_HIGH:
  188. edge = GPIO_INT_HIGH_LEV;
  189. break;
  190. default:
  191. return -EINVAL;
  192. }
  193. if (GPIO_EDGE_SEL >= 0) {
  194. val = readl(port->base + GPIO_EDGE_SEL);
  195. if (edge == GPIO_INT_BOTH_EDGES)
  196. writel(val | (1 << (gpio & 0x1f)),
  197. port->base + GPIO_EDGE_SEL);
  198. else
  199. writel(val & ~(1 << (gpio & 0x1f)),
  200. port->base + GPIO_EDGE_SEL);
  201. }
  202. if (edge != GPIO_INT_BOTH_EDGES) {
  203. reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
  204. bit = gpio & 0xf;
  205. val = readl(reg) & ~(0x3 << (bit << 1));
  206. writel(val | (edge << (bit << 1)), reg);
  207. }
  208. writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
  209. return 0;
  210. }
  211. static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
  212. {
  213. void __iomem *reg = port->base;
  214. u32 bit, val;
  215. int edge;
  216. reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
  217. bit = gpio & 0xf;
  218. val = readl(reg);
  219. edge = (val >> (bit << 1)) & 3;
  220. val &= ~(0x3 << (bit << 1));
  221. if (edge == GPIO_INT_HIGH_LEV) {
  222. edge = GPIO_INT_LOW_LEV;
  223. pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
  224. } else if (edge == GPIO_INT_LOW_LEV) {
  225. edge = GPIO_INT_HIGH_LEV;
  226. pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
  227. } else {
  228. pr_err("mxc: invalid configuration for GPIO %d: %x\n",
  229. gpio, edge);
  230. return;
  231. }
  232. writel(val | (edge << (bit << 1)), reg);
  233. }
  234. /* handle 32 interrupts in one status register */
  235. static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
  236. {
  237. u32 gpio_irq_no_base = port->virtual_irq_start;
  238. while (irq_stat != 0) {
  239. int irqoffset = fls(irq_stat) - 1;
  240. if (port->both_edges & (1 << irqoffset))
  241. mxc_flip_edge(port, irqoffset);
  242. generic_handle_irq(gpio_irq_no_base + irqoffset);
  243. irq_stat &= ~(1 << irqoffset);
  244. }
  245. }
  246. /* MX1 and MX3 has one interrupt *per* gpio port */
  247. static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
  248. {
  249. u32 irq_stat;
  250. struct mxc_gpio_port *port = irq_get_handler_data(irq);
  251. struct irq_chip *chip = irq_get_chip(irq);
  252. chained_irq_enter(chip, desc);
  253. irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
  254. mxc_gpio_irq_handler(port, irq_stat);
  255. chained_irq_exit(chip, desc);
  256. }
  257. /* MX2 has one interrupt *for all* gpio ports */
  258. static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
  259. {
  260. u32 irq_msk, irq_stat;
  261. struct mxc_gpio_port *port;
  262. /* walk through all interrupt status registers */
  263. list_for_each_entry(port, &mxc_gpio_ports, node) {
  264. irq_msk = readl(port->base + GPIO_IMR);
  265. if (!irq_msk)
  266. continue;
  267. irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
  268. if (irq_stat)
  269. mxc_gpio_irq_handler(port, irq_stat);
  270. }
  271. }
  272. /*
  273. * Set interrupt number "irq" in the GPIO as a wake-up source.
  274. * While system is running, all registered GPIO interrupts need to have
  275. * wake-up enabled. When system is suspended, only selected GPIO interrupts
  276. * need to have wake-up enabled.
  277. * @param irq interrupt source number
  278. * @param enable enable as wake-up if equal to non-zero
  279. * @return This function returns 0 on success.
  280. */
  281. static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
  282. {
  283. u32 gpio = irq_to_gpio(d->irq);
  284. u32 gpio_idx = gpio & 0x1F;
  285. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  286. struct mxc_gpio_port *port = gc->private;
  287. if (enable) {
  288. if (port->irq_high && (gpio_idx >= 16))
  289. enable_irq_wake(port->irq_high);
  290. else
  291. enable_irq_wake(port->irq);
  292. } else {
  293. if (port->irq_high && (gpio_idx >= 16))
  294. disable_irq_wake(port->irq_high);
  295. else
  296. disable_irq_wake(port->irq);
  297. }
  298. return 0;
  299. }
  300. static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
  301. {
  302. struct irq_chip_generic *gc;
  303. struct irq_chip_type *ct;
  304. gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
  305. port->base, handle_level_irq);
  306. gc->private = port;
  307. ct = gc->chip_types;
  308. ct->chip.irq_ack = irq_gc_ack_set_bit;
  309. ct->chip.irq_mask = irq_gc_mask_clr_bit;
  310. ct->chip.irq_unmask = irq_gc_mask_set_bit;
  311. ct->chip.irq_set_type = gpio_set_irq_type;
  312. ct->chip.irq_set_wake = gpio_set_wake_irq;
  313. ct->regs.ack = GPIO_ISR;
  314. ct->regs.mask = GPIO_IMR;
  315. irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
  316. IRQ_NOREQUEST, 0);
  317. }
  318. static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
  319. {
  320. const struct of_device_id *of_id =
  321. of_match_device(mxc_gpio_dt_ids, &pdev->dev);
  322. enum mxc_gpio_hwtype hwtype;
  323. if (of_id)
  324. pdev->id_entry = of_id->data;
  325. hwtype = pdev->id_entry->driver_data;
  326. if (mxc_gpio_hwtype) {
  327. /*
  328. * The driver works with a reasonable presupposition,
  329. * that is all gpio ports must be the same type when
  330. * running on one soc.
  331. */
  332. BUG_ON(mxc_gpio_hwtype != hwtype);
  333. return;
  334. }
  335. if (hwtype == IMX35_GPIO)
  336. mxc_gpio_hwdata = &imx35_gpio_hwdata;
  337. else if (hwtype == IMX31_GPIO)
  338. mxc_gpio_hwdata = &imx31_gpio_hwdata;
  339. else
  340. mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
  341. mxc_gpio_hwtype = hwtype;
  342. }
  343. static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
  344. {
  345. struct bgpio_chip *bgc = to_bgpio_chip(gc);
  346. struct mxc_gpio_port *port =
  347. container_of(bgc, struct mxc_gpio_port, bgc);
  348. return port->virtual_irq_start + offset;
  349. }
  350. static int __devinit mxc_gpio_probe(struct platform_device *pdev)
  351. {
  352. struct device_node *np = pdev->dev.of_node;
  353. struct mxc_gpio_port *port;
  354. struct resource *iores;
  355. int err;
  356. mxc_gpio_get_hw(pdev);
  357. port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
  358. if (!port)
  359. return -ENOMEM;
  360. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  361. if (!iores) {
  362. err = -ENODEV;
  363. goto out_kfree;
  364. }
  365. if (!request_mem_region(iores->start, resource_size(iores),
  366. pdev->name)) {
  367. err = -EBUSY;
  368. goto out_kfree;
  369. }
  370. port->base = ioremap(iores->start, resource_size(iores));
  371. if (!port->base) {
  372. err = -ENOMEM;
  373. goto out_release_mem;
  374. }
  375. port->irq_high = platform_get_irq(pdev, 1);
  376. port->irq = platform_get_irq(pdev, 0);
  377. if (port->irq < 0) {
  378. err = -EINVAL;
  379. goto out_iounmap;
  380. }
  381. /* disable the interrupt and clear the status */
  382. writel(0, port->base + GPIO_IMR);
  383. writel(~0, port->base + GPIO_ISR);
  384. if (mxc_gpio_hwtype == IMX21_GPIO) {
  385. /* setup one handler for all GPIO interrupts */
  386. if (pdev->id == 0)
  387. irq_set_chained_handler(port->irq,
  388. mx2_gpio_irq_handler);
  389. } else {
  390. /* setup one handler for each entry */
  391. irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
  392. irq_set_handler_data(port->irq, port);
  393. if (port->irq_high > 0) {
  394. /* setup handler for GPIO 16 to 31 */
  395. irq_set_chained_handler(port->irq_high,
  396. mx3_gpio_irq_handler);
  397. irq_set_handler_data(port->irq_high, port);
  398. }
  399. }
  400. err = bgpio_init(&port->bgc, &pdev->dev, 4,
  401. port->base + GPIO_PSR,
  402. port->base + GPIO_DR, NULL,
  403. port->base + GPIO_GDIR, NULL, 0);
  404. if (err)
  405. goto out_iounmap;
  406. port->bgc.gc.to_irq = mxc_gpio_to_irq;
  407. port->bgc.gc.base = pdev->id * 32;
  408. port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
  409. port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
  410. err = gpiochip_add(&port->bgc.gc);
  411. if (err)
  412. goto out_bgpio_remove;
  413. /*
  414. * In dt case, we use gpio number range dynamically
  415. * allocated by gpio core.
  416. */
  417. port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
  418. pdev->id * 32);
  419. /* gpio-mxc can be a generic irq chip */
  420. mxc_gpio_init_gc(port);
  421. list_add_tail(&port->node, &mxc_gpio_ports);
  422. return 0;
  423. out_bgpio_remove:
  424. bgpio_remove(&port->bgc);
  425. out_iounmap:
  426. iounmap(port->base);
  427. out_release_mem:
  428. release_mem_region(iores->start, resource_size(iores));
  429. out_kfree:
  430. kfree(port);
  431. dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
  432. return err;
  433. }
  434. static struct platform_driver mxc_gpio_driver = {
  435. .driver = {
  436. .name = "gpio-mxc",
  437. .owner = THIS_MODULE,
  438. .of_match_table = mxc_gpio_dt_ids,
  439. },
  440. .probe = mxc_gpio_probe,
  441. .id_table = mxc_gpio_devtype,
  442. };
  443. static int __init gpio_mxc_init(void)
  444. {
  445. return platform_driver_register(&mxc_gpio_driver);
  446. }
  447. postcore_initcall(gpio_mxc_init);
  448. MODULE_AUTHOR("Freescale Semiconductor, "
  449. "Daniel Mack <danielncaiaq.de>, "
  450. "Juergen Beisert <kernel@pengutronix.de>");
  451. MODULE_DESCRIPTION("Freescale MXC GPIO");
  452. MODULE_LICENSE("GPL");