events.c 35 KB

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  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is recieved, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/pci.h>
  39. #include <asm/xen/hypercall.h>
  40. #include <asm/xen/hypervisor.h>
  41. #include <xen/xen.h>
  42. #include <xen/hvm.h>
  43. #include <xen/xen-ops.h>
  44. #include <xen/events.h>
  45. #include <xen/interface/xen.h>
  46. #include <xen/interface/event_channel.h>
  47. #include <xen/interface/hvm/hvm_op.h>
  48. #include <xen/interface/hvm/params.h>
  49. /*
  50. * This lock protects updates to the following mapping and reference-count
  51. * arrays. The lock does not need to be acquired to read the mapping tables.
  52. */
  53. static DEFINE_SPINLOCK(irq_mapping_update_lock);
  54. /* IRQ <-> VIRQ mapping. */
  55. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  56. /* IRQ <-> IPI mapping */
  57. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  58. /* Interrupt types. */
  59. enum xen_irq_type {
  60. IRQT_UNBOUND = 0,
  61. IRQT_PIRQ,
  62. IRQT_VIRQ,
  63. IRQT_IPI,
  64. IRQT_EVTCHN
  65. };
  66. /*
  67. * Packed IRQ information:
  68. * type - enum xen_irq_type
  69. * event channel - irq->event channel mapping
  70. * cpu - cpu this event channel is bound to
  71. * index - type-specific information:
  72. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  73. * guest, or GSI (real passthrough IRQ) of the device.
  74. * VIRQ - virq number
  75. * IPI - IPI vector
  76. * EVTCHN -
  77. */
  78. struct irq_info
  79. {
  80. enum xen_irq_type type; /* type */
  81. unsigned short evtchn; /* event channel */
  82. unsigned short cpu; /* cpu bound */
  83. union {
  84. unsigned short virq;
  85. enum ipi_vector ipi;
  86. struct {
  87. unsigned short pirq;
  88. unsigned short gsi;
  89. unsigned char vector;
  90. unsigned char flags;
  91. } pirq;
  92. } u;
  93. };
  94. #define PIRQ_NEEDS_EOI (1 << 0)
  95. #define PIRQ_SHAREABLE (1 << 1)
  96. static struct irq_info *irq_info;
  97. static int *pirq_to_irq;
  98. static int nr_pirqs;
  99. static int *evtchn_to_irq;
  100. struct cpu_evtchn_s {
  101. unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
  102. };
  103. static __initdata struct cpu_evtchn_s init_evtchn_mask = {
  104. .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
  105. };
  106. static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
  107. static inline unsigned long *cpu_evtchn_mask(int cpu)
  108. {
  109. return cpu_evtchn_mask_p[cpu].bits;
  110. }
  111. /* Xen will never allocate port zero for any purpose. */
  112. #define VALID_EVTCHN(chn) ((chn) != 0)
  113. static struct irq_chip xen_dynamic_chip;
  114. static struct irq_chip xen_percpu_chip;
  115. static struct irq_chip xen_pirq_chip;
  116. /* Constructor for packed IRQ information. */
  117. static struct irq_info mk_unbound_info(void)
  118. {
  119. return (struct irq_info) { .type = IRQT_UNBOUND };
  120. }
  121. static struct irq_info mk_evtchn_info(unsigned short evtchn)
  122. {
  123. return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
  124. .cpu = 0 };
  125. }
  126. static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
  127. {
  128. return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
  129. .cpu = 0, .u.ipi = ipi };
  130. }
  131. static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
  132. {
  133. return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
  134. .cpu = 0, .u.virq = virq };
  135. }
  136. static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
  137. unsigned short gsi, unsigned short vector)
  138. {
  139. return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
  140. .cpu = 0,
  141. .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
  142. }
  143. /*
  144. * Accessors for packed IRQ information.
  145. */
  146. static struct irq_info *info_for_irq(unsigned irq)
  147. {
  148. return &irq_info[irq];
  149. }
  150. static unsigned int evtchn_from_irq(unsigned irq)
  151. {
  152. return info_for_irq(irq)->evtchn;
  153. }
  154. unsigned irq_from_evtchn(unsigned int evtchn)
  155. {
  156. return evtchn_to_irq[evtchn];
  157. }
  158. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  159. static enum ipi_vector ipi_from_irq(unsigned irq)
  160. {
  161. struct irq_info *info = info_for_irq(irq);
  162. BUG_ON(info == NULL);
  163. BUG_ON(info->type != IRQT_IPI);
  164. return info->u.ipi;
  165. }
  166. static unsigned virq_from_irq(unsigned irq)
  167. {
  168. struct irq_info *info = info_for_irq(irq);
  169. BUG_ON(info == NULL);
  170. BUG_ON(info->type != IRQT_VIRQ);
  171. return info->u.virq;
  172. }
  173. static unsigned pirq_from_irq(unsigned irq)
  174. {
  175. struct irq_info *info = info_for_irq(irq);
  176. BUG_ON(info == NULL);
  177. BUG_ON(info->type != IRQT_PIRQ);
  178. return info->u.pirq.pirq;
  179. }
  180. static unsigned gsi_from_irq(unsigned irq)
  181. {
  182. struct irq_info *info = info_for_irq(irq);
  183. BUG_ON(info == NULL);
  184. BUG_ON(info->type != IRQT_PIRQ);
  185. return info->u.pirq.gsi;
  186. }
  187. static unsigned vector_from_irq(unsigned irq)
  188. {
  189. struct irq_info *info = info_for_irq(irq);
  190. BUG_ON(info == NULL);
  191. BUG_ON(info->type != IRQT_PIRQ);
  192. return info->u.pirq.vector;
  193. }
  194. static enum xen_irq_type type_from_irq(unsigned irq)
  195. {
  196. return info_for_irq(irq)->type;
  197. }
  198. static unsigned cpu_from_irq(unsigned irq)
  199. {
  200. return info_for_irq(irq)->cpu;
  201. }
  202. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  203. {
  204. int irq = evtchn_to_irq[evtchn];
  205. unsigned ret = 0;
  206. if (irq != -1)
  207. ret = cpu_from_irq(irq);
  208. return ret;
  209. }
  210. static bool pirq_needs_eoi(unsigned irq)
  211. {
  212. struct irq_info *info = info_for_irq(irq);
  213. BUG_ON(info->type != IRQT_PIRQ);
  214. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  215. }
  216. static inline unsigned long active_evtchns(unsigned int cpu,
  217. struct shared_info *sh,
  218. unsigned int idx)
  219. {
  220. return (sh->evtchn_pending[idx] &
  221. cpu_evtchn_mask(cpu)[idx] &
  222. ~sh->evtchn_mask[idx]);
  223. }
  224. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  225. {
  226. int irq = evtchn_to_irq[chn];
  227. BUG_ON(irq == -1);
  228. #ifdef CONFIG_SMP
  229. cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu));
  230. #endif
  231. clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
  232. set_bit(chn, cpu_evtchn_mask(cpu));
  233. irq_info[irq].cpu = cpu;
  234. }
  235. static void init_evtchn_cpu_bindings(void)
  236. {
  237. int i;
  238. #ifdef CONFIG_SMP
  239. struct irq_desc *desc;
  240. /* By default all event channels notify CPU#0. */
  241. for_each_irq_desc(i, desc) {
  242. cpumask_copy(desc->affinity, cpumask_of(0));
  243. }
  244. #endif
  245. for_each_possible_cpu(i)
  246. memset(cpu_evtchn_mask(i),
  247. (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
  248. }
  249. static inline void clear_evtchn(int port)
  250. {
  251. struct shared_info *s = HYPERVISOR_shared_info;
  252. sync_clear_bit(port, &s->evtchn_pending[0]);
  253. }
  254. static inline void set_evtchn(int port)
  255. {
  256. struct shared_info *s = HYPERVISOR_shared_info;
  257. sync_set_bit(port, &s->evtchn_pending[0]);
  258. }
  259. static inline int test_evtchn(int port)
  260. {
  261. struct shared_info *s = HYPERVISOR_shared_info;
  262. return sync_test_bit(port, &s->evtchn_pending[0]);
  263. }
  264. /**
  265. * notify_remote_via_irq - send event to remote end of event channel via irq
  266. * @irq: irq of event channel to send event to
  267. *
  268. * Unlike notify_remote_via_evtchn(), this is safe to use across
  269. * save/restore. Notifications on a broken connection are silently
  270. * dropped.
  271. */
  272. void notify_remote_via_irq(int irq)
  273. {
  274. int evtchn = evtchn_from_irq(irq);
  275. if (VALID_EVTCHN(evtchn))
  276. notify_remote_via_evtchn(evtchn);
  277. }
  278. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  279. static void mask_evtchn(int port)
  280. {
  281. struct shared_info *s = HYPERVISOR_shared_info;
  282. sync_set_bit(port, &s->evtchn_mask[0]);
  283. }
  284. static void unmask_evtchn(int port)
  285. {
  286. struct shared_info *s = HYPERVISOR_shared_info;
  287. unsigned int cpu = get_cpu();
  288. BUG_ON(!irqs_disabled());
  289. /* Slow path (hypercall) if this is a non-local port. */
  290. if (unlikely(cpu != cpu_from_evtchn(port))) {
  291. struct evtchn_unmask unmask = { .port = port };
  292. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  293. } else {
  294. struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
  295. sync_clear_bit(port, &s->evtchn_mask[0]);
  296. /*
  297. * The following is basically the equivalent of
  298. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  299. * the interrupt edge' if the channel is masked.
  300. */
  301. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  302. !sync_test_and_set_bit(port / BITS_PER_LONG,
  303. &vcpu_info->evtchn_pending_sel))
  304. vcpu_info->evtchn_upcall_pending = 1;
  305. }
  306. put_cpu();
  307. }
  308. static int get_nr_hw_irqs(void)
  309. {
  310. int ret = 1;
  311. #ifdef CONFIG_X86_IO_APIC
  312. ret = get_nr_irqs_gsi();
  313. #endif
  314. return ret;
  315. }
  316. /* callers of this function should make sure that PHYSDEVOP_get_nr_pirqs
  317. * succeeded otherwise nr_pirqs won't hold the right value */
  318. static int find_unbound_pirq(void)
  319. {
  320. int i;
  321. for (i = nr_pirqs-1; i >= 0; i--) {
  322. if (pirq_to_irq[i] < 0)
  323. return i;
  324. }
  325. return -1;
  326. }
  327. static int find_unbound_irq(void)
  328. {
  329. struct irq_data *data;
  330. int irq, res;
  331. int start = get_nr_hw_irqs();
  332. if (start == nr_irqs)
  333. goto no_irqs;
  334. /* nr_irqs is a magic value. Must not use it.*/
  335. for (irq = nr_irqs-1; irq > start; irq--) {
  336. data = irq_get_irq_data(irq);
  337. /* only 0->15 have init'd desc; handle irq > 16 */
  338. if (!data)
  339. break;
  340. if (data->chip == &no_irq_chip)
  341. break;
  342. if (data->chip != &xen_dynamic_chip)
  343. continue;
  344. if (irq_info[irq].type == IRQT_UNBOUND)
  345. return irq;
  346. }
  347. if (irq == start)
  348. goto no_irqs;
  349. res = irq_alloc_desc_at(irq, 0);
  350. if (WARN_ON(res != irq))
  351. return -1;
  352. return irq;
  353. no_irqs:
  354. panic("No available IRQ to bind to: increase nr_irqs!\n");
  355. }
  356. static bool identity_mapped_irq(unsigned irq)
  357. {
  358. /* identity map all the hardware irqs */
  359. return irq < get_nr_hw_irqs();
  360. }
  361. static void pirq_unmask_notify(int irq)
  362. {
  363. struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
  364. if (unlikely(pirq_needs_eoi(irq))) {
  365. int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  366. WARN_ON(rc);
  367. }
  368. }
  369. static void pirq_query_unmask(int irq)
  370. {
  371. struct physdev_irq_status_query irq_status;
  372. struct irq_info *info = info_for_irq(irq);
  373. BUG_ON(info->type != IRQT_PIRQ);
  374. irq_status.irq = pirq_from_irq(irq);
  375. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  376. irq_status.flags = 0;
  377. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  378. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  379. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  380. }
  381. static bool probing_irq(int irq)
  382. {
  383. struct irq_desc *desc = irq_to_desc(irq);
  384. return desc && desc->action == NULL;
  385. }
  386. static unsigned int startup_pirq(unsigned int irq)
  387. {
  388. struct evtchn_bind_pirq bind_pirq;
  389. struct irq_info *info = info_for_irq(irq);
  390. int evtchn = evtchn_from_irq(irq);
  391. int rc;
  392. BUG_ON(info->type != IRQT_PIRQ);
  393. if (VALID_EVTCHN(evtchn))
  394. goto out;
  395. bind_pirq.pirq = pirq_from_irq(irq);
  396. /* NB. We are happy to share unless we are probing. */
  397. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  398. BIND_PIRQ__WILL_SHARE : 0;
  399. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  400. if (rc != 0) {
  401. if (!probing_irq(irq))
  402. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  403. irq);
  404. return 0;
  405. }
  406. evtchn = bind_pirq.port;
  407. pirq_query_unmask(irq);
  408. evtchn_to_irq[evtchn] = irq;
  409. bind_evtchn_to_cpu(evtchn, 0);
  410. info->evtchn = evtchn;
  411. out:
  412. unmask_evtchn(evtchn);
  413. pirq_unmask_notify(irq);
  414. return 0;
  415. }
  416. static void shutdown_pirq(unsigned int irq)
  417. {
  418. struct evtchn_close close;
  419. struct irq_info *info = info_for_irq(irq);
  420. int evtchn = evtchn_from_irq(irq);
  421. BUG_ON(info->type != IRQT_PIRQ);
  422. if (!VALID_EVTCHN(evtchn))
  423. return;
  424. mask_evtchn(evtchn);
  425. close.port = evtchn;
  426. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  427. BUG();
  428. bind_evtchn_to_cpu(evtchn, 0);
  429. evtchn_to_irq[evtchn] = -1;
  430. info->evtchn = 0;
  431. }
  432. static void enable_pirq(unsigned int irq)
  433. {
  434. startup_pirq(irq);
  435. }
  436. static void disable_pirq(unsigned int irq)
  437. {
  438. }
  439. static void ack_pirq(unsigned int irq)
  440. {
  441. int evtchn = evtchn_from_irq(irq);
  442. move_native_irq(irq);
  443. if (VALID_EVTCHN(evtchn)) {
  444. mask_evtchn(evtchn);
  445. clear_evtchn(evtchn);
  446. }
  447. }
  448. static void end_pirq(unsigned int irq)
  449. {
  450. int evtchn = evtchn_from_irq(irq);
  451. struct irq_desc *desc = irq_to_desc(irq);
  452. if (WARN_ON(!desc))
  453. return;
  454. if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) ==
  455. (IRQ_DISABLED|IRQ_PENDING)) {
  456. shutdown_pirq(irq);
  457. } else if (VALID_EVTCHN(evtchn)) {
  458. unmask_evtchn(evtchn);
  459. pirq_unmask_notify(irq);
  460. }
  461. }
  462. static int find_irq_by_gsi(unsigned gsi)
  463. {
  464. int irq;
  465. for (irq = 0; irq < nr_irqs; irq++) {
  466. struct irq_info *info = info_for_irq(irq);
  467. if (info == NULL || info->type != IRQT_PIRQ)
  468. continue;
  469. if (gsi_from_irq(irq) == gsi)
  470. return irq;
  471. }
  472. return -1;
  473. }
  474. int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
  475. {
  476. return xen_map_pirq_gsi(gsi, gsi, shareable, name);
  477. }
  478. /* xen_map_pirq_gsi might allocate irqs from the top down, as a
  479. * consequence don't assume that the irq number returned has a low value
  480. * or can be used as a pirq number unless you know otherwise.
  481. *
  482. * One notable exception is when xen_map_pirq_gsi is called passing an
  483. * hardware gsi as argument, in that case the irq number returned
  484. * matches the gsi number passed as second argument.
  485. *
  486. * Note: We don't assign an event channel until the irq actually started
  487. * up. Return an existing irq if we've already got one for the gsi.
  488. */
  489. int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
  490. {
  491. int irq = 0;
  492. struct physdev_irq irq_op;
  493. spin_lock(&irq_mapping_update_lock);
  494. if ((pirq > nr_pirqs) || (gsi > nr_irqs)) {
  495. printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
  496. pirq > nr_pirqs ? "nr_pirqs" :"",
  497. gsi > nr_irqs ? "nr_irqs" : "");
  498. goto out;
  499. }
  500. irq = find_irq_by_gsi(gsi);
  501. if (irq != -1) {
  502. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  503. irq, gsi);
  504. goto out; /* XXX need refcount? */
  505. }
  506. /* If we are a PV guest, we don't have GSIs (no ACPI passed). Therefore
  507. * we are using the !xen_initial_domain() to drop in the function.*/
  508. if (identity_mapped_irq(gsi) || (!xen_initial_domain() &&
  509. xen_pv_domain())) {
  510. irq = gsi;
  511. irq_alloc_desc_at(irq, 0);
  512. } else
  513. irq = find_unbound_irq();
  514. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  515. handle_level_irq, name);
  516. irq_op.irq = irq;
  517. irq_op.vector = 0;
  518. /* Only the privileged domain can do this. For non-priv, the pcifront
  519. * driver provides a PCI bus that does the call to do exactly
  520. * this in the priv domain. */
  521. if (xen_initial_domain() &&
  522. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  523. irq_free_desc(irq);
  524. irq = -ENOSPC;
  525. goto out;
  526. }
  527. irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
  528. irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
  529. pirq_to_irq[pirq] = irq;
  530. out:
  531. spin_unlock(&irq_mapping_update_lock);
  532. return irq;
  533. }
  534. #ifdef CONFIG_PCI_MSI
  535. #include <linux/msi.h>
  536. #include "../pci/msi.h"
  537. void xen_allocate_pirq_msi(char *name, int *irq, int *pirq)
  538. {
  539. spin_lock(&irq_mapping_update_lock);
  540. *irq = find_unbound_irq();
  541. if (*irq == -1)
  542. goto out;
  543. *pirq = find_unbound_pirq();
  544. if (*pirq == -1)
  545. goto out;
  546. set_irq_chip_and_handler_name(*irq, &xen_pirq_chip,
  547. handle_level_irq, name);
  548. irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0);
  549. pirq_to_irq[*pirq] = *irq;
  550. out:
  551. spin_unlock(&irq_mapping_update_lock);
  552. }
  553. int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
  554. {
  555. int irq = -1;
  556. struct physdev_map_pirq map_irq;
  557. int rc;
  558. int pos;
  559. u32 table_offset, bir;
  560. memset(&map_irq, 0, sizeof(map_irq));
  561. map_irq.domid = DOMID_SELF;
  562. map_irq.type = MAP_PIRQ_TYPE_MSI;
  563. map_irq.index = -1;
  564. map_irq.pirq = -1;
  565. map_irq.bus = dev->bus->number;
  566. map_irq.devfn = dev->devfn;
  567. if (type == PCI_CAP_ID_MSIX) {
  568. pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  569. pci_read_config_dword(dev, msix_table_offset_reg(pos),
  570. &table_offset);
  571. bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
  572. map_irq.table_base = pci_resource_start(dev, bir);
  573. map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
  574. }
  575. spin_lock(&irq_mapping_update_lock);
  576. irq = find_unbound_irq();
  577. if (irq == -1)
  578. goto out;
  579. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  580. if (rc) {
  581. printk(KERN_WARNING "xen map irq failed %d\n", rc);
  582. irq_free_desc(irq);
  583. irq = -1;
  584. goto out;
  585. }
  586. irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
  587. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  588. handle_level_irq,
  589. (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
  590. out:
  591. spin_unlock(&irq_mapping_update_lock);
  592. return irq;
  593. }
  594. #endif
  595. int xen_destroy_irq(int irq)
  596. {
  597. struct irq_desc *desc;
  598. struct physdev_unmap_pirq unmap_irq;
  599. struct irq_info *info = info_for_irq(irq);
  600. int rc = -ENOENT;
  601. spin_lock(&irq_mapping_update_lock);
  602. desc = irq_to_desc(irq);
  603. if (!desc)
  604. goto out;
  605. if (xen_initial_domain()) {
  606. unmap_irq.pirq = info->u.pirq.pirq;
  607. unmap_irq.domid = DOMID_SELF;
  608. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  609. if (rc) {
  610. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  611. goto out;
  612. }
  613. }
  614. irq_info[irq] = mk_unbound_info();
  615. irq_free_desc(irq);
  616. out:
  617. spin_unlock(&irq_mapping_update_lock);
  618. return rc;
  619. }
  620. int xen_vector_from_irq(unsigned irq)
  621. {
  622. return vector_from_irq(irq);
  623. }
  624. int xen_gsi_from_irq(unsigned irq)
  625. {
  626. return gsi_from_irq(irq);
  627. }
  628. int bind_evtchn_to_irq(unsigned int evtchn)
  629. {
  630. int irq;
  631. spin_lock(&irq_mapping_update_lock);
  632. irq = evtchn_to_irq[evtchn];
  633. if (irq == -1) {
  634. irq = find_unbound_irq();
  635. set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
  636. handle_fasteoi_irq, "event");
  637. evtchn_to_irq[evtchn] = irq;
  638. irq_info[irq] = mk_evtchn_info(evtchn);
  639. }
  640. spin_unlock(&irq_mapping_update_lock);
  641. return irq;
  642. }
  643. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  644. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  645. {
  646. struct evtchn_bind_ipi bind_ipi;
  647. int evtchn, irq;
  648. spin_lock(&irq_mapping_update_lock);
  649. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  650. if (irq == -1) {
  651. irq = find_unbound_irq();
  652. if (irq < 0)
  653. goto out;
  654. set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
  655. handle_percpu_irq, "ipi");
  656. bind_ipi.vcpu = cpu;
  657. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  658. &bind_ipi) != 0)
  659. BUG();
  660. evtchn = bind_ipi.port;
  661. evtchn_to_irq[evtchn] = irq;
  662. irq_info[irq] = mk_ipi_info(evtchn, ipi);
  663. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  664. bind_evtchn_to_cpu(evtchn, cpu);
  665. }
  666. out:
  667. spin_unlock(&irq_mapping_update_lock);
  668. return irq;
  669. }
  670. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  671. {
  672. struct evtchn_bind_virq bind_virq;
  673. int evtchn, irq;
  674. spin_lock(&irq_mapping_update_lock);
  675. irq = per_cpu(virq_to_irq, cpu)[virq];
  676. if (irq == -1) {
  677. irq = find_unbound_irq();
  678. set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
  679. handle_percpu_irq, "virq");
  680. bind_virq.virq = virq;
  681. bind_virq.vcpu = cpu;
  682. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  683. &bind_virq) != 0)
  684. BUG();
  685. evtchn = bind_virq.port;
  686. evtchn_to_irq[evtchn] = irq;
  687. irq_info[irq] = mk_virq_info(evtchn, virq);
  688. per_cpu(virq_to_irq, cpu)[virq] = irq;
  689. bind_evtchn_to_cpu(evtchn, cpu);
  690. }
  691. spin_unlock(&irq_mapping_update_lock);
  692. return irq;
  693. }
  694. static void unbind_from_irq(unsigned int irq)
  695. {
  696. struct evtchn_close close;
  697. int evtchn = evtchn_from_irq(irq);
  698. spin_lock(&irq_mapping_update_lock);
  699. if (VALID_EVTCHN(evtchn)) {
  700. close.port = evtchn;
  701. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  702. BUG();
  703. switch (type_from_irq(irq)) {
  704. case IRQT_VIRQ:
  705. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  706. [virq_from_irq(irq)] = -1;
  707. break;
  708. case IRQT_IPI:
  709. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  710. [ipi_from_irq(irq)] = -1;
  711. break;
  712. default:
  713. break;
  714. }
  715. /* Closed ports are implicitly re-bound to VCPU0. */
  716. bind_evtchn_to_cpu(evtchn, 0);
  717. evtchn_to_irq[evtchn] = -1;
  718. }
  719. if (irq_info[irq].type != IRQT_UNBOUND) {
  720. irq_info[irq] = mk_unbound_info();
  721. irq_free_desc(irq);
  722. }
  723. spin_unlock(&irq_mapping_update_lock);
  724. }
  725. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  726. irq_handler_t handler,
  727. unsigned long irqflags,
  728. const char *devname, void *dev_id)
  729. {
  730. unsigned int irq;
  731. int retval;
  732. irq = bind_evtchn_to_irq(evtchn);
  733. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  734. if (retval != 0) {
  735. unbind_from_irq(irq);
  736. return retval;
  737. }
  738. return irq;
  739. }
  740. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  741. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  742. irq_handler_t handler,
  743. unsigned long irqflags, const char *devname, void *dev_id)
  744. {
  745. unsigned int irq;
  746. int retval;
  747. irq = bind_virq_to_irq(virq, cpu);
  748. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  749. if (retval != 0) {
  750. unbind_from_irq(irq);
  751. return retval;
  752. }
  753. return irq;
  754. }
  755. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  756. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  757. unsigned int cpu,
  758. irq_handler_t handler,
  759. unsigned long irqflags,
  760. const char *devname,
  761. void *dev_id)
  762. {
  763. int irq, retval;
  764. irq = bind_ipi_to_irq(ipi, cpu);
  765. if (irq < 0)
  766. return irq;
  767. irqflags |= IRQF_NO_SUSPEND;
  768. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  769. if (retval != 0) {
  770. unbind_from_irq(irq);
  771. return retval;
  772. }
  773. return irq;
  774. }
  775. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  776. {
  777. free_irq(irq, dev_id);
  778. unbind_from_irq(irq);
  779. }
  780. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  781. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  782. {
  783. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  784. BUG_ON(irq < 0);
  785. notify_remote_via_irq(irq);
  786. }
  787. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  788. {
  789. struct shared_info *sh = HYPERVISOR_shared_info;
  790. int cpu = smp_processor_id();
  791. unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
  792. int i;
  793. unsigned long flags;
  794. static DEFINE_SPINLOCK(debug_lock);
  795. struct vcpu_info *v;
  796. spin_lock_irqsave(&debug_lock, flags);
  797. printk("\nvcpu %d\n ", cpu);
  798. for_each_online_cpu(i) {
  799. int pending;
  800. v = per_cpu(xen_vcpu, i);
  801. pending = (get_irq_regs() && i == cpu)
  802. ? xen_irqs_disabled(get_irq_regs())
  803. : v->evtchn_upcall_mask;
  804. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  805. pending, v->evtchn_upcall_pending,
  806. (int)(sizeof(v->evtchn_pending_sel)*2),
  807. v->evtchn_pending_sel);
  808. }
  809. v = per_cpu(xen_vcpu, cpu);
  810. printk("\npending:\n ");
  811. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  812. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  813. sh->evtchn_pending[i],
  814. i % 8 == 0 ? "\n " : " ");
  815. printk("\nglobal mask:\n ");
  816. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  817. printk("%0*lx%s",
  818. (int)(sizeof(sh->evtchn_mask[0])*2),
  819. sh->evtchn_mask[i],
  820. i % 8 == 0 ? "\n " : " ");
  821. printk("\nglobally unmasked:\n ");
  822. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  823. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  824. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  825. i % 8 == 0 ? "\n " : " ");
  826. printk("\nlocal cpu%d mask:\n ", cpu);
  827. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  828. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  829. cpu_evtchn[i],
  830. i % 8 == 0 ? "\n " : " ");
  831. printk("\nlocally unmasked:\n ");
  832. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  833. unsigned long pending = sh->evtchn_pending[i]
  834. & ~sh->evtchn_mask[i]
  835. & cpu_evtchn[i];
  836. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  837. pending, i % 8 == 0 ? "\n " : " ");
  838. }
  839. printk("\npending list:\n");
  840. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  841. if (sync_test_bit(i, sh->evtchn_pending)) {
  842. int word_idx = i / BITS_PER_LONG;
  843. printk(" %d: event %d -> irq %d%s%s%s\n",
  844. cpu_from_evtchn(i), i,
  845. evtchn_to_irq[i],
  846. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  847. ? "" : " l2-clear",
  848. !sync_test_bit(i, sh->evtchn_mask)
  849. ? "" : " globally-masked",
  850. sync_test_bit(i, cpu_evtchn)
  851. ? "" : " locally-masked");
  852. }
  853. }
  854. spin_unlock_irqrestore(&debug_lock, flags);
  855. return IRQ_HANDLED;
  856. }
  857. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  858. /*
  859. * Search the CPUs pending events bitmasks. For each one found, map
  860. * the event number to an irq, and feed it into do_IRQ() for
  861. * handling.
  862. *
  863. * Xen uses a two-level bitmap to speed searching. The first level is
  864. * a bitset of words which contain pending event bits. The second
  865. * level is a bitset of pending events themselves.
  866. */
  867. static void __xen_evtchn_do_upcall(void)
  868. {
  869. int cpu = get_cpu();
  870. struct shared_info *s = HYPERVISOR_shared_info;
  871. struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
  872. unsigned count;
  873. do {
  874. unsigned long pending_words;
  875. vcpu_info->evtchn_upcall_pending = 0;
  876. if (__get_cpu_var(xed_nesting_count)++)
  877. goto out;
  878. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  879. /* Clear master flag /before/ clearing selector flag. */
  880. wmb();
  881. #endif
  882. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  883. while (pending_words != 0) {
  884. unsigned long pending_bits;
  885. int word_idx = __ffs(pending_words);
  886. pending_words &= ~(1UL << word_idx);
  887. while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
  888. int bit_idx = __ffs(pending_bits);
  889. int port = (word_idx * BITS_PER_LONG) + bit_idx;
  890. int irq = evtchn_to_irq[port];
  891. struct irq_desc *desc;
  892. mask_evtchn(port);
  893. clear_evtchn(port);
  894. if (irq != -1) {
  895. desc = irq_to_desc(irq);
  896. if (desc)
  897. generic_handle_irq_desc(irq, desc);
  898. }
  899. }
  900. }
  901. BUG_ON(!irqs_disabled());
  902. count = __get_cpu_var(xed_nesting_count);
  903. __get_cpu_var(xed_nesting_count) = 0;
  904. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  905. out:
  906. put_cpu();
  907. }
  908. void xen_evtchn_do_upcall(struct pt_regs *regs)
  909. {
  910. struct pt_regs *old_regs = set_irq_regs(regs);
  911. exit_idle();
  912. irq_enter();
  913. __xen_evtchn_do_upcall();
  914. irq_exit();
  915. set_irq_regs(old_regs);
  916. }
  917. void xen_hvm_evtchn_do_upcall(void)
  918. {
  919. __xen_evtchn_do_upcall();
  920. }
  921. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  922. /* Rebind a new event channel to an existing irq. */
  923. void rebind_evtchn_irq(int evtchn, int irq)
  924. {
  925. struct irq_info *info = info_for_irq(irq);
  926. /* Make sure the irq is masked, since the new event channel
  927. will also be masked. */
  928. disable_irq(irq);
  929. spin_lock(&irq_mapping_update_lock);
  930. /* After resume the irq<->evtchn mappings are all cleared out */
  931. BUG_ON(evtchn_to_irq[evtchn] != -1);
  932. /* Expect irq to have been bound before,
  933. so there should be a proper type */
  934. BUG_ON(info->type == IRQT_UNBOUND);
  935. evtchn_to_irq[evtchn] = irq;
  936. irq_info[irq] = mk_evtchn_info(evtchn);
  937. spin_unlock(&irq_mapping_update_lock);
  938. /* new event channels are always bound to cpu 0 */
  939. irq_set_affinity(irq, cpumask_of(0));
  940. /* Unmask the event channel. */
  941. enable_irq(irq);
  942. }
  943. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  944. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  945. {
  946. struct evtchn_bind_vcpu bind_vcpu;
  947. int evtchn = evtchn_from_irq(irq);
  948. /* events delivered via platform PCI interrupts are always
  949. * routed to vcpu 0 */
  950. if (!VALID_EVTCHN(evtchn) ||
  951. (xen_hvm_domain() && !xen_have_vector_callback))
  952. return -1;
  953. /* Send future instances of this interrupt to other vcpu. */
  954. bind_vcpu.port = evtchn;
  955. bind_vcpu.vcpu = tcpu;
  956. /*
  957. * If this fails, it usually just indicates that we're dealing with a
  958. * virq or IPI channel, which don't actually need to be rebound. Ignore
  959. * it, but don't do the xenlinux-level rebind in that case.
  960. */
  961. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  962. bind_evtchn_to_cpu(evtchn, tcpu);
  963. return 0;
  964. }
  965. static int set_affinity_irq(unsigned irq, const struct cpumask *dest)
  966. {
  967. unsigned tcpu = cpumask_first(dest);
  968. return rebind_irq_to_cpu(irq, tcpu);
  969. }
  970. int resend_irq_on_evtchn(unsigned int irq)
  971. {
  972. int masked, evtchn = evtchn_from_irq(irq);
  973. struct shared_info *s = HYPERVISOR_shared_info;
  974. if (!VALID_EVTCHN(evtchn))
  975. return 1;
  976. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  977. sync_set_bit(evtchn, s->evtchn_pending);
  978. if (!masked)
  979. unmask_evtchn(evtchn);
  980. return 1;
  981. }
  982. static void enable_dynirq(unsigned int irq)
  983. {
  984. int evtchn = evtchn_from_irq(irq);
  985. if (VALID_EVTCHN(evtchn))
  986. unmask_evtchn(evtchn);
  987. }
  988. static void disable_dynirq(unsigned int irq)
  989. {
  990. int evtchn = evtchn_from_irq(irq);
  991. if (VALID_EVTCHN(evtchn))
  992. mask_evtchn(evtchn);
  993. }
  994. static void ack_dynirq(unsigned int irq)
  995. {
  996. int evtchn = evtchn_from_irq(irq);
  997. move_masked_irq(irq);
  998. if (VALID_EVTCHN(evtchn))
  999. unmask_evtchn(evtchn);
  1000. }
  1001. static int retrigger_dynirq(unsigned int irq)
  1002. {
  1003. int evtchn = evtchn_from_irq(irq);
  1004. struct shared_info *sh = HYPERVISOR_shared_info;
  1005. int ret = 0;
  1006. if (VALID_EVTCHN(evtchn)) {
  1007. int masked;
  1008. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  1009. sync_set_bit(evtchn, sh->evtchn_pending);
  1010. if (!masked)
  1011. unmask_evtchn(evtchn);
  1012. ret = 1;
  1013. }
  1014. return ret;
  1015. }
  1016. static void restore_cpu_virqs(unsigned int cpu)
  1017. {
  1018. struct evtchn_bind_virq bind_virq;
  1019. int virq, irq, evtchn;
  1020. for (virq = 0; virq < NR_VIRQS; virq++) {
  1021. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1022. continue;
  1023. BUG_ON(virq_from_irq(irq) != virq);
  1024. /* Get a new binding from Xen. */
  1025. bind_virq.virq = virq;
  1026. bind_virq.vcpu = cpu;
  1027. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1028. &bind_virq) != 0)
  1029. BUG();
  1030. evtchn = bind_virq.port;
  1031. /* Record the new mapping. */
  1032. evtchn_to_irq[evtchn] = irq;
  1033. irq_info[irq] = mk_virq_info(evtchn, virq);
  1034. bind_evtchn_to_cpu(evtchn, cpu);
  1035. }
  1036. }
  1037. static void restore_cpu_ipis(unsigned int cpu)
  1038. {
  1039. struct evtchn_bind_ipi bind_ipi;
  1040. int ipi, irq, evtchn;
  1041. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1042. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1043. continue;
  1044. BUG_ON(ipi_from_irq(irq) != ipi);
  1045. /* Get a new binding from Xen. */
  1046. bind_ipi.vcpu = cpu;
  1047. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1048. &bind_ipi) != 0)
  1049. BUG();
  1050. evtchn = bind_ipi.port;
  1051. /* Record the new mapping. */
  1052. evtchn_to_irq[evtchn] = irq;
  1053. irq_info[irq] = mk_ipi_info(evtchn, ipi);
  1054. bind_evtchn_to_cpu(evtchn, cpu);
  1055. }
  1056. }
  1057. /* Clear an irq's pending state, in preparation for polling on it */
  1058. void xen_clear_irq_pending(int irq)
  1059. {
  1060. int evtchn = evtchn_from_irq(irq);
  1061. if (VALID_EVTCHN(evtchn))
  1062. clear_evtchn(evtchn);
  1063. }
  1064. EXPORT_SYMBOL(xen_clear_irq_pending);
  1065. void xen_set_irq_pending(int irq)
  1066. {
  1067. int evtchn = evtchn_from_irq(irq);
  1068. if (VALID_EVTCHN(evtchn))
  1069. set_evtchn(evtchn);
  1070. }
  1071. bool xen_test_irq_pending(int irq)
  1072. {
  1073. int evtchn = evtchn_from_irq(irq);
  1074. bool ret = false;
  1075. if (VALID_EVTCHN(evtchn))
  1076. ret = test_evtchn(evtchn);
  1077. return ret;
  1078. }
  1079. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1080. * the irq will be disabled so it won't deliver an interrupt. */
  1081. void xen_poll_irq_timeout(int irq, u64 timeout)
  1082. {
  1083. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1084. if (VALID_EVTCHN(evtchn)) {
  1085. struct sched_poll poll;
  1086. poll.nr_ports = 1;
  1087. poll.timeout = timeout;
  1088. set_xen_guest_handle(poll.ports, &evtchn);
  1089. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1090. BUG();
  1091. }
  1092. }
  1093. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1094. /* Poll waiting for an irq to become pending. In the usual case, the
  1095. * irq will be disabled so it won't deliver an interrupt. */
  1096. void xen_poll_irq(int irq)
  1097. {
  1098. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1099. }
  1100. void xen_irq_resume(void)
  1101. {
  1102. unsigned int cpu, irq, evtchn;
  1103. struct irq_desc *desc;
  1104. init_evtchn_cpu_bindings();
  1105. /* New event-channel space is not 'live' yet. */
  1106. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1107. mask_evtchn(evtchn);
  1108. /* No IRQ <-> event-channel mappings. */
  1109. for (irq = 0; irq < nr_irqs; irq++)
  1110. irq_info[irq].evtchn = 0; /* zap event-channel binding */
  1111. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1112. evtchn_to_irq[evtchn] = -1;
  1113. for_each_possible_cpu(cpu) {
  1114. restore_cpu_virqs(cpu);
  1115. restore_cpu_ipis(cpu);
  1116. }
  1117. /*
  1118. * Unmask any IRQF_NO_SUSPEND IRQs which are enabled. These
  1119. * are not handled by the IRQ core.
  1120. */
  1121. for_each_irq_desc(irq, desc) {
  1122. if (!desc->action || !(desc->action->flags & IRQF_NO_SUSPEND))
  1123. continue;
  1124. if (desc->status & IRQ_DISABLED)
  1125. continue;
  1126. evtchn = evtchn_from_irq(irq);
  1127. if (evtchn == -1)
  1128. continue;
  1129. unmask_evtchn(evtchn);
  1130. }
  1131. }
  1132. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1133. .name = "xen-dyn",
  1134. .disable = disable_dynirq,
  1135. .mask = disable_dynirq,
  1136. .unmask = enable_dynirq,
  1137. .eoi = ack_dynirq,
  1138. .set_affinity = set_affinity_irq,
  1139. .retrigger = retrigger_dynirq,
  1140. };
  1141. static struct irq_chip xen_pirq_chip __read_mostly = {
  1142. .name = "xen-pirq",
  1143. .startup = startup_pirq,
  1144. .shutdown = shutdown_pirq,
  1145. .enable = enable_pirq,
  1146. .unmask = enable_pirq,
  1147. .disable = disable_pirq,
  1148. .mask = disable_pirq,
  1149. .ack = ack_pirq,
  1150. .end = end_pirq,
  1151. .set_affinity = set_affinity_irq,
  1152. .retrigger = retrigger_dynirq,
  1153. };
  1154. static struct irq_chip xen_percpu_chip __read_mostly = {
  1155. .name = "xen-percpu",
  1156. .disable = disable_dynirq,
  1157. .mask = disable_dynirq,
  1158. .unmask = enable_dynirq,
  1159. .ack = ack_dynirq,
  1160. };
  1161. int xen_set_callback_via(uint64_t via)
  1162. {
  1163. struct xen_hvm_param a;
  1164. a.domid = DOMID_SELF;
  1165. a.index = HVM_PARAM_CALLBACK_IRQ;
  1166. a.value = via;
  1167. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1168. }
  1169. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1170. #ifdef CONFIG_XEN_PVHVM
  1171. /* Vector callbacks are better than PCI interrupts to receive event
  1172. * channel notifications because we can receive vector callbacks on any
  1173. * vcpu and we don't need PCI support or APIC interactions. */
  1174. void xen_callback_vector(void)
  1175. {
  1176. int rc;
  1177. uint64_t callback_via;
  1178. if (xen_have_vector_callback) {
  1179. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1180. rc = xen_set_callback_via(callback_via);
  1181. if (rc) {
  1182. printk(KERN_ERR "Request for Xen HVM callback vector"
  1183. " failed.\n");
  1184. xen_have_vector_callback = 0;
  1185. return;
  1186. }
  1187. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1188. "enabled\n");
  1189. /* in the restore case the vector has already been allocated */
  1190. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1191. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1192. }
  1193. }
  1194. #else
  1195. void xen_callback_vector(void) {}
  1196. #endif
  1197. void __init xen_init_IRQ(void)
  1198. {
  1199. int i, rc;
  1200. struct physdev_nr_pirqs op_nr_pirqs;
  1201. cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
  1202. GFP_KERNEL);
  1203. irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
  1204. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_nr_pirqs, &op_nr_pirqs);
  1205. if (rc < 0) {
  1206. nr_pirqs = nr_irqs;
  1207. if (rc != -ENOSYS)
  1208. printk(KERN_WARNING "PHYSDEVOP_get_nr_pirqs returned rc=%d\n", rc);
  1209. } else {
  1210. if (xen_pv_domain() && !xen_initial_domain())
  1211. nr_pirqs = max((int)op_nr_pirqs.nr_pirqs, nr_irqs);
  1212. else
  1213. nr_pirqs = op_nr_pirqs.nr_pirqs;
  1214. }
  1215. pirq_to_irq = kcalloc(nr_pirqs, sizeof(*pirq_to_irq), GFP_KERNEL);
  1216. for (i = 0; i < nr_pirqs; i++)
  1217. pirq_to_irq[i] = -1;
  1218. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1219. GFP_KERNEL);
  1220. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1221. evtchn_to_irq[i] = -1;
  1222. init_evtchn_cpu_bindings();
  1223. /* No event channels are 'live' right now. */
  1224. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1225. mask_evtchn(i);
  1226. if (xen_hvm_domain()) {
  1227. xen_callback_vector();
  1228. native_init_IRQ();
  1229. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1230. * __acpi_register_gsi can point at the right function */
  1231. pci_xen_hvm_init();
  1232. } else {
  1233. irq_ctx_init(smp_processor_id());
  1234. if (xen_initial_domain())
  1235. xen_setup_pirqs();
  1236. }
  1237. }