sh_mobile_hdmi.c 42 KB

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  1. /*
  2. * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
  3. * for SLISHDMI13T and SLIPHDMIT IP cores
  4. *
  5. * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/console.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/slab.h>
  22. #include <linux/types.h>
  23. #include <linux/workqueue.h>
  24. #include <sound/soc-dapm.h>
  25. #include <sound/initval.h>
  26. #include <video/sh_mobile_hdmi.h>
  27. #include <video/sh_mobile_lcdc.h>
  28. #include "sh_mobile_lcdcfb.h"
  29. #define HDMI_SYSTEM_CTRL 0x00 /* System control */
  30. #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
  31. bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  32. #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  33. #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  34. #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
  35. bits 19..16 of Internal CTS */
  36. #define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
  37. #define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
  38. #define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
  39. #define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
  40. #define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
  41. #define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
  42. #define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
  43. #define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
  44. #define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
  45. #define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
  46. #define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
  47. #define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
  48. #define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
  49. #define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
  50. #define HDMI_CATEGORY_CODE 0x13 /* Category code */
  51. #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
  52. #define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
  53. #define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
  54. #define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
  55. /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  56. #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
  57. #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
  58. #define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
  59. #define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
  60. #define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
  61. #define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
  62. #define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
  63. #define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
  64. #define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
  65. #define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
  66. #define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
  67. #define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
  68. #define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
  69. #define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
  70. #define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
  71. #define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
  72. #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
  73. #define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
  74. #define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
  75. #define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
  76. #define HDMI_OUTPUT_OPTION 0x46 /* Output option */
  77. #define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
  78. #define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
  79. #define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
  80. #define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
  81. #define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
  82. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
  83. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
  84. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
  85. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
  86. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
  87. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
  88. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
  89. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
  90. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
  91. #define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
  92. #define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
  93. #define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
  94. #define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
  95. #define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
  96. #define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
  97. #define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
  98. #define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
  99. #define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
  100. #define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
  101. #define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
  102. #define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
  103. #define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
  104. #define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
  105. #define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
  106. #define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
  107. #define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
  108. #define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
  109. #define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
  110. #define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
  111. #define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
  112. #define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
  113. #define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
  114. #define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
  115. #define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
  116. #define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
  117. #define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
  118. #define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
  119. #define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
  120. #define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
  121. #define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
  122. #define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
  123. #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
  124. #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
  125. #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
  126. #define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
  127. #define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
  128. #define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
  129. #define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
  130. #define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
  131. #define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
  132. #define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
  133. #define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
  134. #define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
  135. #define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
  136. #define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
  137. #define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
  138. #define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
  139. #define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
  140. #define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
  141. #define HDMI_SHA0 0xB9 /* sha0 */
  142. #define HDMI_SHA1 0xBA /* sha1 */
  143. #define HDMI_SHA2 0xBB /* sha2 */
  144. #define HDMI_SHA3 0xBC /* sha3 */
  145. #define HDMI_SHA4 0xBD /* sha4 */
  146. #define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
  147. #define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
  148. #define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
  149. #define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
  150. #define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
  151. #define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
  152. #define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
  153. #define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
  154. #define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
  155. #define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
  156. #define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
  157. #define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
  158. #define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
  159. #define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
  160. #define HDMI_AN_SEED 0xCC /* An seed */
  161. #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
  162. #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
  163. #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
  164. #define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
  165. #define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
  166. #define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
  167. #define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
  168. #define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
  169. #define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
  170. #define HDMI_PJ 0xD7 /* Pj */
  171. #define HDMI_SHA_RD 0xD8 /* sha_rd */
  172. #define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
  173. #define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
  174. #define HDMI_PJ_SAVED 0xDB /* Pj saved */
  175. #define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
  176. #define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
  177. #define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
  178. #define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
  179. #define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
  180. #define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
  181. #define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
  182. #define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
  183. #define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
  184. #define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
  185. #define HDMI_AN_7_0 0xE8 /* An[7:0] */
  186. #define HDMI_AN_15_8 0xE9 /* An [15:8] */
  187. #define HDMI_AN_23_16 0xEA /* An [23:16] */
  188. #define HDMI_AN_31_24 0xEB /* An [31:24] */
  189. #define HDMI_AN_39_32 0xEC /* An [39:32] */
  190. #define HDMI_AN_47_40 0xED /* An [47:40] */
  191. #define HDMI_AN_55_48 0xEE /* An [55:48] */
  192. #define HDMI_AN_63_56 0xEF /* An [63:56] */
  193. #define HDMI_PRODUCT_ID 0xF0 /* Product ID */
  194. #define HDMI_REVISION_ID 0xF1 /* Revision ID */
  195. #define HDMI_TEST_MODE 0xFE /* Test mode */
  196. enum hotplug_state {
  197. HDMI_HOTPLUG_DISCONNECTED,
  198. HDMI_HOTPLUG_CONNECTED,
  199. HDMI_HOTPLUG_EDID_DONE,
  200. };
  201. struct sh_hdmi {
  202. void __iomem *base;
  203. enum hotplug_state hp_state; /* hot-plug status */
  204. bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */
  205. struct clk *hdmi_clk;
  206. struct device *dev;
  207. struct fb_info *info;
  208. struct mutex mutex; /* Protect the info pointer */
  209. struct delayed_work edid_work;
  210. struct fb_var_screeninfo var;
  211. struct fb_monspecs monspec;
  212. };
  213. static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
  214. {
  215. iowrite8(data, hdmi->base + reg);
  216. }
  217. static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
  218. {
  219. return ioread8(hdmi->base + reg);
  220. }
  221. /*
  222. * HDMI sound
  223. */
  224. static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
  225. unsigned int reg)
  226. {
  227. struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
  228. return hdmi_read(hdmi, reg);
  229. }
  230. static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
  231. unsigned int reg,
  232. unsigned int value)
  233. {
  234. struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
  235. hdmi_write(hdmi, value, reg);
  236. return 0;
  237. }
  238. static struct snd_soc_dai_driver sh_hdmi_dai = {
  239. .name = "sh_mobile_hdmi-hifi",
  240. .playback = {
  241. .stream_name = "Playback",
  242. .channels_min = 2,
  243. .channels_max = 8,
  244. .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
  245. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
  246. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
  247. SNDRV_PCM_RATE_192000,
  248. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
  249. },
  250. };
  251. static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
  252. {
  253. dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
  254. return 0;
  255. }
  256. static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
  257. .probe = sh_hdmi_snd_probe,
  258. .read = sh_hdmi_snd_read,
  259. .write = sh_hdmi_snd_write,
  260. };
  261. /*
  262. * HDMI video
  263. */
  264. /* External video parameter settings */
  265. static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
  266. {
  267. struct fb_var_screeninfo *var = &hdmi->var;
  268. u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
  269. u8 sync = 0;
  270. htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
  271. hdelay = var->hsync_len + var->left_margin;
  272. hblank = var->right_margin + hdelay;
  273. /*
  274. * Vertical timing looks a bit different in Figure 18,
  275. * but let's try the same first by setting offset = 0
  276. */
  277. vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
  278. vdelay = var->vsync_len + var->upper_margin;
  279. vblank = var->lower_margin + vdelay;
  280. voffset = min(var->upper_margin / 2, 6U);
  281. /*
  282. * [3]: VSYNC polarity: Positive
  283. * [2]: HSYNC polarity: Positive
  284. * [1]: Interlace/Progressive: Progressive
  285. * [0]: External video settings enable: used.
  286. */
  287. if (var->sync & FB_SYNC_HOR_HIGH_ACT)
  288. sync |= 4;
  289. if (var->sync & FB_SYNC_VERT_HIGH_ACT)
  290. sync |= 8;
  291. dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
  292. htotal, hblank, hdelay, var->hsync_len,
  293. vtotal, vblank, vdelay, var->vsync_len, sync);
  294. hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
  295. hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
  296. hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
  297. hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
  298. hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
  299. hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
  300. hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
  301. hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
  302. hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
  303. hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
  304. hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
  305. hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
  306. hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
  307. hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
  308. /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
  309. if (!hdmi->preprogrammed_mode)
  310. hdmi_write(hdmi, sync | 1 | (voffset << 4),
  311. HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
  312. }
  313. /**
  314. * sh_hdmi_video_config()
  315. */
  316. static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
  317. {
  318. /*
  319. * [7:4]: Audio sampling frequency: 48kHz
  320. * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
  321. * [0]: Internal/External DE select: internal
  322. */
  323. hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
  324. /*
  325. * [7:6]: Video output format: RGB 4:4:4
  326. * [5:4]: Input video data width: 8 bit
  327. * [3:1]: EAV/SAV location: channel 1
  328. * [0]: Video input color space: RGB
  329. */
  330. hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
  331. /*
  332. * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
  333. * left at 0 by default, this configures 24bpp and sets the Color Depth
  334. * (CD) field in the General Control Packet
  335. */
  336. hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
  337. }
  338. /**
  339. * sh_hdmi_audio_config()
  340. */
  341. static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
  342. {
  343. u8 data;
  344. struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
  345. /*
  346. * [7:4] L/R data swap control
  347. * [3:0] appropriate N[19:16]
  348. */
  349. hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
  350. /* appropriate N[15:8] */
  351. hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
  352. /* appropriate N[7:0] */
  353. hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
  354. /* [7:4] 48 kHz SPDIF not used */
  355. hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
  356. /*
  357. * [6:5] set required down sampling rate if required
  358. * [4:3] set required audio source
  359. */
  360. switch (pdata->flags & HDMI_SND_SRC_MASK) {
  361. default:
  362. /* fall through */
  363. case HDMI_SND_SRC_I2S:
  364. data = 0x0 << 3;
  365. break;
  366. case HDMI_SND_SRC_SPDIF:
  367. data = 0x1 << 3;
  368. break;
  369. case HDMI_SND_SRC_DSD:
  370. data = 0x2 << 3;
  371. break;
  372. case HDMI_SND_SRC_HBR:
  373. data = 0x3 << 3;
  374. break;
  375. }
  376. hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
  377. /* [3:0] set sending channel number for channel status */
  378. hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
  379. /*
  380. * [5:2] set valid I2S source input pin
  381. * [1:0] set input I2S source mode
  382. */
  383. hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
  384. /* [7:4] set valid DSD source input pin */
  385. hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
  386. /* [7:0] set appropriate I2S input pin swap settings if required */
  387. hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
  388. /*
  389. * [7] set validity bit for channel status
  390. * [3:0] set original sample frequency for channel status
  391. */
  392. hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
  393. /*
  394. * [7] set value for channel status
  395. * [6] set value for channel status
  396. * [5] set copyright bit for channel status
  397. * [4:2] set additional information for channel status
  398. * [1:0] set clock accuracy for channel status
  399. */
  400. hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
  401. /* [7:0] set category code for channel status */
  402. hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
  403. /*
  404. * [7:4] set source number for channel status
  405. * [3:0] set word length for channel status
  406. */
  407. hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
  408. /* [7:4] set sample frequency for channel status */
  409. hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
  410. }
  411. /**
  412. * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
  413. */
  414. static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
  415. {
  416. if (hdmi->var.yres > 480) {
  417. /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
  418. /*
  419. * [1:0] Speed_A
  420. * [3:2] Speed_B
  421. * [4] PLLA_Bypass
  422. * [6] DRV_TEST_EN
  423. * [7] DRV_TEST_IN
  424. */
  425. hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
  426. /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
  427. hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
  428. /*
  429. * [2:0] BGR_I_OFFSET
  430. * [6:4] BGR_V_OFFSET
  431. */
  432. hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
  433. /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
  434. hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
  435. /*
  436. * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
  437. * LPF capacitance, LPF resistance[1]
  438. */
  439. hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
  440. /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
  441. hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
  442. /*
  443. * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
  444. * LPF capacitance, LPF resistance[1]
  445. */
  446. hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
  447. /* DRV_CONFIG, PE_CONFIG */
  448. hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
  449. /*
  450. * [2:0] AMON_SEL (4 == LPF voltage)
  451. * [4] PLLA_CONFIG[16]
  452. * [5] PLLB_CONFIG[16]
  453. */
  454. hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
  455. } else {
  456. /* for 480p8bit 27MHz */
  457. hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
  458. hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
  459. hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
  460. hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
  461. hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
  462. hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
  463. hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
  464. hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
  465. hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
  466. }
  467. }
  468. /**
  469. * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
  470. */
  471. static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
  472. {
  473. u8 vic;
  474. /* AVI InfoFrame */
  475. hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
  476. /* Packet Type = 0x82 */
  477. hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
  478. /* Version = 0x02 */
  479. hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
  480. /* Length = 13 (0x0D) */
  481. hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
  482. /* N. A. Checksum */
  483. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
  484. /*
  485. * Y = RGB
  486. * A0 = No Data
  487. * B = Bar Data not valid
  488. * S = No Data
  489. */
  490. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
  491. /*
  492. * [7:6] C = Colorimetry: no data
  493. * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
  494. * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
  495. */
  496. hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
  497. /*
  498. * ITC = No Data
  499. * EC = xvYCC601
  500. * Q = Default (depends on video format)
  501. * SC = No Known non_uniform Scaling
  502. */
  503. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
  504. /*
  505. * VIC = 1280 x 720p: ignored if external config is used
  506. * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
  507. */
  508. if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
  509. vic = 16;
  510. else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
  511. vic = 2;
  512. else
  513. vic = 4;
  514. hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
  515. /* PR = No Repetition */
  516. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
  517. /* Line Number of End of Top Bar (lower 8 bits) */
  518. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
  519. /* Line Number of End of Top Bar (upper 8 bits) */
  520. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
  521. /* Line Number of Start of Bottom Bar (lower 8 bits) */
  522. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
  523. /* Line Number of Start of Bottom Bar (upper 8 bits) */
  524. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
  525. /* Pixel Number of End of Left Bar (lower 8 bits) */
  526. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
  527. /* Pixel Number of End of Left Bar (upper 8 bits) */
  528. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
  529. /* Pixel Number of Start of Right Bar (lower 8 bits) */
  530. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
  531. /* Pixel Number of Start of Right Bar (upper 8 bits) */
  532. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
  533. }
  534. /**
  535. * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
  536. */
  537. static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
  538. {
  539. /* Audio InfoFrame */
  540. hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
  541. /* Packet Type = 0x84 */
  542. hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
  543. /* Version Number = 0x01 */
  544. hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
  545. /* 0 Length = 10 (0x0A) */
  546. hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
  547. /* n. a. Checksum */
  548. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
  549. /* Audio Channel Count = Refer to Stream Header */
  550. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
  551. /* Refer to Stream Header */
  552. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
  553. /* Format depends on coding type (i.e. CT0...CT3) */
  554. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
  555. /* Speaker Channel Allocation = Front Right + Front Left */
  556. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
  557. /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
  558. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
  559. /* Reserved (0) */
  560. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
  561. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
  562. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
  563. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
  564. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
  565. }
  566. /**
  567. * sh_hdmi_configure() - Initialise HDMI for output
  568. */
  569. static void sh_hdmi_configure(struct sh_hdmi *hdmi)
  570. {
  571. /* Configure video format */
  572. sh_hdmi_video_config(hdmi);
  573. /* Configure audio format */
  574. sh_hdmi_audio_config(hdmi);
  575. /* Configure PHY */
  576. sh_hdmi_phy_config(hdmi);
  577. /* Auxiliary Video Information (AVI) InfoFrame */
  578. sh_hdmi_avi_infoframe_setup(hdmi);
  579. /* Audio InfoFrame */
  580. sh_hdmi_audio_infoframe_setup(hdmi);
  581. /*
  582. * Control packet auto send with VSYNC control: auto send
  583. * General control, Gamut metadata, ISRC, and ACP packets
  584. */
  585. hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
  586. /* FIXME */
  587. msleep(10);
  588. /* PS mode b->d, reset PLLA and PLLB */
  589. hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
  590. udelay(10);
  591. hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
  592. }
  593. static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
  594. const struct fb_videomode *mode)
  595. {
  596. long target = PICOS2KHZ(mode->pixclock) * 1000,
  597. rate = clk_round_rate(hdmi->hdmi_clk, target);
  598. unsigned long rate_error = rate > 0 ? abs(rate - target) : ULONG_MAX;
  599. dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
  600. mode->left_margin, mode->xres,
  601. mode->right_margin, mode->hsync_len,
  602. mode->upper_margin, mode->yres,
  603. mode->lower_margin, mode->vsync_len);
  604. dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz\n", target,
  605. rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
  606. mode->refresh);
  607. return rate_error;
  608. }
  609. static int sh_hdmi_read_edid(struct sh_hdmi *hdmi)
  610. {
  611. struct fb_var_screeninfo tmpvar;
  612. struct fb_var_screeninfo *var = &tmpvar;
  613. const struct fb_videomode *mode, *found = NULL;
  614. struct fb_info *info = hdmi->info;
  615. struct fb_modelist *modelist = NULL;
  616. unsigned int f_width = 0, f_height = 0, f_refresh = 0;
  617. unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
  618. bool exact_match = false;
  619. u8 edid[128];
  620. char *forced;
  621. int i;
  622. /* Read EDID */
  623. dev_dbg(hdmi->dev, "Read back EDID code:");
  624. for (i = 0; i < 128; i++) {
  625. edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
  626. #ifdef DEBUG
  627. if ((i % 16) == 0) {
  628. printk(KERN_CONT "\n");
  629. printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
  630. } else {
  631. printk(KERN_CONT " %02X", edid[i]);
  632. }
  633. #endif
  634. }
  635. #ifdef DEBUG
  636. printk(KERN_CONT "\n");
  637. #endif
  638. fb_edid_to_monspecs(edid, &hdmi->monspec);
  639. fb_get_options("sh_mobile_lcdc", &forced);
  640. if (forced && *forced) {
  641. /* Only primitive parsing so far */
  642. i = sscanf(forced, "%ux%u@%u",
  643. &f_width, &f_height, &f_refresh);
  644. if (i < 2) {
  645. f_width = 0;
  646. f_height = 0;
  647. }
  648. dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
  649. f_width, f_height, f_refresh);
  650. }
  651. /* Walk monitor modes to find the best or the exact match */
  652. for (i = 0, mode = hdmi->monspec.modedb;
  653. f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
  654. i++, mode++) {
  655. unsigned long rate_error = sh_hdmi_rate_error(hdmi, mode);
  656. /* No interest in unmatching modes */
  657. if (f_width != mode->xres || f_height != mode->yres)
  658. continue;
  659. if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
  660. /*
  661. * Exact match if either the refresh rate matches or it
  662. * hasn't been specified and we've found a mode, for
  663. * which we can configure the clock precisely
  664. */
  665. exact_match = true;
  666. else if (found && found_rate_error <= rate_error)
  667. /*
  668. * We otherwise search for the closest matching clock
  669. * rate - either if no refresh rate has been specified
  670. * or we cannot find an exactly matching one
  671. */
  672. continue;
  673. /* Check if supported: sufficient fb memory, supported clock-rate */
  674. fb_videomode_to_var(var, mode);
  675. if (info && info->fbops->fb_check_var &&
  676. info->fbops->fb_check_var(var, info)) {
  677. exact_match = false;
  678. continue;
  679. }
  680. found = mode;
  681. found_rate_error = rate_error;
  682. }
  683. /*
  684. * TODO 1: if no ->info is present, postpone running the config until
  685. * after ->info first gets registered.
  686. * TODO 2: consider registering the HDMI platform device from the LCDC
  687. * driver, and passing ->info with HDMI platform data.
  688. */
  689. if (info && !found) {
  690. modelist = hdmi->info->modelist.next &&
  691. !list_empty(&hdmi->info->modelist) ?
  692. list_entry(hdmi->info->modelist.next,
  693. struct fb_modelist, list) :
  694. NULL;
  695. if (modelist) {
  696. found = &modelist->mode;
  697. found_rate_error = sh_hdmi_rate_error(hdmi, found);
  698. }
  699. }
  700. /* No cookie today */
  701. if (!found)
  702. return -ENXIO;
  703. dev_info(hdmi->dev, "Using %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
  704. modelist ? "default" : "EDID", found->xres, found->yres,
  705. found->refresh, PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
  706. if ((found->xres == 720 && found->yres == 480) ||
  707. (found->xres == 1280 && found->yres == 720) ||
  708. (found->xres == 1920 && found->yres == 1080))
  709. hdmi->preprogrammed_mode = true;
  710. else
  711. hdmi->preprogrammed_mode = false;
  712. fb_videomode_to_var(&hdmi->var, found);
  713. sh_hdmi_external_video_param(hdmi);
  714. return 0;
  715. }
  716. static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
  717. {
  718. struct sh_hdmi *hdmi = dev_id;
  719. u8 status1, status2, mask1, mask2;
  720. /* mode_b and PLLA and PLLB reset */
  721. hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
  722. /* How long shall reset be held? */
  723. udelay(10);
  724. /* mode_b and PLLA and PLLB reset release */
  725. hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
  726. status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
  727. status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
  728. mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
  729. mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
  730. /* Correct would be to ack only set bits, but the datasheet requires 0xff */
  731. hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
  732. hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
  733. if (printk_ratelimit())
  734. dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
  735. irq, status1, mask1, status2, mask2);
  736. if (!((status1 & mask1) | (status2 & mask2))) {
  737. return IRQ_NONE;
  738. } else if (status1 & 0xc0) {
  739. u8 msens;
  740. /* Datasheet specifies 10ms... */
  741. udelay(500);
  742. msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
  743. dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
  744. /* Check, if hot plug & MSENS pin status are both high */
  745. if ((msens & 0xC0) == 0xC0) {
  746. /* Display plug in */
  747. hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
  748. /* Set EDID word address */
  749. hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
  750. /* Set EDID segment pointer */
  751. hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
  752. /* Enable EDID interrupt */
  753. hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
  754. } else if (!(status1 & 0x80)) {
  755. /* Display unplug, beware multiple interrupts */
  756. if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
  757. schedule_delayed_work(&hdmi->edid_work, 0);
  758. hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
  759. /* display_off will switch back to mode_a */
  760. }
  761. } else if (status1 & 2) {
  762. /* EDID error interrupt: retry */
  763. /* Set EDID word address */
  764. hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
  765. /* Set EDID segment pointer */
  766. hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
  767. } else if (status1 & 4) {
  768. /* Disable EDID interrupt */
  769. hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
  770. hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
  771. schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
  772. }
  773. return IRQ_HANDLED;
  774. }
  775. /* locking: called with info->lock held, or before register_framebuffer() */
  776. static void sh_hdmi_display_on(void *arg, struct fb_info *info)
  777. {
  778. /*
  779. * info is guaranteed to be valid, when we are called, because our
  780. * FB_EVENT_FB_UNBIND notify is also called with info->lock held
  781. */
  782. struct sh_hdmi *hdmi = arg;
  783. struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
  784. struct sh_mobile_lcdc_chan *ch = info->par;
  785. dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
  786. pdata->lcd_dev, info->state);
  787. /* No need to lock */
  788. hdmi->info = info;
  789. /*
  790. * hp_state can be set to
  791. * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
  792. * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
  793. * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
  794. */
  795. switch (hdmi->hp_state) {
  796. case HDMI_HOTPLUG_EDID_DONE:
  797. /* PS mode d->e. All functions are active */
  798. hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
  799. dev_dbg(hdmi->dev, "HDMI running\n");
  800. break;
  801. case HDMI_HOTPLUG_DISCONNECTED:
  802. info->state = FBINFO_STATE_SUSPENDED;
  803. default:
  804. hdmi->var = ch->display_var;
  805. }
  806. }
  807. /* locking: called with info->lock held */
  808. static void sh_hdmi_display_off(void *arg)
  809. {
  810. struct sh_hdmi *hdmi = arg;
  811. struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
  812. dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
  813. /* PS mode e->a */
  814. hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
  815. }
  816. static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
  817. {
  818. struct fb_info *info = hdmi->info;
  819. struct sh_mobile_lcdc_chan *ch = info->par;
  820. struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
  821. struct fb_videomode mode1, mode2;
  822. fb_var_to_videomode(&mode1, old_var);
  823. fb_var_to_videomode(&mode2, new_var);
  824. dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
  825. mode1.xres, mode1.yres, mode2.xres, mode2.yres);
  826. if (fb_mode_is_equal(&mode1, &mode2))
  827. return false;
  828. dev_dbg(info->dev, "Switching %u -> %u lines\n",
  829. mode1.yres, mode2.yres);
  830. *old_var = *new_var;
  831. return true;
  832. }
  833. /**
  834. * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
  835. * @hdmi: driver context
  836. * @pixclock: pixel clock period in picoseconds
  837. * return: configured positive rate if successful
  838. * 0 if couldn't set the rate, but managed to enable the clock
  839. * negative error, if couldn't enable the clock
  840. */
  841. static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long pixclock)
  842. {
  843. long rate;
  844. int ret;
  845. rate = PICOS2KHZ(pixclock) * 1000;
  846. rate = clk_round_rate(hdmi->hdmi_clk, rate);
  847. if (rate > 0) {
  848. ret = clk_set_rate(hdmi->hdmi_clk, rate);
  849. if (ret < 0) {
  850. dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", rate, ret);
  851. rate = 0;
  852. } else {
  853. dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", rate);
  854. }
  855. } else {
  856. rate = 0;
  857. dev_warn(hdmi->dev, "Cannot get suitable rate: %ld\n", rate);
  858. }
  859. ret = clk_enable(hdmi->hdmi_clk);
  860. if (ret < 0) {
  861. dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
  862. return ret;
  863. }
  864. return rate;
  865. }
  866. /* Hotplug interrupt occurred, read EDID */
  867. static void sh_hdmi_edid_work_fn(struct work_struct *work)
  868. {
  869. struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
  870. struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
  871. struct sh_mobile_lcdc_chan *ch;
  872. int ret;
  873. dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
  874. pdata->lcd_dev, hdmi->hp_state);
  875. if (!pdata->lcd_dev)
  876. return;
  877. mutex_lock(&hdmi->mutex);
  878. if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
  879. /* A device has been plugged in */
  880. pm_runtime_get_sync(hdmi->dev);
  881. ret = sh_hdmi_read_edid(hdmi);
  882. if (ret < 0)
  883. goto out;
  884. /* Reconfigure the clock */
  885. clk_disable(hdmi->hdmi_clk);
  886. ret = sh_hdmi_clk_configure(hdmi, hdmi->var.pixclock);
  887. if (ret < 0)
  888. goto out;
  889. msleep(10);
  890. sh_hdmi_configure(hdmi);
  891. /* Switched to another (d) power-save mode */
  892. msleep(10);
  893. if (!hdmi->info)
  894. goto out;
  895. ch = hdmi->info->par;
  896. acquire_console_sem();
  897. /* HDMI plug in */
  898. if (!sh_hdmi_must_reconfigure(hdmi) &&
  899. hdmi->info->state == FBINFO_STATE_RUNNING) {
  900. /*
  901. * First activation with the default monitor - just turn
  902. * on, if we run a resume here, the logo disappears
  903. */
  904. if (lock_fb_info(hdmi->info)) {
  905. sh_hdmi_display_on(hdmi, hdmi->info);
  906. unlock_fb_info(hdmi->info);
  907. }
  908. } else {
  909. /* New monitor or have to wake up */
  910. fb_set_suspend(hdmi->info, 0);
  911. }
  912. release_console_sem();
  913. } else {
  914. ret = 0;
  915. if (!hdmi->info)
  916. goto out;
  917. hdmi->monspec.modedb_len = 0;
  918. fb_destroy_modedb(hdmi->monspec.modedb);
  919. hdmi->monspec.modedb = NULL;
  920. acquire_console_sem();
  921. /* HDMI disconnect */
  922. fb_set_suspend(hdmi->info, 1);
  923. release_console_sem();
  924. pm_runtime_put(hdmi->dev);
  925. }
  926. out:
  927. if (ret < 0)
  928. hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
  929. mutex_unlock(&hdmi->mutex);
  930. dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
  931. }
  932. static int sh_hdmi_notify(struct notifier_block *nb,
  933. unsigned long action, void *data);
  934. static struct notifier_block sh_hdmi_notifier = {
  935. .notifier_call = sh_hdmi_notify,
  936. };
  937. static int sh_hdmi_notify(struct notifier_block *nb,
  938. unsigned long action, void *data)
  939. {
  940. struct fb_event *event = data;
  941. struct fb_info *info = event->info;
  942. struct sh_mobile_lcdc_chan *ch = info->par;
  943. struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
  944. struct sh_hdmi *hdmi = board_cfg->board_data;
  945. if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
  946. return NOTIFY_DONE;
  947. switch(action) {
  948. case FB_EVENT_FB_REGISTERED:
  949. /* Unneeded, activation taken care by sh_hdmi_display_on() */
  950. break;
  951. case FB_EVENT_FB_UNREGISTERED:
  952. /*
  953. * We are called from unregister_framebuffer() with the
  954. * info->lock held. This is bad for us, because we can race with
  955. * the scheduled work, which has to call fb_set_suspend(), which
  956. * takes info->lock internally, so, sh_hdmi_edid_work_fn()
  957. * cannot take and hold info->lock for the whole function
  958. * duration. Using an additional lock creates a classical AB-BA
  959. * lock up. Therefore, we have to release the info->lock
  960. * temporarily, synchronise with the work queue and re-acquire
  961. * the info->lock.
  962. */
  963. unlock_fb_info(hdmi->info);
  964. mutex_lock(&hdmi->mutex);
  965. hdmi->info = NULL;
  966. mutex_unlock(&hdmi->mutex);
  967. lock_fb_info(hdmi->info);
  968. return NOTIFY_OK;
  969. }
  970. return NOTIFY_DONE;
  971. }
  972. static int __init sh_hdmi_probe(struct platform_device *pdev)
  973. {
  974. struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
  975. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  976. struct sh_mobile_lcdc_board_cfg *board_cfg;
  977. int irq = platform_get_irq(pdev, 0), ret;
  978. struct sh_hdmi *hdmi;
  979. long rate;
  980. if (!res || !pdata || irq < 0)
  981. return -ENODEV;
  982. hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
  983. if (!hdmi) {
  984. dev_err(&pdev->dev, "Cannot allocate device data\n");
  985. return -ENOMEM;
  986. }
  987. mutex_init(&hdmi->mutex);
  988. hdmi->dev = &pdev->dev;
  989. hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
  990. if (IS_ERR(hdmi->hdmi_clk)) {
  991. ret = PTR_ERR(hdmi->hdmi_clk);
  992. dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
  993. goto egetclk;
  994. }
  995. /* Some arbitrary relaxed pixclock just to get things started */
  996. rate = sh_hdmi_clk_configure(hdmi, 37037);
  997. if (rate < 0) {
  998. ret = rate;
  999. goto erate;
  1000. }
  1001. dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
  1002. if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
  1003. dev_err(&pdev->dev, "HDMI register region already claimed\n");
  1004. ret = -EBUSY;
  1005. goto ereqreg;
  1006. }
  1007. hdmi->base = ioremap(res->start, resource_size(res));
  1008. if (!hdmi->base) {
  1009. dev_err(&pdev->dev, "HDMI register region already claimed\n");
  1010. ret = -ENOMEM;
  1011. goto emap;
  1012. }
  1013. platform_set_drvdata(pdev, hdmi);
  1014. /* Product and revision IDs are 0 in sh-mobile version */
  1015. dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
  1016. hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
  1017. /* Set up LCDC callbacks */
  1018. board_cfg = &pdata->lcd_chan->board_cfg;
  1019. board_cfg->owner = THIS_MODULE;
  1020. board_cfg->board_data = hdmi;
  1021. board_cfg->display_on = sh_hdmi_display_on;
  1022. board_cfg->display_off = sh_hdmi_display_off;
  1023. INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
  1024. pm_runtime_enable(&pdev->dev);
  1025. pm_runtime_resume(&pdev->dev);
  1026. ret = request_irq(irq, sh_hdmi_hotplug, 0,
  1027. dev_name(&pdev->dev), hdmi);
  1028. if (ret < 0) {
  1029. dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
  1030. goto ereqirq;
  1031. }
  1032. ret = snd_soc_register_codec(&pdev->dev,
  1033. &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
  1034. if (ret < 0) {
  1035. dev_err(&pdev->dev, "codec registration failed\n");
  1036. goto ecodec;
  1037. }
  1038. return 0;
  1039. ecodec:
  1040. free_irq(irq, hdmi);
  1041. ereqirq:
  1042. pm_runtime_disable(&pdev->dev);
  1043. iounmap(hdmi->base);
  1044. emap:
  1045. release_mem_region(res->start, resource_size(res));
  1046. ereqreg:
  1047. clk_disable(hdmi->hdmi_clk);
  1048. erate:
  1049. clk_put(hdmi->hdmi_clk);
  1050. egetclk:
  1051. mutex_destroy(&hdmi->mutex);
  1052. kfree(hdmi);
  1053. return ret;
  1054. }
  1055. static int __exit sh_hdmi_remove(struct platform_device *pdev)
  1056. {
  1057. struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
  1058. struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
  1059. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1060. struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
  1061. int irq = platform_get_irq(pdev, 0);
  1062. snd_soc_unregister_codec(&pdev->dev);
  1063. board_cfg->display_on = NULL;
  1064. board_cfg->display_off = NULL;
  1065. board_cfg->board_data = NULL;
  1066. board_cfg->owner = NULL;
  1067. /* No new work will be scheduled, wait for running ISR */
  1068. free_irq(irq, hdmi);
  1069. /* Wait for already scheduled work */
  1070. cancel_delayed_work_sync(&hdmi->edid_work);
  1071. pm_runtime_disable(&pdev->dev);
  1072. clk_disable(hdmi->hdmi_clk);
  1073. clk_put(hdmi->hdmi_clk);
  1074. iounmap(hdmi->base);
  1075. release_mem_region(res->start, resource_size(res));
  1076. mutex_destroy(&hdmi->mutex);
  1077. kfree(hdmi);
  1078. return 0;
  1079. }
  1080. static struct platform_driver sh_hdmi_driver = {
  1081. .remove = __exit_p(sh_hdmi_remove),
  1082. .driver = {
  1083. .name = "sh-mobile-hdmi",
  1084. },
  1085. };
  1086. static int __init sh_hdmi_init(void)
  1087. {
  1088. return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
  1089. }
  1090. module_init(sh_hdmi_init);
  1091. static void __exit sh_hdmi_exit(void)
  1092. {
  1093. platform_driver_unregister(&sh_hdmi_driver);
  1094. }
  1095. module_exit(sh_hdmi_exit);
  1096. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
  1097. MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
  1098. MODULE_LICENSE("GPL v2");