cputable.c 63 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. #include <asm/mmu.h>
  21. struct cpu_spec* cur_cpu_spec = NULL;
  22. EXPORT_SYMBOL(cur_cpu_spec);
  23. /* The platform string corresponding to the real PVR */
  24. const char *powerpc_base_platform;
  25. /* NOTE:
  26. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  27. * the responsibility of the appropriate CPU save/restore functions to
  28. * eventually copy these settings over. Those save/restore aren't yet
  29. * part of the cputable though. That has to be fixed for both ppc32
  30. * and ppc64
  31. */
  32. #ifdef CONFIG_PPC32
  33. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  46. extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec);
  47. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  48. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  49. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  50. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  54. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  55. #endif /* CONFIG_PPC32 */
  56. #ifdef CONFIG_PPC64
  57. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  58. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  59. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  60. extern void __restore_cpu_pa6t(void);
  61. extern void __restore_cpu_ppc970(void);
  62. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  63. extern void __restore_cpu_power7(void);
  64. #endif /* CONFIG_PPC64 */
  65. #if defined(CONFIG_E500)
  66. extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
  67. extern void __restore_cpu_e5500(void);
  68. #endif /* CONFIG_E500 */
  69. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  70. * ones as well...
  71. */
  72. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  73. PPC_FEATURE_HAS_MMU)
  74. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  75. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  76. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  77. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  78. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  79. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  80. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  81. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  82. PPC_FEATURE_TRUE_LE | \
  83. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  84. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  85. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  86. PPC_FEATURE_TRUE_LE | \
  87. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  88. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  89. PPC_FEATURE_TRUE_LE | \
  90. PPC_FEATURE_HAS_ALTIVEC_COMP)
  91. #ifdef CONFIG_PPC_BOOK3E_64
  92. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  93. #else
  94. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  95. PPC_FEATURE_BOOKE)
  96. #endif
  97. static struct cpu_spec __initdata cpu_specs[] = {
  98. #ifdef CONFIG_PPC_BOOK3S_64
  99. { /* Power3 */
  100. .pvr_mask = 0xffff0000,
  101. .pvr_value = 0x00400000,
  102. .cpu_name = "POWER3 (630)",
  103. .cpu_features = CPU_FTRS_POWER3,
  104. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  105. .mmu_features = MMU_FTR_HPTE_TABLE,
  106. .icache_bsize = 128,
  107. .dcache_bsize = 128,
  108. .num_pmcs = 8,
  109. .pmc_type = PPC_PMC_IBM,
  110. .oprofile_cpu_type = "ppc64/power3",
  111. .oprofile_type = PPC_OPROFILE_RS64,
  112. .machine_check = machine_check_generic,
  113. .platform = "power3",
  114. },
  115. { /* Power3+ */
  116. .pvr_mask = 0xffff0000,
  117. .pvr_value = 0x00410000,
  118. .cpu_name = "POWER3 (630+)",
  119. .cpu_features = CPU_FTRS_POWER3,
  120. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  121. .mmu_features = MMU_FTR_HPTE_TABLE,
  122. .icache_bsize = 128,
  123. .dcache_bsize = 128,
  124. .num_pmcs = 8,
  125. .pmc_type = PPC_PMC_IBM,
  126. .oprofile_cpu_type = "ppc64/power3",
  127. .oprofile_type = PPC_OPROFILE_RS64,
  128. .machine_check = machine_check_generic,
  129. .platform = "power3",
  130. },
  131. { /* Northstar */
  132. .pvr_mask = 0xffff0000,
  133. .pvr_value = 0x00330000,
  134. .cpu_name = "RS64-II (northstar)",
  135. .cpu_features = CPU_FTRS_RS64,
  136. .cpu_user_features = COMMON_USER_PPC64,
  137. .mmu_features = MMU_FTR_HPTE_TABLE,
  138. .icache_bsize = 128,
  139. .dcache_bsize = 128,
  140. .num_pmcs = 8,
  141. .pmc_type = PPC_PMC_IBM,
  142. .oprofile_cpu_type = "ppc64/rs64",
  143. .oprofile_type = PPC_OPROFILE_RS64,
  144. .machine_check = machine_check_generic,
  145. .platform = "rs64",
  146. },
  147. { /* Pulsar */
  148. .pvr_mask = 0xffff0000,
  149. .pvr_value = 0x00340000,
  150. .cpu_name = "RS64-III (pulsar)",
  151. .cpu_features = CPU_FTRS_RS64,
  152. .cpu_user_features = COMMON_USER_PPC64,
  153. .mmu_features = MMU_FTR_HPTE_TABLE,
  154. .icache_bsize = 128,
  155. .dcache_bsize = 128,
  156. .num_pmcs = 8,
  157. .pmc_type = PPC_PMC_IBM,
  158. .oprofile_cpu_type = "ppc64/rs64",
  159. .oprofile_type = PPC_OPROFILE_RS64,
  160. .machine_check = machine_check_generic,
  161. .platform = "rs64",
  162. },
  163. { /* I-star */
  164. .pvr_mask = 0xffff0000,
  165. .pvr_value = 0x00360000,
  166. .cpu_name = "RS64-III (icestar)",
  167. .cpu_features = CPU_FTRS_RS64,
  168. .cpu_user_features = COMMON_USER_PPC64,
  169. .mmu_features = MMU_FTR_HPTE_TABLE,
  170. .icache_bsize = 128,
  171. .dcache_bsize = 128,
  172. .num_pmcs = 8,
  173. .pmc_type = PPC_PMC_IBM,
  174. .oprofile_cpu_type = "ppc64/rs64",
  175. .oprofile_type = PPC_OPROFILE_RS64,
  176. .machine_check = machine_check_generic,
  177. .platform = "rs64",
  178. },
  179. { /* S-star */
  180. .pvr_mask = 0xffff0000,
  181. .pvr_value = 0x00370000,
  182. .cpu_name = "RS64-IV (sstar)",
  183. .cpu_features = CPU_FTRS_RS64,
  184. .cpu_user_features = COMMON_USER_PPC64,
  185. .mmu_features = MMU_FTR_HPTE_TABLE,
  186. .icache_bsize = 128,
  187. .dcache_bsize = 128,
  188. .num_pmcs = 8,
  189. .pmc_type = PPC_PMC_IBM,
  190. .oprofile_cpu_type = "ppc64/rs64",
  191. .oprofile_type = PPC_OPROFILE_RS64,
  192. .machine_check = machine_check_generic,
  193. .platform = "rs64",
  194. },
  195. { /* Power4 */
  196. .pvr_mask = 0xffff0000,
  197. .pvr_value = 0x00350000,
  198. .cpu_name = "POWER4 (gp)",
  199. .cpu_features = CPU_FTRS_POWER4,
  200. .cpu_user_features = COMMON_USER_POWER4,
  201. .mmu_features = MMU_FTR_HPTE_TABLE,
  202. .icache_bsize = 128,
  203. .dcache_bsize = 128,
  204. .num_pmcs = 8,
  205. .pmc_type = PPC_PMC_IBM,
  206. .oprofile_cpu_type = "ppc64/power4",
  207. .oprofile_type = PPC_OPROFILE_POWER4,
  208. .machine_check = machine_check_generic,
  209. .platform = "power4",
  210. },
  211. { /* Power4+ */
  212. .pvr_mask = 0xffff0000,
  213. .pvr_value = 0x00380000,
  214. .cpu_name = "POWER4+ (gq)",
  215. .cpu_features = CPU_FTRS_POWER4,
  216. .cpu_user_features = COMMON_USER_POWER4,
  217. .mmu_features = MMU_FTR_HPTE_TABLE,
  218. .icache_bsize = 128,
  219. .dcache_bsize = 128,
  220. .num_pmcs = 8,
  221. .pmc_type = PPC_PMC_IBM,
  222. .oprofile_cpu_type = "ppc64/power4",
  223. .oprofile_type = PPC_OPROFILE_POWER4,
  224. .machine_check = machine_check_generic,
  225. .platform = "power4",
  226. },
  227. { /* PPC970 */
  228. .pvr_mask = 0xffff0000,
  229. .pvr_value = 0x00390000,
  230. .cpu_name = "PPC970",
  231. .cpu_features = CPU_FTRS_PPC970,
  232. .cpu_user_features = COMMON_USER_POWER4 |
  233. PPC_FEATURE_HAS_ALTIVEC_COMP,
  234. .mmu_features = MMU_FTR_HPTE_TABLE,
  235. .icache_bsize = 128,
  236. .dcache_bsize = 128,
  237. .num_pmcs = 8,
  238. .pmc_type = PPC_PMC_IBM,
  239. .cpu_setup = __setup_cpu_ppc970,
  240. .cpu_restore = __restore_cpu_ppc970,
  241. .oprofile_cpu_type = "ppc64/970",
  242. .oprofile_type = PPC_OPROFILE_POWER4,
  243. .machine_check = machine_check_generic,
  244. .platform = "ppc970",
  245. },
  246. { /* PPC970FX */
  247. .pvr_mask = 0xffff0000,
  248. .pvr_value = 0x003c0000,
  249. .cpu_name = "PPC970FX",
  250. .cpu_features = CPU_FTRS_PPC970,
  251. .cpu_user_features = COMMON_USER_POWER4 |
  252. PPC_FEATURE_HAS_ALTIVEC_COMP,
  253. .mmu_features = MMU_FTR_HPTE_TABLE,
  254. .icache_bsize = 128,
  255. .dcache_bsize = 128,
  256. .num_pmcs = 8,
  257. .pmc_type = PPC_PMC_IBM,
  258. .cpu_setup = __setup_cpu_ppc970,
  259. .cpu_restore = __restore_cpu_ppc970,
  260. .oprofile_cpu_type = "ppc64/970",
  261. .oprofile_type = PPC_OPROFILE_POWER4,
  262. .machine_check = machine_check_generic,
  263. .platform = "ppc970",
  264. },
  265. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  266. .pvr_mask = 0xffffffff,
  267. .pvr_value = 0x00440100,
  268. .cpu_name = "PPC970MP",
  269. .cpu_features = CPU_FTRS_PPC970,
  270. .cpu_user_features = COMMON_USER_POWER4 |
  271. PPC_FEATURE_HAS_ALTIVEC_COMP,
  272. .mmu_features = MMU_FTR_HPTE_TABLE,
  273. .icache_bsize = 128,
  274. .dcache_bsize = 128,
  275. .num_pmcs = 8,
  276. .pmc_type = PPC_PMC_IBM,
  277. .cpu_setup = __setup_cpu_ppc970,
  278. .cpu_restore = __restore_cpu_ppc970,
  279. .oprofile_cpu_type = "ppc64/970MP",
  280. .oprofile_type = PPC_OPROFILE_POWER4,
  281. .machine_check = machine_check_generic,
  282. .platform = "ppc970",
  283. },
  284. { /* PPC970MP */
  285. .pvr_mask = 0xffff0000,
  286. .pvr_value = 0x00440000,
  287. .cpu_name = "PPC970MP",
  288. .cpu_features = CPU_FTRS_PPC970,
  289. .cpu_user_features = COMMON_USER_POWER4 |
  290. PPC_FEATURE_HAS_ALTIVEC_COMP,
  291. .mmu_features = MMU_FTR_HPTE_TABLE,
  292. .icache_bsize = 128,
  293. .dcache_bsize = 128,
  294. .num_pmcs = 8,
  295. .pmc_type = PPC_PMC_IBM,
  296. .cpu_setup = __setup_cpu_ppc970MP,
  297. .cpu_restore = __restore_cpu_ppc970,
  298. .oprofile_cpu_type = "ppc64/970MP",
  299. .oprofile_type = PPC_OPROFILE_POWER4,
  300. .machine_check = machine_check_generic,
  301. .platform = "ppc970",
  302. },
  303. { /* PPC970GX */
  304. .pvr_mask = 0xffff0000,
  305. .pvr_value = 0x00450000,
  306. .cpu_name = "PPC970GX",
  307. .cpu_features = CPU_FTRS_PPC970,
  308. .cpu_user_features = COMMON_USER_POWER4 |
  309. PPC_FEATURE_HAS_ALTIVEC_COMP,
  310. .mmu_features = MMU_FTR_HPTE_TABLE,
  311. .icache_bsize = 128,
  312. .dcache_bsize = 128,
  313. .num_pmcs = 8,
  314. .pmc_type = PPC_PMC_IBM,
  315. .cpu_setup = __setup_cpu_ppc970,
  316. .oprofile_cpu_type = "ppc64/970",
  317. .oprofile_type = PPC_OPROFILE_POWER4,
  318. .machine_check = machine_check_generic,
  319. .platform = "ppc970",
  320. },
  321. { /* Power5 GR */
  322. .pvr_mask = 0xffff0000,
  323. .pvr_value = 0x003a0000,
  324. .cpu_name = "POWER5 (gr)",
  325. .cpu_features = CPU_FTRS_POWER5,
  326. .cpu_user_features = COMMON_USER_POWER5,
  327. .mmu_features = MMU_FTR_HPTE_TABLE,
  328. .icache_bsize = 128,
  329. .dcache_bsize = 128,
  330. .num_pmcs = 6,
  331. .pmc_type = PPC_PMC_IBM,
  332. .oprofile_cpu_type = "ppc64/power5",
  333. .oprofile_type = PPC_OPROFILE_POWER4,
  334. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  335. * and above but only works on POWER5 and above
  336. */
  337. .oprofile_mmcra_sihv = MMCRA_SIHV,
  338. .oprofile_mmcra_sipr = MMCRA_SIPR,
  339. .machine_check = machine_check_generic,
  340. .platform = "power5",
  341. },
  342. { /* Power5++ */
  343. .pvr_mask = 0xffffff00,
  344. .pvr_value = 0x003b0300,
  345. .cpu_name = "POWER5+ (gs)",
  346. .cpu_features = CPU_FTRS_POWER5,
  347. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  348. .mmu_features = MMU_FTR_HPTE_TABLE,
  349. .icache_bsize = 128,
  350. .dcache_bsize = 128,
  351. .num_pmcs = 6,
  352. .oprofile_cpu_type = "ppc64/power5++",
  353. .oprofile_type = PPC_OPROFILE_POWER4,
  354. .oprofile_mmcra_sihv = MMCRA_SIHV,
  355. .oprofile_mmcra_sipr = MMCRA_SIPR,
  356. .machine_check = machine_check_generic,
  357. .platform = "power5+",
  358. },
  359. { /* Power5 GS */
  360. .pvr_mask = 0xffff0000,
  361. .pvr_value = 0x003b0000,
  362. .cpu_name = "POWER5+ (gs)",
  363. .cpu_features = CPU_FTRS_POWER5,
  364. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  365. .mmu_features = MMU_FTR_HPTE_TABLE,
  366. .icache_bsize = 128,
  367. .dcache_bsize = 128,
  368. .num_pmcs = 6,
  369. .pmc_type = PPC_PMC_IBM,
  370. .oprofile_cpu_type = "ppc64/power5+",
  371. .oprofile_type = PPC_OPROFILE_POWER4,
  372. .oprofile_mmcra_sihv = MMCRA_SIHV,
  373. .oprofile_mmcra_sipr = MMCRA_SIPR,
  374. .machine_check = machine_check_generic,
  375. .platform = "power5+",
  376. },
  377. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  378. .pvr_mask = 0xffffffff,
  379. .pvr_value = 0x0f000001,
  380. .cpu_name = "POWER5+",
  381. .cpu_features = CPU_FTRS_POWER5,
  382. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  383. .mmu_features = MMU_FTR_HPTE_TABLE,
  384. .icache_bsize = 128,
  385. .dcache_bsize = 128,
  386. .machine_check = machine_check_generic,
  387. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  388. .oprofile_type = PPC_OPROFILE_POWER4,
  389. .platform = "power5+",
  390. },
  391. { /* Power6 */
  392. .pvr_mask = 0xffff0000,
  393. .pvr_value = 0x003e0000,
  394. .cpu_name = "POWER6 (raw)",
  395. .cpu_features = CPU_FTRS_POWER6,
  396. .cpu_user_features = COMMON_USER_POWER6 |
  397. PPC_FEATURE_POWER6_EXT,
  398. .mmu_features = MMU_FTR_HPTE_TABLE,
  399. .icache_bsize = 128,
  400. .dcache_bsize = 128,
  401. .num_pmcs = 6,
  402. .pmc_type = PPC_PMC_IBM,
  403. .oprofile_cpu_type = "ppc64/power6",
  404. .oprofile_type = PPC_OPROFILE_POWER4,
  405. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  406. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  407. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  408. POWER6_MMCRA_OTHER,
  409. .machine_check = machine_check_generic,
  410. .platform = "power6x",
  411. },
  412. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  413. .pvr_mask = 0xffffffff,
  414. .pvr_value = 0x0f000002,
  415. .cpu_name = "POWER6 (architected)",
  416. .cpu_features = CPU_FTRS_POWER6,
  417. .cpu_user_features = COMMON_USER_POWER6,
  418. .mmu_features = MMU_FTR_HPTE_TABLE,
  419. .icache_bsize = 128,
  420. .dcache_bsize = 128,
  421. .machine_check = machine_check_generic,
  422. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  423. .oprofile_type = PPC_OPROFILE_POWER4,
  424. .platform = "power6",
  425. },
  426. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  427. .pvr_mask = 0xffffffff,
  428. .pvr_value = 0x0f000003,
  429. .cpu_name = "POWER7 (architected)",
  430. .cpu_features = CPU_FTRS_POWER7,
  431. .cpu_user_features = COMMON_USER_POWER7,
  432. .mmu_features = MMU_FTR_HPTE_TABLE |
  433. MMU_FTR_TLBIE_206,
  434. .icache_bsize = 128,
  435. .dcache_bsize = 128,
  436. .machine_check = machine_check_generic,
  437. .oprofile_type = PPC_OPROFILE_POWER4,
  438. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  439. .platform = "power7",
  440. },
  441. { /* Power7 */
  442. .pvr_mask = 0xffff0000,
  443. .pvr_value = 0x003f0000,
  444. .cpu_name = "POWER7 (raw)",
  445. .cpu_features = CPU_FTRS_POWER7,
  446. .cpu_user_features = COMMON_USER_POWER7,
  447. .mmu_features = MMU_FTR_HPTE_TABLE |
  448. MMU_FTR_TLBIE_206,
  449. .icache_bsize = 128,
  450. .dcache_bsize = 128,
  451. .num_pmcs = 6,
  452. .pmc_type = PPC_PMC_IBM,
  453. .cpu_setup = __setup_cpu_power7,
  454. .cpu_restore = __restore_cpu_power7,
  455. .oprofile_cpu_type = "ppc64/power7",
  456. .oprofile_type = PPC_OPROFILE_POWER4,
  457. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  458. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  459. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  460. POWER6_MMCRA_OTHER,
  461. .platform = "power7",
  462. },
  463. { /* Cell Broadband Engine */
  464. .pvr_mask = 0xffff0000,
  465. .pvr_value = 0x00700000,
  466. .cpu_name = "Cell Broadband Engine",
  467. .cpu_features = CPU_FTRS_CELL,
  468. .cpu_user_features = COMMON_USER_PPC64 |
  469. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  470. PPC_FEATURE_SMT,
  471. .mmu_features = MMU_FTR_HPTE_TABLE,
  472. .icache_bsize = 128,
  473. .dcache_bsize = 128,
  474. .num_pmcs = 4,
  475. .pmc_type = PPC_PMC_IBM,
  476. .oprofile_cpu_type = "ppc64/cell-be",
  477. .oprofile_type = PPC_OPROFILE_CELL,
  478. .machine_check = machine_check_generic,
  479. .platform = "ppc-cell-be",
  480. },
  481. { /* PA Semi PA6T */
  482. .pvr_mask = 0x7fff0000,
  483. .pvr_value = 0x00900000,
  484. .cpu_name = "PA6T",
  485. .cpu_features = CPU_FTRS_PA6T,
  486. .cpu_user_features = COMMON_USER_PA6T,
  487. .mmu_features = MMU_FTR_HPTE_TABLE,
  488. .icache_bsize = 64,
  489. .dcache_bsize = 64,
  490. .num_pmcs = 6,
  491. .pmc_type = PPC_PMC_PA6T,
  492. .cpu_setup = __setup_cpu_pa6t,
  493. .cpu_restore = __restore_cpu_pa6t,
  494. .oprofile_cpu_type = "ppc64/pa6t",
  495. .oprofile_type = PPC_OPROFILE_PA6T,
  496. .machine_check = machine_check_generic,
  497. .platform = "pa6t",
  498. },
  499. { /* default match */
  500. .pvr_mask = 0x00000000,
  501. .pvr_value = 0x00000000,
  502. .cpu_name = "POWER4 (compatible)",
  503. .cpu_features = CPU_FTRS_COMPATIBLE,
  504. .cpu_user_features = COMMON_USER_PPC64,
  505. .mmu_features = MMU_FTR_HPTE_TABLE,
  506. .icache_bsize = 128,
  507. .dcache_bsize = 128,
  508. .num_pmcs = 6,
  509. .pmc_type = PPC_PMC_IBM,
  510. .machine_check = machine_check_generic,
  511. .platform = "power4",
  512. }
  513. #endif /* CONFIG_PPC_BOOK3S_64 */
  514. #ifdef CONFIG_PPC32
  515. #if CLASSIC_PPC
  516. { /* 601 */
  517. .pvr_mask = 0xffff0000,
  518. .pvr_value = 0x00010000,
  519. .cpu_name = "601",
  520. .cpu_features = CPU_FTRS_PPC601,
  521. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  522. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  523. .mmu_features = MMU_FTR_HPTE_TABLE,
  524. .icache_bsize = 32,
  525. .dcache_bsize = 32,
  526. .machine_check = machine_check_generic,
  527. .platform = "ppc601",
  528. },
  529. { /* 603 */
  530. .pvr_mask = 0xffff0000,
  531. .pvr_value = 0x00030000,
  532. .cpu_name = "603",
  533. .cpu_features = CPU_FTRS_603,
  534. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  535. .mmu_features = 0,
  536. .icache_bsize = 32,
  537. .dcache_bsize = 32,
  538. .cpu_setup = __setup_cpu_603,
  539. .machine_check = machine_check_generic,
  540. .platform = "ppc603",
  541. },
  542. { /* 603e */
  543. .pvr_mask = 0xffff0000,
  544. .pvr_value = 0x00060000,
  545. .cpu_name = "603e",
  546. .cpu_features = CPU_FTRS_603,
  547. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  548. .mmu_features = 0,
  549. .icache_bsize = 32,
  550. .dcache_bsize = 32,
  551. .cpu_setup = __setup_cpu_603,
  552. .machine_check = machine_check_generic,
  553. .platform = "ppc603",
  554. },
  555. { /* 603ev */
  556. .pvr_mask = 0xffff0000,
  557. .pvr_value = 0x00070000,
  558. .cpu_name = "603ev",
  559. .cpu_features = CPU_FTRS_603,
  560. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  561. .mmu_features = 0,
  562. .icache_bsize = 32,
  563. .dcache_bsize = 32,
  564. .cpu_setup = __setup_cpu_603,
  565. .machine_check = machine_check_generic,
  566. .platform = "ppc603",
  567. },
  568. { /* 604 */
  569. .pvr_mask = 0xffff0000,
  570. .pvr_value = 0x00040000,
  571. .cpu_name = "604",
  572. .cpu_features = CPU_FTRS_604,
  573. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  574. .mmu_features = MMU_FTR_HPTE_TABLE,
  575. .icache_bsize = 32,
  576. .dcache_bsize = 32,
  577. .num_pmcs = 2,
  578. .cpu_setup = __setup_cpu_604,
  579. .machine_check = machine_check_generic,
  580. .platform = "ppc604",
  581. },
  582. { /* 604e */
  583. .pvr_mask = 0xfffff000,
  584. .pvr_value = 0x00090000,
  585. .cpu_name = "604e",
  586. .cpu_features = CPU_FTRS_604,
  587. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  588. .mmu_features = MMU_FTR_HPTE_TABLE,
  589. .icache_bsize = 32,
  590. .dcache_bsize = 32,
  591. .num_pmcs = 4,
  592. .cpu_setup = __setup_cpu_604,
  593. .machine_check = machine_check_generic,
  594. .platform = "ppc604",
  595. },
  596. { /* 604r */
  597. .pvr_mask = 0xffff0000,
  598. .pvr_value = 0x00090000,
  599. .cpu_name = "604r",
  600. .cpu_features = CPU_FTRS_604,
  601. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  602. .mmu_features = MMU_FTR_HPTE_TABLE,
  603. .icache_bsize = 32,
  604. .dcache_bsize = 32,
  605. .num_pmcs = 4,
  606. .cpu_setup = __setup_cpu_604,
  607. .machine_check = machine_check_generic,
  608. .platform = "ppc604",
  609. },
  610. { /* 604ev */
  611. .pvr_mask = 0xffff0000,
  612. .pvr_value = 0x000a0000,
  613. .cpu_name = "604ev",
  614. .cpu_features = CPU_FTRS_604,
  615. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  616. .mmu_features = MMU_FTR_HPTE_TABLE,
  617. .icache_bsize = 32,
  618. .dcache_bsize = 32,
  619. .num_pmcs = 4,
  620. .cpu_setup = __setup_cpu_604,
  621. .machine_check = machine_check_generic,
  622. .platform = "ppc604",
  623. },
  624. { /* 740/750 (0x4202, don't support TAU ?) */
  625. .pvr_mask = 0xffffffff,
  626. .pvr_value = 0x00084202,
  627. .cpu_name = "740/750",
  628. .cpu_features = CPU_FTRS_740_NOTAU,
  629. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  630. .mmu_features = MMU_FTR_HPTE_TABLE,
  631. .icache_bsize = 32,
  632. .dcache_bsize = 32,
  633. .num_pmcs = 4,
  634. .cpu_setup = __setup_cpu_750,
  635. .machine_check = machine_check_generic,
  636. .platform = "ppc750",
  637. },
  638. { /* 750CX (80100 and 8010x?) */
  639. .pvr_mask = 0xfffffff0,
  640. .pvr_value = 0x00080100,
  641. .cpu_name = "750CX",
  642. .cpu_features = CPU_FTRS_750,
  643. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  644. .mmu_features = MMU_FTR_HPTE_TABLE,
  645. .icache_bsize = 32,
  646. .dcache_bsize = 32,
  647. .num_pmcs = 4,
  648. .cpu_setup = __setup_cpu_750cx,
  649. .machine_check = machine_check_generic,
  650. .platform = "ppc750",
  651. },
  652. { /* 750CX (82201 and 82202) */
  653. .pvr_mask = 0xfffffff0,
  654. .pvr_value = 0x00082200,
  655. .cpu_name = "750CX",
  656. .cpu_features = CPU_FTRS_750,
  657. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  658. .mmu_features = MMU_FTR_HPTE_TABLE,
  659. .icache_bsize = 32,
  660. .dcache_bsize = 32,
  661. .num_pmcs = 4,
  662. .pmc_type = PPC_PMC_IBM,
  663. .cpu_setup = __setup_cpu_750cx,
  664. .machine_check = machine_check_generic,
  665. .platform = "ppc750",
  666. },
  667. { /* 750CXe (82214) */
  668. .pvr_mask = 0xfffffff0,
  669. .pvr_value = 0x00082210,
  670. .cpu_name = "750CXe",
  671. .cpu_features = CPU_FTRS_750,
  672. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  673. .mmu_features = MMU_FTR_HPTE_TABLE,
  674. .icache_bsize = 32,
  675. .dcache_bsize = 32,
  676. .num_pmcs = 4,
  677. .pmc_type = PPC_PMC_IBM,
  678. .cpu_setup = __setup_cpu_750cx,
  679. .machine_check = machine_check_generic,
  680. .platform = "ppc750",
  681. },
  682. { /* 750CXe "Gekko" (83214) */
  683. .pvr_mask = 0xffffffff,
  684. .pvr_value = 0x00083214,
  685. .cpu_name = "750CXe",
  686. .cpu_features = CPU_FTRS_750,
  687. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  688. .mmu_features = MMU_FTR_HPTE_TABLE,
  689. .icache_bsize = 32,
  690. .dcache_bsize = 32,
  691. .num_pmcs = 4,
  692. .pmc_type = PPC_PMC_IBM,
  693. .cpu_setup = __setup_cpu_750cx,
  694. .machine_check = machine_check_generic,
  695. .platform = "ppc750",
  696. },
  697. { /* 750CL (and "Broadway") */
  698. .pvr_mask = 0xfffff0e0,
  699. .pvr_value = 0x00087000,
  700. .cpu_name = "750CL",
  701. .cpu_features = CPU_FTRS_750CL,
  702. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  703. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  704. .icache_bsize = 32,
  705. .dcache_bsize = 32,
  706. .num_pmcs = 4,
  707. .pmc_type = PPC_PMC_IBM,
  708. .cpu_setup = __setup_cpu_750,
  709. .machine_check = machine_check_generic,
  710. .platform = "ppc750",
  711. .oprofile_cpu_type = "ppc/750",
  712. .oprofile_type = PPC_OPROFILE_G4,
  713. },
  714. { /* 745/755 */
  715. .pvr_mask = 0xfffff000,
  716. .pvr_value = 0x00083000,
  717. .cpu_name = "745/755",
  718. .cpu_features = CPU_FTRS_750,
  719. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  720. .mmu_features = MMU_FTR_HPTE_TABLE,
  721. .icache_bsize = 32,
  722. .dcache_bsize = 32,
  723. .num_pmcs = 4,
  724. .pmc_type = PPC_PMC_IBM,
  725. .cpu_setup = __setup_cpu_750,
  726. .machine_check = machine_check_generic,
  727. .platform = "ppc750",
  728. },
  729. { /* 750FX rev 1.x */
  730. .pvr_mask = 0xffffff00,
  731. .pvr_value = 0x70000100,
  732. .cpu_name = "750FX",
  733. .cpu_features = CPU_FTRS_750FX1,
  734. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  735. .mmu_features = MMU_FTR_HPTE_TABLE,
  736. .icache_bsize = 32,
  737. .dcache_bsize = 32,
  738. .num_pmcs = 4,
  739. .pmc_type = PPC_PMC_IBM,
  740. .cpu_setup = __setup_cpu_750,
  741. .machine_check = machine_check_generic,
  742. .platform = "ppc750",
  743. .oprofile_cpu_type = "ppc/750",
  744. .oprofile_type = PPC_OPROFILE_G4,
  745. },
  746. { /* 750FX rev 2.0 must disable HID0[DPM] */
  747. .pvr_mask = 0xffffffff,
  748. .pvr_value = 0x70000200,
  749. .cpu_name = "750FX",
  750. .cpu_features = CPU_FTRS_750FX2,
  751. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  752. .mmu_features = MMU_FTR_HPTE_TABLE,
  753. .icache_bsize = 32,
  754. .dcache_bsize = 32,
  755. .num_pmcs = 4,
  756. .pmc_type = PPC_PMC_IBM,
  757. .cpu_setup = __setup_cpu_750,
  758. .machine_check = machine_check_generic,
  759. .platform = "ppc750",
  760. .oprofile_cpu_type = "ppc/750",
  761. .oprofile_type = PPC_OPROFILE_G4,
  762. },
  763. { /* 750FX (All revs except 2.0) */
  764. .pvr_mask = 0xffff0000,
  765. .pvr_value = 0x70000000,
  766. .cpu_name = "750FX",
  767. .cpu_features = CPU_FTRS_750FX,
  768. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  769. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  770. .icache_bsize = 32,
  771. .dcache_bsize = 32,
  772. .num_pmcs = 4,
  773. .pmc_type = PPC_PMC_IBM,
  774. .cpu_setup = __setup_cpu_750fx,
  775. .machine_check = machine_check_generic,
  776. .platform = "ppc750",
  777. .oprofile_cpu_type = "ppc/750",
  778. .oprofile_type = PPC_OPROFILE_G4,
  779. },
  780. { /* 750GX */
  781. .pvr_mask = 0xffff0000,
  782. .pvr_value = 0x70020000,
  783. .cpu_name = "750GX",
  784. .cpu_features = CPU_FTRS_750GX,
  785. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  786. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  787. .icache_bsize = 32,
  788. .dcache_bsize = 32,
  789. .num_pmcs = 4,
  790. .pmc_type = PPC_PMC_IBM,
  791. .cpu_setup = __setup_cpu_750fx,
  792. .machine_check = machine_check_generic,
  793. .platform = "ppc750",
  794. .oprofile_cpu_type = "ppc/750",
  795. .oprofile_type = PPC_OPROFILE_G4,
  796. },
  797. { /* 740/750 (L2CR bit need fixup for 740) */
  798. .pvr_mask = 0xffff0000,
  799. .pvr_value = 0x00080000,
  800. .cpu_name = "740/750",
  801. .cpu_features = CPU_FTRS_740,
  802. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  803. .mmu_features = MMU_FTR_HPTE_TABLE,
  804. .icache_bsize = 32,
  805. .dcache_bsize = 32,
  806. .num_pmcs = 4,
  807. .pmc_type = PPC_PMC_IBM,
  808. .cpu_setup = __setup_cpu_750,
  809. .machine_check = machine_check_generic,
  810. .platform = "ppc750",
  811. },
  812. { /* 7400 rev 1.1 ? (no TAU) */
  813. .pvr_mask = 0xffffffff,
  814. .pvr_value = 0x000c1101,
  815. .cpu_name = "7400 (1.1)",
  816. .cpu_features = CPU_FTRS_7400_NOTAU,
  817. .cpu_user_features = COMMON_USER |
  818. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  819. .mmu_features = MMU_FTR_HPTE_TABLE,
  820. .icache_bsize = 32,
  821. .dcache_bsize = 32,
  822. .num_pmcs = 4,
  823. .pmc_type = PPC_PMC_G4,
  824. .cpu_setup = __setup_cpu_7400,
  825. .machine_check = machine_check_generic,
  826. .platform = "ppc7400",
  827. },
  828. { /* 7400 */
  829. .pvr_mask = 0xffff0000,
  830. .pvr_value = 0x000c0000,
  831. .cpu_name = "7400",
  832. .cpu_features = CPU_FTRS_7400,
  833. .cpu_user_features = COMMON_USER |
  834. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  835. .mmu_features = MMU_FTR_HPTE_TABLE,
  836. .icache_bsize = 32,
  837. .dcache_bsize = 32,
  838. .num_pmcs = 4,
  839. .pmc_type = PPC_PMC_G4,
  840. .cpu_setup = __setup_cpu_7400,
  841. .machine_check = machine_check_generic,
  842. .platform = "ppc7400",
  843. },
  844. { /* 7410 */
  845. .pvr_mask = 0xffff0000,
  846. .pvr_value = 0x800c0000,
  847. .cpu_name = "7410",
  848. .cpu_features = CPU_FTRS_7400,
  849. .cpu_user_features = COMMON_USER |
  850. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  851. .mmu_features = MMU_FTR_HPTE_TABLE,
  852. .icache_bsize = 32,
  853. .dcache_bsize = 32,
  854. .num_pmcs = 4,
  855. .pmc_type = PPC_PMC_G4,
  856. .cpu_setup = __setup_cpu_7410,
  857. .machine_check = machine_check_generic,
  858. .platform = "ppc7400",
  859. },
  860. { /* 7450 2.0 - no doze/nap */
  861. .pvr_mask = 0xffffffff,
  862. .pvr_value = 0x80000200,
  863. .cpu_name = "7450",
  864. .cpu_features = CPU_FTRS_7450_20,
  865. .cpu_user_features = COMMON_USER |
  866. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  867. .mmu_features = MMU_FTR_HPTE_TABLE,
  868. .icache_bsize = 32,
  869. .dcache_bsize = 32,
  870. .num_pmcs = 6,
  871. .pmc_type = PPC_PMC_G4,
  872. .cpu_setup = __setup_cpu_745x,
  873. .oprofile_cpu_type = "ppc/7450",
  874. .oprofile_type = PPC_OPROFILE_G4,
  875. .machine_check = machine_check_generic,
  876. .platform = "ppc7450",
  877. },
  878. { /* 7450 2.1 */
  879. .pvr_mask = 0xffffffff,
  880. .pvr_value = 0x80000201,
  881. .cpu_name = "7450",
  882. .cpu_features = CPU_FTRS_7450_21,
  883. .cpu_user_features = COMMON_USER |
  884. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  885. .mmu_features = MMU_FTR_HPTE_TABLE,
  886. .icache_bsize = 32,
  887. .dcache_bsize = 32,
  888. .num_pmcs = 6,
  889. .pmc_type = PPC_PMC_G4,
  890. .cpu_setup = __setup_cpu_745x,
  891. .oprofile_cpu_type = "ppc/7450",
  892. .oprofile_type = PPC_OPROFILE_G4,
  893. .machine_check = machine_check_generic,
  894. .platform = "ppc7450",
  895. },
  896. { /* 7450 2.3 and newer */
  897. .pvr_mask = 0xffff0000,
  898. .pvr_value = 0x80000000,
  899. .cpu_name = "7450",
  900. .cpu_features = CPU_FTRS_7450_23,
  901. .cpu_user_features = COMMON_USER |
  902. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  903. .mmu_features = MMU_FTR_HPTE_TABLE,
  904. .icache_bsize = 32,
  905. .dcache_bsize = 32,
  906. .num_pmcs = 6,
  907. .pmc_type = PPC_PMC_G4,
  908. .cpu_setup = __setup_cpu_745x,
  909. .oprofile_cpu_type = "ppc/7450",
  910. .oprofile_type = PPC_OPROFILE_G4,
  911. .machine_check = machine_check_generic,
  912. .platform = "ppc7450",
  913. },
  914. { /* 7455 rev 1.x */
  915. .pvr_mask = 0xffffff00,
  916. .pvr_value = 0x80010100,
  917. .cpu_name = "7455",
  918. .cpu_features = CPU_FTRS_7455_1,
  919. .cpu_user_features = COMMON_USER |
  920. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  921. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  922. .icache_bsize = 32,
  923. .dcache_bsize = 32,
  924. .num_pmcs = 6,
  925. .pmc_type = PPC_PMC_G4,
  926. .cpu_setup = __setup_cpu_745x,
  927. .oprofile_cpu_type = "ppc/7450",
  928. .oprofile_type = PPC_OPROFILE_G4,
  929. .machine_check = machine_check_generic,
  930. .platform = "ppc7450",
  931. },
  932. { /* 7455 rev 2.0 */
  933. .pvr_mask = 0xffffffff,
  934. .pvr_value = 0x80010200,
  935. .cpu_name = "7455",
  936. .cpu_features = CPU_FTRS_7455_20,
  937. .cpu_user_features = COMMON_USER |
  938. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  939. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  940. .icache_bsize = 32,
  941. .dcache_bsize = 32,
  942. .num_pmcs = 6,
  943. .pmc_type = PPC_PMC_G4,
  944. .cpu_setup = __setup_cpu_745x,
  945. .oprofile_cpu_type = "ppc/7450",
  946. .oprofile_type = PPC_OPROFILE_G4,
  947. .machine_check = machine_check_generic,
  948. .platform = "ppc7450",
  949. },
  950. { /* 7455 others */
  951. .pvr_mask = 0xffff0000,
  952. .pvr_value = 0x80010000,
  953. .cpu_name = "7455",
  954. .cpu_features = CPU_FTRS_7455,
  955. .cpu_user_features = COMMON_USER |
  956. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  957. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  958. .icache_bsize = 32,
  959. .dcache_bsize = 32,
  960. .num_pmcs = 6,
  961. .pmc_type = PPC_PMC_G4,
  962. .cpu_setup = __setup_cpu_745x,
  963. .oprofile_cpu_type = "ppc/7450",
  964. .oprofile_type = PPC_OPROFILE_G4,
  965. .machine_check = machine_check_generic,
  966. .platform = "ppc7450",
  967. },
  968. { /* 7447/7457 Rev 1.0 */
  969. .pvr_mask = 0xffffffff,
  970. .pvr_value = 0x80020100,
  971. .cpu_name = "7447/7457",
  972. .cpu_features = CPU_FTRS_7447_10,
  973. .cpu_user_features = COMMON_USER |
  974. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  975. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  976. .icache_bsize = 32,
  977. .dcache_bsize = 32,
  978. .num_pmcs = 6,
  979. .pmc_type = PPC_PMC_G4,
  980. .cpu_setup = __setup_cpu_745x,
  981. .oprofile_cpu_type = "ppc/7450",
  982. .oprofile_type = PPC_OPROFILE_G4,
  983. .machine_check = machine_check_generic,
  984. .platform = "ppc7450",
  985. },
  986. { /* 7447/7457 Rev 1.1 */
  987. .pvr_mask = 0xffffffff,
  988. .pvr_value = 0x80020101,
  989. .cpu_name = "7447/7457",
  990. .cpu_features = CPU_FTRS_7447_10,
  991. .cpu_user_features = COMMON_USER |
  992. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  993. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  994. .icache_bsize = 32,
  995. .dcache_bsize = 32,
  996. .num_pmcs = 6,
  997. .pmc_type = PPC_PMC_G4,
  998. .cpu_setup = __setup_cpu_745x,
  999. .oprofile_cpu_type = "ppc/7450",
  1000. .oprofile_type = PPC_OPROFILE_G4,
  1001. .machine_check = machine_check_generic,
  1002. .platform = "ppc7450",
  1003. },
  1004. { /* 7447/7457 Rev 1.2 and later */
  1005. .pvr_mask = 0xffff0000,
  1006. .pvr_value = 0x80020000,
  1007. .cpu_name = "7447/7457",
  1008. .cpu_features = CPU_FTRS_7447,
  1009. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1010. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1011. .icache_bsize = 32,
  1012. .dcache_bsize = 32,
  1013. .num_pmcs = 6,
  1014. .pmc_type = PPC_PMC_G4,
  1015. .cpu_setup = __setup_cpu_745x,
  1016. .oprofile_cpu_type = "ppc/7450",
  1017. .oprofile_type = PPC_OPROFILE_G4,
  1018. .machine_check = machine_check_generic,
  1019. .platform = "ppc7450",
  1020. },
  1021. { /* 7447A */
  1022. .pvr_mask = 0xffff0000,
  1023. .pvr_value = 0x80030000,
  1024. .cpu_name = "7447A",
  1025. .cpu_features = CPU_FTRS_7447A,
  1026. .cpu_user_features = COMMON_USER |
  1027. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1028. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1029. .icache_bsize = 32,
  1030. .dcache_bsize = 32,
  1031. .num_pmcs = 6,
  1032. .pmc_type = PPC_PMC_G4,
  1033. .cpu_setup = __setup_cpu_745x,
  1034. .oprofile_cpu_type = "ppc/7450",
  1035. .oprofile_type = PPC_OPROFILE_G4,
  1036. .machine_check = machine_check_generic,
  1037. .platform = "ppc7450",
  1038. },
  1039. { /* 7448 */
  1040. .pvr_mask = 0xffff0000,
  1041. .pvr_value = 0x80040000,
  1042. .cpu_name = "7448",
  1043. .cpu_features = CPU_FTRS_7448,
  1044. .cpu_user_features = COMMON_USER |
  1045. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1046. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1047. .icache_bsize = 32,
  1048. .dcache_bsize = 32,
  1049. .num_pmcs = 6,
  1050. .pmc_type = PPC_PMC_G4,
  1051. .cpu_setup = __setup_cpu_745x,
  1052. .oprofile_cpu_type = "ppc/7450",
  1053. .oprofile_type = PPC_OPROFILE_G4,
  1054. .machine_check = machine_check_generic,
  1055. .platform = "ppc7450",
  1056. },
  1057. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1058. .pvr_mask = 0x7fff0000,
  1059. .pvr_value = 0x00810000,
  1060. .cpu_name = "82xx",
  1061. .cpu_features = CPU_FTRS_82XX,
  1062. .cpu_user_features = COMMON_USER,
  1063. .mmu_features = 0,
  1064. .icache_bsize = 32,
  1065. .dcache_bsize = 32,
  1066. .cpu_setup = __setup_cpu_603,
  1067. .machine_check = machine_check_generic,
  1068. .platform = "ppc603",
  1069. },
  1070. { /* All G2_LE (603e core, plus some) have the same pvr */
  1071. .pvr_mask = 0x7fff0000,
  1072. .pvr_value = 0x00820000,
  1073. .cpu_name = "G2_LE",
  1074. .cpu_features = CPU_FTRS_G2_LE,
  1075. .cpu_user_features = COMMON_USER,
  1076. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1077. .icache_bsize = 32,
  1078. .dcache_bsize = 32,
  1079. .cpu_setup = __setup_cpu_603,
  1080. .machine_check = machine_check_generic,
  1081. .platform = "ppc603",
  1082. },
  1083. { /* e300c1 (a 603e core, plus some) on 83xx */
  1084. .pvr_mask = 0x7fff0000,
  1085. .pvr_value = 0x00830000,
  1086. .cpu_name = "e300c1",
  1087. .cpu_features = CPU_FTRS_E300,
  1088. .cpu_user_features = COMMON_USER,
  1089. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1090. .icache_bsize = 32,
  1091. .dcache_bsize = 32,
  1092. .cpu_setup = __setup_cpu_603,
  1093. .machine_check = machine_check_generic,
  1094. .platform = "ppc603",
  1095. },
  1096. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1097. .pvr_mask = 0x7fff0000,
  1098. .pvr_value = 0x00840000,
  1099. .cpu_name = "e300c2",
  1100. .cpu_features = CPU_FTRS_E300C2,
  1101. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1102. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1103. MMU_FTR_NEED_DTLB_SW_LRU,
  1104. .icache_bsize = 32,
  1105. .dcache_bsize = 32,
  1106. .cpu_setup = __setup_cpu_603,
  1107. .machine_check = machine_check_generic,
  1108. .platform = "ppc603",
  1109. },
  1110. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1111. .pvr_mask = 0x7fff0000,
  1112. .pvr_value = 0x00850000,
  1113. .cpu_name = "e300c3",
  1114. .cpu_features = CPU_FTRS_E300,
  1115. .cpu_user_features = COMMON_USER,
  1116. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1117. MMU_FTR_NEED_DTLB_SW_LRU,
  1118. .icache_bsize = 32,
  1119. .dcache_bsize = 32,
  1120. .cpu_setup = __setup_cpu_603,
  1121. .num_pmcs = 4,
  1122. .oprofile_cpu_type = "ppc/e300",
  1123. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1124. .platform = "ppc603",
  1125. },
  1126. { /* e300c4 (e300c1, plus one IU) */
  1127. .pvr_mask = 0x7fff0000,
  1128. .pvr_value = 0x00860000,
  1129. .cpu_name = "e300c4",
  1130. .cpu_features = CPU_FTRS_E300,
  1131. .cpu_user_features = COMMON_USER,
  1132. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1133. MMU_FTR_NEED_DTLB_SW_LRU,
  1134. .icache_bsize = 32,
  1135. .dcache_bsize = 32,
  1136. .cpu_setup = __setup_cpu_603,
  1137. .machine_check = machine_check_generic,
  1138. .num_pmcs = 4,
  1139. .oprofile_cpu_type = "ppc/e300",
  1140. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1141. .platform = "ppc603",
  1142. },
  1143. { /* default match, we assume split I/D cache & TB (non-601)... */
  1144. .pvr_mask = 0x00000000,
  1145. .pvr_value = 0x00000000,
  1146. .cpu_name = "(generic PPC)",
  1147. .cpu_features = CPU_FTRS_CLASSIC32,
  1148. .cpu_user_features = COMMON_USER,
  1149. .mmu_features = MMU_FTR_HPTE_TABLE,
  1150. .icache_bsize = 32,
  1151. .dcache_bsize = 32,
  1152. .machine_check = machine_check_generic,
  1153. .platform = "ppc603",
  1154. },
  1155. #endif /* CLASSIC_PPC */
  1156. #ifdef CONFIG_8xx
  1157. { /* 8xx */
  1158. .pvr_mask = 0xffff0000,
  1159. .pvr_value = 0x00500000,
  1160. .cpu_name = "8xx",
  1161. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1162. * if the 8xx code is there.... */
  1163. .cpu_features = CPU_FTRS_8XX,
  1164. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1165. .mmu_features = MMU_FTR_TYPE_8xx,
  1166. .icache_bsize = 16,
  1167. .dcache_bsize = 16,
  1168. .platform = "ppc823",
  1169. },
  1170. #endif /* CONFIG_8xx */
  1171. #ifdef CONFIG_40x
  1172. { /* 403GC */
  1173. .pvr_mask = 0xffffff00,
  1174. .pvr_value = 0x00200200,
  1175. .cpu_name = "403GC",
  1176. .cpu_features = CPU_FTRS_40X,
  1177. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1178. .mmu_features = MMU_FTR_TYPE_40x,
  1179. .icache_bsize = 16,
  1180. .dcache_bsize = 16,
  1181. .machine_check = machine_check_4xx,
  1182. .platform = "ppc403",
  1183. },
  1184. { /* 403GCX */
  1185. .pvr_mask = 0xffffff00,
  1186. .pvr_value = 0x00201400,
  1187. .cpu_name = "403GCX",
  1188. .cpu_features = CPU_FTRS_40X,
  1189. .cpu_user_features = PPC_FEATURE_32 |
  1190. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1191. .mmu_features = MMU_FTR_TYPE_40x,
  1192. .icache_bsize = 16,
  1193. .dcache_bsize = 16,
  1194. .machine_check = machine_check_4xx,
  1195. .platform = "ppc403",
  1196. },
  1197. { /* 403G ?? */
  1198. .pvr_mask = 0xffff0000,
  1199. .pvr_value = 0x00200000,
  1200. .cpu_name = "403G ??",
  1201. .cpu_features = CPU_FTRS_40X,
  1202. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1203. .mmu_features = MMU_FTR_TYPE_40x,
  1204. .icache_bsize = 16,
  1205. .dcache_bsize = 16,
  1206. .machine_check = machine_check_4xx,
  1207. .platform = "ppc403",
  1208. },
  1209. { /* 405GP */
  1210. .pvr_mask = 0xffff0000,
  1211. .pvr_value = 0x40110000,
  1212. .cpu_name = "405GP",
  1213. .cpu_features = CPU_FTRS_40X,
  1214. .cpu_user_features = PPC_FEATURE_32 |
  1215. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1216. .mmu_features = MMU_FTR_TYPE_40x,
  1217. .icache_bsize = 32,
  1218. .dcache_bsize = 32,
  1219. .machine_check = machine_check_4xx,
  1220. .platform = "ppc405",
  1221. },
  1222. { /* STB 03xxx */
  1223. .pvr_mask = 0xffff0000,
  1224. .pvr_value = 0x40130000,
  1225. .cpu_name = "STB03xxx",
  1226. .cpu_features = CPU_FTRS_40X,
  1227. .cpu_user_features = PPC_FEATURE_32 |
  1228. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1229. .mmu_features = MMU_FTR_TYPE_40x,
  1230. .icache_bsize = 32,
  1231. .dcache_bsize = 32,
  1232. .machine_check = machine_check_4xx,
  1233. .platform = "ppc405",
  1234. },
  1235. { /* STB 04xxx */
  1236. .pvr_mask = 0xffff0000,
  1237. .pvr_value = 0x41810000,
  1238. .cpu_name = "STB04xxx",
  1239. .cpu_features = CPU_FTRS_40X,
  1240. .cpu_user_features = PPC_FEATURE_32 |
  1241. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1242. .mmu_features = MMU_FTR_TYPE_40x,
  1243. .icache_bsize = 32,
  1244. .dcache_bsize = 32,
  1245. .machine_check = machine_check_4xx,
  1246. .platform = "ppc405",
  1247. },
  1248. { /* NP405L */
  1249. .pvr_mask = 0xffff0000,
  1250. .pvr_value = 0x41610000,
  1251. .cpu_name = "NP405L",
  1252. .cpu_features = CPU_FTRS_40X,
  1253. .cpu_user_features = PPC_FEATURE_32 |
  1254. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1255. .mmu_features = MMU_FTR_TYPE_40x,
  1256. .icache_bsize = 32,
  1257. .dcache_bsize = 32,
  1258. .machine_check = machine_check_4xx,
  1259. .platform = "ppc405",
  1260. },
  1261. { /* NP4GS3 */
  1262. .pvr_mask = 0xffff0000,
  1263. .pvr_value = 0x40B10000,
  1264. .cpu_name = "NP4GS3",
  1265. .cpu_features = CPU_FTRS_40X,
  1266. .cpu_user_features = PPC_FEATURE_32 |
  1267. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1268. .mmu_features = MMU_FTR_TYPE_40x,
  1269. .icache_bsize = 32,
  1270. .dcache_bsize = 32,
  1271. .machine_check = machine_check_4xx,
  1272. .platform = "ppc405",
  1273. },
  1274. { /* NP405H */
  1275. .pvr_mask = 0xffff0000,
  1276. .pvr_value = 0x41410000,
  1277. .cpu_name = "NP405H",
  1278. .cpu_features = CPU_FTRS_40X,
  1279. .cpu_user_features = PPC_FEATURE_32 |
  1280. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1281. .mmu_features = MMU_FTR_TYPE_40x,
  1282. .icache_bsize = 32,
  1283. .dcache_bsize = 32,
  1284. .machine_check = machine_check_4xx,
  1285. .platform = "ppc405",
  1286. },
  1287. { /* 405GPr */
  1288. .pvr_mask = 0xffff0000,
  1289. .pvr_value = 0x50910000,
  1290. .cpu_name = "405GPr",
  1291. .cpu_features = CPU_FTRS_40X,
  1292. .cpu_user_features = PPC_FEATURE_32 |
  1293. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1294. .mmu_features = MMU_FTR_TYPE_40x,
  1295. .icache_bsize = 32,
  1296. .dcache_bsize = 32,
  1297. .machine_check = machine_check_4xx,
  1298. .platform = "ppc405",
  1299. },
  1300. { /* STBx25xx */
  1301. .pvr_mask = 0xffff0000,
  1302. .pvr_value = 0x51510000,
  1303. .cpu_name = "STBx25xx",
  1304. .cpu_features = CPU_FTRS_40X,
  1305. .cpu_user_features = PPC_FEATURE_32 |
  1306. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1307. .mmu_features = MMU_FTR_TYPE_40x,
  1308. .icache_bsize = 32,
  1309. .dcache_bsize = 32,
  1310. .machine_check = machine_check_4xx,
  1311. .platform = "ppc405",
  1312. },
  1313. { /* 405LP */
  1314. .pvr_mask = 0xffff0000,
  1315. .pvr_value = 0x41F10000,
  1316. .cpu_name = "405LP",
  1317. .cpu_features = CPU_FTRS_40X,
  1318. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1319. .mmu_features = MMU_FTR_TYPE_40x,
  1320. .icache_bsize = 32,
  1321. .dcache_bsize = 32,
  1322. .machine_check = machine_check_4xx,
  1323. .platform = "ppc405",
  1324. },
  1325. { /* Xilinx Virtex-II Pro */
  1326. .pvr_mask = 0xfffff000,
  1327. .pvr_value = 0x20010000,
  1328. .cpu_name = "Virtex-II Pro",
  1329. .cpu_features = CPU_FTRS_40X,
  1330. .cpu_user_features = PPC_FEATURE_32 |
  1331. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1332. .mmu_features = MMU_FTR_TYPE_40x,
  1333. .icache_bsize = 32,
  1334. .dcache_bsize = 32,
  1335. .machine_check = machine_check_4xx,
  1336. .platform = "ppc405",
  1337. },
  1338. { /* Xilinx Virtex-4 FX */
  1339. .pvr_mask = 0xfffff000,
  1340. .pvr_value = 0x20011000,
  1341. .cpu_name = "Virtex-4 FX",
  1342. .cpu_features = CPU_FTRS_40X,
  1343. .cpu_user_features = PPC_FEATURE_32 |
  1344. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1345. .mmu_features = MMU_FTR_TYPE_40x,
  1346. .icache_bsize = 32,
  1347. .dcache_bsize = 32,
  1348. .machine_check = machine_check_4xx,
  1349. .platform = "ppc405",
  1350. },
  1351. { /* 405EP */
  1352. .pvr_mask = 0xffff0000,
  1353. .pvr_value = 0x51210000,
  1354. .cpu_name = "405EP",
  1355. .cpu_features = CPU_FTRS_40X,
  1356. .cpu_user_features = PPC_FEATURE_32 |
  1357. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1358. .mmu_features = MMU_FTR_TYPE_40x,
  1359. .icache_bsize = 32,
  1360. .dcache_bsize = 32,
  1361. .machine_check = machine_check_4xx,
  1362. .platform = "ppc405",
  1363. },
  1364. { /* 405EX Rev. A/B with Security */
  1365. .pvr_mask = 0xffff000f,
  1366. .pvr_value = 0x12910007,
  1367. .cpu_name = "405EX Rev. A/B",
  1368. .cpu_features = CPU_FTRS_40X,
  1369. .cpu_user_features = PPC_FEATURE_32 |
  1370. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1371. .mmu_features = MMU_FTR_TYPE_40x,
  1372. .icache_bsize = 32,
  1373. .dcache_bsize = 32,
  1374. .machine_check = machine_check_4xx,
  1375. .platform = "ppc405",
  1376. },
  1377. { /* 405EX Rev. C without Security */
  1378. .pvr_mask = 0xffff000f,
  1379. .pvr_value = 0x1291000d,
  1380. .cpu_name = "405EX Rev. C",
  1381. .cpu_features = CPU_FTRS_40X,
  1382. .cpu_user_features = PPC_FEATURE_32 |
  1383. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1384. .mmu_features = MMU_FTR_TYPE_40x,
  1385. .icache_bsize = 32,
  1386. .dcache_bsize = 32,
  1387. .machine_check = machine_check_4xx,
  1388. .platform = "ppc405",
  1389. },
  1390. { /* 405EX Rev. C with Security */
  1391. .pvr_mask = 0xffff000f,
  1392. .pvr_value = 0x1291000f,
  1393. .cpu_name = "405EX Rev. C",
  1394. .cpu_features = CPU_FTRS_40X,
  1395. .cpu_user_features = PPC_FEATURE_32 |
  1396. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1397. .mmu_features = MMU_FTR_TYPE_40x,
  1398. .icache_bsize = 32,
  1399. .dcache_bsize = 32,
  1400. .machine_check = machine_check_4xx,
  1401. .platform = "ppc405",
  1402. },
  1403. { /* 405EX Rev. D without Security */
  1404. .pvr_mask = 0xffff000f,
  1405. .pvr_value = 0x12910003,
  1406. .cpu_name = "405EX Rev. D",
  1407. .cpu_features = CPU_FTRS_40X,
  1408. .cpu_user_features = PPC_FEATURE_32 |
  1409. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1410. .mmu_features = MMU_FTR_TYPE_40x,
  1411. .icache_bsize = 32,
  1412. .dcache_bsize = 32,
  1413. .machine_check = machine_check_4xx,
  1414. .platform = "ppc405",
  1415. },
  1416. { /* 405EX Rev. D with Security */
  1417. .pvr_mask = 0xffff000f,
  1418. .pvr_value = 0x12910005,
  1419. .cpu_name = "405EX Rev. D",
  1420. .cpu_features = CPU_FTRS_40X,
  1421. .cpu_user_features = PPC_FEATURE_32 |
  1422. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1423. .mmu_features = MMU_FTR_TYPE_40x,
  1424. .icache_bsize = 32,
  1425. .dcache_bsize = 32,
  1426. .machine_check = machine_check_4xx,
  1427. .platform = "ppc405",
  1428. },
  1429. { /* 405EXr Rev. A/B without Security */
  1430. .pvr_mask = 0xffff000f,
  1431. .pvr_value = 0x12910001,
  1432. .cpu_name = "405EXr Rev. A/B",
  1433. .cpu_features = CPU_FTRS_40X,
  1434. .cpu_user_features = PPC_FEATURE_32 |
  1435. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1436. .mmu_features = MMU_FTR_TYPE_40x,
  1437. .icache_bsize = 32,
  1438. .dcache_bsize = 32,
  1439. .machine_check = machine_check_4xx,
  1440. .platform = "ppc405",
  1441. },
  1442. { /* 405EXr Rev. C without Security */
  1443. .pvr_mask = 0xffff000f,
  1444. .pvr_value = 0x12910009,
  1445. .cpu_name = "405EXr Rev. C",
  1446. .cpu_features = CPU_FTRS_40X,
  1447. .cpu_user_features = PPC_FEATURE_32 |
  1448. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1449. .mmu_features = MMU_FTR_TYPE_40x,
  1450. .icache_bsize = 32,
  1451. .dcache_bsize = 32,
  1452. .machine_check = machine_check_4xx,
  1453. .platform = "ppc405",
  1454. },
  1455. { /* 405EXr Rev. C with Security */
  1456. .pvr_mask = 0xffff000f,
  1457. .pvr_value = 0x1291000b,
  1458. .cpu_name = "405EXr Rev. C",
  1459. .cpu_features = CPU_FTRS_40X,
  1460. .cpu_user_features = PPC_FEATURE_32 |
  1461. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1462. .mmu_features = MMU_FTR_TYPE_40x,
  1463. .icache_bsize = 32,
  1464. .dcache_bsize = 32,
  1465. .machine_check = machine_check_4xx,
  1466. .platform = "ppc405",
  1467. },
  1468. { /* 405EXr Rev. D without Security */
  1469. .pvr_mask = 0xffff000f,
  1470. .pvr_value = 0x12910000,
  1471. .cpu_name = "405EXr Rev. D",
  1472. .cpu_features = CPU_FTRS_40X,
  1473. .cpu_user_features = PPC_FEATURE_32 |
  1474. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1475. .mmu_features = MMU_FTR_TYPE_40x,
  1476. .icache_bsize = 32,
  1477. .dcache_bsize = 32,
  1478. .machine_check = machine_check_4xx,
  1479. .platform = "ppc405",
  1480. },
  1481. { /* 405EXr Rev. D with Security */
  1482. .pvr_mask = 0xffff000f,
  1483. .pvr_value = 0x12910002,
  1484. .cpu_name = "405EXr Rev. D",
  1485. .cpu_features = CPU_FTRS_40X,
  1486. .cpu_user_features = PPC_FEATURE_32 |
  1487. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1488. .mmu_features = MMU_FTR_TYPE_40x,
  1489. .icache_bsize = 32,
  1490. .dcache_bsize = 32,
  1491. .machine_check = machine_check_4xx,
  1492. .platform = "ppc405",
  1493. },
  1494. {
  1495. /* 405EZ */
  1496. .pvr_mask = 0xffff0000,
  1497. .pvr_value = 0x41510000,
  1498. .cpu_name = "405EZ",
  1499. .cpu_features = CPU_FTRS_40X,
  1500. .cpu_user_features = PPC_FEATURE_32 |
  1501. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1502. .mmu_features = MMU_FTR_TYPE_40x,
  1503. .icache_bsize = 32,
  1504. .dcache_bsize = 32,
  1505. .machine_check = machine_check_4xx,
  1506. .platform = "ppc405",
  1507. },
  1508. { /* default match */
  1509. .pvr_mask = 0x00000000,
  1510. .pvr_value = 0x00000000,
  1511. .cpu_name = "(generic 40x PPC)",
  1512. .cpu_features = CPU_FTRS_40X,
  1513. .cpu_user_features = PPC_FEATURE_32 |
  1514. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1515. .mmu_features = MMU_FTR_TYPE_40x,
  1516. .icache_bsize = 32,
  1517. .dcache_bsize = 32,
  1518. .machine_check = machine_check_4xx,
  1519. .platform = "ppc405",
  1520. }
  1521. #endif /* CONFIG_40x */
  1522. #ifdef CONFIG_44x
  1523. {
  1524. .pvr_mask = 0xf0000fff,
  1525. .pvr_value = 0x40000850,
  1526. .cpu_name = "440GR Rev. A",
  1527. .cpu_features = CPU_FTRS_44X,
  1528. .cpu_user_features = COMMON_USER_BOOKE,
  1529. .mmu_features = MMU_FTR_TYPE_44x,
  1530. .icache_bsize = 32,
  1531. .dcache_bsize = 32,
  1532. .machine_check = machine_check_4xx,
  1533. .platform = "ppc440",
  1534. },
  1535. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1536. .pvr_mask = 0xf0000fff,
  1537. .pvr_value = 0x40000858,
  1538. .cpu_name = "440EP Rev. A",
  1539. .cpu_features = CPU_FTRS_44X,
  1540. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1541. .mmu_features = MMU_FTR_TYPE_44x,
  1542. .icache_bsize = 32,
  1543. .dcache_bsize = 32,
  1544. .cpu_setup = __setup_cpu_440ep,
  1545. .machine_check = machine_check_4xx,
  1546. .platform = "ppc440",
  1547. },
  1548. {
  1549. .pvr_mask = 0xf0000fff,
  1550. .pvr_value = 0x400008d3,
  1551. .cpu_name = "440GR Rev. B",
  1552. .cpu_features = CPU_FTRS_44X,
  1553. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1554. .mmu_features = MMU_FTR_TYPE_44x,
  1555. .icache_bsize = 32,
  1556. .dcache_bsize = 32,
  1557. .machine_check = machine_check_4xx,
  1558. .platform = "ppc440",
  1559. },
  1560. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1561. .pvr_mask = 0xf0000ff7,
  1562. .pvr_value = 0x400008d4,
  1563. .cpu_name = "440EP Rev. C",
  1564. .cpu_features = CPU_FTRS_44X,
  1565. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1566. .mmu_features = MMU_FTR_TYPE_44x,
  1567. .icache_bsize = 32,
  1568. .dcache_bsize = 32,
  1569. .cpu_setup = __setup_cpu_440ep,
  1570. .machine_check = machine_check_4xx,
  1571. .platform = "ppc440",
  1572. },
  1573. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1574. .pvr_mask = 0xf0000fff,
  1575. .pvr_value = 0x400008db,
  1576. .cpu_name = "440EP Rev. B",
  1577. .cpu_features = CPU_FTRS_44X,
  1578. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1579. .mmu_features = MMU_FTR_TYPE_44x,
  1580. .icache_bsize = 32,
  1581. .dcache_bsize = 32,
  1582. .cpu_setup = __setup_cpu_440ep,
  1583. .machine_check = machine_check_4xx,
  1584. .platform = "ppc440",
  1585. },
  1586. { /* 440GRX */
  1587. .pvr_mask = 0xf0000ffb,
  1588. .pvr_value = 0x200008D0,
  1589. .cpu_name = "440GRX",
  1590. .cpu_features = CPU_FTRS_44X,
  1591. .cpu_user_features = COMMON_USER_BOOKE,
  1592. .mmu_features = MMU_FTR_TYPE_44x,
  1593. .icache_bsize = 32,
  1594. .dcache_bsize = 32,
  1595. .cpu_setup = __setup_cpu_440grx,
  1596. .machine_check = machine_check_440A,
  1597. .platform = "ppc440",
  1598. },
  1599. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1600. .pvr_mask = 0xf0000ffb,
  1601. .pvr_value = 0x200008D8,
  1602. .cpu_name = "440EPX",
  1603. .cpu_features = CPU_FTRS_44X,
  1604. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1605. .mmu_features = MMU_FTR_TYPE_44x,
  1606. .icache_bsize = 32,
  1607. .dcache_bsize = 32,
  1608. .cpu_setup = __setup_cpu_440epx,
  1609. .machine_check = machine_check_440A,
  1610. .platform = "ppc440",
  1611. },
  1612. { /* 440GP Rev. B */
  1613. .pvr_mask = 0xf0000fff,
  1614. .pvr_value = 0x40000440,
  1615. .cpu_name = "440GP Rev. B",
  1616. .cpu_features = CPU_FTRS_44X,
  1617. .cpu_user_features = COMMON_USER_BOOKE,
  1618. .mmu_features = MMU_FTR_TYPE_44x,
  1619. .icache_bsize = 32,
  1620. .dcache_bsize = 32,
  1621. .machine_check = machine_check_4xx,
  1622. .platform = "ppc440gp",
  1623. },
  1624. { /* 440GP Rev. C */
  1625. .pvr_mask = 0xf0000fff,
  1626. .pvr_value = 0x40000481,
  1627. .cpu_name = "440GP Rev. C",
  1628. .cpu_features = CPU_FTRS_44X,
  1629. .cpu_user_features = COMMON_USER_BOOKE,
  1630. .mmu_features = MMU_FTR_TYPE_44x,
  1631. .icache_bsize = 32,
  1632. .dcache_bsize = 32,
  1633. .machine_check = machine_check_4xx,
  1634. .platform = "ppc440gp",
  1635. },
  1636. { /* 440GX Rev. A */
  1637. .pvr_mask = 0xf0000fff,
  1638. .pvr_value = 0x50000850,
  1639. .cpu_name = "440GX Rev. A",
  1640. .cpu_features = CPU_FTRS_44X,
  1641. .cpu_user_features = COMMON_USER_BOOKE,
  1642. .mmu_features = MMU_FTR_TYPE_44x,
  1643. .icache_bsize = 32,
  1644. .dcache_bsize = 32,
  1645. .cpu_setup = __setup_cpu_440gx,
  1646. .machine_check = machine_check_440A,
  1647. .platform = "ppc440",
  1648. },
  1649. { /* 440GX Rev. B */
  1650. .pvr_mask = 0xf0000fff,
  1651. .pvr_value = 0x50000851,
  1652. .cpu_name = "440GX Rev. B",
  1653. .cpu_features = CPU_FTRS_44X,
  1654. .cpu_user_features = COMMON_USER_BOOKE,
  1655. .mmu_features = MMU_FTR_TYPE_44x,
  1656. .icache_bsize = 32,
  1657. .dcache_bsize = 32,
  1658. .cpu_setup = __setup_cpu_440gx,
  1659. .machine_check = machine_check_440A,
  1660. .platform = "ppc440",
  1661. },
  1662. { /* 440GX Rev. C */
  1663. .pvr_mask = 0xf0000fff,
  1664. .pvr_value = 0x50000892,
  1665. .cpu_name = "440GX Rev. C",
  1666. .cpu_features = CPU_FTRS_44X,
  1667. .cpu_user_features = COMMON_USER_BOOKE,
  1668. .mmu_features = MMU_FTR_TYPE_44x,
  1669. .icache_bsize = 32,
  1670. .dcache_bsize = 32,
  1671. .cpu_setup = __setup_cpu_440gx,
  1672. .machine_check = machine_check_440A,
  1673. .platform = "ppc440",
  1674. },
  1675. { /* 440GX Rev. F */
  1676. .pvr_mask = 0xf0000fff,
  1677. .pvr_value = 0x50000894,
  1678. .cpu_name = "440GX Rev. F",
  1679. .cpu_features = CPU_FTRS_44X,
  1680. .cpu_user_features = COMMON_USER_BOOKE,
  1681. .mmu_features = MMU_FTR_TYPE_44x,
  1682. .icache_bsize = 32,
  1683. .dcache_bsize = 32,
  1684. .cpu_setup = __setup_cpu_440gx,
  1685. .machine_check = machine_check_440A,
  1686. .platform = "ppc440",
  1687. },
  1688. { /* 440SP Rev. A */
  1689. .pvr_mask = 0xfff00fff,
  1690. .pvr_value = 0x53200891,
  1691. .cpu_name = "440SP Rev. A",
  1692. .cpu_features = CPU_FTRS_44X,
  1693. .cpu_user_features = COMMON_USER_BOOKE,
  1694. .mmu_features = MMU_FTR_TYPE_44x,
  1695. .icache_bsize = 32,
  1696. .dcache_bsize = 32,
  1697. .machine_check = machine_check_4xx,
  1698. .platform = "ppc440",
  1699. },
  1700. { /* 440SPe Rev. A */
  1701. .pvr_mask = 0xfff00fff,
  1702. .pvr_value = 0x53400890,
  1703. .cpu_name = "440SPe Rev. A",
  1704. .cpu_features = CPU_FTRS_44X,
  1705. .cpu_user_features = COMMON_USER_BOOKE,
  1706. .mmu_features = MMU_FTR_TYPE_44x,
  1707. .icache_bsize = 32,
  1708. .dcache_bsize = 32,
  1709. .cpu_setup = __setup_cpu_440spe,
  1710. .machine_check = machine_check_440A,
  1711. .platform = "ppc440",
  1712. },
  1713. { /* 440SPe Rev. B */
  1714. .pvr_mask = 0xfff00fff,
  1715. .pvr_value = 0x53400891,
  1716. .cpu_name = "440SPe Rev. B",
  1717. .cpu_features = CPU_FTRS_44X,
  1718. .cpu_user_features = COMMON_USER_BOOKE,
  1719. .mmu_features = MMU_FTR_TYPE_44x,
  1720. .icache_bsize = 32,
  1721. .dcache_bsize = 32,
  1722. .cpu_setup = __setup_cpu_440spe,
  1723. .machine_check = machine_check_440A,
  1724. .platform = "ppc440",
  1725. },
  1726. { /* 440 in Xilinx Virtex-5 FXT */
  1727. .pvr_mask = 0xfffffff0,
  1728. .pvr_value = 0x7ff21910,
  1729. .cpu_name = "440 in Virtex-5 FXT",
  1730. .cpu_features = CPU_FTRS_44X,
  1731. .cpu_user_features = COMMON_USER_BOOKE,
  1732. .mmu_features = MMU_FTR_TYPE_44x,
  1733. .icache_bsize = 32,
  1734. .dcache_bsize = 32,
  1735. .cpu_setup = __setup_cpu_440x5,
  1736. .machine_check = machine_check_440A,
  1737. .platform = "ppc440",
  1738. },
  1739. { /* 460EX */
  1740. .pvr_mask = 0xffff0006,
  1741. .pvr_value = 0x13020002,
  1742. .cpu_name = "460EX",
  1743. .cpu_features = CPU_FTRS_440x6,
  1744. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1745. .mmu_features = MMU_FTR_TYPE_44x,
  1746. .icache_bsize = 32,
  1747. .dcache_bsize = 32,
  1748. .cpu_setup = __setup_cpu_460ex,
  1749. .machine_check = machine_check_440A,
  1750. .platform = "ppc440",
  1751. },
  1752. { /* 460EX Rev B */
  1753. .pvr_mask = 0xffff0007,
  1754. .pvr_value = 0x13020004,
  1755. .cpu_name = "460EX Rev. B",
  1756. .cpu_features = CPU_FTRS_440x6,
  1757. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1758. .mmu_features = MMU_FTR_TYPE_44x,
  1759. .icache_bsize = 32,
  1760. .dcache_bsize = 32,
  1761. .cpu_setup = __setup_cpu_460ex,
  1762. .machine_check = machine_check_440A,
  1763. .platform = "ppc440",
  1764. },
  1765. { /* 460GT */
  1766. .pvr_mask = 0xffff0006,
  1767. .pvr_value = 0x13020000,
  1768. .cpu_name = "460GT",
  1769. .cpu_features = CPU_FTRS_440x6,
  1770. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1771. .mmu_features = MMU_FTR_TYPE_44x,
  1772. .icache_bsize = 32,
  1773. .dcache_bsize = 32,
  1774. .cpu_setup = __setup_cpu_460gt,
  1775. .machine_check = machine_check_440A,
  1776. .platform = "ppc440",
  1777. },
  1778. { /* 460GT Rev B */
  1779. .pvr_mask = 0xffff0007,
  1780. .pvr_value = 0x13020005,
  1781. .cpu_name = "460GT Rev. B",
  1782. .cpu_features = CPU_FTRS_440x6,
  1783. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1784. .mmu_features = MMU_FTR_TYPE_44x,
  1785. .icache_bsize = 32,
  1786. .dcache_bsize = 32,
  1787. .cpu_setup = __setup_cpu_460gt,
  1788. .machine_check = machine_check_440A,
  1789. .platform = "ppc440",
  1790. },
  1791. { /* 460SX */
  1792. .pvr_mask = 0xffffff00,
  1793. .pvr_value = 0x13541800,
  1794. .cpu_name = "460SX",
  1795. .cpu_features = CPU_FTRS_44X,
  1796. .cpu_user_features = COMMON_USER_BOOKE,
  1797. .mmu_features = MMU_FTR_TYPE_44x,
  1798. .icache_bsize = 32,
  1799. .dcache_bsize = 32,
  1800. .cpu_setup = __setup_cpu_460sx,
  1801. .machine_check = machine_check_440A,
  1802. .platform = "ppc440",
  1803. },
  1804. { /* 464 in APM821xx */
  1805. .pvr_mask = 0xffffff00,
  1806. .pvr_value = 0x12C41C80,
  1807. .cpu_name = "APM821XX",
  1808. .cpu_features = CPU_FTRS_44X,
  1809. .cpu_user_features = COMMON_USER_BOOKE |
  1810. PPC_FEATURE_HAS_FPU,
  1811. .mmu_features = MMU_FTR_TYPE_44x,
  1812. .icache_bsize = 32,
  1813. .dcache_bsize = 32,
  1814. .cpu_setup = __setup_cpu_apm821xx,
  1815. .machine_check = machine_check_440A,
  1816. .platform = "ppc440",
  1817. },
  1818. { /* 476 core */
  1819. .pvr_mask = 0xffff0000,
  1820. .pvr_value = 0x11a50000,
  1821. .cpu_name = "476",
  1822. .cpu_features = CPU_FTRS_47X,
  1823. .cpu_user_features = COMMON_USER_BOOKE |
  1824. PPC_FEATURE_HAS_FPU,
  1825. .mmu_features = MMU_FTR_TYPE_47x |
  1826. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1827. .icache_bsize = 32,
  1828. .dcache_bsize = 128,
  1829. .machine_check = machine_check_47x,
  1830. .platform = "ppc470",
  1831. },
  1832. { /* 476 iss */
  1833. .pvr_mask = 0xffff0000,
  1834. .pvr_value = 0x00050000,
  1835. .cpu_name = "476",
  1836. .cpu_features = CPU_FTRS_47X,
  1837. .cpu_user_features = COMMON_USER_BOOKE |
  1838. PPC_FEATURE_HAS_FPU,
  1839. .mmu_features = MMU_FTR_TYPE_47x |
  1840. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1841. .icache_bsize = 32,
  1842. .dcache_bsize = 128,
  1843. .machine_check = machine_check_47x,
  1844. .platform = "ppc470",
  1845. },
  1846. { /* default match */
  1847. .pvr_mask = 0x00000000,
  1848. .pvr_value = 0x00000000,
  1849. .cpu_name = "(generic 44x PPC)",
  1850. .cpu_features = CPU_FTRS_44X,
  1851. .cpu_user_features = COMMON_USER_BOOKE,
  1852. .mmu_features = MMU_FTR_TYPE_44x,
  1853. .icache_bsize = 32,
  1854. .dcache_bsize = 32,
  1855. .machine_check = machine_check_4xx,
  1856. .platform = "ppc440",
  1857. }
  1858. #endif /* CONFIG_44x */
  1859. #ifdef CONFIG_E200
  1860. { /* e200z5 */
  1861. .pvr_mask = 0xfff00000,
  1862. .pvr_value = 0x81000000,
  1863. .cpu_name = "e200z5",
  1864. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1865. .cpu_features = CPU_FTRS_E200,
  1866. .cpu_user_features = COMMON_USER_BOOKE |
  1867. PPC_FEATURE_HAS_EFP_SINGLE |
  1868. PPC_FEATURE_UNIFIED_CACHE,
  1869. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1870. .dcache_bsize = 32,
  1871. .machine_check = machine_check_e200,
  1872. .platform = "ppc5554",
  1873. },
  1874. { /* e200z6 */
  1875. .pvr_mask = 0xfff00000,
  1876. .pvr_value = 0x81100000,
  1877. .cpu_name = "e200z6",
  1878. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1879. .cpu_features = CPU_FTRS_E200,
  1880. .cpu_user_features = COMMON_USER_BOOKE |
  1881. PPC_FEATURE_HAS_SPE_COMP |
  1882. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1883. PPC_FEATURE_UNIFIED_CACHE,
  1884. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1885. .dcache_bsize = 32,
  1886. .machine_check = machine_check_e200,
  1887. .platform = "ppc5554",
  1888. },
  1889. { /* default match */
  1890. .pvr_mask = 0x00000000,
  1891. .pvr_value = 0x00000000,
  1892. .cpu_name = "(generic E200 PPC)",
  1893. .cpu_features = CPU_FTRS_E200,
  1894. .cpu_user_features = COMMON_USER_BOOKE |
  1895. PPC_FEATURE_HAS_EFP_SINGLE |
  1896. PPC_FEATURE_UNIFIED_CACHE,
  1897. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1898. .dcache_bsize = 32,
  1899. .cpu_setup = __setup_cpu_e200,
  1900. .machine_check = machine_check_e200,
  1901. .platform = "ppc5554",
  1902. }
  1903. #endif /* CONFIG_E200 */
  1904. #endif /* CONFIG_PPC32 */
  1905. #ifdef CONFIG_E500
  1906. #ifdef CONFIG_PPC32
  1907. { /* e500 */
  1908. .pvr_mask = 0xffff0000,
  1909. .pvr_value = 0x80200000,
  1910. .cpu_name = "e500",
  1911. .cpu_features = CPU_FTRS_E500,
  1912. .cpu_user_features = COMMON_USER_BOOKE |
  1913. PPC_FEATURE_HAS_SPE_COMP |
  1914. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1915. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1916. .icache_bsize = 32,
  1917. .dcache_bsize = 32,
  1918. .num_pmcs = 4,
  1919. .oprofile_cpu_type = "ppc/e500",
  1920. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1921. .cpu_setup = __setup_cpu_e500v1,
  1922. .machine_check = machine_check_e500,
  1923. .platform = "ppc8540",
  1924. },
  1925. { /* e500v2 */
  1926. .pvr_mask = 0xffff0000,
  1927. .pvr_value = 0x80210000,
  1928. .cpu_name = "e500v2",
  1929. .cpu_features = CPU_FTRS_E500_2,
  1930. .cpu_user_features = COMMON_USER_BOOKE |
  1931. PPC_FEATURE_HAS_SPE_COMP |
  1932. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1933. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  1934. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  1935. .icache_bsize = 32,
  1936. .dcache_bsize = 32,
  1937. .num_pmcs = 4,
  1938. .oprofile_cpu_type = "ppc/e500",
  1939. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1940. .cpu_setup = __setup_cpu_e500v2,
  1941. .machine_check = machine_check_e500,
  1942. .platform = "ppc8548",
  1943. },
  1944. { /* e500mc */
  1945. .pvr_mask = 0xffff0000,
  1946. .pvr_value = 0x80230000,
  1947. .cpu_name = "e500mc",
  1948. .cpu_features = CPU_FTRS_E500MC,
  1949. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1950. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1951. MMU_FTR_USE_TLBILX,
  1952. .icache_bsize = 64,
  1953. .dcache_bsize = 64,
  1954. .num_pmcs = 4,
  1955. .oprofile_cpu_type = "ppc/e500mc",
  1956. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1957. .cpu_setup = __setup_cpu_e500mc,
  1958. .machine_check = machine_check_e500mc,
  1959. .platform = "ppce500mc",
  1960. },
  1961. #endif /* CONFIG_PPC32 */
  1962. { /* e5500 */
  1963. .pvr_mask = 0xffff0000,
  1964. .pvr_value = 0x80240000,
  1965. .cpu_name = "e5500",
  1966. .cpu_features = CPU_FTRS_E500MC,
  1967. .cpu_user_features = COMMON_USER_BOOKE,
  1968. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1969. MMU_FTR_USE_TLBILX,
  1970. .icache_bsize = 64,
  1971. .dcache_bsize = 64,
  1972. .num_pmcs = 4,
  1973. .oprofile_cpu_type = "ppc/e500mc",
  1974. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1975. .cpu_setup = __setup_cpu_e5500,
  1976. .cpu_restore = __restore_cpu_e5500,
  1977. .machine_check = machine_check_e500mc,
  1978. .platform = "ppce5500",
  1979. },
  1980. #ifdef CONFIG_PPC32
  1981. { /* default match */
  1982. .pvr_mask = 0x00000000,
  1983. .pvr_value = 0x00000000,
  1984. .cpu_name = "(generic E500 PPC)",
  1985. .cpu_features = CPU_FTRS_E500,
  1986. .cpu_user_features = COMMON_USER_BOOKE |
  1987. PPC_FEATURE_HAS_SPE_COMP |
  1988. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1989. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1990. .icache_bsize = 32,
  1991. .dcache_bsize = 32,
  1992. .machine_check = machine_check_e500,
  1993. .platform = "powerpc",
  1994. }
  1995. #endif /* CONFIG_PPC32 */
  1996. #endif /* CONFIG_E500 */
  1997. #ifdef CONFIG_PPC_BOOK3E_64
  1998. { /* This is a default entry to get going, to be replaced by
  1999. * a real one at some stage
  2000. */
  2001. #define CPU_FTRS_BASE_BOOK3E (CPU_FTR_USE_TB | \
  2002. CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
  2003. CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
  2004. .pvr_mask = 0x00000000,
  2005. .pvr_value = 0x00000000,
  2006. .cpu_name = "Book3E",
  2007. .cpu_features = CPU_FTRS_BASE_BOOK3E,
  2008. .cpu_user_features = COMMON_USER_PPC64,
  2009. .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
  2010. MMU_FTR_USE_TLBIVAX_BCAST |
  2011. MMU_FTR_LOCK_BCAST_INVAL,
  2012. .icache_bsize = 64,
  2013. .dcache_bsize = 64,
  2014. .num_pmcs = 0,
  2015. .machine_check = machine_check_generic,
  2016. .platform = "power6",
  2017. },
  2018. #endif
  2019. };
  2020. static struct cpu_spec the_cpu_spec;
  2021. static void __init setup_cpu_spec(unsigned long offset, struct cpu_spec *s)
  2022. {
  2023. struct cpu_spec *t = &the_cpu_spec;
  2024. struct cpu_spec old;
  2025. t = PTRRELOC(t);
  2026. old = *t;
  2027. /* Copy everything, then do fixups */
  2028. *t = *s;
  2029. /*
  2030. * If we are overriding a previous value derived from the real
  2031. * PVR with a new value obtained using a logical PVR value,
  2032. * don't modify the performance monitor fields.
  2033. */
  2034. if (old.num_pmcs && !s->num_pmcs) {
  2035. t->num_pmcs = old.num_pmcs;
  2036. t->pmc_type = old.pmc_type;
  2037. t->oprofile_type = old.oprofile_type;
  2038. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  2039. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  2040. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  2041. /*
  2042. * If we have passed through this logic once before and
  2043. * have pulled the default case because the real PVR was
  2044. * not found inside cpu_specs[], then we are possibly
  2045. * running in compatibility mode. In that case, let the
  2046. * oprofiler know which set of compatibility counters to
  2047. * pull from by making sure the oprofile_cpu_type string
  2048. * is set to that of compatibility mode. If the
  2049. * oprofile_cpu_type already has a value, then we are
  2050. * possibly overriding a real PVR with a logical one,
  2051. * and, in that case, keep the current value for
  2052. * oprofile_cpu_type.
  2053. */
  2054. if (old.oprofile_cpu_type != NULL) {
  2055. t->oprofile_cpu_type = old.oprofile_cpu_type;
  2056. t->oprofile_type = old.oprofile_type;
  2057. }
  2058. }
  2059. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2060. /*
  2061. * Set the base platform string once; assumes
  2062. * we're called with real pvr first.
  2063. */
  2064. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  2065. *PTRRELOC(&powerpc_base_platform) = t->platform;
  2066. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  2067. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  2068. * that processor. I will consolidate that at a later time, for now,
  2069. * just use #ifdef. We also don't need to PTRRELOC the function
  2070. * pointer on ppc64 and booke as we are running at 0 in real mode
  2071. * on ppc64 and reloc_offset is always 0 on booke.
  2072. */
  2073. if (s->cpu_setup) {
  2074. s->cpu_setup(offset, s);
  2075. }
  2076. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  2077. }
  2078. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  2079. {
  2080. struct cpu_spec *s = cpu_specs;
  2081. int i;
  2082. s = PTRRELOC(s);
  2083. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2084. if ((pvr & s->pvr_mask) == s->pvr_value) {
  2085. setup_cpu_spec(offset, s);
  2086. return s;
  2087. }
  2088. }
  2089. BUG();
  2090. return NULL;
  2091. }