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cpu_setup_fsl_booke.S

cpu_setup_fsl_booke.S 2.0 KB
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  1. /*
    2. 

  2.  * This file contains low level CPU setup functions.
    3. 

  3.  * Kumar Gala <galak@kernel.crashing.org>
    4. 

  4.  * Copyright 2009 Freescale Semiconductor, Inc.
    5. 

  5.  *
    6. 

  6.  * Based on cpu_setup_6xx code by
    7. 

  7.  * Benjamin Herrenschmidt <benh@kernel.crashing.org>
    8. 

  8.  *
    9. 

  9.  * This program is free software; you can redistribute it and/or
    10. 

  10.  * modify it under the terms of the GNU General Public License
    11. 

  11.  * as published by the Free Software Foundation; either version
    12. 

  12.  * 2 of the License, or (at your option) any later version.
    13. 

  13.  *
    14. 

  14.  */
    15. 

  15. 

  16. #include <asm/processor.h>
    17. 

  17. #include <asm/cputable.h>
    18. 

  18. #include <asm/ppc_asm.h>
    19. 

  19. 

  20. _GLOBAL(__e500_icache_setup)
    21. 

  21. 	mfspr	r0, SPRN_L1CSR1
    22. 

  22. 	andi.	r3, r0, L1CSR1_ICE
    23. 

  23. 	bnelr				/* Already enabled */
    24. 

  24. 	oris	r0, r0, L1CSR1_CPE@h
    25. 

  25. 	ori	r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR |  L1CSR1_ICE)
    26. 

  26. 	mtspr	SPRN_L1CSR1, r0		/* Enable I-Cache */
    27. 

  27. 	isync
    28. 

  28. 	blr
    29. 

  29. 

  30. _GLOBAL(__e500_dcache_setup)
    31. 

  31. 	mfspr	r0, SPRN_L1CSR0
    32. 

  32. 	andi.	r3, r0, L1CSR0_DCE
    33. 

  33. 	bnelr				/* Already enabled */
    34. 

  34. 	msync
    35. 

  35. 	isync
    36. 

  36. 	li	r0, 0
    37. 

  37. 	mtspr	SPRN_L1CSR0, r0		/* Disable */
    38. 

  38. 	msync
    39. 

  39. 	isync
    40. 

  40. 	li	r0, (L1CSR0_DCFI | L1CSR0_CLFC)
    41. 

  41. 	mtspr	SPRN_L1CSR0, r0		/* Invalidate */
    42. 

  42. 	isync
    43. 

  43. 1:	mfspr	r0, SPRN_L1CSR0
    44. 

  44. 	andi.	r3, r0, L1CSR0_CLFC
    45. 

  45. 	bne+	1b			/* Wait for lock bits reset */
    46. 

  46. 	oris	r0, r0, L1CSR0_CPE@h
    47. 

  47. 	ori	r0, r0, L1CSR0_DCE
    48. 

  48. 	msync
    49. 

  49. 	isync
    50. 

  50. 	mtspr	SPRN_L1CSR0, r0		/* Enable */
    51. 

  51. 	isync
    52. 

  52. 	blr
    53. 

  53. 

  54. #ifdef CONFIG_PPC32
    55. 

  55. _GLOBAL(__setup_cpu_e200)
    56. 

  56. 	/* enable dedicated debug exception handling resources (Debug APU) */
    57. 

  57. 	mfspr	r3,SPRN_HID0
    58. 

  58. 	ori	r3,r3,HID0_DAPUEN@l
    59. 

  59. 	mtspr	SPRN_HID0,r3
    60. 

  60. 	b	__setup_e200_ivors
    61. 

  61. _GLOBAL(__setup_cpu_e500v1)
    62. 

  62. _GLOBAL(__setup_cpu_e500v2)
    63. 

  63. 	mflr	r4
    64. 

  64. 	bl	__e500_icache_setup
    65. 

  65. 	bl	__e500_dcache_setup
    66. 

  66. 	bl	__setup_e500_ivors
    67. 

  67. 	mtlr	r4
    68. 

  68. 	blr
    69. 

  69. _GLOBAL(__setup_cpu_e500mc)
    70. 

  70. 	mflr	r4
    71. 

  71. 	bl	__e500_icache_setup
    72. 

  72. 	bl	__e500_dcache_setup
    73. 

  73. 	bl	__setup_e500mc_ivors
    74. 

  74. 	mtlr	r4
    75. 

  75. 	blr
    76. 

  76. #endif
    77. 

  77. /* Right now, restore and setup are the same thing */
    78. 

  78. _GLOBAL(__restore_cpu_e5500)
    79. 

  79. _GLOBAL(__setup_cpu_e5500)
    80. 

  80. 	mflr	r4
    81. 

  81. 	bl	__e500_icache_setup
    82. 

  82. 	bl	__e500_dcache_setup
    83. 

  83. #ifdef CONFIG_PPC_BOOK3E_64
    84. 

  84. 	bl	.__setup_base_ivors
    85. 

  85. #else
    86. 

  86. 	bl	__setup_e500mc_ivors
    87. 

  87. #endif
    88. 

  88. 	mtlr	r4
    89. 

  89. 	blr
    90.