setup.c 22 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2004-2007 Cavium Networks
  7. * Copyright (C) 2008 Wind River Systems
  8. */
  9. #include <linux/init.h>
  10. #include <linux/console.h>
  11. #include <linux/delay.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/serial.h>
  15. #include <linux/smp.h>
  16. #include <linux/types.h>
  17. #include <linux/string.h> /* for memset */
  18. #include <linux/tty.h>
  19. #include <linux/time.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/serial_core.h>
  22. #include <linux/serial_8250.h>
  23. #include <asm/processor.h>
  24. #include <asm/reboot.h>
  25. #include <asm/smp-ops.h>
  26. #include <asm/system.h>
  27. #include <asm/irq_cpu.h>
  28. #include <asm/mipsregs.h>
  29. #include <asm/bootinfo.h>
  30. #include <asm/sections.h>
  31. #include <asm/time.h>
  32. #include <asm/octeon/octeon.h>
  33. #include <asm/octeon/pci-octeon.h>
  34. #include <asm/octeon/cvmx-mio-defs.h>
  35. #ifdef CONFIG_CAVIUM_DECODE_RSL
  36. extern void cvmx_interrupt_rsl_decode(void);
  37. extern int __cvmx_interrupt_ecc_report_single_bit_errors;
  38. extern void cvmx_interrupt_rsl_enable(void);
  39. #endif
  40. extern struct plat_smp_ops octeon_smp_ops;
  41. #ifdef CONFIG_PCI
  42. extern void pci_console_init(const char *arg);
  43. #endif
  44. static unsigned long long MAX_MEMORY = 512ull << 20;
  45. struct octeon_boot_descriptor *octeon_boot_desc_ptr;
  46. struct cvmx_bootinfo *octeon_bootinfo;
  47. EXPORT_SYMBOL(octeon_bootinfo);
  48. #ifdef CONFIG_CAVIUM_RESERVE32
  49. uint64_t octeon_reserve32_memory;
  50. EXPORT_SYMBOL(octeon_reserve32_memory);
  51. #endif
  52. static int octeon_uart;
  53. extern asmlinkage void handle_int(void);
  54. extern asmlinkage void plat_irq_dispatch(void);
  55. /**
  56. * Return non zero if we are currently running in the Octeon simulator
  57. *
  58. * Returns
  59. */
  60. int octeon_is_simulation(void)
  61. {
  62. return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
  63. }
  64. EXPORT_SYMBOL(octeon_is_simulation);
  65. /**
  66. * Return true if Octeon is in PCI Host mode. This means
  67. * Linux can control the PCI bus.
  68. *
  69. * Returns Non zero if Octeon in host mode.
  70. */
  71. int octeon_is_pci_host(void)
  72. {
  73. #ifdef CONFIG_PCI
  74. return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
  75. #else
  76. return 0;
  77. #endif
  78. }
  79. /**
  80. * Get the clock rate of Octeon
  81. *
  82. * Returns Clock rate in HZ
  83. */
  84. uint64_t octeon_get_clock_rate(void)
  85. {
  86. struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
  87. return sysinfo->cpu_clock_hz;
  88. }
  89. EXPORT_SYMBOL(octeon_get_clock_rate);
  90. static u64 octeon_io_clock_rate;
  91. u64 octeon_get_io_clock_rate(void)
  92. {
  93. return octeon_io_clock_rate;
  94. }
  95. EXPORT_SYMBOL(octeon_get_io_clock_rate);
  96. /**
  97. * Write to the LCD display connected to the bootbus. This display
  98. * exists on most Cavium evaluation boards. If it doesn't exist, then
  99. * this function doesn't do anything.
  100. *
  101. * @s: String to write
  102. */
  103. void octeon_write_lcd(const char *s)
  104. {
  105. if (octeon_bootinfo->led_display_base_addr) {
  106. void __iomem *lcd_address =
  107. ioremap_nocache(octeon_bootinfo->led_display_base_addr,
  108. 8);
  109. int i;
  110. for (i = 0; i < 8; i++, s++) {
  111. if (*s)
  112. iowrite8(*s, lcd_address + i);
  113. else
  114. iowrite8(' ', lcd_address + i);
  115. }
  116. iounmap(lcd_address);
  117. }
  118. }
  119. /**
  120. * Return the console uart passed by the bootloader
  121. *
  122. * Returns uart (0 or 1)
  123. */
  124. int octeon_get_boot_uart(void)
  125. {
  126. int uart;
  127. #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
  128. uart = 1;
  129. #else
  130. uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
  131. 1 : 0;
  132. #endif
  133. return uart;
  134. }
  135. /**
  136. * Get the coremask Linux was booted on.
  137. *
  138. * Returns Core mask
  139. */
  140. int octeon_get_boot_coremask(void)
  141. {
  142. return octeon_boot_desc_ptr->core_mask;
  143. }
  144. /**
  145. * Check the hardware BIST results for a CPU
  146. */
  147. void octeon_check_cpu_bist(void)
  148. {
  149. const int coreid = cvmx_get_core_num();
  150. unsigned long long mask;
  151. unsigned long long bist_val;
  152. /* Check BIST results for COP0 registers */
  153. mask = 0x1f00000000ull;
  154. bist_val = read_octeon_c0_icacheerr();
  155. if (bist_val & mask)
  156. pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
  157. coreid, bist_val);
  158. bist_val = read_octeon_c0_dcacheerr();
  159. if (bist_val & 1)
  160. pr_err("Core%d L1 Dcache parity error: "
  161. "CacheErr(dcache) = 0x%llx\n",
  162. coreid, bist_val);
  163. mask = 0xfc00000000000000ull;
  164. bist_val = read_c0_cvmmemctl();
  165. if (bist_val & mask)
  166. pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
  167. coreid, bist_val);
  168. write_octeon_c0_dcacheerr(0);
  169. }
  170. /**
  171. * Reboot Octeon
  172. *
  173. * @command: Command to pass to the bootloader. Currently ignored.
  174. */
  175. static void octeon_restart(char *command)
  176. {
  177. /* Disable all watchdogs before soft reset. They don't get cleared */
  178. #ifdef CONFIG_SMP
  179. int cpu;
  180. for_each_online_cpu(cpu)
  181. cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
  182. #else
  183. cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
  184. #endif
  185. mb();
  186. while (1)
  187. cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
  188. }
  189. /**
  190. * Permanently stop a core.
  191. *
  192. * @arg: Ignored.
  193. */
  194. static void octeon_kill_core(void *arg)
  195. {
  196. mb();
  197. if (octeon_is_simulation()) {
  198. /* The simulator needs the watchdog to stop for dead cores */
  199. cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
  200. /* A break instruction causes the simulator stop a core */
  201. asm volatile ("sync\nbreak");
  202. }
  203. }
  204. /**
  205. * Halt the system
  206. */
  207. static void octeon_halt(void)
  208. {
  209. smp_call_function(octeon_kill_core, NULL, 0);
  210. switch (octeon_bootinfo->board_type) {
  211. case CVMX_BOARD_TYPE_NAO38:
  212. /* Driving a 1 to GPIO 12 shuts off this board */
  213. cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
  214. cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
  215. break;
  216. default:
  217. octeon_write_lcd("PowerOff");
  218. break;
  219. }
  220. octeon_kill_core(NULL);
  221. }
  222. /**
  223. * Handle all the error condition interrupts that might occur.
  224. *
  225. */
  226. #ifdef CONFIG_CAVIUM_DECODE_RSL
  227. static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
  228. {
  229. cvmx_interrupt_rsl_decode();
  230. return IRQ_HANDLED;
  231. }
  232. #endif
  233. /**
  234. * Return a string representing the system type
  235. *
  236. * Returns
  237. */
  238. const char *octeon_board_type_string(void)
  239. {
  240. static char name[80];
  241. sprintf(name, "%s (%s)",
  242. cvmx_board_type_to_string(octeon_bootinfo->board_type),
  243. octeon_model_get_string(read_c0_prid()));
  244. return name;
  245. }
  246. const char *get_system_type(void)
  247. __attribute__ ((alias("octeon_board_type_string")));
  248. void octeon_user_io_init(void)
  249. {
  250. union octeon_cvmemctl cvmmemctl;
  251. union cvmx_iob_fau_timeout fau_timeout;
  252. union cvmx_pow_nw_tim nm_tim;
  253. uint64_t cvmctl;
  254. /* Get the current settings for CP0_CVMMEMCTL_REG */
  255. cvmmemctl.u64 = read_c0_cvmmemctl();
  256. /* R/W If set, marked write-buffer entries time out the same
  257. * as as other entries; if clear, marked write-buffer entries
  258. * use the maximum timeout. */
  259. cvmmemctl.s.dismarkwblongto = 1;
  260. /* R/W If set, a merged store does not clear the write-buffer
  261. * entry timeout state. */
  262. cvmmemctl.s.dismrgclrwbto = 0;
  263. /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
  264. * word location for an IOBDMA. The other 8 bits come from the
  265. * SCRADDR field of the IOBDMA. */
  266. cvmmemctl.s.iobdmascrmsb = 0;
  267. /* R/W If set, SYNCWS and SYNCS only order marked stores; if
  268. * clear, SYNCWS and SYNCS only order unmarked
  269. * stores. SYNCWSMARKED has no effect when DISSYNCWS is
  270. * set. */
  271. cvmmemctl.s.syncwsmarked = 0;
  272. /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
  273. cvmmemctl.s.dissyncws = 0;
  274. /* R/W If set, no stall happens on write buffer full. */
  275. if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
  276. cvmmemctl.s.diswbfst = 1;
  277. else
  278. cvmmemctl.s.diswbfst = 0;
  279. /* R/W If set (and SX set), supervisor-level loads/stores can
  280. * use XKPHYS addresses with <48>==0 */
  281. cvmmemctl.s.xkmemenas = 0;
  282. /* R/W If set (and UX set), user-level loads/stores can use
  283. * XKPHYS addresses with VA<48>==0 */
  284. cvmmemctl.s.xkmemenau = 0;
  285. /* R/W If set (and SX set), supervisor-level loads/stores can
  286. * use XKPHYS addresses with VA<48>==1 */
  287. cvmmemctl.s.xkioenas = 0;
  288. /* R/W If set (and UX set), user-level loads/stores can use
  289. * XKPHYS addresses with VA<48>==1 */
  290. cvmmemctl.s.xkioenau = 0;
  291. /* R/W If set, all stores act as SYNCW (NOMERGE must be set
  292. * when this is set) RW, reset to 0. */
  293. cvmmemctl.s.allsyncw = 0;
  294. /* R/W If set, no stores merge, and all stores reach the
  295. * coherent bus in order. */
  296. cvmmemctl.s.nomerge = 0;
  297. /* R/W Selects the bit in the counter used for DID time-outs 0
  298. * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
  299. * between 1x and 2x this interval. For example, with
  300. * DIDTTO=3, expiration interval is between 16K and 32K. */
  301. cvmmemctl.s.didtto = 0;
  302. /* R/W If set, the (mem) CSR clock never turns off. */
  303. cvmmemctl.s.csrckalwys = 0;
  304. /* R/W If set, mclk never turns off. */
  305. cvmmemctl.s.mclkalwys = 0;
  306. /* R/W Selects the bit in the counter used for write buffer
  307. * flush time-outs (WBFLT+11) is the bit position in an
  308. * internal counter used to determine expiration. The write
  309. * buffer expires between 1x and 2x this interval. For
  310. * example, with WBFLT = 0, a write buffer expires between 2K
  311. * and 4K cycles after the write buffer entry is allocated. */
  312. cvmmemctl.s.wbfltime = 0;
  313. /* R/W If set, do not put Istream in the L2 cache. */
  314. cvmmemctl.s.istrnol2 = 0;
  315. /*
  316. * R/W The write buffer threshold. As per erratum Core-14752
  317. * for CN63XX, a sc/scd might fail if the write buffer is
  318. * full. Lowering WBTHRESH greatly lowers the chances of the
  319. * write buffer ever being full and triggering the erratum.
  320. */
  321. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
  322. cvmmemctl.s.wbthresh = 4;
  323. else
  324. cvmmemctl.s.wbthresh = 10;
  325. /* R/W If set, CVMSEG is available for loads/stores in
  326. * kernel/debug mode. */
  327. #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
  328. cvmmemctl.s.cvmsegenak = 1;
  329. #else
  330. cvmmemctl.s.cvmsegenak = 0;
  331. #endif
  332. /* R/W If set, CVMSEG is available for loads/stores in
  333. * supervisor mode. */
  334. cvmmemctl.s.cvmsegenas = 0;
  335. /* R/W If set, CVMSEG is available for loads/stores in user
  336. * mode. */
  337. cvmmemctl.s.cvmsegenau = 0;
  338. /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
  339. * is max legal value. */
  340. cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
  341. write_c0_cvmmemctl(cvmmemctl.u64);
  342. if (smp_processor_id() == 0)
  343. pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
  344. CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
  345. CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
  346. /* Move the performance counter interrupts to IRQ 6 */
  347. cvmctl = read_c0_cvmctl();
  348. cvmctl &= ~(7 << 7);
  349. cvmctl |= 6 << 7;
  350. write_c0_cvmctl(cvmctl);
  351. /* Set a default for the hardware timeouts */
  352. fau_timeout.u64 = 0;
  353. fau_timeout.s.tout_val = 0xfff;
  354. /* Disable tagwait FAU timeout */
  355. fau_timeout.s.tout_enb = 0;
  356. cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
  357. nm_tim.u64 = 0;
  358. /* 4096 cycles */
  359. nm_tim.s.nw_tim = 3;
  360. cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
  361. write_octeon_c0_icacheerr(0);
  362. write_c0_derraddr1(0);
  363. }
  364. /**
  365. * Early entry point for arch setup
  366. */
  367. void __init prom_init(void)
  368. {
  369. struct cvmx_sysinfo *sysinfo;
  370. const int coreid = cvmx_get_core_num();
  371. int i;
  372. int argc;
  373. #ifdef CONFIG_CAVIUM_RESERVE32
  374. int64_t addr = -1;
  375. #endif
  376. /*
  377. * The bootloader passes a pointer to the boot descriptor in
  378. * $a3, this is available as fw_arg3.
  379. */
  380. octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
  381. octeon_bootinfo =
  382. cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
  383. cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
  384. sysinfo = cvmx_sysinfo_get();
  385. memset(sysinfo, 0, sizeof(*sysinfo));
  386. sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
  387. sysinfo->phy_mem_desc_ptr =
  388. cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
  389. sysinfo->core_mask = octeon_bootinfo->core_mask;
  390. sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
  391. sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
  392. sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
  393. sysinfo->board_type = octeon_bootinfo->board_type;
  394. sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
  395. sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
  396. memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
  397. sizeof(sysinfo->mac_addr_base));
  398. sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
  399. memcpy(sysinfo->board_serial_number,
  400. octeon_bootinfo->board_serial_number,
  401. sizeof(sysinfo->board_serial_number));
  402. sysinfo->compact_flash_common_base_addr =
  403. octeon_bootinfo->compact_flash_common_base_addr;
  404. sysinfo->compact_flash_attribute_base_addr =
  405. octeon_bootinfo->compact_flash_attribute_base_addr;
  406. sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
  407. sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
  408. sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
  409. if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
  410. /* I/O clock runs at a different rate than the CPU. */
  411. union cvmx_mio_rst_boot rst_boot;
  412. rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
  413. octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
  414. } else {
  415. octeon_io_clock_rate = sysinfo->cpu_clock_hz;
  416. }
  417. /*
  418. * Only enable the LED controller if we're running on a CN38XX, CN58XX,
  419. * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
  420. */
  421. if (!octeon_is_simulation() &&
  422. octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
  423. cvmx_write_csr(CVMX_LED_EN, 0);
  424. cvmx_write_csr(CVMX_LED_PRT, 0);
  425. cvmx_write_csr(CVMX_LED_DBG, 0);
  426. cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
  427. cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
  428. cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
  429. cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
  430. cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
  431. cvmx_write_csr(CVMX_LED_EN, 1);
  432. }
  433. #ifdef CONFIG_CAVIUM_RESERVE32
  434. /*
  435. * We need to temporarily allocate all memory in the reserve32
  436. * region. This makes sure the kernel doesn't allocate this
  437. * memory when it is getting memory from the
  438. * bootloader. Later, after the memory allocations are
  439. * complete, the reserve32 will be freed.
  440. *
  441. * Allocate memory for RESERVED32 aligned on 2MB boundary. This
  442. * is in case we later use hugetlb entries with it.
  443. */
  444. addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
  445. 0, 0, 2 << 20,
  446. "CAVIUM_RESERVE32", 0);
  447. if (addr < 0)
  448. pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
  449. else
  450. octeon_reserve32_memory = addr;
  451. #endif
  452. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
  453. if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
  454. pr_info("Skipping L2 locking due to reduced L2 cache size\n");
  455. } else {
  456. uint32_t ebase = read_c0_ebase() & 0x3ffff000;
  457. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
  458. /* TLB refill */
  459. cvmx_l2c_lock_mem_region(ebase, 0x100);
  460. #endif
  461. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
  462. /* General exception */
  463. cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
  464. #endif
  465. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
  466. /* Interrupt handler */
  467. cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
  468. #endif
  469. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
  470. cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
  471. cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
  472. #endif
  473. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
  474. cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
  475. #endif
  476. }
  477. #endif
  478. octeon_check_cpu_bist();
  479. octeon_uart = octeon_get_boot_uart();
  480. /*
  481. * Disable All CIU Interrupts. The ones we need will be
  482. * enabled later. Read the SUM register so we know the write
  483. * completed.
  484. */
  485. cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
  486. cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
  487. cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
  488. cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
  489. cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
  490. #ifdef CONFIG_SMP
  491. octeon_write_lcd("LinuxSMP");
  492. #else
  493. octeon_write_lcd("Linux");
  494. #endif
  495. #ifdef CONFIG_CAVIUM_GDB
  496. /*
  497. * When debugging the linux kernel, force the cores to enter
  498. * the debug exception handler to break in.
  499. */
  500. if (octeon_get_boot_debug_flag()) {
  501. cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num());
  502. cvmx_read_csr(CVMX_CIU_DINT);
  503. }
  504. #endif
  505. /*
  506. * BIST should always be enabled when doing a soft reset. L2
  507. * Cache locking for instance is not cleared unless BIST is
  508. * enabled. Unfortunately due to a chip errata G-200 for
  509. * Cn38XX and CN31XX, BIST msut be disabled on these parts.
  510. */
  511. if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
  512. OCTEON_IS_MODEL(OCTEON_CN31XX))
  513. cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
  514. else
  515. cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
  516. /* Default to 64MB in the simulator to speed things up */
  517. if (octeon_is_simulation())
  518. MAX_MEMORY = 64ull << 20;
  519. arcs_cmdline[0] = 0;
  520. argc = octeon_boot_desc_ptr->argc;
  521. for (i = 0; i < argc; i++) {
  522. const char *arg =
  523. cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
  524. if ((strncmp(arg, "MEM=", 4) == 0) ||
  525. (strncmp(arg, "mem=", 4) == 0)) {
  526. sscanf(arg + 4, "%llu", &MAX_MEMORY);
  527. MAX_MEMORY <<= 20;
  528. if (MAX_MEMORY == 0)
  529. MAX_MEMORY = 32ull << 30;
  530. } else if (strcmp(arg, "ecc_verbose") == 0) {
  531. #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
  532. __cvmx_interrupt_ecc_report_single_bit_errors = 1;
  533. pr_notice("Reporting of single bit ECC errors is "
  534. "turned on\n");
  535. #endif
  536. } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
  537. sizeof(arcs_cmdline) - 1) {
  538. strcat(arcs_cmdline, " ");
  539. strcat(arcs_cmdline, arg);
  540. }
  541. }
  542. if (strstr(arcs_cmdline, "console=") == NULL) {
  543. #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
  544. strcat(arcs_cmdline, " console=ttyS0,115200");
  545. #else
  546. if (octeon_uart == 1)
  547. strcat(arcs_cmdline, " console=ttyS1,115200");
  548. else
  549. strcat(arcs_cmdline, " console=ttyS0,115200");
  550. #endif
  551. }
  552. if (octeon_is_simulation()) {
  553. /*
  554. * The simulator uses a mtdram device pre filled with
  555. * the filesystem. Also specify the calibration delay
  556. * to avoid calculating it every time.
  557. */
  558. strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
  559. }
  560. mips_hpt_frequency = octeon_get_clock_rate();
  561. octeon_init_cvmcount();
  562. octeon_setup_delays();
  563. _machine_restart = octeon_restart;
  564. _machine_halt = octeon_halt;
  565. octeon_user_io_init();
  566. register_smp_ops(&octeon_smp_ops);
  567. }
  568. /* Exclude a single page from the regions obtained in plat_mem_setup. */
  569. static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
  570. {
  571. if (addr > *mem && addr < *mem + *size) {
  572. u64 inc = addr - *mem;
  573. add_memory_region(*mem, inc, BOOT_MEM_RAM);
  574. *mem += inc;
  575. *size -= inc;
  576. }
  577. if (addr == *mem && *size > PAGE_SIZE) {
  578. *mem += PAGE_SIZE;
  579. *size -= PAGE_SIZE;
  580. }
  581. }
  582. void __init plat_mem_setup(void)
  583. {
  584. uint64_t mem_alloc_size;
  585. uint64_t total;
  586. int64_t memory;
  587. total = 0;
  588. /* First add the init memory we will be returning. */
  589. memory = __pa_symbol(&__init_begin) & PAGE_MASK;
  590. mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory;
  591. if (mem_alloc_size > 0) {
  592. add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
  593. total += mem_alloc_size;
  594. }
  595. /*
  596. * The Mips memory init uses the first memory location for
  597. * some memory vectors. When SPARSEMEM is in use, it doesn't
  598. * verify that the size is big enough for the final
  599. * vectors. Making the smallest chuck 4MB seems to be enough
  600. * to consistantly work.
  601. */
  602. mem_alloc_size = 4 << 20;
  603. if (mem_alloc_size > MAX_MEMORY)
  604. mem_alloc_size = MAX_MEMORY;
  605. /*
  606. * When allocating memory, we want incrementing addresses from
  607. * bootmem_alloc so the code in add_memory_region can merge
  608. * regions next to each other.
  609. */
  610. cvmx_bootmem_lock();
  611. while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
  612. && (total < MAX_MEMORY)) {
  613. #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
  614. memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
  615. __pa_symbol(&__init_end), -1,
  616. 0x100000,
  617. CVMX_BOOTMEM_FLAG_NO_LOCKING);
  618. #elif defined(CONFIG_HIGHMEM)
  619. memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31,
  620. 0x100000,
  621. CVMX_BOOTMEM_FLAG_NO_LOCKING);
  622. #else
  623. memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20,
  624. 0x100000,
  625. CVMX_BOOTMEM_FLAG_NO_LOCKING);
  626. #endif
  627. if (memory >= 0) {
  628. u64 size = mem_alloc_size;
  629. /*
  630. * exclude a page at the beginning and end of
  631. * the 256MB PCIe 'hole' so the kernel will not
  632. * try to allocate multi-page buffers that
  633. * span the discontinuity.
  634. */
  635. memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
  636. &memory, &size);
  637. memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
  638. CVMX_PCIE_BAR1_PHYS_SIZE,
  639. &memory, &size);
  640. /*
  641. * This function automatically merges address
  642. * regions next to each other if they are
  643. * received in incrementing order.
  644. */
  645. if (size)
  646. add_memory_region(memory, size, BOOT_MEM_RAM);
  647. total += mem_alloc_size;
  648. } else {
  649. break;
  650. }
  651. }
  652. cvmx_bootmem_unlock();
  653. #ifdef CONFIG_CAVIUM_RESERVE32
  654. /*
  655. * Now that we've allocated the kernel memory it is safe to
  656. * free the reserved region. We free it here so that builtin
  657. * drivers can use the memory.
  658. */
  659. if (octeon_reserve32_memory)
  660. cvmx_bootmem_free_named("CAVIUM_RESERVE32");
  661. #endif /* CONFIG_CAVIUM_RESERVE32 */
  662. if (total == 0)
  663. panic("Unable to allocate memory from "
  664. "cvmx_bootmem_phy_alloc\n");
  665. }
  666. /*
  667. * Emit one character to the boot UART. Exported for use by the
  668. * watchdog timer.
  669. */
  670. int prom_putchar(char c)
  671. {
  672. uint64_t lsrval;
  673. /* Spin until there is room */
  674. do {
  675. lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
  676. } while ((lsrval & 0x20) == 0);
  677. /* Write the byte */
  678. cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
  679. return 1;
  680. }
  681. EXPORT_SYMBOL(prom_putchar);
  682. void prom_free_prom_memory(void)
  683. {
  684. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
  685. /* Check for presence of Core-14449 fix. */
  686. u32 insn;
  687. u32 *foo;
  688. foo = &insn;
  689. asm volatile("# before" : : : "memory");
  690. prefetch(foo);
  691. asm volatile(
  692. ".set push\n\t"
  693. ".set noreorder\n\t"
  694. "bal 1f\n\t"
  695. "nop\n"
  696. "1:\tlw %0,-12($31)\n\t"
  697. ".set pop\n\t"
  698. : "=r" (insn) : : "$31", "memory");
  699. if ((insn >> 26) != 0x33)
  700. panic("No PREF instruction at Core-14449 probe point.\n");
  701. if (((insn >> 16) & 0x1f) != 28)
  702. panic("Core-14449 WAR not in place (%04x).\n"
  703. "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);
  704. }
  705. #ifdef CONFIG_CAVIUM_DECODE_RSL
  706. cvmx_interrupt_rsl_enable();
  707. /* Add an interrupt handler for general failures. */
  708. if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
  709. "RML/RSL", octeon_rlm_interrupt)) {
  710. panic("Unable to request_irq(OCTEON_IRQ_RML)\n");
  711. }
  712. #endif
  713. }