platform.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494
  1. /*
  2. * Platform device support for Au1x00 SoCs.
  3. *
  4. * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
  5. *
  6. * (C) Copyright Embedded Alley Solutions, Inc 2005
  7. * Author: Pantelis Antoniou <pantelis@embeddedalley.com>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/dma-mapping.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/serial_8250.h>
  17. #include <linux/init.h>
  18. #include <asm/mach-au1x00/au1xxx.h>
  19. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  20. #include <asm/mach-au1x00/au1100_mmc.h>
  21. #include <asm/mach-au1x00/au1xxx_eth.h>
  22. #include <prom.h>
  23. static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
  24. unsigned int old_state)
  25. {
  26. switch (state) {
  27. case 0:
  28. if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) {
  29. /* power-on sequence as suggested in the databooks */
  30. __raw_writel(0, port->membase + UART_MOD_CNTRL);
  31. wmb();
  32. __raw_writel(1, port->membase + UART_MOD_CNTRL);
  33. wmb();
  34. }
  35. __raw_writel(3, port->membase + UART_MOD_CNTRL); /* full on */
  36. wmb();
  37. serial8250_do_pm(port, state, old_state);
  38. break;
  39. case 3: /* power off */
  40. serial8250_do_pm(port, state, old_state);
  41. __raw_writel(0, port->membase + UART_MOD_CNTRL);
  42. wmb();
  43. break;
  44. default:
  45. serial8250_do_pm(port, state, old_state);
  46. break;
  47. }
  48. }
  49. #define PORT(_base, _irq) \
  50. { \
  51. .mapbase = _base, \
  52. .irq = _irq, \
  53. .regshift = 2, \
  54. .iotype = UPIO_AU, \
  55. .flags = UPF_SKIP_TEST | UPF_IOREMAP | \
  56. UPF_FIXED_TYPE, \
  57. .type = PORT_16550A, \
  58. .pm = alchemy_8250_pm, \
  59. }
  60. static struct plat_serial8250_port au1x00_uart_data[] = {
  61. #if defined(CONFIG_SOC_AU1000)
  62. PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
  63. PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
  64. PORT(UART2_PHYS_ADDR, AU1000_UART2_INT),
  65. PORT(UART3_PHYS_ADDR, AU1000_UART3_INT),
  66. #elif defined(CONFIG_SOC_AU1500)
  67. PORT(UART0_PHYS_ADDR, AU1500_UART0_INT),
  68. PORT(UART3_PHYS_ADDR, AU1500_UART3_INT),
  69. #elif defined(CONFIG_SOC_AU1100)
  70. PORT(UART0_PHYS_ADDR, AU1100_UART0_INT),
  71. PORT(UART1_PHYS_ADDR, AU1100_UART1_INT),
  72. PORT(UART3_PHYS_ADDR, AU1100_UART3_INT),
  73. #elif defined(CONFIG_SOC_AU1550)
  74. PORT(UART0_PHYS_ADDR, AU1550_UART0_INT),
  75. PORT(UART1_PHYS_ADDR, AU1550_UART1_INT),
  76. PORT(UART3_PHYS_ADDR, AU1550_UART3_INT),
  77. #elif defined(CONFIG_SOC_AU1200)
  78. PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
  79. PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
  80. #endif
  81. { },
  82. };
  83. static struct platform_device au1xx0_uart_device = {
  84. .name = "serial8250",
  85. .id = PLAT8250_DEV_AU1X00,
  86. .dev = {
  87. .platform_data = au1x00_uart_data,
  88. },
  89. };
  90. /* OHCI (USB full speed host controller) */
  91. static struct resource au1xxx_usb_ohci_resources[] = {
  92. [0] = {
  93. .start = USB_OHCI_BASE,
  94. .end = USB_OHCI_BASE + USB_OHCI_LEN - 1,
  95. .flags = IORESOURCE_MEM,
  96. },
  97. [1] = {
  98. .start = FOR_PLATFORM_C_USB_HOST_INT,
  99. .end = FOR_PLATFORM_C_USB_HOST_INT,
  100. .flags = IORESOURCE_IRQ,
  101. },
  102. };
  103. /* The dmamask must be set for OHCI to work */
  104. static u64 ohci_dmamask = DMA_BIT_MASK(32);
  105. static struct platform_device au1xxx_usb_ohci_device = {
  106. .name = "au1xxx-ohci",
  107. .id = 0,
  108. .dev = {
  109. .dma_mask = &ohci_dmamask,
  110. .coherent_dma_mask = DMA_BIT_MASK(32),
  111. },
  112. .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources),
  113. .resource = au1xxx_usb_ohci_resources,
  114. };
  115. /*** AU1100 LCD controller ***/
  116. #ifdef CONFIG_FB_AU1100
  117. static struct resource au1100_lcd_resources[] = {
  118. [0] = {
  119. .start = LCD_PHYS_ADDR,
  120. .end = LCD_PHYS_ADDR + 0x800 - 1,
  121. .flags = IORESOURCE_MEM,
  122. },
  123. [1] = {
  124. .start = AU1100_LCD_INT,
  125. .end = AU1100_LCD_INT,
  126. .flags = IORESOURCE_IRQ,
  127. }
  128. };
  129. static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
  130. static struct platform_device au1100_lcd_device = {
  131. .name = "au1100-lcd",
  132. .id = 0,
  133. .dev = {
  134. .dma_mask = &au1100_lcd_dmamask,
  135. .coherent_dma_mask = DMA_BIT_MASK(32),
  136. },
  137. .num_resources = ARRAY_SIZE(au1100_lcd_resources),
  138. .resource = au1100_lcd_resources,
  139. };
  140. #endif
  141. #ifdef CONFIG_SOC_AU1200
  142. /* EHCI (USB high speed host controller) */
  143. static struct resource au1xxx_usb_ehci_resources[] = {
  144. [0] = {
  145. .start = USB_EHCI_BASE,
  146. .end = USB_EHCI_BASE + USB_EHCI_LEN - 1,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. [1] = {
  150. .start = AU1200_USB_INT,
  151. .end = AU1200_USB_INT,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. };
  155. static u64 ehci_dmamask = DMA_BIT_MASK(32);
  156. static struct platform_device au1xxx_usb_ehci_device = {
  157. .name = "au1xxx-ehci",
  158. .id = 0,
  159. .dev = {
  160. .dma_mask = &ehci_dmamask,
  161. .coherent_dma_mask = DMA_BIT_MASK(32),
  162. },
  163. .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources),
  164. .resource = au1xxx_usb_ehci_resources,
  165. };
  166. /* Au1200 UDC (USB gadget controller) */
  167. static struct resource au1xxx_usb_gdt_resources[] = {
  168. [0] = {
  169. .start = USB_UDC_BASE,
  170. .end = USB_UDC_BASE + USB_UDC_LEN - 1,
  171. .flags = IORESOURCE_MEM,
  172. },
  173. [1] = {
  174. .start = AU1200_USB_INT,
  175. .end = AU1200_USB_INT,
  176. .flags = IORESOURCE_IRQ,
  177. },
  178. };
  179. static u64 udc_dmamask = DMA_BIT_MASK(32);
  180. static struct platform_device au1xxx_usb_gdt_device = {
  181. .name = "au1xxx-udc",
  182. .id = 0,
  183. .dev = {
  184. .dma_mask = &udc_dmamask,
  185. .coherent_dma_mask = DMA_BIT_MASK(32),
  186. },
  187. .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources),
  188. .resource = au1xxx_usb_gdt_resources,
  189. };
  190. /* Au1200 UOC (USB OTG controller) */
  191. static struct resource au1xxx_usb_otg_resources[] = {
  192. [0] = {
  193. .start = USB_UOC_BASE,
  194. .end = USB_UOC_BASE + USB_UOC_LEN - 1,
  195. .flags = IORESOURCE_MEM,
  196. },
  197. [1] = {
  198. .start = AU1200_USB_INT,
  199. .end = AU1200_USB_INT,
  200. .flags = IORESOURCE_IRQ,
  201. },
  202. };
  203. static u64 uoc_dmamask = DMA_BIT_MASK(32);
  204. static struct platform_device au1xxx_usb_otg_device = {
  205. .name = "au1xxx-uoc",
  206. .id = 0,
  207. .dev = {
  208. .dma_mask = &uoc_dmamask,
  209. .coherent_dma_mask = DMA_BIT_MASK(32),
  210. },
  211. .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources),
  212. .resource = au1xxx_usb_otg_resources,
  213. };
  214. static struct resource au1200_lcd_resources[] = {
  215. [0] = {
  216. .start = LCD_PHYS_ADDR,
  217. .end = LCD_PHYS_ADDR + 0x800 - 1,
  218. .flags = IORESOURCE_MEM,
  219. },
  220. [1] = {
  221. .start = AU1200_LCD_INT,
  222. .end = AU1200_LCD_INT,
  223. .flags = IORESOURCE_IRQ,
  224. }
  225. };
  226. static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
  227. static struct platform_device au1200_lcd_device = {
  228. .name = "au1200-lcd",
  229. .id = 0,
  230. .dev = {
  231. .dma_mask = &au1200_lcd_dmamask,
  232. .coherent_dma_mask = DMA_BIT_MASK(32),
  233. },
  234. .num_resources = ARRAY_SIZE(au1200_lcd_resources),
  235. .resource = au1200_lcd_resources,
  236. };
  237. static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
  238. extern struct au1xmmc_platform_data au1xmmc_platdata[2];
  239. static struct resource au1200_mmc0_resources[] = {
  240. [0] = {
  241. .start = SD0_PHYS_ADDR,
  242. .end = SD0_PHYS_ADDR + 0x7ffff,
  243. .flags = IORESOURCE_MEM,
  244. },
  245. [1] = {
  246. .start = AU1200_SD_INT,
  247. .end = AU1200_SD_INT,
  248. .flags = IORESOURCE_IRQ,
  249. },
  250. [2] = {
  251. .start = DSCR_CMD0_SDMS_TX0,
  252. .end = DSCR_CMD0_SDMS_TX0,
  253. .flags = IORESOURCE_DMA,
  254. },
  255. [3] = {
  256. .start = DSCR_CMD0_SDMS_RX0,
  257. .end = DSCR_CMD0_SDMS_RX0,
  258. .flags = IORESOURCE_DMA,
  259. }
  260. };
  261. static struct platform_device au1200_mmc0_device = {
  262. .name = "au1xxx-mmc",
  263. .id = 0,
  264. .dev = {
  265. .dma_mask = &au1xxx_mmc_dmamask,
  266. .coherent_dma_mask = DMA_BIT_MASK(32),
  267. .platform_data = &au1xmmc_platdata[0],
  268. },
  269. .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
  270. .resource = au1200_mmc0_resources,
  271. };
  272. #ifndef CONFIG_MIPS_DB1200
  273. static struct resource au1200_mmc1_resources[] = {
  274. [0] = {
  275. .start = SD1_PHYS_ADDR,
  276. .end = SD1_PHYS_ADDR + 0x7ffff,
  277. .flags = IORESOURCE_MEM,
  278. },
  279. [1] = {
  280. .start = AU1200_SD_INT,
  281. .end = AU1200_SD_INT,
  282. .flags = IORESOURCE_IRQ,
  283. },
  284. [2] = {
  285. .start = DSCR_CMD0_SDMS_TX1,
  286. .end = DSCR_CMD0_SDMS_TX1,
  287. .flags = IORESOURCE_DMA,
  288. },
  289. [3] = {
  290. .start = DSCR_CMD0_SDMS_RX1,
  291. .end = DSCR_CMD0_SDMS_RX1,
  292. .flags = IORESOURCE_DMA,
  293. }
  294. };
  295. static struct platform_device au1200_mmc1_device = {
  296. .name = "au1xxx-mmc",
  297. .id = 1,
  298. .dev = {
  299. .dma_mask = &au1xxx_mmc_dmamask,
  300. .coherent_dma_mask = DMA_BIT_MASK(32),
  301. .platform_data = &au1xmmc_platdata[1],
  302. },
  303. .num_resources = ARRAY_SIZE(au1200_mmc1_resources),
  304. .resource = au1200_mmc1_resources,
  305. };
  306. #endif /* #ifndef CONFIG_MIPS_DB1200 */
  307. #endif /* #ifdef CONFIG_SOC_AU1200 */
  308. /* All Alchemy demoboards with I2C have this #define in their headers */
  309. #ifdef SMBUS_PSC_BASE
  310. static struct resource pbdb_smbus_resources[] = {
  311. {
  312. .start = CPHYSADDR(SMBUS_PSC_BASE),
  313. .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
  314. .flags = IORESOURCE_MEM,
  315. },
  316. };
  317. static struct platform_device pbdb_smbus_device = {
  318. .name = "au1xpsc_smbus",
  319. .id = 0, /* bus number */
  320. .num_resources = ARRAY_SIZE(pbdb_smbus_resources),
  321. .resource = pbdb_smbus_resources,
  322. };
  323. #endif
  324. /* Macro to help defining the Ethernet MAC resources */
  325. #define MAC_RES(_base, _enable, _irq) \
  326. { \
  327. .start = CPHYSADDR(_base), \
  328. .end = CPHYSADDR(_base + 0xffff), \
  329. .flags = IORESOURCE_MEM, \
  330. }, \
  331. { \
  332. .start = CPHYSADDR(_enable), \
  333. .end = CPHYSADDR(_enable + 0x3), \
  334. .flags = IORESOURCE_MEM, \
  335. }, \
  336. { \
  337. .start = _irq, \
  338. .end = _irq, \
  339. .flags = IORESOURCE_IRQ \
  340. }
  341. static struct resource au1xxx_eth0_resources[] = {
  342. #if defined(CONFIG_SOC_AU1000)
  343. MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT),
  344. #elif defined(CONFIG_SOC_AU1100)
  345. MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT),
  346. #elif defined(CONFIG_SOC_AU1550)
  347. MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT),
  348. #elif defined(CONFIG_SOC_AU1500)
  349. MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT),
  350. #endif
  351. };
  352. static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
  353. .phy1_search_mac0 = 1,
  354. };
  355. static struct platform_device au1xxx_eth0_device = {
  356. .name = "au1000-eth",
  357. .id = 0,
  358. .num_resources = ARRAY_SIZE(au1xxx_eth0_resources),
  359. .resource = au1xxx_eth0_resources,
  360. .dev.platform_data = &au1xxx_eth0_platform_data,
  361. };
  362. #ifndef CONFIG_SOC_AU1100
  363. static struct resource au1xxx_eth1_resources[] = {
  364. #if defined(CONFIG_SOC_AU1000)
  365. MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT),
  366. #elif defined(CONFIG_SOC_AU1550)
  367. MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT),
  368. #elif defined(CONFIG_SOC_AU1500)
  369. MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT),
  370. #endif
  371. };
  372. static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
  373. .phy1_search_mac0 = 1,
  374. };
  375. static struct platform_device au1xxx_eth1_device = {
  376. .name = "au1000-eth",
  377. .id = 1,
  378. .num_resources = ARRAY_SIZE(au1xxx_eth1_resources),
  379. .resource = au1xxx_eth1_resources,
  380. .dev.platform_data = &au1xxx_eth1_platform_data,
  381. };
  382. #endif
  383. void __init au1xxx_override_eth_cfg(unsigned int port,
  384. struct au1000_eth_platform_data *eth_data)
  385. {
  386. if (!eth_data || port > 1)
  387. return;
  388. if (port == 0)
  389. memcpy(&au1xxx_eth0_platform_data, eth_data,
  390. sizeof(struct au1000_eth_platform_data));
  391. #ifndef CONFIG_SOC_AU1100
  392. else
  393. memcpy(&au1xxx_eth1_platform_data, eth_data,
  394. sizeof(struct au1000_eth_platform_data));
  395. #endif
  396. }
  397. static struct platform_device *au1xxx_platform_devices[] __initdata = {
  398. &au1xx0_uart_device,
  399. &au1xxx_usb_ohci_device,
  400. #ifdef CONFIG_FB_AU1100
  401. &au1100_lcd_device,
  402. #endif
  403. #ifdef CONFIG_SOC_AU1200
  404. &au1xxx_usb_ehci_device,
  405. &au1xxx_usb_gdt_device,
  406. &au1xxx_usb_otg_device,
  407. &au1200_lcd_device,
  408. &au1200_mmc0_device,
  409. #ifndef CONFIG_MIPS_DB1200
  410. &au1200_mmc1_device,
  411. #endif
  412. #endif
  413. #ifdef SMBUS_PSC_BASE
  414. &pbdb_smbus_device,
  415. #endif
  416. &au1xxx_eth0_device,
  417. };
  418. static int __init au1xxx_platform_init(void)
  419. {
  420. unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
  421. int err, i;
  422. unsigned char ethaddr[6];
  423. /* Fill up uartclk. */
  424. for (i = 0; au1x00_uart_data[i].flags; i++)
  425. au1x00_uart_data[i].uartclk = uartclk;
  426. /* use firmware-provided mac addr if available and necessary */
  427. i = prom_get_ethernet_addr(ethaddr);
  428. if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
  429. memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
  430. err = platform_add_devices(au1xxx_platform_devices,
  431. ARRAY_SIZE(au1xxx_platform_devices));
  432. #ifndef CONFIG_SOC_AU1100
  433. ethaddr[5] += 1; /* next addr for 2nd MAC */
  434. if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
  435. memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
  436. /* Register second MAC if enabled in pinfunc */
  437. if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
  438. err = platform_device_register(&au1xxx_eth1_device);
  439. #endif
  440. return err;
  441. }
  442. arch_initcall(au1xxx_platform_init);