ste_dma40.h 6.1 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2007-2010
  3. * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
  4. * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
  5. * License terms: GNU General Public License (GPL) version 2
  6. */
  7. #ifndef STE_DMA40_H
  8. #define STE_DMA40_H
  9. #include <linux/dmaengine.h>
  10. #include <linux/workqueue.h>
  11. #include <linux/interrupt.h>
  12. /* dev types for memcpy */
  13. #define STEDMA40_DEV_DST_MEMORY (-1)
  14. #define STEDMA40_DEV_SRC_MEMORY (-1)
  15. enum stedma40_mode {
  16. STEDMA40_MODE_LOGICAL = 0,
  17. STEDMA40_MODE_PHYSICAL,
  18. STEDMA40_MODE_OPERATION,
  19. };
  20. enum stedma40_mode_opt {
  21. STEDMA40_PCHAN_BASIC_MODE = 0,
  22. STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
  23. STEDMA40_PCHAN_MODULO_MODE,
  24. STEDMA40_PCHAN_DOUBLE_DST_MODE,
  25. STEDMA40_LCHAN_SRC_PHY_DST_LOG,
  26. STEDMA40_LCHAN_SRC_LOG_DST_PHY,
  27. };
  28. #define STEDMA40_ESIZE_8_BIT 0x0
  29. #define STEDMA40_ESIZE_16_BIT 0x1
  30. #define STEDMA40_ESIZE_32_BIT 0x2
  31. #define STEDMA40_ESIZE_64_BIT 0x3
  32. /* The value 4 indicates that PEN-reg shall be set to 0 */
  33. #define STEDMA40_PSIZE_PHY_1 0x4
  34. #define STEDMA40_PSIZE_PHY_2 0x0
  35. #define STEDMA40_PSIZE_PHY_4 0x1
  36. #define STEDMA40_PSIZE_PHY_8 0x2
  37. #define STEDMA40_PSIZE_PHY_16 0x3
  38. /*
  39. * The number of elements differ in logical and
  40. * physical mode
  41. */
  42. #define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
  43. #define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
  44. #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
  45. #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
  46. /* Maximum number of possible physical channels */
  47. #define STEDMA40_MAX_PHYS 32
  48. enum stedma40_flow_ctrl {
  49. STEDMA40_NO_FLOW_CTRL,
  50. STEDMA40_FLOW_CTRL,
  51. };
  52. enum stedma40_periph_data_width {
  53. STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
  54. STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
  55. STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
  56. STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
  57. };
  58. enum stedma40_xfer_dir {
  59. STEDMA40_MEM_TO_MEM = 1,
  60. STEDMA40_MEM_TO_PERIPH,
  61. STEDMA40_PERIPH_TO_MEM,
  62. STEDMA40_PERIPH_TO_PERIPH
  63. };
  64. /**
  65. * struct stedma40_chan_cfg - dst/src channel configuration
  66. *
  67. * @big_endian: true if the src/dst should be read as big endian
  68. * @data_width: Data width of the src/dst hardware
  69. * @p_size: Burst size
  70. * @flow_ctrl: Flow control on/off.
  71. */
  72. struct stedma40_half_channel_info {
  73. bool big_endian;
  74. enum stedma40_periph_data_width data_width;
  75. int psize;
  76. enum stedma40_flow_ctrl flow_ctrl;
  77. };
  78. /**
  79. * struct stedma40_chan_cfg - Structure to be filled by client drivers.
  80. *
  81. * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
  82. * @high_priority: true if high-priority
  83. * @mode: channel mode: physical, logical, or operation
  84. * @mode_opt: options for the chosen channel mode
  85. * @src_dev_type: Src device type
  86. * @dst_dev_type: Dst device type
  87. * @src_info: Parameters for dst half channel
  88. * @dst_info: Parameters for dst half channel
  89. *
  90. *
  91. * This structure has to be filled by the client drivers.
  92. * It is recommended to do all dma configurations for clients in the machine.
  93. *
  94. */
  95. struct stedma40_chan_cfg {
  96. enum stedma40_xfer_dir dir;
  97. bool high_priority;
  98. enum stedma40_mode mode;
  99. enum stedma40_mode_opt mode_opt;
  100. int src_dev_type;
  101. int dst_dev_type;
  102. struct stedma40_half_channel_info src_info;
  103. struct stedma40_half_channel_info dst_info;
  104. };
  105. /**
  106. * struct stedma40_platform_data - Configuration struct for the dma device.
  107. *
  108. * @dev_len: length of dev_tx and dev_rx
  109. * @dev_tx: mapping between destination event line and io address
  110. * @dev_rx: mapping between source event line and io address
  111. * @memcpy: list of memcpy event lines
  112. * @memcpy_len: length of memcpy
  113. * @memcpy_conf_phy: default configuration of physical channel memcpy
  114. * @memcpy_conf_log: default configuration of logical channel memcpy
  115. * @disabled_channels: A vector, ending with -1, that marks physical channels
  116. * that are for different reasons not available for the driver.
  117. */
  118. struct stedma40_platform_data {
  119. u32 dev_len;
  120. const dma_addr_t *dev_tx;
  121. const dma_addr_t *dev_rx;
  122. int *memcpy;
  123. u32 memcpy_len;
  124. struct stedma40_chan_cfg *memcpy_conf_phy;
  125. struct stedma40_chan_cfg *memcpy_conf_log;
  126. int disabled_channels[STEDMA40_MAX_PHYS];
  127. };
  128. #ifdef CONFIG_STE_DMA40
  129. /**
  130. * stedma40_filter() - Provides stedma40_chan_cfg to the
  131. * ste_dma40 dma driver via the dmaengine framework.
  132. * does some checking of what's provided.
  133. *
  134. * Never directly called by client. It used by dmaengine.
  135. * @chan: dmaengine handle.
  136. * @data: Must be of type: struct stedma40_chan_cfg and is
  137. * the configuration of the framework.
  138. *
  139. *
  140. */
  141. bool stedma40_filter(struct dma_chan *chan, void *data);
  142. /**
  143. * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
  144. * scattergatter lists.
  145. *
  146. * @chan: dmaengine handle
  147. * @sgl_dst: Destination scatter list
  148. * @sgl_src: Source scatter list
  149. * @sgl_len: The length of each scatterlist. Both lists must be of equal length
  150. * and each element must match the corresponding element in the other scatter
  151. * list.
  152. * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
  153. */
  154. struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
  155. struct scatterlist *sgl_dst,
  156. struct scatterlist *sgl_src,
  157. unsigned int sgl_len,
  158. unsigned long flags);
  159. /**
  160. * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
  161. * (=device)
  162. *
  163. * @chan: dmaengine handle
  164. * @addr: source or destination physicall address.
  165. * @size: bytes to transfer
  166. * @direction: direction of transfer
  167. * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
  168. */
  169. static inline struct
  170. dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
  171. dma_addr_t addr,
  172. unsigned int size,
  173. enum dma_data_direction direction,
  174. unsigned long flags)
  175. {
  176. struct scatterlist sg;
  177. sg_init_table(&sg, 1);
  178. sg.dma_address = addr;
  179. sg.length = size;
  180. return chan->device->device_prep_slave_sg(chan, &sg, 1,
  181. direction, flags);
  182. }
  183. #else
  184. static inline bool stedma40_filter(struct dma_chan *chan, void *data)
  185. {
  186. return false;
  187. }
  188. static inline struct
  189. dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
  190. dma_addr_t addr,
  191. unsigned int size,
  192. enum dma_data_direction direction,
  193. unsigned long flags)
  194. {
  195. return NULL;
  196. }
  197. #endif
  198. #endif