cache-l2x0.c 8.0 KB

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  1. /*
  2. * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
  3. *
  4. * Copyright (C) 2007 ARM Limited
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/io.h>
  22. #include <asm/cacheflush.h>
  23. #include <asm/hardware/cache-l2x0.h>
  24. #define CACHE_LINE_SIZE 32
  25. static void __iomem *l2x0_base;
  26. static DEFINE_SPINLOCK(l2x0_lock);
  27. static uint32_t l2x0_way_mask; /* Bitmask of active ways */
  28. static uint32_t l2x0_size;
  29. static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
  30. {
  31. /* wait for cache operation by line or way to complete */
  32. while (readl_relaxed(reg) & mask)
  33. ;
  34. }
  35. #ifdef CONFIG_CACHE_PL310
  36. static inline void cache_wait(void __iomem *reg, unsigned long mask)
  37. {
  38. /* cache operations by line are atomic on PL310 */
  39. }
  40. #else
  41. #define cache_wait cache_wait_way
  42. #endif
  43. static inline void cache_sync(void)
  44. {
  45. void __iomem *base = l2x0_base;
  46. writel_relaxed(0, base + L2X0_CACHE_SYNC);
  47. cache_wait(base + L2X0_CACHE_SYNC, 1);
  48. }
  49. static inline void l2x0_clean_line(unsigned long addr)
  50. {
  51. void __iomem *base = l2x0_base;
  52. cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
  53. writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
  54. }
  55. static inline void l2x0_inv_line(unsigned long addr)
  56. {
  57. void __iomem *base = l2x0_base;
  58. cache_wait(base + L2X0_INV_LINE_PA, 1);
  59. writel_relaxed(addr, base + L2X0_INV_LINE_PA);
  60. }
  61. #ifdef CONFIG_PL310_ERRATA_588369
  62. static void debug_writel(unsigned long val)
  63. {
  64. extern void omap_smc1(u32 fn, u32 arg);
  65. /*
  66. * Texas Instrument secure monitor api to modify the
  67. * PL310 Debug Control Register.
  68. */
  69. omap_smc1(0x100, val);
  70. }
  71. static inline void l2x0_flush_line(unsigned long addr)
  72. {
  73. void __iomem *base = l2x0_base;
  74. /* Clean by PA followed by Invalidate by PA */
  75. cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
  76. writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
  77. cache_wait(base + L2X0_INV_LINE_PA, 1);
  78. writel_relaxed(addr, base + L2X0_INV_LINE_PA);
  79. }
  80. #else
  81. /* Optimised out for non-errata case */
  82. static inline void debug_writel(unsigned long val)
  83. {
  84. }
  85. static inline void l2x0_flush_line(unsigned long addr)
  86. {
  87. void __iomem *base = l2x0_base;
  88. cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
  89. writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
  90. }
  91. #endif
  92. static void l2x0_cache_sync(void)
  93. {
  94. unsigned long flags;
  95. spin_lock_irqsave(&l2x0_lock, flags);
  96. cache_sync();
  97. spin_unlock_irqrestore(&l2x0_lock, flags);
  98. }
  99. static void l2x0_flush_all(void)
  100. {
  101. unsigned long flags;
  102. /* clean all ways */
  103. spin_lock_irqsave(&l2x0_lock, flags);
  104. writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
  105. cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
  106. cache_sync();
  107. spin_unlock_irqrestore(&l2x0_lock, flags);
  108. }
  109. static void l2x0_clean_all(void)
  110. {
  111. unsigned long flags;
  112. /* clean all ways */
  113. spin_lock_irqsave(&l2x0_lock, flags);
  114. writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
  115. cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
  116. cache_sync();
  117. spin_unlock_irqrestore(&l2x0_lock, flags);
  118. }
  119. static void l2x0_inv_all(void)
  120. {
  121. unsigned long flags;
  122. /* invalidate all ways */
  123. spin_lock_irqsave(&l2x0_lock, flags);
  124. /* Invalidating when L2 is enabled is a nono */
  125. BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
  126. writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
  127. cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
  128. cache_sync();
  129. spin_unlock_irqrestore(&l2x0_lock, flags);
  130. }
  131. static void l2x0_inv_range(unsigned long start, unsigned long end)
  132. {
  133. void __iomem *base = l2x0_base;
  134. unsigned long flags;
  135. spin_lock_irqsave(&l2x0_lock, flags);
  136. if (start & (CACHE_LINE_SIZE - 1)) {
  137. start &= ~(CACHE_LINE_SIZE - 1);
  138. debug_writel(0x03);
  139. l2x0_flush_line(start);
  140. debug_writel(0x00);
  141. start += CACHE_LINE_SIZE;
  142. }
  143. if (end & (CACHE_LINE_SIZE - 1)) {
  144. end &= ~(CACHE_LINE_SIZE - 1);
  145. debug_writel(0x03);
  146. l2x0_flush_line(end);
  147. debug_writel(0x00);
  148. }
  149. while (start < end) {
  150. unsigned long blk_end = start + min(end - start, 4096UL);
  151. while (start < blk_end) {
  152. l2x0_inv_line(start);
  153. start += CACHE_LINE_SIZE;
  154. }
  155. if (blk_end < end) {
  156. spin_unlock_irqrestore(&l2x0_lock, flags);
  157. spin_lock_irqsave(&l2x0_lock, flags);
  158. }
  159. }
  160. cache_wait(base + L2X0_INV_LINE_PA, 1);
  161. cache_sync();
  162. spin_unlock_irqrestore(&l2x0_lock, flags);
  163. }
  164. static void l2x0_clean_range(unsigned long start, unsigned long end)
  165. {
  166. void __iomem *base = l2x0_base;
  167. unsigned long flags;
  168. if ((end - start) >= l2x0_size) {
  169. l2x0_clean_all();
  170. return;
  171. }
  172. spin_lock_irqsave(&l2x0_lock, flags);
  173. start &= ~(CACHE_LINE_SIZE - 1);
  174. while (start < end) {
  175. unsigned long blk_end = start + min(end - start, 4096UL);
  176. while (start < blk_end) {
  177. l2x0_clean_line(start);
  178. start += CACHE_LINE_SIZE;
  179. }
  180. if (blk_end < end) {
  181. spin_unlock_irqrestore(&l2x0_lock, flags);
  182. spin_lock_irqsave(&l2x0_lock, flags);
  183. }
  184. }
  185. cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
  186. cache_sync();
  187. spin_unlock_irqrestore(&l2x0_lock, flags);
  188. }
  189. static void l2x0_flush_range(unsigned long start, unsigned long end)
  190. {
  191. void __iomem *base = l2x0_base;
  192. unsigned long flags;
  193. if ((end - start) >= l2x0_size) {
  194. l2x0_flush_all();
  195. return;
  196. }
  197. spin_lock_irqsave(&l2x0_lock, flags);
  198. start &= ~(CACHE_LINE_SIZE - 1);
  199. while (start < end) {
  200. unsigned long blk_end = start + min(end - start, 4096UL);
  201. debug_writel(0x03);
  202. while (start < blk_end) {
  203. l2x0_flush_line(start);
  204. start += CACHE_LINE_SIZE;
  205. }
  206. debug_writel(0x00);
  207. if (blk_end < end) {
  208. spin_unlock_irqrestore(&l2x0_lock, flags);
  209. spin_lock_irqsave(&l2x0_lock, flags);
  210. }
  211. }
  212. cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
  213. cache_sync();
  214. spin_unlock_irqrestore(&l2x0_lock, flags);
  215. }
  216. static void l2x0_disable(void)
  217. {
  218. unsigned long flags;
  219. spin_lock_irqsave(&l2x0_lock, flags);
  220. writel(0, l2x0_base + L2X0_CTRL);
  221. spin_unlock_irqrestore(&l2x0_lock, flags);
  222. }
  223. void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
  224. {
  225. __u32 aux;
  226. __u32 cache_id;
  227. __u32 way_size = 0;
  228. int ways;
  229. const char *type;
  230. l2x0_base = base;
  231. cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
  232. aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  233. aux &= aux_mask;
  234. aux |= aux_val;
  235. /* Determine the number of ways */
  236. switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
  237. case L2X0_CACHE_ID_PART_L310:
  238. if (aux & (1 << 16))
  239. ways = 16;
  240. else
  241. ways = 8;
  242. type = "L310";
  243. break;
  244. case L2X0_CACHE_ID_PART_L210:
  245. ways = (aux >> 13) & 0xf;
  246. type = "L210";
  247. break;
  248. default:
  249. /* Assume unknown chips have 8 ways */
  250. ways = 8;
  251. type = "L2x0 series";
  252. break;
  253. }
  254. l2x0_way_mask = (1 << ways) - 1;
  255. /*
  256. * L2 cache Size = Way size * Number of ways
  257. */
  258. way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
  259. way_size = 1 << (way_size + 3);
  260. l2x0_size = ways * way_size * SZ_1K;
  261. /*
  262. * Check if l2x0 controller is already enabled.
  263. * If you are booting from non-secure mode
  264. * accessing the below registers will fault.
  265. */
  266. if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
  267. /* l2x0 controller is disabled */
  268. writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
  269. l2x0_inv_all();
  270. /* enable L2X0 */
  271. writel_relaxed(1, l2x0_base + L2X0_CTRL);
  272. }
  273. outer_cache.inv_range = l2x0_inv_range;
  274. outer_cache.clean_range = l2x0_clean_range;
  275. outer_cache.flush_range = l2x0_flush_range;
  276. outer_cache.sync = l2x0_cache_sync;
  277. outer_cache.flush_all = l2x0_flush_all;
  278. outer_cache.inv_all = l2x0_inv_all;
  279. outer_cache.disable = l2x0_disable;
  280. printk(KERN_INFO "%s cache controller enabled\n", type);
  281. printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
  282. ways, cache_id, aux, l2x0_size);
  283. }