devices.c 21 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <asm/pmu.h>
  7. #include <mach/udc.h>
  8. #include <mach/pxa3xx-u2d.h>
  9. #include <mach/pxafb.h>
  10. #include <mach/mmc.h>
  11. #include <mach/irda.h>
  12. #include <mach/ohci.h>
  13. #include <plat/pxa27x_keypad.h>
  14. #include <mach/pxa2xx_spi.h>
  15. #include <mach/camera.h>
  16. #include <mach/audio.h>
  17. #include <mach/hardware.h>
  18. #include <plat/i2c.h>
  19. #include <plat/pxa3xx_nand.h>
  20. #include "devices.h"
  21. #include "generic.h"
  22. void __init pxa_register_device(struct platform_device *dev, void *data)
  23. {
  24. int ret;
  25. dev->dev.platform_data = data;
  26. ret = platform_device_register(dev);
  27. if (ret)
  28. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  29. }
  30. static struct resource pxa_resource_pmu = {
  31. .start = IRQ_PMU,
  32. .end = IRQ_PMU,
  33. .flags = IORESOURCE_IRQ,
  34. };
  35. struct platform_device pxa_device_pmu = {
  36. .name = "arm-pmu",
  37. .id = ARM_PMU_DEVICE_CPU,
  38. .resource = &pxa_resource_pmu,
  39. .num_resources = 1,
  40. };
  41. static struct resource pxamci_resources[] = {
  42. [0] = {
  43. .start = 0x41100000,
  44. .end = 0x41100fff,
  45. .flags = IORESOURCE_MEM,
  46. },
  47. [1] = {
  48. .start = IRQ_MMC,
  49. .end = IRQ_MMC,
  50. .flags = IORESOURCE_IRQ,
  51. },
  52. [2] = {
  53. .start = 21,
  54. .end = 21,
  55. .flags = IORESOURCE_DMA,
  56. },
  57. [3] = {
  58. .start = 22,
  59. .end = 22,
  60. .flags = IORESOURCE_DMA,
  61. },
  62. };
  63. static u64 pxamci_dmamask = 0xffffffffUL;
  64. struct platform_device pxa_device_mci = {
  65. .name = "pxa2xx-mci",
  66. .id = 0,
  67. .dev = {
  68. .dma_mask = &pxamci_dmamask,
  69. .coherent_dma_mask = 0xffffffff,
  70. },
  71. .num_resources = ARRAY_SIZE(pxamci_resources),
  72. .resource = pxamci_resources,
  73. };
  74. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  75. {
  76. pxa_register_device(&pxa_device_mci, info);
  77. }
  78. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  79. .gpio_pullup = -1,
  80. .gpio_vbus = -1,
  81. };
  82. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  83. {
  84. memcpy(&pxa_udc_info, info, sizeof *info);
  85. }
  86. static struct resource pxa2xx_udc_resources[] = {
  87. [0] = {
  88. .start = 0x40600000,
  89. .end = 0x4060ffff,
  90. .flags = IORESOURCE_MEM,
  91. },
  92. [1] = {
  93. .start = IRQ_USB,
  94. .end = IRQ_USB,
  95. .flags = IORESOURCE_IRQ,
  96. },
  97. };
  98. static u64 udc_dma_mask = ~(u32)0;
  99. struct platform_device pxa25x_device_udc = {
  100. .name = "pxa25x-udc",
  101. .id = -1,
  102. .resource = pxa2xx_udc_resources,
  103. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  104. .dev = {
  105. .platform_data = &pxa_udc_info,
  106. .dma_mask = &udc_dma_mask,
  107. }
  108. };
  109. struct platform_device pxa27x_device_udc = {
  110. .name = "pxa27x-udc",
  111. .id = -1,
  112. .resource = pxa2xx_udc_resources,
  113. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  114. .dev = {
  115. .platform_data = &pxa_udc_info,
  116. .dma_mask = &udc_dma_mask,
  117. }
  118. };
  119. #ifdef CONFIG_PXA3xx
  120. static struct resource pxa3xx_u2d_resources[] = {
  121. [0] = {
  122. .start = 0x54100000,
  123. .end = 0x54100fff,
  124. .flags = IORESOURCE_MEM,
  125. },
  126. [1] = {
  127. .start = IRQ_USB2,
  128. .end = IRQ_USB2,
  129. .flags = IORESOURCE_IRQ,
  130. },
  131. };
  132. struct platform_device pxa3xx_device_u2d = {
  133. .name = "pxa3xx-u2d",
  134. .id = -1,
  135. .resource = pxa3xx_u2d_resources,
  136. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  137. };
  138. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  139. {
  140. pxa_register_device(&pxa3xx_device_u2d, info);
  141. }
  142. #endif /* CONFIG_PXA3xx */
  143. static struct resource pxafb_resources[] = {
  144. [0] = {
  145. .start = 0x44000000,
  146. .end = 0x4400ffff,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. [1] = {
  150. .start = IRQ_LCD,
  151. .end = IRQ_LCD,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. };
  155. static u64 fb_dma_mask = ~(u64)0;
  156. struct platform_device pxa_device_fb = {
  157. .name = "pxa2xx-fb",
  158. .id = -1,
  159. .dev = {
  160. .dma_mask = &fb_dma_mask,
  161. .coherent_dma_mask = 0xffffffff,
  162. },
  163. .num_resources = ARRAY_SIZE(pxafb_resources),
  164. .resource = pxafb_resources,
  165. };
  166. void __init set_pxa_fb_info(struct pxafb_mach_info *info)
  167. {
  168. pxa_register_device(&pxa_device_fb, info);
  169. }
  170. void __init set_pxa_fb_parent(struct device *parent_dev)
  171. {
  172. pxa_device_fb.dev.parent = parent_dev;
  173. }
  174. static struct resource pxa_resource_ffuart[] = {
  175. {
  176. .start = 0x40100000,
  177. .end = 0x40100023,
  178. .flags = IORESOURCE_MEM,
  179. }, {
  180. .start = IRQ_FFUART,
  181. .end = IRQ_FFUART,
  182. .flags = IORESOURCE_IRQ,
  183. }
  184. };
  185. struct platform_device pxa_device_ffuart = {
  186. .name = "pxa2xx-uart",
  187. .id = 0,
  188. .resource = pxa_resource_ffuart,
  189. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  190. };
  191. void __init pxa_set_ffuart_info(void *info)
  192. {
  193. pxa_register_device(&pxa_device_ffuart, info);
  194. }
  195. static struct resource pxa_resource_btuart[] = {
  196. {
  197. .start = 0x40200000,
  198. .end = 0x40200023,
  199. .flags = IORESOURCE_MEM,
  200. }, {
  201. .start = IRQ_BTUART,
  202. .end = IRQ_BTUART,
  203. .flags = IORESOURCE_IRQ,
  204. }
  205. };
  206. struct platform_device pxa_device_btuart = {
  207. .name = "pxa2xx-uart",
  208. .id = 1,
  209. .resource = pxa_resource_btuart,
  210. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  211. };
  212. void __init pxa_set_btuart_info(void *info)
  213. {
  214. pxa_register_device(&pxa_device_btuart, info);
  215. }
  216. static struct resource pxa_resource_stuart[] = {
  217. {
  218. .start = 0x40700000,
  219. .end = 0x40700023,
  220. .flags = IORESOURCE_MEM,
  221. }, {
  222. .start = IRQ_STUART,
  223. .end = IRQ_STUART,
  224. .flags = IORESOURCE_IRQ,
  225. }
  226. };
  227. struct platform_device pxa_device_stuart = {
  228. .name = "pxa2xx-uart",
  229. .id = 2,
  230. .resource = pxa_resource_stuart,
  231. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  232. };
  233. void __init pxa_set_stuart_info(void *info)
  234. {
  235. pxa_register_device(&pxa_device_stuart, info);
  236. }
  237. static struct resource pxa_resource_hwuart[] = {
  238. {
  239. .start = 0x41600000,
  240. .end = 0x4160002F,
  241. .flags = IORESOURCE_MEM,
  242. }, {
  243. .start = IRQ_HWUART,
  244. .end = IRQ_HWUART,
  245. .flags = IORESOURCE_IRQ,
  246. }
  247. };
  248. struct platform_device pxa_device_hwuart = {
  249. .name = "pxa2xx-uart",
  250. .id = 3,
  251. .resource = pxa_resource_hwuart,
  252. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  253. };
  254. void __init pxa_set_hwuart_info(void *info)
  255. {
  256. if (cpu_is_pxa255())
  257. pxa_register_device(&pxa_device_hwuart, info);
  258. else
  259. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  260. }
  261. static struct resource pxai2c_resources[] = {
  262. {
  263. .start = 0x40301680,
  264. .end = 0x403016a3,
  265. .flags = IORESOURCE_MEM,
  266. }, {
  267. .start = IRQ_I2C,
  268. .end = IRQ_I2C,
  269. .flags = IORESOURCE_IRQ,
  270. },
  271. };
  272. struct platform_device pxa_device_i2c = {
  273. .name = "pxa2xx-i2c",
  274. .id = 0,
  275. .resource = pxai2c_resources,
  276. .num_resources = ARRAY_SIZE(pxai2c_resources),
  277. };
  278. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  279. {
  280. pxa_register_device(&pxa_device_i2c, info);
  281. }
  282. #ifdef CONFIG_PXA27x
  283. static struct resource pxa27x_resources_i2c_power[] = {
  284. {
  285. .start = 0x40f00180,
  286. .end = 0x40f001a3,
  287. .flags = IORESOURCE_MEM,
  288. }, {
  289. .start = IRQ_PWRI2C,
  290. .end = IRQ_PWRI2C,
  291. .flags = IORESOURCE_IRQ,
  292. },
  293. };
  294. struct platform_device pxa27x_device_i2c_power = {
  295. .name = "pxa2xx-i2c",
  296. .id = 1,
  297. .resource = pxa27x_resources_i2c_power,
  298. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  299. };
  300. #endif
  301. #ifdef CONFIG_PXA3xx
  302. static struct resource pxa3xx_resources_i2c_power[] = {
  303. {
  304. .start = 0x40f500c0,
  305. .end = 0x40f500d3,
  306. .flags = IORESOURCE_MEM,
  307. }, {
  308. .start = IRQ_PWRI2C,
  309. .end = IRQ_PWRI2C,
  310. .flags = IORESOURCE_IRQ,
  311. },
  312. };
  313. struct platform_device pxa3xx_device_i2c_power = {
  314. .name = "pxa3xx-pwri2c",
  315. .id = 1,
  316. .resource = pxa3xx_resources_i2c_power,
  317. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  318. };
  319. #endif
  320. static struct resource pxai2s_resources[] = {
  321. {
  322. .start = 0x40400000,
  323. .end = 0x40400083,
  324. .flags = IORESOURCE_MEM,
  325. }, {
  326. .start = IRQ_I2S,
  327. .end = IRQ_I2S,
  328. .flags = IORESOURCE_IRQ,
  329. },
  330. };
  331. struct platform_device pxa_device_i2s = {
  332. .name = "pxa2xx-i2s",
  333. .id = -1,
  334. .resource = pxai2s_resources,
  335. .num_resources = ARRAY_SIZE(pxai2s_resources),
  336. };
  337. struct platform_device pxa_device_asoc_ssp1 = {
  338. .name = "pxa-ssp-dai",
  339. .id = 0,
  340. };
  341. struct platform_device pxa_device_asoc_ssp2= {
  342. .name = "pxa-ssp-dai",
  343. .id = 1,
  344. };
  345. struct platform_device pxa_device_asoc_ssp3 = {
  346. .name = "pxa-ssp-dai",
  347. .id = 2,
  348. };
  349. struct platform_device pxa_device_asoc_ssp4 = {
  350. .name = "pxa-ssp-dai",
  351. .id = 3,
  352. };
  353. struct platform_device pxa_device_asoc_platform = {
  354. .name = "pxa-pcm-audio",
  355. .id = -1,
  356. };
  357. static u64 pxaficp_dmamask = ~(u32)0;
  358. struct platform_device pxa_device_ficp = {
  359. .name = "pxa2xx-ir",
  360. .id = -1,
  361. .dev = {
  362. .dma_mask = &pxaficp_dmamask,
  363. .coherent_dma_mask = 0xffffffff,
  364. },
  365. };
  366. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  367. {
  368. pxa_register_device(&pxa_device_ficp, info);
  369. }
  370. static struct resource pxa_rtc_resources[] = {
  371. [0] = {
  372. .start = 0x40900000,
  373. .end = 0x40900000 + 0x3b,
  374. .flags = IORESOURCE_MEM,
  375. },
  376. [1] = {
  377. .start = IRQ_RTC1Hz,
  378. .end = IRQ_RTC1Hz,
  379. .flags = IORESOURCE_IRQ,
  380. },
  381. [2] = {
  382. .start = IRQ_RTCAlrm,
  383. .end = IRQ_RTCAlrm,
  384. .flags = IORESOURCE_IRQ,
  385. },
  386. };
  387. struct platform_device sa1100_device_rtc = {
  388. .name = "sa1100-rtc",
  389. .id = -1,
  390. };
  391. struct platform_device pxa_device_rtc = {
  392. .name = "pxa-rtc",
  393. .id = -1,
  394. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  395. .resource = pxa_rtc_resources,
  396. };
  397. static struct resource pxa_ac97_resources[] = {
  398. [0] = {
  399. .start = 0x40500000,
  400. .end = 0x40500000 + 0xfff,
  401. .flags = IORESOURCE_MEM,
  402. },
  403. [1] = {
  404. .start = IRQ_AC97,
  405. .end = IRQ_AC97,
  406. .flags = IORESOURCE_IRQ,
  407. },
  408. };
  409. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  410. struct platform_device pxa_device_ac97 = {
  411. .name = "pxa2xx-ac97",
  412. .id = -1,
  413. .dev = {
  414. .dma_mask = &pxa_ac97_dmamask,
  415. .coherent_dma_mask = 0xffffffff,
  416. },
  417. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  418. .resource = pxa_ac97_resources,
  419. };
  420. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  421. {
  422. pxa_register_device(&pxa_device_ac97, ops);
  423. }
  424. #ifdef CONFIG_PXA25x
  425. static struct resource pxa25x_resource_pwm0[] = {
  426. [0] = {
  427. .start = 0x40b00000,
  428. .end = 0x40b0000f,
  429. .flags = IORESOURCE_MEM,
  430. },
  431. };
  432. struct platform_device pxa25x_device_pwm0 = {
  433. .name = "pxa25x-pwm",
  434. .id = 0,
  435. .resource = pxa25x_resource_pwm0,
  436. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  437. };
  438. static struct resource pxa25x_resource_pwm1[] = {
  439. [0] = {
  440. .start = 0x40c00000,
  441. .end = 0x40c0000f,
  442. .flags = IORESOURCE_MEM,
  443. },
  444. };
  445. struct platform_device pxa25x_device_pwm1 = {
  446. .name = "pxa25x-pwm",
  447. .id = 1,
  448. .resource = pxa25x_resource_pwm1,
  449. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  450. };
  451. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  452. static struct resource pxa25x_resource_ssp[] = {
  453. [0] = {
  454. .start = 0x41000000,
  455. .end = 0x4100001f,
  456. .flags = IORESOURCE_MEM,
  457. },
  458. [1] = {
  459. .start = IRQ_SSP,
  460. .end = IRQ_SSP,
  461. .flags = IORESOURCE_IRQ,
  462. },
  463. [2] = {
  464. /* DRCMR for RX */
  465. .start = 13,
  466. .end = 13,
  467. .flags = IORESOURCE_DMA,
  468. },
  469. [3] = {
  470. /* DRCMR for TX */
  471. .start = 14,
  472. .end = 14,
  473. .flags = IORESOURCE_DMA,
  474. },
  475. };
  476. struct platform_device pxa25x_device_ssp = {
  477. .name = "pxa25x-ssp",
  478. .id = 0,
  479. .dev = {
  480. .dma_mask = &pxa25x_ssp_dma_mask,
  481. .coherent_dma_mask = DMA_BIT_MASK(32),
  482. },
  483. .resource = pxa25x_resource_ssp,
  484. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  485. };
  486. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  487. static struct resource pxa25x_resource_nssp[] = {
  488. [0] = {
  489. .start = 0x41400000,
  490. .end = 0x4140002f,
  491. .flags = IORESOURCE_MEM,
  492. },
  493. [1] = {
  494. .start = IRQ_NSSP,
  495. .end = IRQ_NSSP,
  496. .flags = IORESOURCE_IRQ,
  497. },
  498. [2] = {
  499. /* DRCMR for RX */
  500. .start = 15,
  501. .end = 15,
  502. .flags = IORESOURCE_DMA,
  503. },
  504. [3] = {
  505. /* DRCMR for TX */
  506. .start = 16,
  507. .end = 16,
  508. .flags = IORESOURCE_DMA,
  509. },
  510. };
  511. struct platform_device pxa25x_device_nssp = {
  512. .name = "pxa25x-nssp",
  513. .id = 1,
  514. .dev = {
  515. .dma_mask = &pxa25x_nssp_dma_mask,
  516. .coherent_dma_mask = DMA_BIT_MASK(32),
  517. },
  518. .resource = pxa25x_resource_nssp,
  519. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  520. };
  521. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  522. static struct resource pxa25x_resource_assp[] = {
  523. [0] = {
  524. .start = 0x41500000,
  525. .end = 0x4150002f,
  526. .flags = IORESOURCE_MEM,
  527. },
  528. [1] = {
  529. .start = IRQ_ASSP,
  530. .end = IRQ_ASSP,
  531. .flags = IORESOURCE_IRQ,
  532. },
  533. [2] = {
  534. /* DRCMR for RX */
  535. .start = 23,
  536. .end = 23,
  537. .flags = IORESOURCE_DMA,
  538. },
  539. [3] = {
  540. /* DRCMR for TX */
  541. .start = 24,
  542. .end = 24,
  543. .flags = IORESOURCE_DMA,
  544. },
  545. };
  546. struct platform_device pxa25x_device_assp = {
  547. /* ASSP is basically equivalent to NSSP */
  548. .name = "pxa25x-nssp",
  549. .id = 2,
  550. .dev = {
  551. .dma_mask = &pxa25x_assp_dma_mask,
  552. .coherent_dma_mask = DMA_BIT_MASK(32),
  553. },
  554. .resource = pxa25x_resource_assp,
  555. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  556. };
  557. #endif /* CONFIG_PXA25x */
  558. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  559. static struct resource pxa27x_resource_keypad[] = {
  560. [0] = {
  561. .start = 0x41500000,
  562. .end = 0x4150004c,
  563. .flags = IORESOURCE_MEM,
  564. },
  565. [1] = {
  566. .start = IRQ_KEYPAD,
  567. .end = IRQ_KEYPAD,
  568. .flags = IORESOURCE_IRQ,
  569. },
  570. };
  571. struct platform_device pxa27x_device_keypad = {
  572. .name = "pxa27x-keypad",
  573. .id = -1,
  574. .resource = pxa27x_resource_keypad,
  575. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  576. };
  577. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  578. {
  579. pxa_register_device(&pxa27x_device_keypad, info);
  580. }
  581. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  582. static struct resource pxa27x_resource_ohci[] = {
  583. [0] = {
  584. .start = 0x4C000000,
  585. .end = 0x4C00ff6f,
  586. .flags = IORESOURCE_MEM,
  587. },
  588. [1] = {
  589. .start = IRQ_USBH1,
  590. .end = IRQ_USBH1,
  591. .flags = IORESOURCE_IRQ,
  592. },
  593. };
  594. struct platform_device pxa27x_device_ohci = {
  595. .name = "pxa27x-ohci",
  596. .id = -1,
  597. .dev = {
  598. .dma_mask = &pxa27x_ohci_dma_mask,
  599. .coherent_dma_mask = DMA_BIT_MASK(32),
  600. },
  601. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  602. .resource = pxa27x_resource_ohci,
  603. };
  604. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  605. {
  606. pxa_register_device(&pxa27x_device_ohci, info);
  607. }
  608. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  609. static struct resource pxa27x_resource_ssp1[] = {
  610. [0] = {
  611. .start = 0x41000000,
  612. .end = 0x4100003f,
  613. .flags = IORESOURCE_MEM,
  614. },
  615. [1] = {
  616. .start = IRQ_SSP,
  617. .end = IRQ_SSP,
  618. .flags = IORESOURCE_IRQ,
  619. },
  620. [2] = {
  621. /* DRCMR for RX */
  622. .start = 13,
  623. .end = 13,
  624. .flags = IORESOURCE_DMA,
  625. },
  626. [3] = {
  627. /* DRCMR for TX */
  628. .start = 14,
  629. .end = 14,
  630. .flags = IORESOURCE_DMA,
  631. },
  632. };
  633. struct platform_device pxa27x_device_ssp1 = {
  634. .name = "pxa27x-ssp",
  635. .id = 0,
  636. .dev = {
  637. .dma_mask = &pxa27x_ssp1_dma_mask,
  638. .coherent_dma_mask = DMA_BIT_MASK(32),
  639. },
  640. .resource = pxa27x_resource_ssp1,
  641. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  642. };
  643. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  644. static struct resource pxa27x_resource_ssp2[] = {
  645. [0] = {
  646. .start = 0x41700000,
  647. .end = 0x4170003f,
  648. .flags = IORESOURCE_MEM,
  649. },
  650. [1] = {
  651. .start = IRQ_SSP2,
  652. .end = IRQ_SSP2,
  653. .flags = IORESOURCE_IRQ,
  654. },
  655. [2] = {
  656. /* DRCMR for RX */
  657. .start = 15,
  658. .end = 15,
  659. .flags = IORESOURCE_DMA,
  660. },
  661. [3] = {
  662. /* DRCMR for TX */
  663. .start = 16,
  664. .end = 16,
  665. .flags = IORESOURCE_DMA,
  666. },
  667. };
  668. struct platform_device pxa27x_device_ssp2 = {
  669. .name = "pxa27x-ssp",
  670. .id = 1,
  671. .dev = {
  672. .dma_mask = &pxa27x_ssp2_dma_mask,
  673. .coherent_dma_mask = DMA_BIT_MASK(32),
  674. },
  675. .resource = pxa27x_resource_ssp2,
  676. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  677. };
  678. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  679. static struct resource pxa27x_resource_ssp3[] = {
  680. [0] = {
  681. .start = 0x41900000,
  682. .end = 0x4190003f,
  683. .flags = IORESOURCE_MEM,
  684. },
  685. [1] = {
  686. .start = IRQ_SSP3,
  687. .end = IRQ_SSP3,
  688. .flags = IORESOURCE_IRQ,
  689. },
  690. [2] = {
  691. /* DRCMR for RX */
  692. .start = 66,
  693. .end = 66,
  694. .flags = IORESOURCE_DMA,
  695. },
  696. [3] = {
  697. /* DRCMR for TX */
  698. .start = 67,
  699. .end = 67,
  700. .flags = IORESOURCE_DMA,
  701. },
  702. };
  703. struct platform_device pxa27x_device_ssp3 = {
  704. .name = "pxa27x-ssp",
  705. .id = 2,
  706. .dev = {
  707. .dma_mask = &pxa27x_ssp3_dma_mask,
  708. .coherent_dma_mask = DMA_BIT_MASK(32),
  709. },
  710. .resource = pxa27x_resource_ssp3,
  711. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  712. };
  713. static struct resource pxa27x_resource_pwm0[] = {
  714. [0] = {
  715. .start = 0x40b00000,
  716. .end = 0x40b0001f,
  717. .flags = IORESOURCE_MEM,
  718. },
  719. };
  720. struct platform_device pxa27x_device_pwm0 = {
  721. .name = "pxa27x-pwm",
  722. .id = 0,
  723. .resource = pxa27x_resource_pwm0,
  724. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  725. };
  726. static struct resource pxa27x_resource_pwm1[] = {
  727. [0] = {
  728. .start = 0x40c00000,
  729. .end = 0x40c0001f,
  730. .flags = IORESOURCE_MEM,
  731. },
  732. };
  733. struct platform_device pxa27x_device_pwm1 = {
  734. .name = "pxa27x-pwm",
  735. .id = 1,
  736. .resource = pxa27x_resource_pwm1,
  737. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  738. };
  739. static struct resource pxa27x_resource_camera[] = {
  740. [0] = {
  741. .start = 0x50000000,
  742. .end = 0x50000fff,
  743. .flags = IORESOURCE_MEM,
  744. },
  745. [1] = {
  746. .start = IRQ_CAMERA,
  747. .end = IRQ_CAMERA,
  748. .flags = IORESOURCE_IRQ,
  749. },
  750. };
  751. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  752. static struct platform_device pxa27x_device_camera = {
  753. .name = "pxa27x-camera",
  754. .id = 0, /* This is used to put cameras on this interface */
  755. .dev = {
  756. .dma_mask = &pxa27x_dma_mask_camera,
  757. .coherent_dma_mask = 0xffffffff,
  758. },
  759. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  760. .resource = pxa27x_resource_camera,
  761. };
  762. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  763. {
  764. pxa_register_device(&pxa27x_device_camera, info);
  765. }
  766. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  767. #ifdef CONFIG_PXA3xx
  768. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  769. static struct resource pxa3xx_resource_ssp4[] = {
  770. [0] = {
  771. .start = 0x41a00000,
  772. .end = 0x41a0003f,
  773. .flags = IORESOURCE_MEM,
  774. },
  775. [1] = {
  776. .start = IRQ_SSP4,
  777. .end = IRQ_SSP4,
  778. .flags = IORESOURCE_IRQ,
  779. },
  780. [2] = {
  781. /* DRCMR for RX */
  782. .start = 2,
  783. .end = 2,
  784. .flags = IORESOURCE_DMA,
  785. },
  786. [3] = {
  787. /* DRCMR for TX */
  788. .start = 3,
  789. .end = 3,
  790. .flags = IORESOURCE_DMA,
  791. },
  792. };
  793. struct platform_device pxa3xx_device_ssp4 = {
  794. /* PXA3xx SSP is basically equivalent to PXA27x */
  795. .name = "pxa27x-ssp",
  796. .id = 3,
  797. .dev = {
  798. .dma_mask = &pxa3xx_ssp4_dma_mask,
  799. .coherent_dma_mask = DMA_BIT_MASK(32),
  800. },
  801. .resource = pxa3xx_resource_ssp4,
  802. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  803. };
  804. static struct resource pxa3xx_resources_mci2[] = {
  805. [0] = {
  806. .start = 0x42000000,
  807. .end = 0x42000fff,
  808. .flags = IORESOURCE_MEM,
  809. },
  810. [1] = {
  811. .start = IRQ_MMC2,
  812. .end = IRQ_MMC2,
  813. .flags = IORESOURCE_IRQ,
  814. },
  815. [2] = {
  816. .start = 93,
  817. .end = 93,
  818. .flags = IORESOURCE_DMA,
  819. },
  820. [3] = {
  821. .start = 94,
  822. .end = 94,
  823. .flags = IORESOURCE_DMA,
  824. },
  825. };
  826. struct platform_device pxa3xx_device_mci2 = {
  827. .name = "pxa2xx-mci",
  828. .id = 1,
  829. .dev = {
  830. .dma_mask = &pxamci_dmamask,
  831. .coherent_dma_mask = 0xffffffff,
  832. },
  833. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  834. .resource = pxa3xx_resources_mci2,
  835. };
  836. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  837. {
  838. pxa_register_device(&pxa3xx_device_mci2, info);
  839. }
  840. static struct resource pxa3xx_resources_mci3[] = {
  841. [0] = {
  842. .start = 0x42500000,
  843. .end = 0x42500fff,
  844. .flags = IORESOURCE_MEM,
  845. },
  846. [1] = {
  847. .start = IRQ_MMC3,
  848. .end = IRQ_MMC3,
  849. .flags = IORESOURCE_IRQ,
  850. },
  851. [2] = {
  852. .start = 100,
  853. .end = 100,
  854. .flags = IORESOURCE_DMA,
  855. },
  856. [3] = {
  857. .start = 101,
  858. .end = 101,
  859. .flags = IORESOURCE_DMA,
  860. },
  861. };
  862. struct platform_device pxa3xx_device_mci3 = {
  863. .name = "pxa2xx-mci",
  864. .id = 2,
  865. .dev = {
  866. .dma_mask = &pxamci_dmamask,
  867. .coherent_dma_mask = 0xffffffff,
  868. },
  869. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  870. .resource = pxa3xx_resources_mci3,
  871. };
  872. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  873. {
  874. pxa_register_device(&pxa3xx_device_mci3, info);
  875. }
  876. static struct resource pxa3xx_resources_nand[] = {
  877. [0] = {
  878. .start = 0x43100000,
  879. .end = 0x43100053,
  880. .flags = IORESOURCE_MEM,
  881. },
  882. [1] = {
  883. .start = IRQ_NAND,
  884. .end = IRQ_NAND,
  885. .flags = IORESOURCE_IRQ,
  886. },
  887. [2] = {
  888. /* DRCMR for Data DMA */
  889. .start = 97,
  890. .end = 97,
  891. .flags = IORESOURCE_DMA,
  892. },
  893. [3] = {
  894. /* DRCMR for Command DMA */
  895. .start = 99,
  896. .end = 99,
  897. .flags = IORESOURCE_DMA,
  898. },
  899. };
  900. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  901. struct platform_device pxa3xx_device_nand = {
  902. .name = "pxa3xx-nand",
  903. .id = -1,
  904. .dev = {
  905. .dma_mask = &pxa3xx_nand_dma_mask,
  906. .coherent_dma_mask = DMA_BIT_MASK(32),
  907. },
  908. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  909. .resource = pxa3xx_resources_nand,
  910. };
  911. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  912. {
  913. pxa_register_device(&pxa3xx_device_nand, info);
  914. }
  915. static struct resource pxa3xx_resources_gcu[] = {
  916. {
  917. .start = 0x54000000,
  918. .end = 0x54000fff,
  919. .flags = IORESOURCE_MEM,
  920. },
  921. {
  922. .start = IRQ_GCU,
  923. .end = IRQ_GCU,
  924. .flags = IORESOURCE_IRQ,
  925. },
  926. };
  927. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  928. struct platform_device pxa3xx_device_gcu = {
  929. .name = "pxa3xx-gcu",
  930. .id = -1,
  931. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  932. .resource = pxa3xx_resources_gcu,
  933. .dev = {
  934. .dma_mask = &pxa3xx_gcu_dmamask,
  935. .coherent_dma_mask = 0xffffffff,
  936. },
  937. };
  938. #endif /* CONFIG_PXA3xx */
  939. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  940. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  941. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  942. {
  943. struct platform_device *pd;
  944. pd = platform_device_alloc("pxa2xx-spi", id);
  945. if (pd == NULL) {
  946. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  947. id);
  948. return;
  949. }
  950. pd->dev.platform_data = info;
  951. platform_device_add(pd);
  952. }