pm34xx.c 29 KB

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  1. /*
  2. * OMAP3 Power Management Routines
  3. *
  4. * Copyright (C) 2006-2008 Nokia Corporation
  5. * Tony Lindgren <tony@atomide.com>
  6. * Jouni Hogander
  7. *
  8. * Copyright (C) 2007 Texas Instruments, Inc.
  9. * Rajendra Nayak <rnayak@ti.com>
  10. *
  11. * Copyright (C) 2005 Texas Instruments, Inc.
  12. * Richard Woodruff <r-woodruff2@ti.com>
  13. *
  14. * Based on pm.c for omap1
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. #include <linux/pm.h>
  21. #include <linux/suspend.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/module.h>
  24. #include <linux/list.h>
  25. #include <linux/err.h>
  26. #include <linux/gpio.h>
  27. #include <linux/clk.h>
  28. #include <linux/delay.h>
  29. #include <linux/slab.h>
  30. #include <linux/console.h>
  31. #include <plat/sram.h>
  32. #include <plat/clockdomain.h>
  33. #include <plat/powerdomain.h>
  34. #include <plat/serial.h>
  35. #include <plat/sdrc.h>
  36. #include <plat/prcm.h>
  37. #include <plat/gpmc.h>
  38. #include <plat/dma.h>
  39. #include <asm/tlbflush.h>
  40. #include "cm.h"
  41. #include "cm-regbits-34xx.h"
  42. #include "prm-regbits-34xx.h"
  43. #include "prm.h"
  44. #include "pm.h"
  45. #include "sdrc.h"
  46. #include "control.h"
  47. /* Scratchpad offsets */
  48. #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4
  49. #define OMAP343X_TABLE_VALUE_OFFSET 0xc0
  50. #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
  51. struct power_state {
  52. struct powerdomain *pwrdm;
  53. u32 next_state;
  54. #ifdef CONFIG_SUSPEND
  55. u32 saved_state;
  56. #endif
  57. struct list_head node;
  58. };
  59. static LIST_HEAD(pwrst_list);
  60. static void (*_omap_sram_idle)(u32 *addr, int save_state);
  61. static int (*_omap_save_secure_sram)(u32 *addr);
  62. static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  63. static struct powerdomain *core_pwrdm, *per_pwrdm;
  64. static struct powerdomain *cam_pwrdm;
  65. static inline void omap3_per_save_context(void)
  66. {
  67. omap_gpio_save_context();
  68. }
  69. static inline void omap3_per_restore_context(void)
  70. {
  71. omap_gpio_restore_context();
  72. }
  73. static void omap3_enable_io_chain(void)
  74. {
  75. int timeout = 0;
  76. if (omap_rev() >= OMAP3430_REV_ES3_1) {
  77. prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
  78. PM_WKEN);
  79. /* Do a readback to assure write has been done */
  80. prm_read_mod_reg(WKUP_MOD, PM_WKEN);
  81. while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
  82. OMAP3430_ST_IO_CHAIN_MASK)) {
  83. timeout++;
  84. if (timeout > 1000) {
  85. printk(KERN_ERR "Wake up daisy chain "
  86. "activation failed.\n");
  87. return;
  88. }
  89. prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
  90. WKUP_MOD, PM_WKEN);
  91. }
  92. }
  93. }
  94. static void omap3_disable_io_chain(void)
  95. {
  96. if (omap_rev() >= OMAP3430_REV_ES3_1)
  97. prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
  98. PM_WKEN);
  99. }
  100. static void omap3_core_save_context(void)
  101. {
  102. u32 control_padconf_off;
  103. /* Save the padconf registers */
  104. control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
  105. control_padconf_off |= START_PADCONF_SAVE;
  106. omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
  107. /* wait for the save to complete */
  108. while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
  109. & PADCONF_SAVE_DONE))
  110. udelay(1);
  111. /*
  112. * Force write last pad into memory, as this can fail in some
  113. * cases according to erratas 1.157, 1.185
  114. */
  115. omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
  116. OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
  117. /* Save the Interrupt controller context */
  118. omap_intc_save_context();
  119. /* Save the GPMC context */
  120. omap3_gpmc_save_context();
  121. /* Save the system control module context, padconf already save above*/
  122. omap3_control_save_context();
  123. omap_dma_global_context_save();
  124. }
  125. static void omap3_core_restore_context(void)
  126. {
  127. /* Restore the control module context, padconf restored by h/w */
  128. omap3_control_restore_context();
  129. /* Restore the GPMC context */
  130. omap3_gpmc_restore_context();
  131. /* Restore the interrupt controller context */
  132. omap_intc_restore_context();
  133. omap_dma_global_context_restore();
  134. }
  135. /*
  136. * FIXME: This function should be called before entering off-mode after
  137. * OMAP3 secure services have been accessed. Currently it is only called
  138. * once during boot sequence, but this works as we are not using secure
  139. * services.
  140. */
  141. static void omap3_save_secure_ram_context(u32 target_mpu_state)
  142. {
  143. u32 ret;
  144. if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
  145. /*
  146. * MPU next state must be set to POWER_ON temporarily,
  147. * otherwise the WFI executed inside the ROM code
  148. * will hang the system.
  149. */
  150. pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
  151. ret = _omap_save_secure_sram((u32 *)
  152. __pa(omap3_secure_ram_storage));
  153. pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
  154. /* Following is for error tracking, it should not happen */
  155. if (ret) {
  156. printk(KERN_ERR "save_secure_sram() returns %08x\n",
  157. ret);
  158. while (1)
  159. ;
  160. }
  161. }
  162. }
  163. /*
  164. * PRCM Interrupt Handler Helper Function
  165. *
  166. * The purpose of this function is to clear any wake-up events latched
  167. * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
  168. * may occur whilst attempting to clear a PM_WKST_x register and thus
  169. * set another bit in this register. A while loop is used to ensure
  170. * that any peripheral wake-up events occurring while attempting to
  171. * clear the PM_WKST_x are detected and cleared.
  172. */
  173. static int prcm_clear_mod_irqs(s16 module, u8 regs)
  174. {
  175. u32 wkst, fclk, iclk, clken;
  176. u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
  177. u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
  178. u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
  179. u16 grpsel_off = (regs == 3) ?
  180. OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
  181. int c = 0;
  182. wkst = prm_read_mod_reg(module, wkst_off);
  183. wkst &= prm_read_mod_reg(module, grpsel_off);
  184. if (wkst) {
  185. iclk = cm_read_mod_reg(module, iclk_off);
  186. fclk = cm_read_mod_reg(module, fclk_off);
  187. while (wkst) {
  188. clken = wkst;
  189. cm_set_mod_reg_bits(clken, module, iclk_off);
  190. /*
  191. * For USBHOST, we don't know whether HOST1 or
  192. * HOST2 woke us up, so enable both f-clocks
  193. */
  194. if (module == OMAP3430ES2_USBHOST_MOD)
  195. clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
  196. cm_set_mod_reg_bits(clken, module, fclk_off);
  197. prm_write_mod_reg(wkst, module, wkst_off);
  198. wkst = prm_read_mod_reg(module, wkst_off);
  199. c++;
  200. }
  201. cm_write_mod_reg(iclk, module, iclk_off);
  202. cm_write_mod_reg(fclk, module, fclk_off);
  203. }
  204. return c;
  205. }
  206. static int _prcm_int_handle_wakeup(void)
  207. {
  208. int c;
  209. c = prcm_clear_mod_irqs(WKUP_MOD, 1);
  210. c += prcm_clear_mod_irqs(CORE_MOD, 1);
  211. c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
  212. if (omap_rev() > OMAP3430_REV_ES1_0) {
  213. c += prcm_clear_mod_irqs(CORE_MOD, 3);
  214. c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
  215. }
  216. return c;
  217. }
  218. /*
  219. * PRCM Interrupt Handler
  220. *
  221. * The PRM_IRQSTATUS_MPU register indicates if there are any pending
  222. * interrupts from the PRCM for the MPU. These bits must be cleared in
  223. * order to clear the PRCM interrupt. The PRCM interrupt handler is
  224. * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
  225. * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
  226. * register indicates that a wake-up event is pending for the MPU and
  227. * this bit can only be cleared if the all the wake-up events latched
  228. * in the various PM_WKST_x registers have been cleared. The interrupt
  229. * handler is implemented using a do-while loop so that if a wake-up
  230. * event occurred during the processing of the prcm interrupt handler
  231. * (setting a bit in the corresponding PM_WKST_x register and thus
  232. * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
  233. * this would be handled.
  234. */
  235. static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
  236. {
  237. u32 irqenable_mpu, irqstatus_mpu;
  238. int c = 0;
  239. irqenable_mpu = prm_read_mod_reg(OCP_MOD,
  240. OMAP3_PRM_IRQENABLE_MPU_OFFSET);
  241. irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
  242. OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
  243. irqstatus_mpu &= irqenable_mpu;
  244. do {
  245. if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
  246. OMAP3430_IO_ST_MASK)) {
  247. c = _prcm_int_handle_wakeup();
  248. /*
  249. * Is the MPU PRCM interrupt handler racing with the
  250. * IVA2 PRCM interrupt handler ?
  251. */
  252. WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
  253. "but no wakeup sources are marked\n");
  254. } else {
  255. /* XXX we need to expand our PRCM interrupt handler */
  256. WARN(1, "prcm: WARNING: PRCM interrupt received, but "
  257. "no code to handle it (%08x)\n", irqstatus_mpu);
  258. }
  259. prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
  260. OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
  261. irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
  262. OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
  263. irqstatus_mpu &= irqenable_mpu;
  264. } while (irqstatus_mpu);
  265. return IRQ_HANDLED;
  266. }
  267. static void restore_control_register(u32 val)
  268. {
  269. __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
  270. }
  271. /* Function to restore the table entry that was modified for enabling MMU */
  272. static void restore_table_entry(void)
  273. {
  274. void __iomem *scratchpad_address;
  275. u32 previous_value, control_reg_value;
  276. u32 *address;
  277. scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
  278. /* Get address of entry that was modified */
  279. address = (u32 *)__raw_readl(scratchpad_address +
  280. OMAP343X_TABLE_ADDRESS_OFFSET);
  281. /* Get the previous value which needs to be restored */
  282. previous_value = __raw_readl(scratchpad_address +
  283. OMAP343X_TABLE_VALUE_OFFSET);
  284. address = __va(address);
  285. *address = previous_value;
  286. flush_tlb_all();
  287. control_reg_value = __raw_readl(scratchpad_address
  288. + OMAP343X_CONTROL_REG_VALUE_OFFSET);
  289. /* This will enable caches and prediction */
  290. restore_control_register(control_reg_value);
  291. }
  292. void omap_sram_idle(void)
  293. {
  294. /* Variable to tell what needs to be saved and restored
  295. * in omap_sram_idle*/
  296. /* save_state = 0 => Nothing to save and restored */
  297. /* save_state = 1 => Only L1 and logic lost */
  298. /* save_state = 2 => Only L2 lost */
  299. /* save_state = 3 => L1, L2 and logic lost */
  300. int save_state = 0;
  301. int mpu_next_state = PWRDM_POWER_ON;
  302. int per_next_state = PWRDM_POWER_ON;
  303. int core_next_state = PWRDM_POWER_ON;
  304. int core_prev_state, per_prev_state;
  305. u32 sdrc_pwr = 0;
  306. if (!_omap_sram_idle)
  307. return;
  308. pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
  309. pwrdm_clear_all_prev_pwrst(neon_pwrdm);
  310. pwrdm_clear_all_prev_pwrst(core_pwrdm);
  311. pwrdm_clear_all_prev_pwrst(per_pwrdm);
  312. mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
  313. switch (mpu_next_state) {
  314. case PWRDM_POWER_ON:
  315. case PWRDM_POWER_RET:
  316. /* No need to save context */
  317. save_state = 0;
  318. break;
  319. case PWRDM_POWER_OFF:
  320. save_state = 3;
  321. break;
  322. default:
  323. /* Invalid state */
  324. printk(KERN_ERR "Invalid mpu state in sram_idle\n");
  325. return;
  326. }
  327. pwrdm_pre_transition();
  328. /* NEON control */
  329. if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
  330. pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
  331. /* Enable IO-PAD and IO-CHAIN wakeups */
  332. per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
  333. core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
  334. if (omap3_has_io_wakeup() &&
  335. (per_next_state < PWRDM_POWER_ON ||
  336. core_next_state < PWRDM_POWER_ON)) {
  337. prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
  338. omap3_enable_io_chain();
  339. }
  340. /* Block console output in case it is on one of the OMAP UARTs */
  341. if (per_next_state < PWRDM_POWER_ON ||
  342. core_next_state < PWRDM_POWER_ON)
  343. if (try_acquire_console_sem())
  344. goto console_still_active;
  345. /* PER */
  346. if (per_next_state < PWRDM_POWER_ON) {
  347. omap_uart_prepare_idle(2);
  348. omap_uart_prepare_idle(3);
  349. omap2_gpio_prepare_for_idle(per_next_state);
  350. if (per_next_state == PWRDM_POWER_OFF)
  351. omap3_per_save_context();
  352. }
  353. /* CORE */
  354. if (core_next_state < PWRDM_POWER_ON) {
  355. omap_uart_prepare_idle(0);
  356. omap_uart_prepare_idle(1);
  357. if (core_next_state == PWRDM_POWER_OFF) {
  358. omap3_core_save_context();
  359. omap3_prcm_save_context();
  360. }
  361. }
  362. omap3_intc_prepare_idle();
  363. /*
  364. * On EMU/HS devices ROM code restores a SRDC value
  365. * from scratchpad which has automatic self refresh on timeout
  366. * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
  367. * Hence store/restore the SDRC_POWER register here.
  368. */
  369. if (omap_rev() >= OMAP3430_REV_ES3_0 &&
  370. omap_type() != OMAP2_DEVICE_TYPE_GP &&
  371. core_next_state == PWRDM_POWER_OFF)
  372. sdrc_pwr = sdrc_read_reg(SDRC_POWER);
  373. /*
  374. * omap3_arm_context is the location where ARM registers
  375. * get saved. The restore path then reads from this
  376. * location and restores them back.
  377. */
  378. _omap_sram_idle(omap3_arm_context, save_state);
  379. cpu_init();
  380. /* Restore normal SDRC POWER settings */
  381. if (omap_rev() >= OMAP3430_REV_ES3_0 &&
  382. omap_type() != OMAP2_DEVICE_TYPE_GP &&
  383. core_next_state == PWRDM_POWER_OFF)
  384. sdrc_write_reg(sdrc_pwr, SDRC_POWER);
  385. /* Restore table entry modified during MMU restoration */
  386. if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
  387. restore_table_entry();
  388. /* CORE */
  389. if (core_next_state < PWRDM_POWER_ON) {
  390. core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
  391. if (core_prev_state == PWRDM_POWER_OFF) {
  392. omap3_core_restore_context();
  393. omap3_prcm_restore_context();
  394. omap3_sram_restore_context();
  395. omap2_sms_restore_context();
  396. }
  397. omap_uart_resume_idle(0);
  398. omap_uart_resume_idle(1);
  399. if (core_next_state == PWRDM_POWER_OFF)
  400. prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
  401. OMAP3430_GR_MOD,
  402. OMAP3_PRM_VOLTCTRL_OFFSET);
  403. }
  404. omap3_intc_resume_idle();
  405. /* PER */
  406. if (per_next_state < PWRDM_POWER_ON) {
  407. per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
  408. omap2_gpio_resume_after_idle();
  409. if (per_prev_state == PWRDM_POWER_OFF)
  410. omap3_per_restore_context();
  411. omap_uart_resume_idle(2);
  412. omap_uart_resume_idle(3);
  413. }
  414. release_console_sem();
  415. console_still_active:
  416. /* Disable IO-PAD and IO-CHAIN wakeup */
  417. if (omap3_has_io_wakeup() &&
  418. (per_next_state < PWRDM_POWER_ON ||
  419. core_next_state < PWRDM_POWER_ON)) {
  420. prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
  421. omap3_disable_io_chain();
  422. }
  423. pwrdm_post_transition();
  424. omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
  425. }
  426. int omap3_can_sleep(void)
  427. {
  428. if (!sleep_while_idle)
  429. return 0;
  430. if (!omap_uart_can_sleep())
  431. return 0;
  432. return 1;
  433. }
  434. static void omap3_pm_idle(void)
  435. {
  436. local_irq_disable();
  437. local_fiq_disable();
  438. if (!omap3_can_sleep())
  439. goto out;
  440. if (omap_irq_pending() || need_resched())
  441. goto out;
  442. omap_sram_idle();
  443. out:
  444. local_fiq_enable();
  445. local_irq_enable();
  446. }
  447. #ifdef CONFIG_SUSPEND
  448. static suspend_state_t suspend_state;
  449. static int omap3_pm_prepare(void)
  450. {
  451. disable_hlt();
  452. return 0;
  453. }
  454. static int omap3_pm_suspend(void)
  455. {
  456. struct power_state *pwrst;
  457. int state, ret = 0;
  458. if (wakeup_timer_seconds || wakeup_timer_milliseconds)
  459. omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
  460. wakeup_timer_milliseconds);
  461. /* Read current next_pwrsts */
  462. list_for_each_entry(pwrst, &pwrst_list, node)
  463. pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
  464. /* Set ones wanted by suspend */
  465. list_for_each_entry(pwrst, &pwrst_list, node) {
  466. if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
  467. goto restore;
  468. if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
  469. goto restore;
  470. }
  471. omap_uart_prepare_suspend();
  472. omap3_intc_suspend();
  473. omap_sram_idle();
  474. restore:
  475. /* Restore next_pwrsts */
  476. list_for_each_entry(pwrst, &pwrst_list, node) {
  477. state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
  478. if (state > pwrst->next_state) {
  479. printk(KERN_INFO "Powerdomain (%s) didn't enter "
  480. "target state %d\n",
  481. pwrst->pwrdm->name, pwrst->next_state);
  482. ret = -1;
  483. }
  484. omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
  485. }
  486. if (ret)
  487. printk(KERN_ERR "Could not enter target state in pm_suspend\n");
  488. else
  489. printk(KERN_INFO "Successfully put all powerdomains "
  490. "to target state\n");
  491. return ret;
  492. }
  493. static int omap3_pm_enter(suspend_state_t unused)
  494. {
  495. int ret = 0;
  496. switch (suspend_state) {
  497. case PM_SUSPEND_STANDBY:
  498. case PM_SUSPEND_MEM:
  499. ret = omap3_pm_suspend();
  500. break;
  501. default:
  502. ret = -EINVAL;
  503. }
  504. return ret;
  505. }
  506. static void omap3_pm_finish(void)
  507. {
  508. enable_hlt();
  509. }
  510. /* Hooks to enable / disable UART interrupts during suspend */
  511. static int omap3_pm_begin(suspend_state_t state)
  512. {
  513. suspend_state = state;
  514. omap_uart_enable_irqs(0);
  515. return 0;
  516. }
  517. static void omap3_pm_end(void)
  518. {
  519. suspend_state = PM_SUSPEND_ON;
  520. omap_uart_enable_irqs(1);
  521. return;
  522. }
  523. static struct platform_suspend_ops omap_pm_ops = {
  524. .begin = omap3_pm_begin,
  525. .end = omap3_pm_end,
  526. .prepare = omap3_pm_prepare,
  527. .enter = omap3_pm_enter,
  528. .finish = omap3_pm_finish,
  529. .valid = suspend_valid_only_mem,
  530. };
  531. #endif /* CONFIG_SUSPEND */
  532. /**
  533. * omap3_iva_idle(): ensure IVA is in idle so it can be put into
  534. * retention
  535. *
  536. * In cases where IVA2 is activated by bootcode, it may prevent
  537. * full-chip retention or off-mode because it is not idle. This
  538. * function forces the IVA2 into idle state so it can go
  539. * into retention/off and thus allow full-chip retention/off.
  540. *
  541. **/
  542. static void __init omap3_iva_idle(void)
  543. {
  544. /* ensure IVA2 clock is disabled */
  545. cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
  546. /* if no clock activity, nothing else to do */
  547. if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
  548. OMAP3430_CLKACTIVITY_IVA2_MASK))
  549. return;
  550. /* Reset IVA2 */
  551. prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
  552. OMAP3430_RST2_IVA2_MASK |
  553. OMAP3430_RST3_IVA2_MASK,
  554. OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
  555. /* Enable IVA2 clock */
  556. cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
  557. OMAP3430_IVA2_MOD, CM_FCLKEN);
  558. /* Set IVA2 boot mode to 'idle' */
  559. omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
  560. OMAP343X_CONTROL_IVA2_BOOTMOD);
  561. /* Un-reset IVA2 */
  562. prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
  563. /* Disable IVA2 clock */
  564. cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
  565. /* Reset IVA2 */
  566. prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
  567. OMAP3430_RST2_IVA2_MASK |
  568. OMAP3430_RST3_IVA2_MASK,
  569. OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
  570. }
  571. static void __init omap3_d2d_idle(void)
  572. {
  573. u16 mask, padconf;
  574. /* In a stand alone OMAP3430 where there is not a stacked
  575. * modem for the D2D Idle Ack and D2D MStandby must be pulled
  576. * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
  577. * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
  578. mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
  579. padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
  580. padconf |= mask;
  581. omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
  582. padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
  583. padconf |= mask;
  584. omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
  585. /* reset modem */
  586. prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
  587. OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
  588. CORE_MOD, OMAP2_RM_RSTCTRL);
  589. prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
  590. }
  591. static void __init prcm_setup_regs(void)
  592. {
  593. u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
  594. OMAP3630_AUTO_UART4_MASK : 0;
  595. u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
  596. OMAP3630_EN_UART4_MASK : 0;
  597. u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
  598. OMAP3630_GRPSEL_UART4_MASK : 0;
  599. /* XXX Reset all wkdeps. This should be done when initializing
  600. * powerdomains */
  601. prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
  602. prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
  603. prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
  604. prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
  605. prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
  606. prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
  607. if (omap_rev() > OMAP3430_REV_ES1_0) {
  608. prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
  609. prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
  610. } else
  611. prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
  612. /*
  613. * Enable interface clock autoidle for all modules.
  614. * Note that in the long run this should be done by clockfw
  615. */
  616. cm_write_mod_reg(
  617. OMAP3430_AUTO_MODEM_MASK |
  618. OMAP3430ES2_AUTO_MMC3_MASK |
  619. OMAP3430ES2_AUTO_ICR_MASK |
  620. OMAP3430_AUTO_AES2_MASK |
  621. OMAP3430_AUTO_SHA12_MASK |
  622. OMAP3430_AUTO_DES2_MASK |
  623. OMAP3430_AUTO_MMC2_MASK |
  624. OMAP3430_AUTO_MMC1_MASK |
  625. OMAP3430_AUTO_MSPRO_MASK |
  626. OMAP3430_AUTO_HDQ_MASK |
  627. OMAP3430_AUTO_MCSPI4_MASK |
  628. OMAP3430_AUTO_MCSPI3_MASK |
  629. OMAP3430_AUTO_MCSPI2_MASK |
  630. OMAP3430_AUTO_MCSPI1_MASK |
  631. OMAP3430_AUTO_I2C3_MASK |
  632. OMAP3430_AUTO_I2C2_MASK |
  633. OMAP3430_AUTO_I2C1_MASK |
  634. OMAP3430_AUTO_UART2_MASK |
  635. OMAP3430_AUTO_UART1_MASK |
  636. OMAP3430_AUTO_GPT11_MASK |
  637. OMAP3430_AUTO_GPT10_MASK |
  638. OMAP3430_AUTO_MCBSP5_MASK |
  639. OMAP3430_AUTO_MCBSP1_MASK |
  640. OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
  641. OMAP3430_AUTO_MAILBOXES_MASK |
  642. OMAP3430_AUTO_OMAPCTRL_MASK |
  643. OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
  644. OMAP3430_AUTO_HSOTGUSB_MASK |
  645. OMAP3430_AUTO_SAD2D_MASK |
  646. OMAP3430_AUTO_SSI_MASK,
  647. CORE_MOD, CM_AUTOIDLE1);
  648. cm_write_mod_reg(
  649. OMAP3430_AUTO_PKA_MASK |
  650. OMAP3430_AUTO_AES1_MASK |
  651. OMAP3430_AUTO_RNG_MASK |
  652. OMAP3430_AUTO_SHA11_MASK |
  653. OMAP3430_AUTO_DES1_MASK,
  654. CORE_MOD, CM_AUTOIDLE2);
  655. if (omap_rev() > OMAP3430_REV_ES1_0) {
  656. cm_write_mod_reg(
  657. OMAP3430_AUTO_MAD2D_MASK |
  658. OMAP3430ES2_AUTO_USBTLL_MASK,
  659. CORE_MOD, CM_AUTOIDLE3);
  660. }
  661. cm_write_mod_reg(
  662. OMAP3430_AUTO_WDT2_MASK |
  663. OMAP3430_AUTO_WDT1_MASK |
  664. OMAP3430_AUTO_GPIO1_MASK |
  665. OMAP3430_AUTO_32KSYNC_MASK |
  666. OMAP3430_AUTO_GPT12_MASK |
  667. OMAP3430_AUTO_GPT1_MASK,
  668. WKUP_MOD, CM_AUTOIDLE);
  669. cm_write_mod_reg(
  670. OMAP3430_AUTO_DSS_MASK,
  671. OMAP3430_DSS_MOD,
  672. CM_AUTOIDLE);
  673. cm_write_mod_reg(
  674. OMAP3430_AUTO_CAM_MASK,
  675. OMAP3430_CAM_MOD,
  676. CM_AUTOIDLE);
  677. cm_write_mod_reg(
  678. omap3630_auto_uart4_mask |
  679. OMAP3430_AUTO_GPIO6_MASK |
  680. OMAP3430_AUTO_GPIO5_MASK |
  681. OMAP3430_AUTO_GPIO4_MASK |
  682. OMAP3430_AUTO_GPIO3_MASK |
  683. OMAP3430_AUTO_GPIO2_MASK |
  684. OMAP3430_AUTO_WDT3_MASK |
  685. OMAP3430_AUTO_UART3_MASK |
  686. OMAP3430_AUTO_GPT9_MASK |
  687. OMAP3430_AUTO_GPT8_MASK |
  688. OMAP3430_AUTO_GPT7_MASK |
  689. OMAP3430_AUTO_GPT6_MASK |
  690. OMAP3430_AUTO_GPT5_MASK |
  691. OMAP3430_AUTO_GPT4_MASK |
  692. OMAP3430_AUTO_GPT3_MASK |
  693. OMAP3430_AUTO_GPT2_MASK |
  694. OMAP3430_AUTO_MCBSP4_MASK |
  695. OMAP3430_AUTO_MCBSP3_MASK |
  696. OMAP3430_AUTO_MCBSP2_MASK,
  697. OMAP3430_PER_MOD,
  698. CM_AUTOIDLE);
  699. if (omap_rev() > OMAP3430_REV_ES1_0) {
  700. cm_write_mod_reg(
  701. OMAP3430ES2_AUTO_USBHOST_MASK,
  702. OMAP3430ES2_USBHOST_MOD,
  703. CM_AUTOIDLE);
  704. }
  705. omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
  706. /*
  707. * Set all plls to autoidle. This is needed until autoidle is
  708. * enabled by clockfw
  709. */
  710. cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
  711. OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
  712. cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
  713. MPU_MOD,
  714. CM_AUTOIDLE2);
  715. cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
  716. (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
  717. PLL_MOD,
  718. CM_AUTOIDLE);
  719. cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
  720. PLL_MOD,
  721. CM_AUTOIDLE2);
  722. /*
  723. * Enable control of expternal oscillator through
  724. * sys_clkreq. In the long run clock framework should
  725. * take care of this.
  726. */
  727. prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
  728. 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
  729. OMAP3430_GR_MOD,
  730. OMAP3_PRM_CLKSRC_CTRL_OFFSET);
  731. /* setup wakup source */
  732. prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
  733. OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
  734. WKUP_MOD, PM_WKEN);
  735. /* No need to write EN_IO, that is always enabled */
  736. prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
  737. OMAP3430_GRPSEL_GPT1_MASK |
  738. OMAP3430_GRPSEL_GPT12_MASK,
  739. WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
  740. /* For some reason IO doesn't generate wakeup event even if
  741. * it is selected to mpu wakeup goup */
  742. prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
  743. OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
  744. /* Enable PM_WKEN to support DSS LPR */
  745. prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
  746. OMAP3430_DSS_MOD, PM_WKEN);
  747. /* Enable wakeups in PER */
  748. prm_write_mod_reg(omap3630_en_uart4_mask |
  749. OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
  750. OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
  751. OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
  752. OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
  753. OMAP3430_EN_MCBSP4_MASK,
  754. OMAP3430_PER_MOD, PM_WKEN);
  755. /* and allow them to wake up MPU */
  756. prm_write_mod_reg(omap3630_grpsel_uart4_mask |
  757. OMAP3430_GRPSEL_GPIO2_MASK |
  758. OMAP3430_GRPSEL_GPIO3_MASK |
  759. OMAP3430_GRPSEL_GPIO4_MASK |
  760. OMAP3430_GRPSEL_GPIO5_MASK |
  761. OMAP3430_GRPSEL_GPIO6_MASK |
  762. OMAP3430_GRPSEL_UART3_MASK |
  763. OMAP3430_GRPSEL_MCBSP2_MASK |
  764. OMAP3430_GRPSEL_MCBSP3_MASK |
  765. OMAP3430_GRPSEL_MCBSP4_MASK,
  766. OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
  767. /* Don't attach IVA interrupts */
  768. prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
  769. prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
  770. prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
  771. prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
  772. /* Clear any pending 'reset' flags */
  773. prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
  774. prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
  775. prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
  776. prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
  777. prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
  778. prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
  779. prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
  780. /* Clear any pending PRCM interrupts */
  781. prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
  782. omap3_iva_idle();
  783. omap3_d2d_idle();
  784. }
  785. void omap3_pm_off_mode_enable(int enable)
  786. {
  787. struct power_state *pwrst;
  788. u32 state;
  789. if (enable)
  790. state = PWRDM_POWER_OFF;
  791. else
  792. state = PWRDM_POWER_RET;
  793. #ifdef CONFIG_CPU_IDLE
  794. omap3_cpuidle_update_states();
  795. #endif
  796. list_for_each_entry(pwrst, &pwrst_list, node) {
  797. pwrst->next_state = state;
  798. omap_set_pwrdm_state(pwrst->pwrdm, state);
  799. }
  800. }
  801. int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
  802. {
  803. struct power_state *pwrst;
  804. list_for_each_entry(pwrst, &pwrst_list, node) {
  805. if (pwrst->pwrdm == pwrdm)
  806. return pwrst->next_state;
  807. }
  808. return -EINVAL;
  809. }
  810. int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
  811. {
  812. struct power_state *pwrst;
  813. list_for_each_entry(pwrst, &pwrst_list, node) {
  814. if (pwrst->pwrdm == pwrdm) {
  815. pwrst->next_state = state;
  816. return 0;
  817. }
  818. }
  819. return -EINVAL;
  820. }
  821. static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  822. {
  823. struct power_state *pwrst;
  824. if (!pwrdm->pwrsts)
  825. return 0;
  826. pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
  827. if (!pwrst)
  828. return -ENOMEM;
  829. pwrst->pwrdm = pwrdm;
  830. pwrst->next_state = PWRDM_POWER_RET;
  831. list_add(&pwrst->node, &pwrst_list);
  832. if (pwrdm_has_hdwr_sar(pwrdm))
  833. pwrdm_enable_hdwr_sar(pwrdm);
  834. return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
  835. }
  836. /*
  837. * Enable hw supervised mode for all clockdomains if it's
  838. * supported. Initiate sleep transition for other clockdomains, if
  839. * they are not used
  840. */
  841. static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
  842. {
  843. if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
  844. omap2_clkdm_allow_idle(clkdm);
  845. else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
  846. atomic_read(&clkdm->usecount) == 0)
  847. omap2_clkdm_sleep(clkdm);
  848. return 0;
  849. }
  850. void omap_push_sram_idle(void)
  851. {
  852. _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
  853. omap34xx_cpu_suspend_sz);
  854. if (omap_type() != OMAP2_DEVICE_TYPE_GP)
  855. _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
  856. save_secure_ram_context_sz);
  857. }
  858. static int __init omap3_pm_init(void)
  859. {
  860. struct power_state *pwrst, *tmp;
  861. struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
  862. int ret;
  863. if (!cpu_is_omap34xx())
  864. return -ENODEV;
  865. printk(KERN_ERR "Power Management for TI OMAP3.\n");
  866. /* XXX prcm_setup_regs needs to be before enabling hw
  867. * supervised mode for powerdomains */
  868. prcm_setup_regs();
  869. ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
  870. (irq_handler_t)prcm_interrupt_handler,
  871. IRQF_DISABLED, "prcm", NULL);
  872. if (ret) {
  873. printk(KERN_ERR "request_irq failed to register for 0x%x\n",
  874. INT_34XX_PRCM_MPU_IRQ);
  875. goto err1;
  876. }
  877. ret = pwrdm_for_each(pwrdms_setup, NULL);
  878. if (ret) {
  879. printk(KERN_ERR "Failed to setup powerdomains\n");
  880. goto err2;
  881. }
  882. (void) clkdm_for_each(clkdms_setup, NULL);
  883. mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
  884. if (mpu_pwrdm == NULL) {
  885. printk(KERN_ERR "Failed to get mpu_pwrdm\n");
  886. goto err2;
  887. }
  888. neon_pwrdm = pwrdm_lookup("neon_pwrdm");
  889. per_pwrdm = pwrdm_lookup("per_pwrdm");
  890. core_pwrdm = pwrdm_lookup("core_pwrdm");
  891. cam_pwrdm = pwrdm_lookup("cam_pwrdm");
  892. neon_clkdm = clkdm_lookup("neon_clkdm");
  893. mpu_clkdm = clkdm_lookup("mpu_clkdm");
  894. per_clkdm = clkdm_lookup("per_clkdm");
  895. core_clkdm = clkdm_lookup("core_clkdm");
  896. omap_push_sram_idle();
  897. #ifdef CONFIG_SUSPEND
  898. suspend_set_ops(&omap_pm_ops);
  899. #endif /* CONFIG_SUSPEND */
  900. pm_idle = omap3_pm_idle;
  901. omap3_idle_init();
  902. clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
  903. if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
  904. omap3_secure_ram_storage =
  905. kmalloc(0x803F, GFP_KERNEL);
  906. if (!omap3_secure_ram_storage)
  907. printk(KERN_ERR "Memory allocation failed when"
  908. "allocating for secure sram context\n");
  909. local_irq_disable();
  910. local_fiq_disable();
  911. omap_dma_global_context_save();
  912. omap3_save_secure_ram_context(PWRDM_POWER_ON);
  913. omap_dma_global_context_restore();
  914. local_irq_enable();
  915. local_fiq_enable();
  916. }
  917. omap3_save_scratchpad_contents();
  918. err1:
  919. return ret;
  920. err2:
  921. free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
  922. list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
  923. list_del(&pwrst->node);
  924. kfree(pwrst);
  925. }
  926. return ret;
  927. }
  928. late_initcall(omap3_pm_init);