omap_hwmod_44xx_data.c 29 KB

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  1. /*
  2. * Hardware modules present on the OMAP44xx chips
  3. *
  4. * Copyright (C) 2009-2010 Texas Instruments, Inc.
  5. * Copyright (C) 2009-2010 Nokia Corporation
  6. *
  7. * Paul Walmsley
  8. * Benoit Cousson
  9. *
  10. * This file is automatically generated from the OMAP hardware databases.
  11. * We respectfully ask that any modifications to this file be coordinated
  12. * with the public linux-omap@vger.kernel.org mailing list and the
  13. * authors above to ensure that the autogeneration scripts are kept
  14. * up-to-date with the file contents.
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. #include <linux/io.h>
  21. #include <plat/omap_hwmod.h>
  22. #include <plat/cpu.h>
  23. #include "omap_hwmod_common_data.h"
  24. #include "cm.h"
  25. #include "prm-regbits-44xx.h"
  26. /* Base offset for all OMAP4 interrupts external to MPUSS */
  27. #define OMAP44XX_IRQ_GIC_START 32
  28. /* Base offset for all OMAP4 dma requests */
  29. #define OMAP44XX_DMA_REQ_START 1
  30. /* Backward references (IPs with Bus Master capability) */
  31. static struct omap_hwmod omap44xx_dmm_hwmod;
  32. static struct omap_hwmod omap44xx_emif_fw_hwmod;
  33. static struct omap_hwmod omap44xx_l3_instr_hwmod;
  34. static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  35. static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  36. static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  37. static struct omap_hwmod omap44xx_l4_abe_hwmod;
  38. static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  39. static struct omap_hwmod omap44xx_l4_per_hwmod;
  40. static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  41. static struct omap_hwmod omap44xx_mpu_hwmod;
  42. static struct omap_hwmod omap44xx_mpu_private_hwmod;
  43. /*
  44. * Interconnects omap_hwmod structures
  45. * hwmods that compose the global OMAP interconnect
  46. */
  47. /*
  48. * 'dmm' class
  49. * instance(s): dmm
  50. */
  51. static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  52. .name = "dmm",
  53. };
  54. /* dmm interface data */
  55. /* l3_main_1 -> dmm */
  56. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  57. .master = &omap44xx_l3_main_1_hwmod,
  58. .slave = &omap44xx_dmm_hwmod,
  59. .clk = "l3_div_ck",
  60. .user = OCP_USER_MPU | OCP_USER_SDMA,
  61. };
  62. /* mpu -> dmm */
  63. static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  64. .master = &omap44xx_mpu_hwmod,
  65. .slave = &omap44xx_dmm_hwmod,
  66. .clk = "l3_div_ck",
  67. .user = OCP_USER_MPU | OCP_USER_SDMA,
  68. };
  69. /* dmm slave ports */
  70. static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
  71. &omap44xx_l3_main_1__dmm,
  72. &omap44xx_mpu__dmm,
  73. };
  74. static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  75. { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  76. };
  77. static struct omap_hwmod omap44xx_dmm_hwmod = {
  78. .name = "dmm",
  79. .class = &omap44xx_dmm_hwmod_class,
  80. .slaves = omap44xx_dmm_slaves,
  81. .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
  82. .mpu_irqs = omap44xx_dmm_irqs,
  83. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
  84. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  85. };
  86. /*
  87. * 'emif_fw' class
  88. * instance(s): emif_fw
  89. */
  90. static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
  91. .name = "emif_fw",
  92. };
  93. /* emif_fw interface data */
  94. /* dmm -> emif_fw */
  95. static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
  96. .master = &omap44xx_dmm_hwmod,
  97. .slave = &omap44xx_emif_fw_hwmod,
  98. .clk = "l3_div_ck",
  99. .user = OCP_USER_MPU | OCP_USER_SDMA,
  100. };
  101. /* l4_cfg -> emif_fw */
  102. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
  103. .master = &omap44xx_l4_cfg_hwmod,
  104. .slave = &omap44xx_emif_fw_hwmod,
  105. .clk = "l4_div_ck",
  106. .user = OCP_USER_MPU | OCP_USER_SDMA,
  107. };
  108. /* emif_fw slave ports */
  109. static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
  110. &omap44xx_dmm__emif_fw,
  111. &omap44xx_l4_cfg__emif_fw,
  112. };
  113. static struct omap_hwmod omap44xx_emif_fw_hwmod = {
  114. .name = "emif_fw",
  115. .class = &omap44xx_emif_fw_hwmod_class,
  116. .slaves = omap44xx_emif_fw_slaves,
  117. .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
  118. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  119. };
  120. /*
  121. * 'l3' class
  122. * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  123. */
  124. static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  125. .name = "l3",
  126. };
  127. /* l3_instr interface data */
  128. /* l3_main_3 -> l3_instr */
  129. static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
  130. .master = &omap44xx_l3_main_3_hwmod,
  131. .slave = &omap44xx_l3_instr_hwmod,
  132. .clk = "l3_div_ck",
  133. .user = OCP_USER_MPU | OCP_USER_SDMA,
  134. };
  135. /* l3_instr slave ports */
  136. static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
  137. &omap44xx_l3_main_3__l3_instr,
  138. };
  139. static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  140. .name = "l3_instr",
  141. .class = &omap44xx_l3_hwmod_class,
  142. .slaves = omap44xx_l3_instr_slaves,
  143. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
  144. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  145. };
  146. /* l3_main_2 -> l3_main_1 */
  147. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
  148. .master = &omap44xx_l3_main_2_hwmod,
  149. .slave = &omap44xx_l3_main_1_hwmod,
  150. .clk = "l3_div_ck",
  151. .user = OCP_USER_MPU | OCP_USER_SDMA,
  152. };
  153. /* l4_cfg -> l3_main_1 */
  154. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
  155. .master = &omap44xx_l4_cfg_hwmod,
  156. .slave = &omap44xx_l3_main_1_hwmod,
  157. .clk = "l4_div_ck",
  158. .user = OCP_USER_MPU | OCP_USER_SDMA,
  159. };
  160. /* mpu -> l3_main_1 */
  161. static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
  162. .master = &omap44xx_mpu_hwmod,
  163. .slave = &omap44xx_l3_main_1_hwmod,
  164. .clk = "l3_div_ck",
  165. .user = OCP_USER_MPU | OCP_USER_SDMA,
  166. };
  167. /* l3_main_1 slave ports */
  168. static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
  169. &omap44xx_l3_main_2__l3_main_1,
  170. &omap44xx_l4_cfg__l3_main_1,
  171. &omap44xx_mpu__l3_main_1,
  172. };
  173. static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  174. .name = "l3_main_1",
  175. .class = &omap44xx_l3_hwmod_class,
  176. .slaves = omap44xx_l3_main_1_slaves,
  177. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
  178. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  179. };
  180. /* l3_main_2 interface data */
  181. /* l3_main_1 -> l3_main_2 */
  182. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
  183. .master = &omap44xx_l3_main_1_hwmod,
  184. .slave = &omap44xx_l3_main_2_hwmod,
  185. .clk = "l3_div_ck",
  186. .user = OCP_USER_MPU | OCP_USER_SDMA,
  187. };
  188. /* l4_cfg -> l3_main_2 */
  189. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
  190. .master = &omap44xx_l4_cfg_hwmod,
  191. .slave = &omap44xx_l3_main_2_hwmod,
  192. .clk = "l4_div_ck",
  193. .user = OCP_USER_MPU | OCP_USER_SDMA,
  194. };
  195. /* l3_main_2 slave ports */
  196. static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
  197. &omap44xx_l3_main_1__l3_main_2,
  198. &omap44xx_l4_cfg__l3_main_2,
  199. };
  200. static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
  201. .name = "l3_main_2",
  202. .class = &omap44xx_l3_hwmod_class,
  203. .slaves = omap44xx_l3_main_2_slaves,
  204. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
  205. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  206. };
  207. /* l3_main_3 interface data */
  208. /* l3_main_1 -> l3_main_3 */
  209. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
  210. .master = &omap44xx_l3_main_1_hwmod,
  211. .slave = &omap44xx_l3_main_3_hwmod,
  212. .clk = "l3_div_ck",
  213. .user = OCP_USER_MPU | OCP_USER_SDMA,
  214. };
  215. /* l3_main_2 -> l3_main_3 */
  216. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
  217. .master = &omap44xx_l3_main_2_hwmod,
  218. .slave = &omap44xx_l3_main_3_hwmod,
  219. .clk = "l3_div_ck",
  220. .user = OCP_USER_MPU | OCP_USER_SDMA,
  221. };
  222. /* l4_cfg -> l3_main_3 */
  223. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
  224. .master = &omap44xx_l4_cfg_hwmod,
  225. .slave = &omap44xx_l3_main_3_hwmod,
  226. .clk = "l4_div_ck",
  227. .user = OCP_USER_MPU | OCP_USER_SDMA,
  228. };
  229. /* l3_main_3 slave ports */
  230. static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
  231. &omap44xx_l3_main_1__l3_main_3,
  232. &omap44xx_l3_main_2__l3_main_3,
  233. &omap44xx_l4_cfg__l3_main_3,
  234. };
  235. static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
  236. .name = "l3_main_3",
  237. .class = &omap44xx_l3_hwmod_class,
  238. .slaves = omap44xx_l3_main_3_slaves,
  239. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
  240. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  241. };
  242. /*
  243. * 'l4' class
  244. * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
  245. */
  246. static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
  247. .name = "l4",
  248. };
  249. /* l4_abe interface data */
  250. /* l3_main_1 -> l4_abe */
  251. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
  252. .master = &omap44xx_l3_main_1_hwmod,
  253. .slave = &omap44xx_l4_abe_hwmod,
  254. .clk = "l3_div_ck",
  255. .user = OCP_USER_MPU | OCP_USER_SDMA,
  256. };
  257. /* mpu -> l4_abe */
  258. static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
  259. .master = &omap44xx_mpu_hwmod,
  260. .slave = &omap44xx_l4_abe_hwmod,
  261. .clk = "ocp_abe_iclk",
  262. .user = OCP_USER_MPU | OCP_USER_SDMA,
  263. };
  264. /* l4_abe slave ports */
  265. static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
  266. &omap44xx_l3_main_1__l4_abe,
  267. &omap44xx_mpu__l4_abe,
  268. };
  269. static struct omap_hwmod omap44xx_l4_abe_hwmod = {
  270. .name = "l4_abe",
  271. .class = &omap44xx_l4_hwmod_class,
  272. .slaves = omap44xx_l4_abe_slaves,
  273. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
  274. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  275. };
  276. /* l4_cfg interface data */
  277. /* l3_main_1 -> l4_cfg */
  278. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
  279. .master = &omap44xx_l3_main_1_hwmod,
  280. .slave = &omap44xx_l4_cfg_hwmod,
  281. .clk = "l3_div_ck",
  282. .user = OCP_USER_MPU | OCP_USER_SDMA,
  283. };
  284. /* l4_cfg slave ports */
  285. static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
  286. &omap44xx_l3_main_1__l4_cfg,
  287. };
  288. static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
  289. .name = "l4_cfg",
  290. .class = &omap44xx_l4_hwmod_class,
  291. .slaves = omap44xx_l4_cfg_slaves,
  292. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
  293. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  294. };
  295. /* l4_per interface data */
  296. /* l3_main_2 -> l4_per */
  297. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
  298. .master = &omap44xx_l3_main_2_hwmod,
  299. .slave = &omap44xx_l4_per_hwmod,
  300. .clk = "l3_div_ck",
  301. .user = OCP_USER_MPU | OCP_USER_SDMA,
  302. };
  303. /* l4_per slave ports */
  304. static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
  305. &omap44xx_l3_main_2__l4_per,
  306. };
  307. static struct omap_hwmod omap44xx_l4_per_hwmod = {
  308. .name = "l4_per",
  309. .class = &omap44xx_l4_hwmod_class,
  310. .slaves = omap44xx_l4_per_slaves,
  311. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
  312. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  313. };
  314. /* l4_wkup interface data */
  315. /* l4_cfg -> l4_wkup */
  316. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
  317. .master = &omap44xx_l4_cfg_hwmod,
  318. .slave = &omap44xx_l4_wkup_hwmod,
  319. .clk = "l4_div_ck",
  320. .user = OCP_USER_MPU | OCP_USER_SDMA,
  321. };
  322. /* l4_wkup slave ports */
  323. static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
  324. &omap44xx_l4_cfg__l4_wkup,
  325. };
  326. static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
  327. .name = "l4_wkup",
  328. .class = &omap44xx_l4_hwmod_class,
  329. .slaves = omap44xx_l4_wkup_slaves,
  330. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
  331. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  332. };
  333. /*
  334. * 'i2c' class
  335. * multimaster high-speed i2c controller
  336. */
  337. static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
  338. .sysc_offs = 0x0010,
  339. .syss_offs = 0x0090,
  340. .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  341. SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
  342. SYSC_HAS_AUTOIDLE),
  343. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  344. .sysc_fields = &omap_hwmod_sysc_type1,
  345. };
  346. static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
  347. .name = "i2c",
  348. .sysc = &omap44xx_i2c_sysc,
  349. };
  350. /* i2c1 */
  351. static struct omap_hwmod omap44xx_i2c1_hwmod;
  352. static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
  353. { .irq = 56 + OMAP44XX_IRQ_GIC_START },
  354. };
  355. static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
  356. { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
  357. { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
  358. };
  359. static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
  360. {
  361. .pa_start = 0x48070000,
  362. .pa_end = 0x480700ff,
  363. .flags = ADDR_TYPE_RT
  364. },
  365. };
  366. /* l4_per -> i2c1 */
  367. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
  368. .master = &omap44xx_l4_per_hwmod,
  369. .slave = &omap44xx_i2c1_hwmod,
  370. .clk = "l4_div_ck",
  371. .addr = omap44xx_i2c1_addrs,
  372. .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
  373. .user = OCP_USER_MPU | OCP_USER_SDMA,
  374. };
  375. /* i2c1 slave ports */
  376. static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
  377. &omap44xx_l4_per__i2c1,
  378. };
  379. static struct omap_hwmod omap44xx_i2c1_hwmod = {
  380. .name = "i2c1",
  381. .class = &omap44xx_i2c_hwmod_class,
  382. .flags = HWMOD_INIT_NO_RESET,
  383. .mpu_irqs = omap44xx_i2c1_irqs,
  384. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
  385. .sdma_reqs = omap44xx_i2c1_sdma_reqs,
  386. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
  387. .main_clk = "i2c1_fck",
  388. .prcm = {
  389. .omap4 = {
  390. .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
  391. },
  392. },
  393. .slaves = omap44xx_i2c1_slaves,
  394. .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
  395. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  396. };
  397. /* i2c2 */
  398. static struct omap_hwmod omap44xx_i2c2_hwmod;
  399. static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
  400. { .irq = 57 + OMAP44XX_IRQ_GIC_START },
  401. };
  402. static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
  403. { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
  404. { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
  405. };
  406. static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
  407. {
  408. .pa_start = 0x48072000,
  409. .pa_end = 0x480720ff,
  410. .flags = ADDR_TYPE_RT
  411. },
  412. };
  413. /* l4_per -> i2c2 */
  414. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
  415. .master = &omap44xx_l4_per_hwmod,
  416. .slave = &omap44xx_i2c2_hwmod,
  417. .clk = "l4_div_ck",
  418. .addr = omap44xx_i2c2_addrs,
  419. .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
  420. .user = OCP_USER_MPU | OCP_USER_SDMA,
  421. };
  422. /* i2c2 slave ports */
  423. static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
  424. &omap44xx_l4_per__i2c2,
  425. };
  426. static struct omap_hwmod omap44xx_i2c2_hwmod = {
  427. .name = "i2c2",
  428. .class = &omap44xx_i2c_hwmod_class,
  429. .flags = HWMOD_INIT_NO_RESET,
  430. .mpu_irqs = omap44xx_i2c2_irqs,
  431. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
  432. .sdma_reqs = omap44xx_i2c2_sdma_reqs,
  433. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
  434. .main_clk = "i2c2_fck",
  435. .prcm = {
  436. .omap4 = {
  437. .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
  438. },
  439. },
  440. .slaves = omap44xx_i2c2_slaves,
  441. .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
  442. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  443. };
  444. /* i2c3 */
  445. static struct omap_hwmod omap44xx_i2c3_hwmod;
  446. static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
  447. { .irq = 61 + OMAP44XX_IRQ_GIC_START },
  448. };
  449. static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
  450. { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
  451. { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
  452. };
  453. static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
  454. {
  455. .pa_start = 0x48060000,
  456. .pa_end = 0x480600ff,
  457. .flags = ADDR_TYPE_RT
  458. },
  459. };
  460. /* l4_per -> i2c3 */
  461. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
  462. .master = &omap44xx_l4_per_hwmod,
  463. .slave = &omap44xx_i2c3_hwmod,
  464. .clk = "l4_div_ck",
  465. .addr = omap44xx_i2c3_addrs,
  466. .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
  467. .user = OCP_USER_MPU | OCP_USER_SDMA,
  468. };
  469. /* i2c3 slave ports */
  470. static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
  471. &omap44xx_l4_per__i2c3,
  472. };
  473. static struct omap_hwmod omap44xx_i2c3_hwmod = {
  474. .name = "i2c3",
  475. .class = &omap44xx_i2c_hwmod_class,
  476. .flags = HWMOD_INIT_NO_RESET,
  477. .mpu_irqs = omap44xx_i2c3_irqs,
  478. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
  479. .sdma_reqs = omap44xx_i2c3_sdma_reqs,
  480. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
  481. .main_clk = "i2c3_fck",
  482. .prcm = {
  483. .omap4 = {
  484. .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
  485. },
  486. },
  487. .slaves = omap44xx_i2c3_slaves,
  488. .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
  489. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  490. };
  491. /* i2c4 */
  492. static struct omap_hwmod omap44xx_i2c4_hwmod;
  493. static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
  494. { .irq = 62 + OMAP44XX_IRQ_GIC_START },
  495. };
  496. static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
  497. { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
  498. { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
  499. };
  500. static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
  501. {
  502. .pa_start = 0x48350000,
  503. .pa_end = 0x483500ff,
  504. .flags = ADDR_TYPE_RT
  505. },
  506. };
  507. /* l4_per -> i2c4 */
  508. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
  509. .master = &omap44xx_l4_per_hwmod,
  510. .slave = &omap44xx_i2c4_hwmod,
  511. .clk = "l4_div_ck",
  512. .addr = omap44xx_i2c4_addrs,
  513. .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
  514. .user = OCP_USER_MPU | OCP_USER_SDMA,
  515. };
  516. /* i2c4 slave ports */
  517. static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
  518. &omap44xx_l4_per__i2c4,
  519. };
  520. static struct omap_hwmod omap44xx_i2c4_hwmod = {
  521. .name = "i2c4",
  522. .class = &omap44xx_i2c_hwmod_class,
  523. .flags = HWMOD_INIT_NO_RESET,
  524. .mpu_irqs = omap44xx_i2c4_irqs,
  525. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
  526. .sdma_reqs = omap44xx_i2c4_sdma_reqs,
  527. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
  528. .main_clk = "i2c4_fck",
  529. .prcm = {
  530. .omap4 = {
  531. .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
  532. },
  533. },
  534. .slaves = omap44xx_i2c4_slaves,
  535. .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
  536. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  537. };
  538. /*
  539. * 'mpu_bus' class
  540. * instance(s): mpu_private
  541. */
  542. static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
  543. .name = "mpu_bus",
  544. };
  545. /* mpu_private interface data */
  546. /* mpu -> mpu_private */
  547. static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
  548. .master = &omap44xx_mpu_hwmod,
  549. .slave = &omap44xx_mpu_private_hwmod,
  550. .clk = "l3_div_ck",
  551. .user = OCP_USER_MPU | OCP_USER_SDMA,
  552. };
  553. /* mpu_private slave ports */
  554. static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
  555. &omap44xx_mpu__mpu_private,
  556. };
  557. static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  558. .name = "mpu_private",
  559. .class = &omap44xx_mpu_bus_hwmod_class,
  560. .slaves = omap44xx_mpu_private_slaves,
  561. .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
  562. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  563. };
  564. /*
  565. * 'mpu' class
  566. * mpu sub-system
  567. */
  568. static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
  569. .name = "mpu",
  570. };
  571. /* mpu */
  572. static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
  573. { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
  574. { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
  575. { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
  576. };
  577. /* mpu master ports */
  578. static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
  579. &omap44xx_mpu__l3_main_1,
  580. &omap44xx_mpu__l4_abe,
  581. &omap44xx_mpu__dmm,
  582. };
  583. static struct omap_hwmod omap44xx_mpu_hwmod = {
  584. .name = "mpu",
  585. .class = &omap44xx_mpu_hwmod_class,
  586. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  587. .mpu_irqs = omap44xx_mpu_irqs,
  588. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
  589. .main_clk = "dpll_mpu_m2_ck",
  590. .prcm = {
  591. .omap4 = {
  592. .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
  593. },
  594. },
  595. .masters = omap44xx_mpu_masters,
  596. .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
  597. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  598. };
  599. /*
  600. * 'wd_timer' class
  601. * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  602. * overflow condition
  603. */
  604. static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
  605. .rev_offs = 0x0000,
  606. .sysc_offs = 0x0010,
  607. .syss_offs = 0x0014,
  608. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
  609. SYSC_HAS_SOFTRESET),
  610. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  611. .sysc_fields = &omap_hwmod_sysc_type1,
  612. };
  613. /*
  614. * 'uart' class
  615. * universal asynchronous receiver/transmitter (uart)
  616. */
  617. static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
  618. .rev_offs = 0x0050,
  619. .sysc_offs = 0x0054,
  620. .syss_offs = 0x0058,
  621. .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  622. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  623. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  624. .sysc_fields = &omap_hwmod_sysc_type1,
  625. };
  626. static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
  627. .name = "wd_timer",
  628. .sysc = &omap44xx_wd_timer_sysc,
  629. };
  630. /* wd_timer2 */
  631. static struct omap_hwmod omap44xx_wd_timer2_hwmod;
  632. static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
  633. { .irq = 80 + OMAP44XX_IRQ_GIC_START },
  634. };
  635. static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
  636. {
  637. .pa_start = 0x4a314000,
  638. .pa_end = 0x4a31407f,
  639. .flags = ADDR_TYPE_RT
  640. },
  641. };
  642. static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
  643. .name = "uart",
  644. .sysc = &omap44xx_uart_sysc,
  645. };
  646. /* uart1 */
  647. static struct omap_hwmod omap44xx_uart1_hwmod;
  648. static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
  649. { .irq = 72 + OMAP44XX_IRQ_GIC_START },
  650. };
  651. static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
  652. { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
  653. { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
  654. };
  655. static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
  656. {
  657. .pa_start = 0x4806a000,
  658. .pa_end = 0x4806a0ff,
  659. .flags = ADDR_TYPE_RT
  660. },
  661. };
  662. /* l4_per -> uart1 */
  663. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
  664. .master = &omap44xx_l4_per_hwmod,
  665. .slave = &omap44xx_uart1_hwmod,
  666. .clk = "l4_div_ck",
  667. .addr = omap44xx_uart1_addrs,
  668. .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
  669. .user = OCP_USER_MPU | OCP_USER_SDMA,
  670. };
  671. /* uart1 slave ports */
  672. static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
  673. &omap44xx_l4_per__uart1,
  674. };
  675. static struct omap_hwmod omap44xx_uart1_hwmod = {
  676. .name = "uart1",
  677. .class = &omap44xx_uart_hwmod_class,
  678. .mpu_irqs = omap44xx_uart1_irqs,
  679. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
  680. .sdma_reqs = omap44xx_uart1_sdma_reqs,
  681. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
  682. .main_clk = "uart1_fck",
  683. .prcm = {
  684. .omap4 = {
  685. .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
  686. },
  687. },
  688. .slaves = omap44xx_uart1_slaves,
  689. .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
  690. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  691. };
  692. /* uart2 */
  693. static struct omap_hwmod omap44xx_uart2_hwmod;
  694. static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
  695. { .irq = 73 + OMAP44XX_IRQ_GIC_START },
  696. };
  697. static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
  698. { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
  699. { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
  700. };
  701. static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
  702. {
  703. .pa_start = 0x4806c000,
  704. .pa_end = 0x4806c0ff,
  705. .flags = ADDR_TYPE_RT
  706. },
  707. };
  708. /* l4_wkup -> wd_timer2 */
  709. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
  710. .master = &omap44xx_l4_wkup_hwmod,
  711. .slave = &omap44xx_wd_timer2_hwmod,
  712. .clk = "l4_wkup_clk_mux_ck",
  713. .addr = omap44xx_wd_timer2_addrs,
  714. .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
  715. .user = OCP_USER_MPU | OCP_USER_SDMA,
  716. };
  717. /* wd_timer2 slave ports */
  718. static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
  719. &omap44xx_l4_wkup__wd_timer2,
  720. };
  721. static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
  722. .name = "wd_timer2",
  723. .class = &omap44xx_wd_timer_hwmod_class,
  724. .mpu_irqs = omap44xx_wd_timer2_irqs,
  725. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
  726. .main_clk = "wd_timer2_fck",
  727. .prcm = {
  728. .omap4 = {
  729. .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
  730. },
  731. },
  732. .slaves = omap44xx_wd_timer2_slaves,
  733. .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
  734. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  735. };
  736. /* wd_timer3 */
  737. static struct omap_hwmod omap44xx_wd_timer3_hwmod;
  738. static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
  739. { .irq = 36 + OMAP44XX_IRQ_GIC_START },
  740. };
  741. static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
  742. {
  743. .pa_start = 0x40130000,
  744. .pa_end = 0x4013007f,
  745. .flags = ADDR_TYPE_RT
  746. },
  747. };
  748. /* l4_per -> uart2 */
  749. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
  750. .master = &omap44xx_l4_per_hwmod,
  751. .slave = &omap44xx_uart2_hwmod,
  752. .clk = "l4_div_ck",
  753. .addr = omap44xx_uart2_addrs,
  754. .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
  755. .user = OCP_USER_MPU | OCP_USER_SDMA,
  756. };
  757. /* uart2 slave ports */
  758. static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
  759. &omap44xx_l4_per__uart2,
  760. };
  761. static struct omap_hwmod omap44xx_uart2_hwmod = {
  762. .name = "uart2",
  763. .class = &omap44xx_uart_hwmod_class,
  764. .mpu_irqs = omap44xx_uart2_irqs,
  765. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
  766. .sdma_reqs = omap44xx_uart2_sdma_reqs,
  767. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
  768. .main_clk = "uart2_fck",
  769. .prcm = {
  770. .omap4 = {
  771. .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
  772. },
  773. },
  774. .slaves = omap44xx_uart2_slaves,
  775. .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
  776. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  777. };
  778. /* uart3 */
  779. static struct omap_hwmod omap44xx_uart3_hwmod;
  780. static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
  781. { .irq = 74 + OMAP44XX_IRQ_GIC_START },
  782. };
  783. static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
  784. { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
  785. { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
  786. };
  787. static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
  788. {
  789. .pa_start = 0x48020000,
  790. .pa_end = 0x480200ff,
  791. .flags = ADDR_TYPE_RT
  792. },
  793. };
  794. /* l4_abe -> wd_timer3 */
  795. static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
  796. .master = &omap44xx_l4_abe_hwmod,
  797. .slave = &omap44xx_wd_timer3_hwmod,
  798. .clk = "ocp_abe_iclk",
  799. .addr = omap44xx_wd_timer3_addrs,
  800. .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
  801. .user = OCP_USER_MPU,
  802. };
  803. /* l4_abe -> wd_timer3 (dma) */
  804. static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
  805. {
  806. .pa_start = 0x49030000,
  807. .pa_end = 0x4903007f,
  808. .flags = ADDR_TYPE_RT
  809. },
  810. };
  811. /* l4_per -> uart3 */
  812. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
  813. .master = &omap44xx_l4_per_hwmod,
  814. .slave = &omap44xx_uart3_hwmod,
  815. .clk = "l4_div_ck",
  816. .addr = omap44xx_uart3_addrs,
  817. .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
  818. .user = OCP_USER_MPU | OCP_USER_SDMA,
  819. };
  820. /* uart3 slave ports */
  821. static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
  822. &omap44xx_l4_per__uart3,
  823. };
  824. static struct omap_hwmod omap44xx_uart3_hwmod = {
  825. .name = "uart3",
  826. .class = &omap44xx_uart_hwmod_class,
  827. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  828. .mpu_irqs = omap44xx_uart3_irqs,
  829. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
  830. .sdma_reqs = omap44xx_uart3_sdma_reqs,
  831. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
  832. .main_clk = "uart3_fck",
  833. .prcm = {
  834. .omap4 = {
  835. .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
  836. },
  837. },
  838. .slaves = omap44xx_uart3_slaves,
  839. .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
  840. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  841. };
  842. /* uart4 */
  843. static struct omap_hwmod omap44xx_uart4_hwmod;
  844. static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
  845. { .irq = 70 + OMAP44XX_IRQ_GIC_START },
  846. };
  847. static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
  848. { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
  849. { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
  850. };
  851. static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
  852. {
  853. .pa_start = 0x4806e000,
  854. .pa_end = 0x4806e0ff,
  855. .flags = ADDR_TYPE_RT
  856. },
  857. };
  858. static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
  859. .master = &omap44xx_l4_abe_hwmod,
  860. .slave = &omap44xx_wd_timer3_hwmod,
  861. .clk = "ocp_abe_iclk",
  862. .addr = omap44xx_wd_timer3_dma_addrs,
  863. .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
  864. .user = OCP_USER_SDMA,
  865. };
  866. /* wd_timer3 slave ports */
  867. static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
  868. &omap44xx_l4_abe__wd_timer3,
  869. &omap44xx_l4_abe__wd_timer3_dma,
  870. };
  871. static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
  872. .name = "wd_timer3",
  873. .class = &omap44xx_wd_timer_hwmod_class,
  874. .mpu_irqs = omap44xx_wd_timer3_irqs,
  875. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
  876. .main_clk = "wd_timer3_fck",
  877. .prcm = {
  878. .omap4 = {
  879. .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
  880. },
  881. },
  882. .slaves = omap44xx_wd_timer3_slaves,
  883. .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
  884. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  885. };
  886. /* l4_per -> uart4 */
  887. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
  888. .master = &omap44xx_l4_per_hwmod,
  889. .slave = &omap44xx_uart4_hwmod,
  890. .clk = "l4_div_ck",
  891. .addr = omap44xx_uart4_addrs,
  892. .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
  893. .user = OCP_USER_MPU | OCP_USER_SDMA,
  894. };
  895. /* uart4 slave ports */
  896. static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
  897. &omap44xx_l4_per__uart4,
  898. };
  899. static struct omap_hwmod omap44xx_uart4_hwmod = {
  900. .name = "uart4",
  901. .class = &omap44xx_uart_hwmod_class,
  902. .mpu_irqs = omap44xx_uart4_irqs,
  903. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
  904. .sdma_reqs = omap44xx_uart4_sdma_reqs,
  905. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
  906. .main_clk = "uart4_fck",
  907. .prcm = {
  908. .omap4 = {
  909. .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
  910. },
  911. },
  912. .slaves = omap44xx_uart4_slaves,
  913. .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
  914. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  915. };
  916. static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
  917. /* dmm class */
  918. &omap44xx_dmm_hwmod,
  919. /* emif_fw class */
  920. &omap44xx_emif_fw_hwmod,
  921. /* l3 class */
  922. &omap44xx_l3_instr_hwmod,
  923. &omap44xx_l3_main_1_hwmod,
  924. &omap44xx_l3_main_2_hwmod,
  925. &omap44xx_l3_main_3_hwmod,
  926. /* l4 class */
  927. &omap44xx_l4_abe_hwmod,
  928. &omap44xx_l4_cfg_hwmod,
  929. &omap44xx_l4_per_hwmod,
  930. &omap44xx_l4_wkup_hwmod,
  931. /* i2c class */
  932. &omap44xx_i2c1_hwmod,
  933. &omap44xx_i2c2_hwmod,
  934. &omap44xx_i2c3_hwmod,
  935. &omap44xx_i2c4_hwmod,
  936. /* mpu_bus class */
  937. &omap44xx_mpu_private_hwmod,
  938. /* mpu class */
  939. &omap44xx_mpu_hwmod,
  940. /* wd_timer class */
  941. &omap44xx_wd_timer2_hwmod,
  942. &omap44xx_wd_timer3_hwmod,
  943. /* uart class */
  944. &omap44xx_uart1_hwmod,
  945. &omap44xx_uart2_hwmod,
  946. &omap44xx_uart3_hwmod,
  947. &omap44xx_uart4_hwmod,
  948. NULL,
  949. };
  950. int __init omap44xx_hwmod_init(void)
  951. {
  952. return omap_hwmod_init(omap44xx_hwmods);
  953. }