omap_hwmod_3xxx_data.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763
  1. /*
  2. * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
  3. *
  4. * Copyright (C) 2009-2010 Nokia Corporation
  5. * Paul Walmsley
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * The data in this file should be completely autogeneratable from
  12. * the TI hardware database or other technical documentation.
  13. *
  14. * XXX these should be marked initdata for multi-OMAP kernels
  15. */
  16. #include <plat/omap_hwmod.h>
  17. #include <mach/irqs.h>
  18. #include <plat/cpu.h>
  19. #include <plat/dma.h>
  20. #include <plat/serial.h>
  21. #include <plat/l4_3xxx.h>
  22. #include <plat/i2c.h>
  23. #include <plat/omap34xx.h>
  24. #include "omap_hwmod_common_data.h"
  25. #include "prm-regbits-34xx.h"
  26. #include "cm-regbits-34xx.h"
  27. /*
  28. * OMAP3xxx hardware module integration data
  29. *
  30. * ALl of the data in this section should be autogeneratable from the
  31. * TI hardware database or other technical documentation. Data that
  32. * is driver-specific or driver-kernel integration-specific belongs
  33. * elsewhere.
  34. */
  35. static struct omap_hwmod omap3xxx_mpu_hwmod;
  36. static struct omap_hwmod omap3xxx_iva_hwmod;
  37. static struct omap_hwmod omap3xxx_l3_main_hwmod;
  38. static struct omap_hwmod omap3xxx_l4_core_hwmod;
  39. static struct omap_hwmod omap3xxx_l4_per_hwmod;
  40. static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  41. static struct omap_hwmod omap3xxx_i2c1_hwmod;
  42. static struct omap_hwmod omap3xxx_i2c2_hwmod;
  43. static struct omap_hwmod omap3xxx_i2c3_hwmod;
  44. /* L3 -> L4_CORE interface */
  45. static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  46. .master = &omap3xxx_l3_main_hwmod,
  47. .slave = &omap3xxx_l4_core_hwmod,
  48. .user = OCP_USER_MPU | OCP_USER_SDMA,
  49. };
  50. /* L3 -> L4_PER interface */
  51. static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  52. .master = &omap3xxx_l3_main_hwmod,
  53. .slave = &omap3xxx_l4_per_hwmod,
  54. .user = OCP_USER_MPU | OCP_USER_SDMA,
  55. };
  56. /* MPU -> L3 interface */
  57. static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
  58. .master = &omap3xxx_mpu_hwmod,
  59. .slave = &omap3xxx_l3_main_hwmod,
  60. .user = OCP_USER_MPU,
  61. };
  62. /* Slave interfaces on the L3 interconnect */
  63. static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
  64. &omap3xxx_mpu__l3_main,
  65. };
  66. /* Master interfaces on the L3 interconnect */
  67. static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
  68. &omap3xxx_l3_main__l4_core,
  69. &omap3xxx_l3_main__l4_per,
  70. };
  71. /* L3 */
  72. static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  73. .name = "l3_main",
  74. .class = &l3_hwmod_class,
  75. .masters = omap3xxx_l3_main_masters,
  76. .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
  77. .slaves = omap3xxx_l3_main_slaves,
  78. .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
  79. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  80. .flags = HWMOD_NO_IDLEST,
  81. };
  82. static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
  83. static struct omap_hwmod omap3xxx_uart1_hwmod;
  84. static struct omap_hwmod omap3xxx_uart2_hwmod;
  85. static struct omap_hwmod omap3xxx_uart3_hwmod;
  86. static struct omap_hwmod omap3xxx_uart4_hwmod;
  87. /* L4_CORE -> L4_WKUP interface */
  88. static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
  89. .master = &omap3xxx_l4_core_hwmod,
  90. .slave = &omap3xxx_l4_wkup_hwmod,
  91. .user = OCP_USER_MPU | OCP_USER_SDMA,
  92. };
  93. /* L4 CORE -> UART1 interface */
  94. static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
  95. {
  96. .pa_start = OMAP3_UART1_BASE,
  97. .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
  98. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  99. },
  100. };
  101. static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
  102. .master = &omap3xxx_l4_core_hwmod,
  103. .slave = &omap3xxx_uart1_hwmod,
  104. .clk = "uart1_ick",
  105. .addr = omap3xxx_uart1_addr_space,
  106. .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
  107. .user = OCP_USER_MPU | OCP_USER_SDMA,
  108. };
  109. /* L4 CORE -> UART2 interface */
  110. static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
  111. {
  112. .pa_start = OMAP3_UART2_BASE,
  113. .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
  114. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  115. },
  116. };
  117. static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
  118. .master = &omap3xxx_l4_core_hwmod,
  119. .slave = &omap3xxx_uart2_hwmod,
  120. .clk = "uart2_ick",
  121. .addr = omap3xxx_uart2_addr_space,
  122. .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
  123. .user = OCP_USER_MPU | OCP_USER_SDMA,
  124. };
  125. /* L4 PER -> UART3 interface */
  126. static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
  127. {
  128. .pa_start = OMAP3_UART3_BASE,
  129. .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
  130. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  131. },
  132. };
  133. static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
  134. .master = &omap3xxx_l4_per_hwmod,
  135. .slave = &omap3xxx_uart3_hwmod,
  136. .clk = "uart3_ick",
  137. .addr = omap3xxx_uart3_addr_space,
  138. .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
  139. .user = OCP_USER_MPU | OCP_USER_SDMA,
  140. };
  141. /* L4 PER -> UART4 interface */
  142. static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
  143. {
  144. .pa_start = OMAP3_UART4_BASE,
  145. .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
  146. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  147. },
  148. };
  149. static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
  150. .master = &omap3xxx_l4_per_hwmod,
  151. .slave = &omap3xxx_uart4_hwmod,
  152. .clk = "uart4_ick",
  153. .addr = omap3xxx_uart4_addr_space,
  154. .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
  155. .user = OCP_USER_MPU | OCP_USER_SDMA,
  156. };
  157. /* I2C IP block address space length (in bytes) */
  158. #define OMAP2_I2C_AS_LEN 128
  159. /* L4 CORE -> I2C1 interface */
  160. static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
  161. {
  162. .pa_start = 0x48070000,
  163. .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
  164. .flags = ADDR_TYPE_RT,
  165. },
  166. };
  167. static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
  168. .master = &omap3xxx_l4_core_hwmod,
  169. .slave = &omap3xxx_i2c1_hwmod,
  170. .clk = "i2c1_ick",
  171. .addr = omap3xxx_i2c1_addr_space,
  172. .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
  173. .fw = {
  174. .omap2 = {
  175. .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
  176. .l4_prot_group = 7,
  177. .flags = OMAP_FIREWALL_L4,
  178. }
  179. },
  180. .user = OCP_USER_MPU | OCP_USER_SDMA,
  181. };
  182. /* L4 CORE -> I2C2 interface */
  183. static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
  184. {
  185. .pa_start = 0x48072000,
  186. .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
  187. .flags = ADDR_TYPE_RT,
  188. },
  189. };
  190. static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
  191. .master = &omap3xxx_l4_core_hwmod,
  192. .slave = &omap3xxx_i2c2_hwmod,
  193. .clk = "i2c2_ick",
  194. .addr = omap3xxx_i2c2_addr_space,
  195. .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
  196. .fw = {
  197. .omap2 = {
  198. .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
  199. .l4_prot_group = 7,
  200. .flags = OMAP_FIREWALL_L4,
  201. }
  202. },
  203. .user = OCP_USER_MPU | OCP_USER_SDMA,
  204. };
  205. /* L4 CORE -> I2C3 interface */
  206. static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
  207. {
  208. .pa_start = 0x48060000,
  209. .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
  210. .flags = ADDR_TYPE_RT,
  211. },
  212. };
  213. static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
  214. .master = &omap3xxx_l4_core_hwmod,
  215. .slave = &omap3xxx_i2c3_hwmod,
  216. .clk = "i2c3_ick",
  217. .addr = omap3xxx_i2c3_addr_space,
  218. .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
  219. .fw = {
  220. .omap2 = {
  221. .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
  222. .l4_prot_group = 7,
  223. .flags = OMAP_FIREWALL_L4,
  224. }
  225. },
  226. .user = OCP_USER_MPU | OCP_USER_SDMA,
  227. };
  228. /* Slave interfaces on the L4_CORE interconnect */
  229. static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
  230. &omap3xxx_l3_main__l4_core,
  231. };
  232. /* Master interfaces on the L4_CORE interconnect */
  233. static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
  234. &omap3xxx_l4_core__l4_wkup,
  235. &omap3_l4_core__uart1,
  236. &omap3_l4_core__uart2,
  237. &omap3_l4_core__i2c1,
  238. &omap3_l4_core__i2c2,
  239. &omap3_l4_core__i2c3,
  240. };
  241. /* L4 CORE */
  242. static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  243. .name = "l4_core",
  244. .class = &l4_hwmod_class,
  245. .masters = omap3xxx_l4_core_masters,
  246. .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
  247. .slaves = omap3xxx_l4_core_slaves,
  248. .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
  249. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  250. .flags = HWMOD_NO_IDLEST,
  251. };
  252. /* Slave interfaces on the L4_PER interconnect */
  253. static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
  254. &omap3xxx_l3_main__l4_per,
  255. };
  256. /* Master interfaces on the L4_PER interconnect */
  257. static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
  258. &omap3_l4_per__uart3,
  259. &omap3_l4_per__uart4,
  260. };
  261. /* L4 PER */
  262. static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  263. .name = "l4_per",
  264. .class = &l4_hwmod_class,
  265. .masters = omap3xxx_l4_per_masters,
  266. .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
  267. .slaves = omap3xxx_l4_per_slaves,
  268. .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
  269. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  270. .flags = HWMOD_NO_IDLEST,
  271. };
  272. /* Slave interfaces on the L4_WKUP interconnect */
  273. static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
  274. &omap3xxx_l4_core__l4_wkup,
  275. };
  276. /* Master interfaces on the L4_WKUP interconnect */
  277. static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
  278. };
  279. /* L4 WKUP */
  280. static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  281. .name = "l4_wkup",
  282. .class = &l4_hwmod_class,
  283. .masters = omap3xxx_l4_wkup_masters,
  284. .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
  285. .slaves = omap3xxx_l4_wkup_slaves,
  286. .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
  287. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  288. .flags = HWMOD_NO_IDLEST,
  289. };
  290. /* Master interfaces on the MPU device */
  291. static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
  292. &omap3xxx_mpu__l3_main,
  293. };
  294. /* MPU */
  295. static struct omap_hwmod omap3xxx_mpu_hwmod = {
  296. .name = "mpu",
  297. .class = &mpu_hwmod_class,
  298. .main_clk = "arm_fck",
  299. .masters = omap3xxx_mpu_masters,
  300. .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
  301. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  302. };
  303. /*
  304. * IVA2_2 interface data
  305. */
  306. /* IVA2 <- L3 interface */
  307. static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
  308. .master = &omap3xxx_l3_main_hwmod,
  309. .slave = &omap3xxx_iva_hwmod,
  310. .clk = "iva2_ck",
  311. .user = OCP_USER_MPU | OCP_USER_SDMA,
  312. };
  313. static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
  314. &omap3xxx_l3__iva,
  315. };
  316. /*
  317. * IVA2 (IVA2)
  318. */
  319. static struct omap_hwmod omap3xxx_iva_hwmod = {
  320. .name = "iva",
  321. .class = &iva_hwmod_class,
  322. .masters = omap3xxx_iva_masters,
  323. .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
  324. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  325. };
  326. /* l4_wkup -> wd_timer2 */
  327. static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
  328. {
  329. .pa_start = 0x48314000,
  330. .pa_end = 0x4831407f,
  331. .flags = ADDR_TYPE_RT
  332. },
  333. };
  334. static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
  335. .master = &omap3xxx_l4_wkup_hwmod,
  336. .slave = &omap3xxx_wd_timer2_hwmod,
  337. .clk = "wdt2_ick",
  338. .addr = omap3xxx_wd_timer2_addrs,
  339. .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
  340. .user = OCP_USER_MPU | OCP_USER_SDMA,
  341. };
  342. /*
  343. * 'wd_timer' class
  344. * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  345. * overflow condition
  346. */
  347. static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
  348. .rev_offs = 0x0000,
  349. .sysc_offs = 0x0010,
  350. .syss_offs = 0x0014,
  351. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
  352. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  353. SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
  354. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  355. .sysc_fields = &omap_hwmod_sysc_type1,
  356. };
  357. /* I2C common */
  358. static struct omap_hwmod_class_sysconfig i2c_sysc = {
  359. .rev_offs = 0x00,
  360. .sysc_offs = 0x20,
  361. .syss_offs = 0x10,
  362. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  363. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  364. SYSC_HAS_AUTOIDLE),
  365. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  366. .sysc_fields = &omap_hwmod_sysc_type1,
  367. };
  368. static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
  369. .name = "wd_timer",
  370. .sysc = &omap3xxx_wd_timer_sysc,
  371. };
  372. /* wd_timer2 */
  373. static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
  374. &omap3xxx_l4_wkup__wd_timer2,
  375. };
  376. static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
  377. .name = "wd_timer2",
  378. .class = &omap3xxx_wd_timer_hwmod_class,
  379. .main_clk = "wdt2_fck",
  380. .prcm = {
  381. .omap2 = {
  382. .prcm_reg_id = 1,
  383. .module_bit = OMAP3430_EN_WDT2_SHIFT,
  384. .module_offs = WKUP_MOD,
  385. .idlest_reg_id = 1,
  386. .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
  387. },
  388. },
  389. .slaves = omap3xxx_wd_timer2_slaves,
  390. .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
  391. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  392. };
  393. /* UART common */
  394. static struct omap_hwmod_class_sysconfig uart_sysc = {
  395. .rev_offs = 0x50,
  396. .sysc_offs = 0x54,
  397. .syss_offs = 0x58,
  398. .sysc_flags = (SYSC_HAS_SIDLEMODE |
  399. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  400. SYSC_HAS_AUTOIDLE),
  401. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  402. .sysc_fields = &omap_hwmod_sysc_type1,
  403. };
  404. static struct omap_hwmod_class uart_class = {
  405. .name = "uart",
  406. .sysc = &uart_sysc,
  407. };
  408. /* UART1 */
  409. static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
  410. { .irq = INT_24XX_UART1_IRQ, },
  411. };
  412. static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
  413. { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
  414. { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
  415. };
  416. static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
  417. &omap3_l4_core__uart1,
  418. };
  419. static struct omap_hwmod omap3xxx_uart1_hwmod = {
  420. .name = "uart1",
  421. .mpu_irqs = uart1_mpu_irqs,
  422. .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
  423. .sdma_reqs = uart1_sdma_reqs,
  424. .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
  425. .main_clk = "uart1_fck",
  426. .prcm = {
  427. .omap2 = {
  428. .module_offs = CORE_MOD,
  429. .prcm_reg_id = 1,
  430. .module_bit = OMAP3430_EN_UART1_SHIFT,
  431. .idlest_reg_id = 1,
  432. .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
  433. },
  434. },
  435. .slaves = omap3xxx_uart1_slaves,
  436. .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
  437. .class = &uart_class,
  438. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  439. };
  440. /* UART2 */
  441. static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
  442. { .irq = INT_24XX_UART2_IRQ, },
  443. };
  444. static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
  445. { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
  446. { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
  447. };
  448. static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
  449. &omap3_l4_core__uart2,
  450. };
  451. static struct omap_hwmod omap3xxx_uart2_hwmod = {
  452. .name = "uart2",
  453. .mpu_irqs = uart2_mpu_irqs,
  454. .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
  455. .sdma_reqs = uart2_sdma_reqs,
  456. .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
  457. .main_clk = "uart2_fck",
  458. .prcm = {
  459. .omap2 = {
  460. .module_offs = CORE_MOD,
  461. .prcm_reg_id = 1,
  462. .module_bit = OMAP3430_EN_UART2_SHIFT,
  463. .idlest_reg_id = 1,
  464. .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
  465. },
  466. },
  467. .slaves = omap3xxx_uart2_slaves,
  468. .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
  469. .class = &uart_class,
  470. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  471. };
  472. /* UART3 */
  473. static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
  474. { .irq = INT_24XX_UART3_IRQ, },
  475. };
  476. static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
  477. { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
  478. { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
  479. };
  480. static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
  481. &omap3_l4_per__uart3,
  482. };
  483. static struct omap_hwmod omap3xxx_uart3_hwmod = {
  484. .name = "uart3",
  485. .mpu_irqs = uart3_mpu_irqs,
  486. .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
  487. .sdma_reqs = uart3_sdma_reqs,
  488. .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
  489. .main_clk = "uart3_fck",
  490. .prcm = {
  491. .omap2 = {
  492. .module_offs = OMAP3430_PER_MOD,
  493. .prcm_reg_id = 1,
  494. .module_bit = OMAP3430_EN_UART3_SHIFT,
  495. .idlest_reg_id = 1,
  496. .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
  497. },
  498. },
  499. .slaves = omap3xxx_uart3_slaves,
  500. .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
  501. .class = &uart_class,
  502. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  503. };
  504. /* UART4 */
  505. static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
  506. { .irq = INT_36XX_UART4_IRQ, },
  507. };
  508. static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
  509. { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
  510. { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
  511. };
  512. static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
  513. &omap3_l4_per__uart4,
  514. };
  515. static struct omap_hwmod omap3xxx_uart4_hwmod = {
  516. .name = "uart4",
  517. .mpu_irqs = uart4_mpu_irqs,
  518. .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
  519. .sdma_reqs = uart4_sdma_reqs,
  520. .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
  521. .main_clk = "uart4_fck",
  522. .prcm = {
  523. .omap2 = {
  524. .module_offs = OMAP3430_PER_MOD,
  525. .prcm_reg_id = 1,
  526. .module_bit = OMAP3630_EN_UART4_SHIFT,
  527. .idlest_reg_id = 1,
  528. .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
  529. },
  530. },
  531. .slaves = omap3xxx_uart4_slaves,
  532. .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
  533. .class = &uart_class,
  534. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
  535. };
  536. static struct omap_hwmod_class i2c_class = {
  537. .name = "i2c",
  538. .sysc = &i2c_sysc,
  539. };
  540. /* I2C1 */
  541. static struct omap_i2c_dev_attr i2c1_dev_attr = {
  542. .fifo_depth = 8, /* bytes */
  543. };
  544. static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
  545. { .irq = INT_24XX_I2C1_IRQ, },
  546. };
  547. static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
  548. { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
  549. { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
  550. };
  551. static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
  552. &omap3_l4_core__i2c1,
  553. };
  554. static struct omap_hwmod omap3xxx_i2c1_hwmod = {
  555. .name = "i2c1",
  556. .mpu_irqs = i2c1_mpu_irqs,
  557. .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
  558. .sdma_reqs = i2c1_sdma_reqs,
  559. .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
  560. .main_clk = "i2c1_fck",
  561. .prcm = {
  562. .omap2 = {
  563. .module_offs = CORE_MOD,
  564. .prcm_reg_id = 1,
  565. .module_bit = OMAP3430_EN_I2C1_SHIFT,
  566. .idlest_reg_id = 1,
  567. .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
  568. },
  569. },
  570. .slaves = omap3xxx_i2c1_slaves,
  571. .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
  572. .class = &i2c_class,
  573. .dev_attr = &i2c1_dev_attr,
  574. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  575. };
  576. /* I2C2 */
  577. static struct omap_i2c_dev_attr i2c2_dev_attr = {
  578. .fifo_depth = 8, /* bytes */
  579. };
  580. static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
  581. { .irq = INT_24XX_I2C2_IRQ, },
  582. };
  583. static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
  584. { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
  585. { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
  586. };
  587. static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
  588. &omap3_l4_core__i2c2,
  589. };
  590. static struct omap_hwmod omap3xxx_i2c2_hwmod = {
  591. .name = "i2c2",
  592. .mpu_irqs = i2c2_mpu_irqs,
  593. .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
  594. .sdma_reqs = i2c2_sdma_reqs,
  595. .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
  596. .main_clk = "i2c2_fck",
  597. .prcm = {
  598. .omap2 = {
  599. .module_offs = CORE_MOD,
  600. .prcm_reg_id = 1,
  601. .module_bit = OMAP3430_EN_I2C2_SHIFT,
  602. .idlest_reg_id = 1,
  603. .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
  604. },
  605. },
  606. .slaves = omap3xxx_i2c2_slaves,
  607. .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
  608. .class = &i2c_class,
  609. .dev_attr = &i2c2_dev_attr,
  610. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  611. };
  612. /* I2C3 */
  613. static struct omap_i2c_dev_attr i2c3_dev_attr = {
  614. .fifo_depth = 64, /* bytes */
  615. };
  616. static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
  617. { .irq = INT_34XX_I2C3_IRQ, },
  618. };
  619. static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
  620. { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
  621. { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
  622. };
  623. static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
  624. &omap3_l4_core__i2c3,
  625. };
  626. static struct omap_hwmod omap3xxx_i2c3_hwmod = {
  627. .name = "i2c3",
  628. .mpu_irqs = i2c3_mpu_irqs,
  629. .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
  630. .sdma_reqs = i2c3_sdma_reqs,
  631. .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
  632. .main_clk = "i2c3_fck",
  633. .prcm = {
  634. .omap2 = {
  635. .module_offs = CORE_MOD,
  636. .prcm_reg_id = 1,
  637. .module_bit = OMAP3430_EN_I2C3_SHIFT,
  638. .idlest_reg_id = 1,
  639. .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
  640. },
  641. },
  642. .slaves = omap3xxx_i2c3_slaves,
  643. .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
  644. .class = &i2c_class,
  645. .dev_attr = &i2c3_dev_attr,
  646. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  647. };
  648. static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
  649. &omap3xxx_l3_main_hwmod,
  650. &omap3xxx_l4_core_hwmod,
  651. &omap3xxx_l4_per_hwmod,
  652. &omap3xxx_l4_wkup_hwmod,
  653. &omap3xxx_mpu_hwmod,
  654. &omap3xxx_iva_hwmod,
  655. &omap3xxx_wd_timer2_hwmod,
  656. &omap3xxx_uart1_hwmod,
  657. &omap3xxx_uart2_hwmod,
  658. &omap3xxx_uart3_hwmod,
  659. &omap3xxx_uart4_hwmod,
  660. &omap3xxx_i2c1_hwmod,
  661. &omap3xxx_i2c2_hwmod,
  662. &omap3xxx_i2c3_hwmod,
  663. NULL,
  664. };
  665. int __init omap3xxx_hwmod_init(void)
  666. {
  667. return omap_hwmod_init(omap3xxx_hwmods);
  668. }