devices.c 25 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/devices.c
  3. *
  4. * OMAP2 platform device setup/initialization
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/io.h>
  15. #include <linux/clk.h>
  16. #include <linux/err.h>
  17. #include <mach/hardware.h>
  18. #include <mach/irqs.h>
  19. #include <asm/mach-types.h>
  20. #include <asm/mach/map.h>
  21. #include <asm/pmu.h>
  22. #include <plat/tc.h>
  23. #include <plat/board.h>
  24. #include <plat/mcbsp.h>
  25. #include <mach/gpio.h>
  26. #include <plat/mmc.h>
  27. #include <plat/dma.h>
  28. #include <plat/omap_hwmod.h>
  29. #include <plat/omap_device.h>
  30. #include "mux.h"
  31. #include "control.h"
  32. #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
  33. static struct resource cam_resources[] = {
  34. {
  35. .start = OMAP24XX_CAMERA_BASE,
  36. .end = OMAP24XX_CAMERA_BASE + 0xfff,
  37. .flags = IORESOURCE_MEM,
  38. },
  39. {
  40. .start = INT_24XX_CAM_IRQ,
  41. .flags = IORESOURCE_IRQ,
  42. }
  43. };
  44. static struct platform_device omap_cam_device = {
  45. .name = "omap24xxcam",
  46. .id = -1,
  47. .num_resources = ARRAY_SIZE(cam_resources),
  48. .resource = cam_resources,
  49. };
  50. static inline void omap_init_camera(void)
  51. {
  52. platform_device_register(&omap_cam_device);
  53. }
  54. #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
  55. static struct resource omap3isp_resources[] = {
  56. {
  57. .start = OMAP3430_ISP_BASE,
  58. .end = OMAP3430_ISP_END,
  59. .flags = IORESOURCE_MEM,
  60. },
  61. {
  62. .start = OMAP3430_ISP_CBUFF_BASE,
  63. .end = OMAP3430_ISP_CBUFF_END,
  64. .flags = IORESOURCE_MEM,
  65. },
  66. {
  67. .start = OMAP3430_ISP_CCP2_BASE,
  68. .end = OMAP3430_ISP_CCP2_END,
  69. .flags = IORESOURCE_MEM,
  70. },
  71. {
  72. .start = OMAP3430_ISP_CCDC_BASE,
  73. .end = OMAP3430_ISP_CCDC_END,
  74. .flags = IORESOURCE_MEM,
  75. },
  76. {
  77. .start = OMAP3430_ISP_HIST_BASE,
  78. .end = OMAP3430_ISP_HIST_END,
  79. .flags = IORESOURCE_MEM,
  80. },
  81. {
  82. .start = OMAP3430_ISP_H3A_BASE,
  83. .end = OMAP3430_ISP_H3A_END,
  84. .flags = IORESOURCE_MEM,
  85. },
  86. {
  87. .start = OMAP3430_ISP_PREV_BASE,
  88. .end = OMAP3430_ISP_PREV_END,
  89. .flags = IORESOURCE_MEM,
  90. },
  91. {
  92. .start = OMAP3430_ISP_RESZ_BASE,
  93. .end = OMAP3430_ISP_RESZ_END,
  94. .flags = IORESOURCE_MEM,
  95. },
  96. {
  97. .start = OMAP3430_ISP_SBL_BASE,
  98. .end = OMAP3430_ISP_SBL_END,
  99. .flags = IORESOURCE_MEM,
  100. },
  101. {
  102. .start = OMAP3430_ISP_CSI2A_BASE,
  103. .end = OMAP3430_ISP_CSI2A_END,
  104. .flags = IORESOURCE_MEM,
  105. },
  106. {
  107. .start = OMAP3430_ISP_CSI2PHY_BASE,
  108. .end = OMAP3430_ISP_CSI2PHY_END,
  109. .flags = IORESOURCE_MEM,
  110. },
  111. {
  112. .start = INT_34XX_CAM_IRQ,
  113. .flags = IORESOURCE_IRQ,
  114. }
  115. };
  116. static struct platform_device omap3isp_device = {
  117. .name = "omap3isp",
  118. .id = -1,
  119. .num_resources = ARRAY_SIZE(omap3isp_resources),
  120. .resource = omap3isp_resources,
  121. };
  122. static inline void omap_init_camera(void)
  123. {
  124. platform_device_register(&omap3isp_device);
  125. }
  126. #else
  127. static inline void omap_init_camera(void)
  128. {
  129. }
  130. #endif
  131. #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
  132. #define MBOX_REG_SIZE 0x120
  133. #ifdef CONFIG_ARCH_OMAP2
  134. static struct resource omap2_mbox_resources[] = {
  135. {
  136. .start = OMAP24XX_MAILBOX_BASE,
  137. .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
  138. .flags = IORESOURCE_MEM,
  139. },
  140. {
  141. .start = INT_24XX_MAIL_U0_MPU,
  142. .flags = IORESOURCE_IRQ,
  143. .name = "dsp",
  144. },
  145. {
  146. .start = INT_24XX_MAIL_U3_MPU,
  147. .flags = IORESOURCE_IRQ,
  148. .name = "iva",
  149. },
  150. };
  151. static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
  152. #else
  153. #define omap2_mbox_resources NULL
  154. #define omap2_mbox_resources_sz 0
  155. #endif
  156. #ifdef CONFIG_ARCH_OMAP3
  157. static struct resource omap3_mbox_resources[] = {
  158. {
  159. .start = OMAP34XX_MAILBOX_BASE,
  160. .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
  161. .flags = IORESOURCE_MEM,
  162. },
  163. {
  164. .start = INT_24XX_MAIL_U0_MPU,
  165. .flags = IORESOURCE_IRQ,
  166. .name = "dsp",
  167. },
  168. };
  169. static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
  170. #else
  171. #define omap3_mbox_resources NULL
  172. #define omap3_mbox_resources_sz 0
  173. #endif
  174. #ifdef CONFIG_ARCH_OMAP4
  175. #define OMAP4_MBOX_REG_SIZE 0x130
  176. static struct resource omap4_mbox_resources[] = {
  177. {
  178. .start = OMAP44XX_MAILBOX_BASE,
  179. .end = OMAP44XX_MAILBOX_BASE +
  180. OMAP4_MBOX_REG_SIZE - 1,
  181. .flags = IORESOURCE_MEM,
  182. },
  183. {
  184. .start = OMAP44XX_IRQ_MAIL_U0,
  185. .flags = IORESOURCE_IRQ,
  186. .name = "mbox",
  187. },
  188. };
  189. static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
  190. #else
  191. #define omap4_mbox_resources NULL
  192. #define omap4_mbox_resources_sz 0
  193. #endif
  194. static struct platform_device mbox_device = {
  195. .name = "omap-mailbox",
  196. .id = -1,
  197. };
  198. static inline void omap_init_mbox(void)
  199. {
  200. if (cpu_is_omap24xx()) {
  201. mbox_device.resource = omap2_mbox_resources;
  202. mbox_device.num_resources = omap2_mbox_resources_sz;
  203. } else if (cpu_is_omap34xx()) {
  204. mbox_device.resource = omap3_mbox_resources;
  205. mbox_device.num_resources = omap3_mbox_resources_sz;
  206. } else if (cpu_is_omap44xx()) {
  207. mbox_device.resource = omap4_mbox_resources;
  208. mbox_device.num_resources = omap4_mbox_resources_sz;
  209. } else {
  210. pr_err("%s: platform not supported\n", __func__);
  211. return;
  212. }
  213. platform_device_register(&mbox_device);
  214. }
  215. #else
  216. static inline void omap_init_mbox(void) { }
  217. #endif /* CONFIG_OMAP_MBOX_FWK */
  218. static inline void omap_init_sti(void) {}
  219. #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
  220. static struct platform_device omap_pcm = {
  221. .name = "omap-pcm-audio",
  222. .id = -1,
  223. };
  224. /*
  225. * OMAP2420 has 2 McBSP ports
  226. * OMAP2430 has 5 McBSP ports
  227. * OMAP3 has 5 McBSP ports
  228. * OMAP4 has 4 McBSP ports
  229. */
  230. OMAP_MCBSP_PLATFORM_DEVICE(1);
  231. OMAP_MCBSP_PLATFORM_DEVICE(2);
  232. OMAP_MCBSP_PLATFORM_DEVICE(3);
  233. OMAP_MCBSP_PLATFORM_DEVICE(4);
  234. OMAP_MCBSP_PLATFORM_DEVICE(5);
  235. static void omap_init_audio(void)
  236. {
  237. platform_device_register(&omap_mcbsp1);
  238. platform_device_register(&omap_mcbsp2);
  239. if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
  240. platform_device_register(&omap_mcbsp3);
  241. platform_device_register(&omap_mcbsp4);
  242. }
  243. if (cpu_is_omap243x() || cpu_is_omap34xx())
  244. platform_device_register(&omap_mcbsp5);
  245. platform_device_register(&omap_pcm);
  246. }
  247. #else
  248. static inline void omap_init_audio(void) {}
  249. #endif
  250. #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
  251. #include <plat/mcspi.h>
  252. #define OMAP2_MCSPI1_BASE 0x48098000
  253. #define OMAP2_MCSPI2_BASE 0x4809a000
  254. #define OMAP2_MCSPI3_BASE 0x480b8000
  255. #define OMAP2_MCSPI4_BASE 0x480ba000
  256. #define OMAP4_MCSPI1_BASE 0x48098100
  257. #define OMAP4_MCSPI2_BASE 0x4809a100
  258. #define OMAP4_MCSPI3_BASE 0x480b8100
  259. #define OMAP4_MCSPI4_BASE 0x480ba100
  260. static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
  261. .num_cs = 4,
  262. };
  263. static struct resource omap2_mcspi1_resources[] = {
  264. {
  265. .start = OMAP2_MCSPI1_BASE,
  266. .end = OMAP2_MCSPI1_BASE + 0xff,
  267. .flags = IORESOURCE_MEM,
  268. },
  269. };
  270. static struct platform_device omap2_mcspi1 = {
  271. .name = "omap2_mcspi",
  272. .id = 1,
  273. .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
  274. .resource = omap2_mcspi1_resources,
  275. .dev = {
  276. .platform_data = &omap2_mcspi1_config,
  277. },
  278. };
  279. static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
  280. .num_cs = 2,
  281. };
  282. static struct resource omap2_mcspi2_resources[] = {
  283. {
  284. .start = OMAP2_MCSPI2_BASE,
  285. .end = OMAP2_MCSPI2_BASE + 0xff,
  286. .flags = IORESOURCE_MEM,
  287. },
  288. };
  289. static struct platform_device omap2_mcspi2 = {
  290. .name = "omap2_mcspi",
  291. .id = 2,
  292. .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
  293. .resource = omap2_mcspi2_resources,
  294. .dev = {
  295. .platform_data = &omap2_mcspi2_config,
  296. },
  297. };
  298. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
  299. defined(CONFIG_ARCH_OMAP4)
  300. static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
  301. .num_cs = 2,
  302. };
  303. static struct resource omap2_mcspi3_resources[] = {
  304. {
  305. .start = OMAP2_MCSPI3_BASE,
  306. .end = OMAP2_MCSPI3_BASE + 0xff,
  307. .flags = IORESOURCE_MEM,
  308. },
  309. };
  310. static struct platform_device omap2_mcspi3 = {
  311. .name = "omap2_mcspi",
  312. .id = 3,
  313. .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
  314. .resource = omap2_mcspi3_resources,
  315. .dev = {
  316. .platform_data = &omap2_mcspi3_config,
  317. },
  318. };
  319. #endif
  320. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  321. static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
  322. .num_cs = 1,
  323. };
  324. static struct resource omap2_mcspi4_resources[] = {
  325. {
  326. .start = OMAP2_MCSPI4_BASE,
  327. .end = OMAP2_MCSPI4_BASE + 0xff,
  328. .flags = IORESOURCE_MEM,
  329. },
  330. };
  331. static struct platform_device omap2_mcspi4 = {
  332. .name = "omap2_mcspi",
  333. .id = 4,
  334. .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
  335. .resource = omap2_mcspi4_resources,
  336. .dev = {
  337. .platform_data = &omap2_mcspi4_config,
  338. },
  339. };
  340. #endif
  341. #ifdef CONFIG_ARCH_OMAP4
  342. static inline void omap4_mcspi_fixup(void)
  343. {
  344. omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
  345. omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
  346. omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
  347. omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
  348. omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
  349. omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
  350. omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
  351. omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
  352. }
  353. #else
  354. static inline void omap4_mcspi_fixup(void)
  355. {
  356. }
  357. #endif
  358. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
  359. defined(CONFIG_ARCH_OMAP4)
  360. static inline void omap2_mcspi3_init(void)
  361. {
  362. platform_device_register(&omap2_mcspi3);
  363. }
  364. #else
  365. static inline void omap2_mcspi3_init(void)
  366. {
  367. }
  368. #endif
  369. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  370. static inline void omap2_mcspi4_init(void)
  371. {
  372. platform_device_register(&omap2_mcspi4);
  373. }
  374. #else
  375. static inline void omap2_mcspi4_init(void)
  376. {
  377. }
  378. #endif
  379. static void omap_init_mcspi(void)
  380. {
  381. if (cpu_is_omap44xx())
  382. omap4_mcspi_fixup();
  383. platform_device_register(&omap2_mcspi1);
  384. platform_device_register(&omap2_mcspi2);
  385. if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
  386. omap2_mcspi3_init();
  387. if (cpu_is_omap343x() || cpu_is_omap44xx())
  388. omap2_mcspi4_init();
  389. }
  390. #else
  391. static inline void omap_init_mcspi(void) {}
  392. #endif
  393. static struct resource omap2_pmu_resource = {
  394. .start = 3,
  395. .end = 3,
  396. .flags = IORESOURCE_IRQ,
  397. };
  398. static struct resource omap3_pmu_resource = {
  399. .start = INT_34XX_BENCH_MPU_EMUL,
  400. .end = INT_34XX_BENCH_MPU_EMUL,
  401. .flags = IORESOURCE_IRQ,
  402. };
  403. static struct platform_device omap_pmu_device = {
  404. .name = "arm-pmu",
  405. .id = ARM_PMU_DEVICE_CPU,
  406. .num_resources = 1,
  407. };
  408. static void omap_init_pmu(void)
  409. {
  410. if (cpu_is_omap24xx())
  411. omap_pmu_device.resource = &omap2_pmu_resource;
  412. else if (cpu_is_omap34xx())
  413. omap_pmu_device.resource = &omap3_pmu_resource;
  414. else
  415. return;
  416. platform_device_register(&omap_pmu_device);
  417. }
  418. #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
  419. #ifdef CONFIG_ARCH_OMAP2
  420. static struct resource omap2_sham_resources[] = {
  421. {
  422. .start = OMAP24XX_SEC_SHA1MD5_BASE,
  423. .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
  424. .flags = IORESOURCE_MEM,
  425. },
  426. {
  427. .start = INT_24XX_SHA1MD5,
  428. .flags = IORESOURCE_IRQ,
  429. }
  430. };
  431. static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
  432. #else
  433. #define omap2_sham_resources NULL
  434. #define omap2_sham_resources_sz 0
  435. #endif
  436. #ifdef CONFIG_ARCH_OMAP3
  437. static struct resource omap3_sham_resources[] = {
  438. {
  439. .start = OMAP34XX_SEC_SHA1MD5_BASE,
  440. .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
  441. .flags = IORESOURCE_MEM,
  442. },
  443. {
  444. .start = INT_34XX_SHA1MD52_IRQ,
  445. .flags = IORESOURCE_IRQ,
  446. },
  447. {
  448. .start = OMAP34XX_DMA_SHA1MD5_RX,
  449. .flags = IORESOURCE_DMA,
  450. }
  451. };
  452. static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
  453. #else
  454. #define omap3_sham_resources NULL
  455. #define omap3_sham_resources_sz 0
  456. #endif
  457. static struct platform_device sham_device = {
  458. .name = "omap-sham",
  459. .id = -1,
  460. };
  461. static void omap_init_sham(void)
  462. {
  463. if (cpu_is_omap24xx()) {
  464. sham_device.resource = omap2_sham_resources;
  465. sham_device.num_resources = omap2_sham_resources_sz;
  466. } else if (cpu_is_omap34xx()) {
  467. sham_device.resource = omap3_sham_resources;
  468. sham_device.num_resources = omap3_sham_resources_sz;
  469. } else {
  470. pr_err("%s: platform not supported\n", __func__);
  471. return;
  472. }
  473. platform_device_register(&sham_device);
  474. }
  475. #else
  476. static inline void omap_init_sham(void) { }
  477. #endif
  478. #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
  479. #ifdef CONFIG_ARCH_OMAP2
  480. static struct resource omap2_aes_resources[] = {
  481. {
  482. .start = OMAP24XX_SEC_AES_BASE,
  483. .end = OMAP24XX_SEC_AES_BASE + 0x4C,
  484. .flags = IORESOURCE_MEM,
  485. },
  486. {
  487. .start = OMAP24XX_DMA_AES_TX,
  488. .flags = IORESOURCE_DMA,
  489. },
  490. {
  491. .start = OMAP24XX_DMA_AES_RX,
  492. .flags = IORESOURCE_DMA,
  493. }
  494. };
  495. static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
  496. #else
  497. #define omap2_aes_resources NULL
  498. #define omap2_aes_resources_sz 0
  499. #endif
  500. #ifdef CONFIG_ARCH_OMAP3
  501. static struct resource omap3_aes_resources[] = {
  502. {
  503. .start = OMAP34XX_SEC_AES_BASE,
  504. .end = OMAP34XX_SEC_AES_BASE + 0x4C,
  505. .flags = IORESOURCE_MEM,
  506. },
  507. {
  508. .start = OMAP34XX_DMA_AES2_TX,
  509. .flags = IORESOURCE_DMA,
  510. },
  511. {
  512. .start = OMAP34XX_DMA_AES2_RX,
  513. .flags = IORESOURCE_DMA,
  514. }
  515. };
  516. static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
  517. #else
  518. #define omap3_aes_resources NULL
  519. #define omap3_aes_resources_sz 0
  520. #endif
  521. static struct platform_device aes_device = {
  522. .name = "omap-aes",
  523. .id = -1,
  524. };
  525. static void omap_init_aes(void)
  526. {
  527. if (cpu_is_omap24xx()) {
  528. aes_device.resource = omap2_aes_resources;
  529. aes_device.num_resources = omap2_aes_resources_sz;
  530. } else if (cpu_is_omap34xx()) {
  531. aes_device.resource = omap3_aes_resources;
  532. aes_device.num_resources = omap3_aes_resources_sz;
  533. } else {
  534. pr_err("%s: platform not supported\n", __func__);
  535. return;
  536. }
  537. platform_device_register(&aes_device);
  538. }
  539. #else
  540. static inline void omap_init_aes(void) { }
  541. #endif
  542. /*-------------------------------------------------------------------------*/
  543. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  544. #define MMCHS_SYSCONFIG 0x0010
  545. #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
  546. #define MMCHS_SYSSTATUS 0x0014
  547. #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
  548. static struct platform_device dummy_pdev = {
  549. .dev = {
  550. .bus = &platform_bus_type,
  551. },
  552. };
  553. /**
  554. * omap_hsmmc_reset() - Full reset of each HS-MMC controller
  555. *
  556. * Ensure that each MMC controller is fully reset. Controllers
  557. * left in an unknown state (by bootloader) may prevent retention
  558. * or OFF-mode. This is especially important in cases where the
  559. * MMC driver is not enabled, _or_ built as a module.
  560. *
  561. * In order for reset to work, interface, functional and debounce
  562. * clocks must be enabled. The debounce clock comes from func_32k_clk
  563. * and is not under SW control, so we only enable i- and f-clocks.
  564. **/
  565. static void __init omap_hsmmc_reset(void)
  566. {
  567. u32 i, nr_controllers;
  568. if (cpu_is_omap242x())
  569. return;
  570. nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
  571. (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
  572. for (i = 0; i < nr_controllers; i++) {
  573. u32 v, base = 0;
  574. struct clk *iclk, *fclk;
  575. struct device *dev = &dummy_pdev.dev;
  576. switch (i) {
  577. case 0:
  578. base = OMAP2_MMC1_BASE;
  579. break;
  580. case 1:
  581. base = OMAP2_MMC2_BASE;
  582. break;
  583. case 2:
  584. base = OMAP3_MMC3_BASE;
  585. break;
  586. case 3:
  587. if (!cpu_is_omap44xx())
  588. return;
  589. base = OMAP4_MMC4_BASE;
  590. break;
  591. case 4:
  592. if (!cpu_is_omap44xx())
  593. return;
  594. base = OMAP4_MMC5_BASE;
  595. break;
  596. }
  597. if (cpu_is_omap44xx())
  598. base += OMAP4_MMC_REG_OFFSET;
  599. dummy_pdev.id = i;
  600. dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
  601. iclk = clk_get(dev, "ick");
  602. if (iclk && clk_enable(iclk))
  603. iclk = NULL;
  604. fclk = clk_get(dev, "fck");
  605. if (fclk && clk_enable(fclk))
  606. fclk = NULL;
  607. if (!iclk || !fclk) {
  608. printk(KERN_WARNING
  609. "%s: Unable to enable clocks for MMC%d, "
  610. "cannot reset.\n", __func__, i);
  611. break;
  612. }
  613. omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
  614. v = omap_readl(base + MMCHS_SYSSTATUS);
  615. while (!(omap_readl(base + MMCHS_SYSSTATUS) &
  616. MMCHS_SYSSTATUS_RESETDONE))
  617. cpu_relax();
  618. if (fclk) {
  619. clk_disable(fclk);
  620. clk_put(fclk);
  621. }
  622. if (iclk) {
  623. clk_disable(iclk);
  624. clk_put(iclk);
  625. }
  626. }
  627. }
  628. #else
  629. static inline void omap_hsmmc_reset(void) {}
  630. #endif
  631. #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
  632. defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  633. static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
  634. int controller_nr)
  635. {
  636. if ((mmc_controller->slots[0].switch_pin > 0) && \
  637. (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
  638. omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
  639. OMAP_PIN_INPUT_PULLUP);
  640. if ((mmc_controller->slots[0].gpio_wp > 0) && \
  641. (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
  642. omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
  643. OMAP_PIN_INPUT_PULLUP);
  644. if (cpu_is_omap2420() && controller_nr == 0) {
  645. omap_mux_init_signal("sdmmc_cmd", 0);
  646. omap_mux_init_signal("sdmmc_clki", 0);
  647. omap_mux_init_signal("sdmmc_clko", 0);
  648. omap_mux_init_signal("sdmmc_dat0", 0);
  649. omap_mux_init_signal("sdmmc_dat_dir0", 0);
  650. omap_mux_init_signal("sdmmc_cmd_dir", 0);
  651. if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
  652. omap_mux_init_signal("sdmmc_dat1", 0);
  653. omap_mux_init_signal("sdmmc_dat2", 0);
  654. omap_mux_init_signal("sdmmc_dat3", 0);
  655. omap_mux_init_signal("sdmmc_dat_dir1", 0);
  656. omap_mux_init_signal("sdmmc_dat_dir2", 0);
  657. omap_mux_init_signal("sdmmc_dat_dir3", 0);
  658. }
  659. /*
  660. * Use internal loop-back in MMC/SDIO Module Input Clock
  661. * selection
  662. */
  663. if (mmc_controller->slots[0].internal_clock) {
  664. u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  665. v |= (1 << 24);
  666. omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
  667. }
  668. }
  669. if (cpu_is_omap34xx()) {
  670. if (controller_nr == 0) {
  671. omap_mux_init_signal("sdmmc1_clk",
  672. OMAP_PIN_INPUT_PULLUP);
  673. omap_mux_init_signal("sdmmc1_cmd",
  674. OMAP_PIN_INPUT_PULLUP);
  675. omap_mux_init_signal("sdmmc1_dat0",
  676. OMAP_PIN_INPUT_PULLUP);
  677. if (mmc_controller->slots[0].caps &
  678. (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
  679. omap_mux_init_signal("sdmmc1_dat1",
  680. OMAP_PIN_INPUT_PULLUP);
  681. omap_mux_init_signal("sdmmc1_dat2",
  682. OMAP_PIN_INPUT_PULLUP);
  683. omap_mux_init_signal("sdmmc1_dat3",
  684. OMAP_PIN_INPUT_PULLUP);
  685. }
  686. if (mmc_controller->slots[0].caps &
  687. MMC_CAP_8_BIT_DATA) {
  688. omap_mux_init_signal("sdmmc1_dat4",
  689. OMAP_PIN_INPUT_PULLUP);
  690. omap_mux_init_signal("sdmmc1_dat5",
  691. OMAP_PIN_INPUT_PULLUP);
  692. omap_mux_init_signal("sdmmc1_dat6",
  693. OMAP_PIN_INPUT_PULLUP);
  694. omap_mux_init_signal("sdmmc1_dat7",
  695. OMAP_PIN_INPUT_PULLUP);
  696. }
  697. }
  698. if (controller_nr == 1) {
  699. /* MMC2 */
  700. omap_mux_init_signal("sdmmc2_clk",
  701. OMAP_PIN_INPUT_PULLUP);
  702. omap_mux_init_signal("sdmmc2_cmd",
  703. OMAP_PIN_INPUT_PULLUP);
  704. omap_mux_init_signal("sdmmc2_dat0",
  705. OMAP_PIN_INPUT_PULLUP);
  706. /*
  707. * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
  708. * in the board-*.c files
  709. */
  710. if (mmc_controller->slots[0].caps &
  711. (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
  712. omap_mux_init_signal("sdmmc2_dat1",
  713. OMAP_PIN_INPUT_PULLUP);
  714. omap_mux_init_signal("sdmmc2_dat2",
  715. OMAP_PIN_INPUT_PULLUP);
  716. omap_mux_init_signal("sdmmc2_dat3",
  717. OMAP_PIN_INPUT_PULLUP);
  718. }
  719. if (mmc_controller->slots[0].caps &
  720. MMC_CAP_8_BIT_DATA) {
  721. omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
  722. OMAP_PIN_INPUT_PULLUP);
  723. omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
  724. OMAP_PIN_INPUT_PULLUP);
  725. omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
  726. OMAP_PIN_INPUT_PULLUP);
  727. omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
  728. OMAP_PIN_INPUT_PULLUP);
  729. }
  730. }
  731. /*
  732. * For MMC3 the pins need to be muxed in the board-*.c files
  733. */
  734. }
  735. }
  736. void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
  737. int nr_controllers)
  738. {
  739. int i;
  740. char *name;
  741. for (i = 0; i < nr_controllers; i++) {
  742. unsigned long base, size;
  743. unsigned int irq = 0;
  744. if (!mmc_data[i])
  745. continue;
  746. omap2_mmc_mux(mmc_data[i], i);
  747. switch (i) {
  748. case 0:
  749. base = OMAP2_MMC1_BASE;
  750. irq = INT_24XX_MMC_IRQ;
  751. break;
  752. case 1:
  753. base = OMAP2_MMC2_BASE;
  754. irq = INT_24XX_MMC2_IRQ;
  755. break;
  756. case 2:
  757. if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
  758. return;
  759. base = OMAP3_MMC3_BASE;
  760. irq = INT_34XX_MMC3_IRQ;
  761. break;
  762. case 3:
  763. if (!cpu_is_omap44xx())
  764. return;
  765. base = OMAP4_MMC4_BASE;
  766. irq = OMAP44XX_IRQ_MMC4;
  767. break;
  768. case 4:
  769. if (!cpu_is_omap44xx())
  770. return;
  771. base = OMAP4_MMC5_BASE;
  772. irq = OMAP44XX_IRQ_MMC5;
  773. break;
  774. default:
  775. continue;
  776. }
  777. if (cpu_is_omap2420()) {
  778. size = OMAP2420_MMC_SIZE;
  779. name = "mmci-omap";
  780. } else if (cpu_is_omap44xx()) {
  781. if (i < 3)
  782. irq += OMAP44XX_IRQ_GIC_START;
  783. size = OMAP4_HSMMC_SIZE;
  784. name = "mmci-omap-hs";
  785. } else {
  786. size = OMAP3_HSMMC_SIZE;
  787. name = "mmci-omap-hs";
  788. }
  789. omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
  790. };
  791. }
  792. #endif
  793. /*-------------------------------------------------------------------------*/
  794. #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
  795. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
  796. #define OMAP_HDQ_BASE 0x480B2000
  797. #endif
  798. static struct resource omap_hdq_resources[] = {
  799. {
  800. .start = OMAP_HDQ_BASE,
  801. .end = OMAP_HDQ_BASE + 0x1C,
  802. .flags = IORESOURCE_MEM,
  803. },
  804. {
  805. .start = INT_24XX_HDQ_IRQ,
  806. .flags = IORESOURCE_IRQ,
  807. },
  808. };
  809. static struct platform_device omap_hdq_dev = {
  810. .name = "omap_hdq",
  811. .id = 0,
  812. .dev = {
  813. .platform_data = NULL,
  814. },
  815. .num_resources = ARRAY_SIZE(omap_hdq_resources),
  816. .resource = omap_hdq_resources,
  817. };
  818. static inline void omap_hdq_init(void)
  819. {
  820. (void) platform_device_register(&omap_hdq_dev);
  821. }
  822. #else
  823. static inline void omap_hdq_init(void) {}
  824. #endif
  825. /*---------------------------------------------------------------------------*/
  826. #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
  827. defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
  828. #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
  829. static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
  830. };
  831. #else
  832. static struct resource omap_vout_resource[2] = {
  833. };
  834. #endif
  835. static struct platform_device omap_vout_device = {
  836. .name = "omap_vout",
  837. .num_resources = ARRAY_SIZE(omap_vout_resource),
  838. .resource = &omap_vout_resource[0],
  839. .id = -1,
  840. };
  841. static void omap_init_vout(void)
  842. {
  843. if (platform_device_register(&omap_vout_device) < 0)
  844. printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
  845. }
  846. #else
  847. static inline void omap_init_vout(void) {}
  848. #endif
  849. /*-------------------------------------------------------------------------*/
  850. /*
  851. * Inorder to avoid any assumptions from bootloader regarding WDT
  852. * settings, WDT module is reset during init. This enables the watchdog
  853. * timer. Hence it is required to disable the watchdog after the WDT reset
  854. * during init. Otherwise the system would reboot as per the default
  855. * watchdog timer registers settings.
  856. */
  857. #define OMAP_WDT_WPS (0x34)
  858. #define OMAP_WDT_SPR (0x48)
  859. static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused)
  860. {
  861. void __iomem *base;
  862. int ret;
  863. if (!oh) {
  864. pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
  865. return -EINVAL;
  866. }
  867. base = omap_hwmod_get_mpu_rt_va(oh);
  868. if (!base) {
  869. pr_err("%s: Could not get the base address for %s\n",
  870. oh->name, __func__);
  871. return -EINVAL;
  872. }
  873. /* Enable the clocks before accessing the WDT registers */
  874. ret = omap_hwmod_enable(oh);
  875. if (ret) {
  876. pr_err("%s: Could not enable clocks for %s\n",
  877. oh->name, __func__);
  878. return ret;
  879. }
  880. /* sequence required to disable watchdog */
  881. __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
  882. while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
  883. cpu_relax();
  884. __raw_writel(0x5555, base + OMAP_WDT_SPR);
  885. while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
  886. cpu_relax();
  887. ret = omap_hwmod_idle(oh);
  888. if (ret)
  889. pr_err("%s: Could not disable clocks for %s\n",
  890. oh->name, __func__);
  891. return ret;
  892. }
  893. static void __init omap_disable_wdt(void)
  894. {
  895. if (cpu_class_is_omap2())
  896. omap_hwmod_for_each_by_class("wd_timer",
  897. omap2_disable_wdt, NULL);
  898. return;
  899. }
  900. static int __init omap2_init_devices(void)
  901. {
  902. /* please keep these calls, and their implementations above,
  903. * in alphabetical order so they're easier to sort through.
  904. */
  905. omap_disable_wdt();
  906. omap_hsmmc_reset();
  907. omap_init_audio();
  908. omap_init_camera();
  909. omap_init_mbox();
  910. omap_init_mcspi();
  911. omap_init_pmu();
  912. omap_hdq_init();
  913. omap_init_sti();
  914. omap_init_sham();
  915. omap_init_aes();
  916. omap_init_vout();
  917. return 0;
  918. }
  919. arch_initcall(omap2_init_devices);
  920. #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
  921. struct omap_device_pm_latency omap_wdt_latency[] = {
  922. [0] = {
  923. .deactivate_func = omap_device_idle_hwmods,
  924. .activate_func = omap_device_enable_hwmods,
  925. .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
  926. },
  927. };
  928. static int __init omap_init_wdt(void)
  929. {
  930. int id = -1;
  931. struct omap_device *od;
  932. struct omap_hwmod *oh;
  933. char *oh_name = "wd_timer2";
  934. char *dev_name = "omap_wdt";
  935. if (!cpu_class_is_omap2())
  936. return 0;
  937. oh = omap_hwmod_lookup(oh_name);
  938. if (!oh) {
  939. pr_err("Could not look up wd_timer%d hwmod\n", id);
  940. return -EINVAL;
  941. }
  942. od = omap_device_build(dev_name, id, oh, NULL, 0,
  943. omap_wdt_latency,
  944. ARRAY_SIZE(omap_wdt_latency), 0);
  945. WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
  946. dev_name, oh->name);
  947. return 0;
  948. }
  949. subsys_initcall(omap_init_wdt);
  950. #endif