clock44xx_data.c 92 KB

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  1. /*
  2. * OMAP4 Clock data
  3. *
  4. * Copyright (C) 2009-2010 Texas Instruments, Inc.
  5. * Copyright (C) 2009-2010 Nokia Corporation
  6. *
  7. * Paul Walmsley (paul@pwsan.com)
  8. * Rajendra Nayak (rnayak@ti.com)
  9. * Benoit Cousson (b-cousson@ti.com)
  10. *
  11. * This file is automatically generated from the OMAP hardware databases.
  12. * We respectfully ask that any modifications to this file be coordinated
  13. * with the public linux-omap@vger.kernel.org mailing list and the
  14. * authors above to ensure that the autogeneration scripts are kept
  15. * up-to-date with the file contents.
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License version 2 as
  19. * published by the Free Software Foundation.
  20. *
  21. * XXX Some of the ES1 clocks have been removed/changed; once support
  22. * is added for discriminating clocks by ES level, these should be added back
  23. * in.
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/list.h>
  27. #include <linux/clk.h>
  28. #include <plat/clkdev_omap.h>
  29. #include "clock.h"
  30. #include "clock44xx.h"
  31. #include "cm.h"
  32. #include "cm-regbits-44xx.h"
  33. #include "prm.h"
  34. #include "prm-regbits-44xx.h"
  35. #include "control.h"
  36. /* Root clocks */
  37. static struct clk extalt_clkin_ck = {
  38. .name = "extalt_clkin_ck",
  39. .rate = 59000000,
  40. .ops = &clkops_null,
  41. };
  42. static struct clk pad_clks_ck = {
  43. .name = "pad_clks_ck",
  44. .rate = 12000000,
  45. .ops = &clkops_null,
  46. };
  47. static struct clk pad_slimbus_core_clks_ck = {
  48. .name = "pad_slimbus_core_clks_ck",
  49. .rate = 12000000,
  50. .ops = &clkops_null,
  51. };
  52. static struct clk secure_32k_clk_src_ck = {
  53. .name = "secure_32k_clk_src_ck",
  54. .rate = 32768,
  55. .ops = &clkops_null,
  56. };
  57. static struct clk slimbus_clk = {
  58. .name = "slimbus_clk",
  59. .rate = 12000000,
  60. .ops = &clkops_null,
  61. };
  62. static struct clk sys_32k_ck = {
  63. .name = "sys_32k_ck",
  64. .rate = 32768,
  65. .ops = &clkops_null,
  66. };
  67. static struct clk virt_12000000_ck = {
  68. .name = "virt_12000000_ck",
  69. .ops = &clkops_null,
  70. .rate = 12000000,
  71. };
  72. static struct clk virt_13000000_ck = {
  73. .name = "virt_13000000_ck",
  74. .ops = &clkops_null,
  75. .rate = 13000000,
  76. };
  77. static struct clk virt_16800000_ck = {
  78. .name = "virt_16800000_ck",
  79. .ops = &clkops_null,
  80. .rate = 16800000,
  81. };
  82. static struct clk virt_19200000_ck = {
  83. .name = "virt_19200000_ck",
  84. .ops = &clkops_null,
  85. .rate = 19200000,
  86. };
  87. static struct clk virt_26000000_ck = {
  88. .name = "virt_26000000_ck",
  89. .ops = &clkops_null,
  90. .rate = 26000000,
  91. };
  92. static struct clk virt_27000000_ck = {
  93. .name = "virt_27000000_ck",
  94. .ops = &clkops_null,
  95. .rate = 27000000,
  96. };
  97. static struct clk virt_38400000_ck = {
  98. .name = "virt_38400000_ck",
  99. .ops = &clkops_null,
  100. .rate = 38400000,
  101. };
  102. static const struct clksel_rate div_1_0_rates[] = {
  103. { .div = 1, .val = 0, .flags = RATE_IN_4430 },
  104. { .div = 0 },
  105. };
  106. static const struct clksel_rate div_1_1_rates[] = {
  107. { .div = 1, .val = 1, .flags = RATE_IN_4430 },
  108. { .div = 0 },
  109. };
  110. static const struct clksel_rate div_1_2_rates[] = {
  111. { .div = 1, .val = 2, .flags = RATE_IN_4430 },
  112. { .div = 0 },
  113. };
  114. static const struct clksel_rate div_1_3_rates[] = {
  115. { .div = 1, .val = 3, .flags = RATE_IN_4430 },
  116. { .div = 0 },
  117. };
  118. static const struct clksel_rate div_1_4_rates[] = {
  119. { .div = 1, .val = 4, .flags = RATE_IN_4430 },
  120. { .div = 0 },
  121. };
  122. static const struct clksel_rate div_1_5_rates[] = {
  123. { .div = 1, .val = 5, .flags = RATE_IN_4430 },
  124. { .div = 0 },
  125. };
  126. static const struct clksel_rate div_1_6_rates[] = {
  127. { .div = 1, .val = 6, .flags = RATE_IN_4430 },
  128. { .div = 0 },
  129. };
  130. static const struct clksel_rate div_1_7_rates[] = {
  131. { .div = 1, .val = 7, .flags = RATE_IN_4430 },
  132. { .div = 0 },
  133. };
  134. static const struct clksel sys_clkin_sel[] = {
  135. { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
  136. { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
  137. { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
  138. { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
  139. { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
  140. { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
  141. { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
  142. { .parent = NULL },
  143. };
  144. static struct clk sys_clkin_ck = {
  145. .name = "sys_clkin_ck",
  146. .rate = 38400000,
  147. .clksel = sys_clkin_sel,
  148. .init = &omap2_init_clksel_parent,
  149. .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
  150. .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
  151. .ops = &clkops_null,
  152. .recalc = &omap2_clksel_recalc,
  153. };
  154. static struct clk tie_low_clock_ck = {
  155. .name = "tie_low_clock_ck",
  156. .rate = 0,
  157. .ops = &clkops_null,
  158. };
  159. static struct clk utmi_phy_clkout_ck = {
  160. .name = "utmi_phy_clkout_ck",
  161. .rate = 60000000,
  162. .ops = &clkops_null,
  163. };
  164. static struct clk xclk60mhsp1_ck = {
  165. .name = "xclk60mhsp1_ck",
  166. .rate = 60000000,
  167. .ops = &clkops_null,
  168. };
  169. static struct clk xclk60mhsp2_ck = {
  170. .name = "xclk60mhsp2_ck",
  171. .rate = 60000000,
  172. .ops = &clkops_null,
  173. };
  174. static struct clk xclk60motg_ck = {
  175. .name = "xclk60motg_ck",
  176. .rate = 60000000,
  177. .ops = &clkops_null,
  178. };
  179. /* Module clocks and DPLL outputs */
  180. static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
  181. { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
  182. { .parent = &sys_32k_ck, .rates = div_1_1_rates },
  183. { .parent = NULL },
  184. };
  185. static struct clk abe_dpll_bypass_clk_mux_ck = {
  186. .name = "abe_dpll_bypass_clk_mux_ck",
  187. .parent = &sys_clkin_ck,
  188. .ops = &clkops_null,
  189. .recalc = &followparent_recalc,
  190. };
  191. static struct clk abe_dpll_refclk_mux_ck = {
  192. .name = "abe_dpll_refclk_mux_ck",
  193. .parent = &sys_clkin_ck,
  194. .clksel = abe_dpll_bypass_clk_mux_sel,
  195. .init = &omap2_init_clksel_parent,
  196. .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
  197. .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
  198. .ops = &clkops_null,
  199. .recalc = &omap2_clksel_recalc,
  200. };
  201. /* DPLL_ABE */
  202. static struct dpll_data dpll_abe_dd = {
  203. .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
  204. .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
  205. .clk_ref = &abe_dpll_refclk_mux_ck,
  206. .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
  207. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  208. .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
  209. .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
  210. .mult_mask = OMAP4430_DPLL_MULT_MASK,
  211. .div1_mask = OMAP4430_DPLL_DIV_MASK,
  212. .enable_mask = OMAP4430_DPLL_EN_MASK,
  213. .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
  214. .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
  215. .max_multiplier = OMAP4430_MAX_DPLL_MULT,
  216. .max_divider = OMAP4430_MAX_DPLL_DIV,
  217. .min_divider = 1,
  218. };
  219. static struct clk dpll_abe_ck = {
  220. .name = "dpll_abe_ck",
  221. .parent = &abe_dpll_refclk_mux_ck,
  222. .dpll_data = &dpll_abe_dd,
  223. .init = &omap2_init_dpll_parent,
  224. .ops = &clkops_omap3_noncore_dpll_ops,
  225. .recalc = &omap3_dpll_recalc,
  226. .round_rate = &omap2_dpll_round_rate,
  227. .set_rate = &omap3_noncore_dpll_set_rate,
  228. };
  229. static struct clk dpll_abe_m2x2_ck = {
  230. .name = "dpll_abe_m2x2_ck",
  231. .parent = &dpll_abe_ck,
  232. .ops = &clkops_null,
  233. .recalc = &followparent_recalc,
  234. };
  235. static struct clk abe_24m_fclk = {
  236. .name = "abe_24m_fclk",
  237. .parent = &dpll_abe_m2x2_ck,
  238. .ops = &clkops_null,
  239. .recalc = &followparent_recalc,
  240. };
  241. static const struct clksel_rate div3_1to4_rates[] = {
  242. { .div = 1, .val = 0, .flags = RATE_IN_4430 },
  243. { .div = 2, .val = 1, .flags = RATE_IN_4430 },
  244. { .div = 4, .val = 2, .flags = RATE_IN_4430 },
  245. { .div = 0 },
  246. };
  247. static const struct clksel abe_clk_div[] = {
  248. { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
  249. { .parent = NULL },
  250. };
  251. static struct clk abe_clk = {
  252. .name = "abe_clk",
  253. .parent = &dpll_abe_m2x2_ck,
  254. .clksel = abe_clk_div,
  255. .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
  256. .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
  257. .ops = &clkops_null,
  258. .recalc = &omap2_clksel_recalc,
  259. .round_rate = &omap2_clksel_round_rate,
  260. .set_rate = &omap2_clksel_set_rate,
  261. };
  262. static const struct clksel_rate div2_1to2_rates[] = {
  263. { .div = 1, .val = 0, .flags = RATE_IN_4430 },
  264. { .div = 2, .val = 1, .flags = RATE_IN_4430 },
  265. { .div = 0 },
  266. };
  267. static const struct clksel aess_fclk_div[] = {
  268. { .parent = &abe_clk, .rates = div2_1to2_rates },
  269. { .parent = NULL },
  270. };
  271. static struct clk aess_fclk = {
  272. .name = "aess_fclk",
  273. .parent = &abe_clk,
  274. .clksel = aess_fclk_div,
  275. .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
  276. .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
  277. .ops = &clkops_null,
  278. .recalc = &omap2_clksel_recalc,
  279. .round_rate = &omap2_clksel_round_rate,
  280. .set_rate = &omap2_clksel_set_rate,
  281. };
  282. static const struct clksel_rate div31_1to31_rates[] = {
  283. { .div = 1, .val = 1, .flags = RATE_IN_4430 },
  284. { .div = 2, .val = 2, .flags = RATE_IN_4430 },
  285. { .div = 3, .val = 3, .flags = RATE_IN_4430 },
  286. { .div = 4, .val = 4, .flags = RATE_IN_4430 },
  287. { .div = 5, .val = 5, .flags = RATE_IN_4430 },
  288. { .div = 6, .val = 6, .flags = RATE_IN_4430 },
  289. { .div = 7, .val = 7, .flags = RATE_IN_4430 },
  290. { .div = 8, .val = 8, .flags = RATE_IN_4430 },
  291. { .div = 9, .val = 9, .flags = RATE_IN_4430 },
  292. { .div = 10, .val = 10, .flags = RATE_IN_4430 },
  293. { .div = 11, .val = 11, .flags = RATE_IN_4430 },
  294. { .div = 12, .val = 12, .flags = RATE_IN_4430 },
  295. { .div = 13, .val = 13, .flags = RATE_IN_4430 },
  296. { .div = 14, .val = 14, .flags = RATE_IN_4430 },
  297. { .div = 15, .val = 15, .flags = RATE_IN_4430 },
  298. { .div = 16, .val = 16, .flags = RATE_IN_4430 },
  299. { .div = 17, .val = 17, .flags = RATE_IN_4430 },
  300. { .div = 18, .val = 18, .flags = RATE_IN_4430 },
  301. { .div = 19, .val = 19, .flags = RATE_IN_4430 },
  302. { .div = 20, .val = 20, .flags = RATE_IN_4430 },
  303. { .div = 21, .val = 21, .flags = RATE_IN_4430 },
  304. { .div = 22, .val = 22, .flags = RATE_IN_4430 },
  305. { .div = 23, .val = 23, .flags = RATE_IN_4430 },
  306. { .div = 24, .val = 24, .flags = RATE_IN_4430 },
  307. { .div = 25, .val = 25, .flags = RATE_IN_4430 },
  308. { .div = 26, .val = 26, .flags = RATE_IN_4430 },
  309. { .div = 27, .val = 27, .flags = RATE_IN_4430 },
  310. { .div = 28, .val = 28, .flags = RATE_IN_4430 },
  311. { .div = 29, .val = 29, .flags = RATE_IN_4430 },
  312. { .div = 30, .val = 30, .flags = RATE_IN_4430 },
  313. { .div = 31, .val = 31, .flags = RATE_IN_4430 },
  314. { .div = 0 },
  315. };
  316. static const struct clksel dpll_abe_m3_div[] = {
  317. { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
  318. { .parent = NULL },
  319. };
  320. static struct clk dpll_abe_m3_ck = {
  321. .name = "dpll_abe_m3_ck",
  322. .parent = &dpll_abe_ck,
  323. .clksel = dpll_abe_m3_div,
  324. .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
  325. .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
  326. .ops = &clkops_null,
  327. .recalc = &omap2_clksel_recalc,
  328. .round_rate = &omap2_clksel_round_rate,
  329. .set_rate = &omap2_clksel_set_rate,
  330. };
  331. static const struct clksel core_hsd_byp_clk_mux_sel[] = {
  332. { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
  333. { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
  334. { .parent = NULL },
  335. };
  336. static struct clk core_hsd_byp_clk_mux_ck = {
  337. .name = "core_hsd_byp_clk_mux_ck",
  338. .parent = &sys_clkin_ck,
  339. .clksel = core_hsd_byp_clk_mux_sel,
  340. .init = &omap2_init_clksel_parent,
  341. .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
  342. .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
  343. .ops = &clkops_null,
  344. .recalc = &omap2_clksel_recalc,
  345. };
  346. /* DPLL_CORE */
  347. static struct dpll_data dpll_core_dd = {
  348. .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
  349. .clk_bypass = &core_hsd_byp_clk_mux_ck,
  350. .clk_ref = &sys_clkin_ck,
  351. .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
  352. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  353. .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
  354. .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
  355. .mult_mask = OMAP4430_DPLL_MULT_MASK,
  356. .div1_mask = OMAP4430_DPLL_DIV_MASK,
  357. .enable_mask = OMAP4430_DPLL_EN_MASK,
  358. .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
  359. .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
  360. .max_multiplier = OMAP4430_MAX_DPLL_MULT,
  361. .max_divider = OMAP4430_MAX_DPLL_DIV,
  362. .min_divider = 1,
  363. };
  364. static struct clk dpll_core_ck = {
  365. .name = "dpll_core_ck",
  366. .parent = &sys_clkin_ck,
  367. .dpll_data = &dpll_core_dd,
  368. .init = &omap2_init_dpll_parent,
  369. .ops = &clkops_null,
  370. .recalc = &omap3_dpll_recalc,
  371. };
  372. static const struct clksel dpll_core_m6_div[] = {
  373. { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
  374. { .parent = NULL },
  375. };
  376. static struct clk dpll_core_m6_ck = {
  377. .name = "dpll_core_m6_ck",
  378. .parent = &dpll_core_ck,
  379. .clksel = dpll_core_m6_div,
  380. .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
  381. .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
  382. .ops = &clkops_null,
  383. .recalc = &omap2_clksel_recalc,
  384. .round_rate = &omap2_clksel_round_rate,
  385. .set_rate = &omap2_clksel_set_rate,
  386. };
  387. static const struct clksel dbgclk_mux_sel[] = {
  388. { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
  389. { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
  390. { .parent = NULL },
  391. };
  392. static struct clk dbgclk_mux_ck = {
  393. .name = "dbgclk_mux_ck",
  394. .parent = &sys_clkin_ck,
  395. .ops = &clkops_null,
  396. .recalc = &followparent_recalc,
  397. };
  398. static struct clk dpll_core_m2_ck = {
  399. .name = "dpll_core_m2_ck",
  400. .parent = &dpll_core_ck,
  401. .clksel = dpll_core_m6_div,
  402. .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
  403. .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
  404. .ops = &clkops_null,
  405. .recalc = &omap2_clksel_recalc,
  406. .round_rate = &omap2_clksel_round_rate,
  407. .set_rate = &omap2_clksel_set_rate,
  408. };
  409. static struct clk ddrphy_ck = {
  410. .name = "ddrphy_ck",
  411. .parent = &dpll_core_m2_ck,
  412. .ops = &clkops_null,
  413. .recalc = &followparent_recalc,
  414. };
  415. static struct clk dpll_core_m5_ck = {
  416. .name = "dpll_core_m5_ck",
  417. .parent = &dpll_core_ck,
  418. .clksel = dpll_core_m6_div,
  419. .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
  420. .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
  421. .ops = &clkops_null,
  422. .recalc = &omap2_clksel_recalc,
  423. .round_rate = &omap2_clksel_round_rate,
  424. .set_rate = &omap2_clksel_set_rate,
  425. };
  426. static const struct clksel div_core_div[] = {
  427. { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
  428. { .parent = NULL },
  429. };
  430. static struct clk div_core_ck = {
  431. .name = "div_core_ck",
  432. .parent = &dpll_core_m5_ck,
  433. .clksel = div_core_div,
  434. .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
  435. .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
  436. .ops = &clkops_null,
  437. .recalc = &omap2_clksel_recalc,
  438. .round_rate = &omap2_clksel_round_rate,
  439. .set_rate = &omap2_clksel_set_rate,
  440. };
  441. static const struct clksel_rate div4_1to8_rates[] = {
  442. { .div = 1, .val = 0, .flags = RATE_IN_4430 },
  443. { .div = 2, .val = 1, .flags = RATE_IN_4430 },
  444. { .div = 4, .val = 2, .flags = RATE_IN_4430 },
  445. { .div = 8, .val = 3, .flags = RATE_IN_4430 },
  446. { .div = 0 },
  447. };
  448. static const struct clksel div_iva_hs_clk_div[] = {
  449. { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
  450. { .parent = NULL },
  451. };
  452. static struct clk div_iva_hs_clk = {
  453. .name = "div_iva_hs_clk",
  454. .parent = &dpll_core_m5_ck,
  455. .clksel = div_iva_hs_clk_div,
  456. .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
  457. .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
  458. .ops = &clkops_null,
  459. .recalc = &omap2_clksel_recalc,
  460. .round_rate = &omap2_clksel_round_rate,
  461. .set_rate = &omap2_clksel_set_rate,
  462. };
  463. static struct clk div_mpu_hs_clk = {
  464. .name = "div_mpu_hs_clk",
  465. .parent = &dpll_core_m5_ck,
  466. .clksel = div_iva_hs_clk_div,
  467. .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
  468. .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
  469. .ops = &clkops_null,
  470. .recalc = &omap2_clksel_recalc,
  471. .round_rate = &omap2_clksel_round_rate,
  472. .set_rate = &omap2_clksel_set_rate,
  473. };
  474. static struct clk dpll_core_m4_ck = {
  475. .name = "dpll_core_m4_ck",
  476. .parent = &dpll_core_ck,
  477. .clksel = dpll_core_m6_div,
  478. .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
  479. .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
  480. .ops = &clkops_null,
  481. .recalc = &omap2_clksel_recalc,
  482. .round_rate = &omap2_clksel_round_rate,
  483. .set_rate = &omap2_clksel_set_rate,
  484. };
  485. static struct clk dll_clk_div_ck = {
  486. .name = "dll_clk_div_ck",
  487. .parent = &dpll_core_m4_ck,
  488. .ops = &clkops_null,
  489. .recalc = &followparent_recalc,
  490. };
  491. static struct clk dpll_abe_m2_ck = {
  492. .name = "dpll_abe_m2_ck",
  493. .parent = &dpll_abe_ck,
  494. .clksel = dpll_abe_m3_div,
  495. .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
  496. .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
  497. .ops = &clkops_null,
  498. .recalc = &omap2_clksel_recalc,
  499. .round_rate = &omap2_clksel_round_rate,
  500. .set_rate = &omap2_clksel_set_rate,
  501. };
  502. static struct clk dpll_core_m3_ck = {
  503. .name = "dpll_core_m3_ck",
  504. .parent = &dpll_core_ck,
  505. .clksel = dpll_core_m6_div,
  506. .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
  507. .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
  508. .ops = &clkops_null,
  509. .recalc = &omap2_clksel_recalc,
  510. .round_rate = &omap2_clksel_round_rate,
  511. .set_rate = &omap2_clksel_set_rate,
  512. };
  513. static struct clk dpll_core_m7_ck = {
  514. .name = "dpll_core_m7_ck",
  515. .parent = &dpll_core_ck,
  516. .clksel = dpll_core_m6_div,
  517. .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
  518. .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
  519. .ops = &clkops_null,
  520. .recalc = &omap2_clksel_recalc,
  521. .round_rate = &omap2_clksel_round_rate,
  522. .set_rate = &omap2_clksel_set_rate,
  523. };
  524. static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
  525. { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
  526. { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
  527. { .parent = NULL },
  528. };
  529. static struct clk iva_hsd_byp_clk_mux_ck = {
  530. .name = "iva_hsd_byp_clk_mux_ck",
  531. .parent = &sys_clkin_ck,
  532. .ops = &clkops_null,
  533. .recalc = &followparent_recalc,
  534. };
  535. /* DPLL_IVA */
  536. static struct dpll_data dpll_iva_dd = {
  537. .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
  538. .clk_bypass = &iva_hsd_byp_clk_mux_ck,
  539. .clk_ref = &sys_clkin_ck,
  540. .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
  541. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  542. .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
  543. .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
  544. .mult_mask = OMAP4430_DPLL_MULT_MASK,
  545. .div1_mask = OMAP4430_DPLL_DIV_MASK,
  546. .enable_mask = OMAP4430_DPLL_EN_MASK,
  547. .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
  548. .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
  549. .max_multiplier = OMAP4430_MAX_DPLL_MULT,
  550. .max_divider = OMAP4430_MAX_DPLL_DIV,
  551. .min_divider = 1,
  552. };
  553. static struct clk dpll_iva_ck = {
  554. .name = "dpll_iva_ck",
  555. .parent = &sys_clkin_ck,
  556. .dpll_data = &dpll_iva_dd,
  557. .init = &omap2_init_dpll_parent,
  558. .ops = &clkops_omap3_noncore_dpll_ops,
  559. .recalc = &omap3_dpll_recalc,
  560. .round_rate = &omap2_dpll_round_rate,
  561. .set_rate = &omap3_noncore_dpll_set_rate,
  562. };
  563. static const struct clksel dpll_iva_m4_div[] = {
  564. { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
  565. { .parent = NULL },
  566. };
  567. static struct clk dpll_iva_m4_ck = {
  568. .name = "dpll_iva_m4_ck",
  569. .parent = &dpll_iva_ck,
  570. .clksel = dpll_iva_m4_div,
  571. .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
  572. .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
  573. .ops = &clkops_null,
  574. .recalc = &omap2_clksel_recalc,
  575. .round_rate = &omap2_clksel_round_rate,
  576. .set_rate = &omap2_clksel_set_rate,
  577. };
  578. static struct clk dpll_iva_m5_ck = {
  579. .name = "dpll_iva_m5_ck",
  580. .parent = &dpll_iva_ck,
  581. .clksel = dpll_iva_m4_div,
  582. .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
  583. .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
  584. .ops = &clkops_null,
  585. .recalc = &omap2_clksel_recalc,
  586. .round_rate = &omap2_clksel_round_rate,
  587. .set_rate = &omap2_clksel_set_rate,
  588. };
  589. /* DPLL_MPU */
  590. static struct dpll_data dpll_mpu_dd = {
  591. .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
  592. .clk_bypass = &div_mpu_hs_clk,
  593. .clk_ref = &sys_clkin_ck,
  594. .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
  595. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  596. .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
  597. .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
  598. .mult_mask = OMAP4430_DPLL_MULT_MASK,
  599. .div1_mask = OMAP4430_DPLL_DIV_MASK,
  600. .enable_mask = OMAP4430_DPLL_EN_MASK,
  601. .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
  602. .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
  603. .max_multiplier = OMAP4430_MAX_DPLL_MULT,
  604. .max_divider = OMAP4430_MAX_DPLL_DIV,
  605. .min_divider = 1,
  606. };
  607. static struct clk dpll_mpu_ck = {
  608. .name = "dpll_mpu_ck",
  609. .parent = &sys_clkin_ck,
  610. .dpll_data = &dpll_mpu_dd,
  611. .init = &omap2_init_dpll_parent,
  612. .ops = &clkops_omap3_noncore_dpll_ops,
  613. .recalc = &omap3_dpll_recalc,
  614. .round_rate = &omap2_dpll_round_rate,
  615. .set_rate = &omap3_noncore_dpll_set_rate,
  616. };
  617. static const struct clksel dpll_mpu_m2_div[] = {
  618. { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
  619. { .parent = NULL },
  620. };
  621. static struct clk dpll_mpu_m2_ck = {
  622. .name = "dpll_mpu_m2_ck",
  623. .parent = &dpll_mpu_ck,
  624. .clksel = dpll_mpu_m2_div,
  625. .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
  626. .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
  627. .ops = &clkops_null,
  628. .recalc = &omap2_clksel_recalc,
  629. .round_rate = &omap2_clksel_round_rate,
  630. .set_rate = &omap2_clksel_set_rate,
  631. };
  632. static struct clk per_hs_clk_div_ck = {
  633. .name = "per_hs_clk_div_ck",
  634. .parent = &dpll_abe_m3_ck,
  635. .ops = &clkops_null,
  636. .recalc = &followparent_recalc,
  637. };
  638. static const struct clksel per_hsd_byp_clk_mux_sel[] = {
  639. { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
  640. { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
  641. { .parent = NULL },
  642. };
  643. static struct clk per_hsd_byp_clk_mux_ck = {
  644. .name = "per_hsd_byp_clk_mux_ck",
  645. .parent = &sys_clkin_ck,
  646. .clksel = per_hsd_byp_clk_mux_sel,
  647. .init = &omap2_init_clksel_parent,
  648. .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
  649. .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
  650. .ops = &clkops_null,
  651. .recalc = &omap2_clksel_recalc,
  652. };
  653. /* DPLL_PER */
  654. static struct dpll_data dpll_per_dd = {
  655. .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
  656. .clk_bypass = &per_hsd_byp_clk_mux_ck,
  657. .clk_ref = &sys_clkin_ck,
  658. .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
  659. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  660. .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
  661. .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
  662. .mult_mask = OMAP4430_DPLL_MULT_MASK,
  663. .div1_mask = OMAP4430_DPLL_DIV_MASK,
  664. .enable_mask = OMAP4430_DPLL_EN_MASK,
  665. .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
  666. .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
  667. .max_multiplier = OMAP4430_MAX_DPLL_MULT,
  668. .max_divider = OMAP4430_MAX_DPLL_DIV,
  669. .min_divider = 1,
  670. };
  671. static struct clk dpll_per_ck = {
  672. .name = "dpll_per_ck",
  673. .parent = &sys_clkin_ck,
  674. .dpll_data = &dpll_per_dd,
  675. .init = &omap2_init_dpll_parent,
  676. .ops = &clkops_omap3_noncore_dpll_ops,
  677. .recalc = &omap3_dpll_recalc,
  678. .round_rate = &omap2_dpll_round_rate,
  679. .set_rate = &omap3_noncore_dpll_set_rate,
  680. };
  681. static const struct clksel dpll_per_m2_div[] = {
  682. { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
  683. { .parent = NULL },
  684. };
  685. static struct clk dpll_per_m2_ck = {
  686. .name = "dpll_per_m2_ck",
  687. .parent = &dpll_per_ck,
  688. .clksel = dpll_per_m2_div,
  689. .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
  690. .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
  691. .ops = &clkops_null,
  692. .recalc = &omap2_clksel_recalc,
  693. .round_rate = &omap2_clksel_round_rate,
  694. .set_rate = &omap2_clksel_set_rate,
  695. };
  696. static struct clk dpll_per_m2x2_ck = {
  697. .name = "dpll_per_m2x2_ck",
  698. .parent = &dpll_per_ck,
  699. .ops = &clkops_null,
  700. .recalc = &followparent_recalc,
  701. };
  702. static struct clk dpll_per_m3_ck = {
  703. .name = "dpll_per_m3_ck",
  704. .parent = &dpll_per_ck,
  705. .clksel = dpll_per_m2_div,
  706. .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
  707. .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
  708. .ops = &clkops_null,
  709. .recalc = &omap2_clksel_recalc,
  710. .round_rate = &omap2_clksel_round_rate,
  711. .set_rate = &omap2_clksel_set_rate,
  712. };
  713. static struct clk dpll_per_m4_ck = {
  714. .name = "dpll_per_m4_ck",
  715. .parent = &dpll_per_ck,
  716. .clksel = dpll_per_m2_div,
  717. .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
  718. .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
  719. .ops = &clkops_null,
  720. .recalc = &omap2_clksel_recalc,
  721. .round_rate = &omap2_clksel_round_rate,
  722. .set_rate = &omap2_clksel_set_rate,
  723. };
  724. static struct clk dpll_per_m5_ck = {
  725. .name = "dpll_per_m5_ck",
  726. .parent = &dpll_per_ck,
  727. .clksel = dpll_per_m2_div,
  728. .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
  729. .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
  730. .ops = &clkops_null,
  731. .recalc = &omap2_clksel_recalc,
  732. .round_rate = &omap2_clksel_round_rate,
  733. .set_rate = &omap2_clksel_set_rate,
  734. };
  735. static struct clk dpll_per_m6_ck = {
  736. .name = "dpll_per_m6_ck",
  737. .parent = &dpll_per_ck,
  738. .clksel = dpll_per_m2_div,
  739. .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
  740. .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
  741. .ops = &clkops_null,
  742. .recalc = &omap2_clksel_recalc,
  743. .round_rate = &omap2_clksel_round_rate,
  744. .set_rate = &omap2_clksel_set_rate,
  745. };
  746. static struct clk dpll_per_m7_ck = {
  747. .name = "dpll_per_m7_ck",
  748. .parent = &dpll_per_ck,
  749. .clksel = dpll_per_m2_div,
  750. .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
  751. .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
  752. .ops = &clkops_null,
  753. .recalc = &omap2_clksel_recalc,
  754. .round_rate = &omap2_clksel_round_rate,
  755. .set_rate = &omap2_clksel_set_rate,
  756. };
  757. /* DPLL_UNIPRO */
  758. static struct dpll_data dpll_unipro_dd = {
  759. .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
  760. .clk_bypass = &sys_clkin_ck,
  761. .clk_ref = &sys_clkin_ck,
  762. .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
  763. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  764. .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
  765. .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
  766. .mult_mask = OMAP4430_DPLL_MULT_MASK,
  767. .div1_mask = OMAP4430_DPLL_DIV_MASK,
  768. .enable_mask = OMAP4430_DPLL_EN_MASK,
  769. .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
  770. .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
  771. .max_multiplier = OMAP4430_MAX_DPLL_MULT,
  772. .max_divider = OMAP4430_MAX_DPLL_DIV,
  773. .min_divider = 1,
  774. };
  775. static struct clk dpll_unipro_ck = {
  776. .name = "dpll_unipro_ck",
  777. .parent = &sys_clkin_ck,
  778. .dpll_data = &dpll_unipro_dd,
  779. .init = &omap2_init_dpll_parent,
  780. .ops = &clkops_omap3_noncore_dpll_ops,
  781. .recalc = &omap3_dpll_recalc,
  782. .round_rate = &omap2_dpll_round_rate,
  783. .set_rate = &omap3_noncore_dpll_set_rate,
  784. };
  785. static const struct clksel dpll_unipro_m2x2_div[] = {
  786. { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
  787. { .parent = NULL },
  788. };
  789. static struct clk dpll_unipro_m2x2_ck = {
  790. .name = "dpll_unipro_m2x2_ck",
  791. .parent = &dpll_unipro_ck,
  792. .clksel = dpll_unipro_m2x2_div,
  793. .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
  794. .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
  795. .ops = &clkops_null,
  796. .recalc = &omap2_clksel_recalc,
  797. .round_rate = &omap2_clksel_round_rate,
  798. .set_rate = &omap2_clksel_set_rate,
  799. };
  800. static struct clk usb_hs_clk_div_ck = {
  801. .name = "usb_hs_clk_div_ck",
  802. .parent = &dpll_abe_m3_ck,
  803. .ops = &clkops_null,
  804. .recalc = &followparent_recalc,
  805. };
  806. /* DPLL_USB */
  807. static struct dpll_data dpll_usb_dd = {
  808. .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
  809. .clk_bypass = &usb_hs_clk_div_ck,
  810. .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
  811. .clk_ref = &sys_clkin_ck,
  812. .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
  813. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  814. .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
  815. .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
  816. .mult_mask = OMAP4430_DPLL_MULT_MASK,
  817. .div1_mask = OMAP4430_DPLL_DIV_MASK,
  818. .enable_mask = OMAP4430_DPLL_EN_MASK,
  819. .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
  820. .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
  821. .max_multiplier = OMAP4430_MAX_DPLL_MULT,
  822. .max_divider = OMAP4430_MAX_DPLL_DIV,
  823. .min_divider = 1,
  824. };
  825. static struct clk dpll_usb_ck = {
  826. .name = "dpll_usb_ck",
  827. .parent = &sys_clkin_ck,
  828. .dpll_data = &dpll_usb_dd,
  829. .init = &omap2_init_dpll_parent,
  830. .ops = &clkops_omap3_noncore_dpll_ops,
  831. .recalc = &omap3_dpll_recalc,
  832. .round_rate = &omap2_dpll_round_rate,
  833. .set_rate = &omap3_noncore_dpll_set_rate,
  834. };
  835. static struct clk dpll_usb_clkdcoldo_ck = {
  836. .name = "dpll_usb_clkdcoldo_ck",
  837. .parent = &dpll_usb_ck,
  838. .ops = &clkops_null,
  839. .recalc = &followparent_recalc,
  840. };
  841. static const struct clksel dpll_usb_m2_div[] = {
  842. { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
  843. { .parent = NULL },
  844. };
  845. static struct clk dpll_usb_m2_ck = {
  846. .name = "dpll_usb_m2_ck",
  847. .parent = &dpll_usb_ck,
  848. .clksel = dpll_usb_m2_div,
  849. .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
  850. .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
  851. .ops = &clkops_null,
  852. .recalc = &omap2_clksel_recalc,
  853. .round_rate = &omap2_clksel_round_rate,
  854. .set_rate = &omap2_clksel_set_rate,
  855. };
  856. static const struct clksel ducati_clk_mux_sel[] = {
  857. { .parent = &div_core_ck, .rates = div_1_0_rates },
  858. { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
  859. { .parent = NULL },
  860. };
  861. static struct clk ducati_clk_mux_ck = {
  862. .name = "ducati_clk_mux_ck",
  863. .parent = &div_core_ck,
  864. .clksel = ducati_clk_mux_sel,
  865. .init = &omap2_init_clksel_parent,
  866. .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
  867. .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
  868. .ops = &clkops_null,
  869. .recalc = &omap2_clksel_recalc,
  870. };
  871. static struct clk func_12m_fclk = {
  872. .name = "func_12m_fclk",
  873. .parent = &dpll_per_m2x2_ck,
  874. .ops = &clkops_null,
  875. .recalc = &followparent_recalc,
  876. };
  877. static struct clk func_24m_clk = {
  878. .name = "func_24m_clk",
  879. .parent = &dpll_per_m2_ck,
  880. .ops = &clkops_null,
  881. .recalc = &followparent_recalc,
  882. };
  883. static struct clk func_24mc_fclk = {
  884. .name = "func_24mc_fclk",
  885. .parent = &dpll_per_m2x2_ck,
  886. .ops = &clkops_null,
  887. .recalc = &followparent_recalc,
  888. };
  889. static const struct clksel_rate div2_4to8_rates[] = {
  890. { .div = 4, .val = 0, .flags = RATE_IN_4430 },
  891. { .div = 8, .val = 1, .flags = RATE_IN_4430 },
  892. { .div = 0 },
  893. };
  894. static const struct clksel func_48m_fclk_div[] = {
  895. { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
  896. { .parent = NULL },
  897. };
  898. static struct clk func_48m_fclk = {
  899. .name = "func_48m_fclk",
  900. .parent = &dpll_per_m2x2_ck,
  901. .clksel = func_48m_fclk_div,
  902. .clksel_reg = OMAP4430_CM_SCALE_FCLK,
  903. .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
  904. .ops = &clkops_null,
  905. .recalc = &omap2_clksel_recalc,
  906. .round_rate = &omap2_clksel_round_rate,
  907. .set_rate = &omap2_clksel_set_rate,
  908. };
  909. static struct clk func_48mc_fclk = {
  910. .name = "func_48mc_fclk",
  911. .parent = &dpll_per_m2x2_ck,
  912. .ops = &clkops_null,
  913. .recalc = &followparent_recalc,
  914. };
  915. static const struct clksel_rate div2_2to4_rates[] = {
  916. { .div = 2, .val = 0, .flags = RATE_IN_4430 },
  917. { .div = 4, .val = 1, .flags = RATE_IN_4430 },
  918. { .div = 0 },
  919. };
  920. static const struct clksel func_64m_fclk_div[] = {
  921. { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
  922. { .parent = NULL },
  923. };
  924. static struct clk func_64m_fclk = {
  925. .name = "func_64m_fclk",
  926. .parent = &dpll_per_m4_ck,
  927. .clksel = func_64m_fclk_div,
  928. .clksel_reg = OMAP4430_CM_SCALE_FCLK,
  929. .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
  930. .ops = &clkops_null,
  931. .recalc = &omap2_clksel_recalc,
  932. .round_rate = &omap2_clksel_round_rate,
  933. .set_rate = &omap2_clksel_set_rate,
  934. };
  935. static const struct clksel func_96m_fclk_div[] = {
  936. { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
  937. { .parent = NULL },
  938. };
  939. static struct clk func_96m_fclk = {
  940. .name = "func_96m_fclk",
  941. .parent = &dpll_per_m2x2_ck,
  942. .clksel = func_96m_fclk_div,
  943. .clksel_reg = OMAP4430_CM_SCALE_FCLK,
  944. .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
  945. .ops = &clkops_null,
  946. .recalc = &omap2_clksel_recalc,
  947. .round_rate = &omap2_clksel_round_rate,
  948. .set_rate = &omap2_clksel_set_rate,
  949. };
  950. static const struct clksel hsmmc6_fclk_sel[] = {
  951. { .parent = &func_64m_fclk, .rates = div_1_0_rates },
  952. { .parent = &func_96m_fclk, .rates = div_1_1_rates },
  953. { .parent = NULL },
  954. };
  955. static struct clk hsmmc6_fclk = {
  956. .name = "hsmmc6_fclk",
  957. .parent = &func_64m_fclk,
  958. .ops = &clkops_null,
  959. .recalc = &followparent_recalc,
  960. };
  961. static const struct clksel_rate div2_1to8_rates[] = {
  962. { .div = 1, .val = 0, .flags = RATE_IN_4430 },
  963. { .div = 8, .val = 1, .flags = RATE_IN_4430 },
  964. { .div = 0 },
  965. };
  966. static const struct clksel init_60m_fclk_div[] = {
  967. { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
  968. { .parent = NULL },
  969. };
  970. static struct clk init_60m_fclk = {
  971. .name = "init_60m_fclk",
  972. .parent = &dpll_usb_m2_ck,
  973. .clksel = init_60m_fclk_div,
  974. .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
  975. .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
  976. .ops = &clkops_null,
  977. .recalc = &omap2_clksel_recalc,
  978. .round_rate = &omap2_clksel_round_rate,
  979. .set_rate = &omap2_clksel_set_rate,
  980. };
  981. static const struct clksel l3_div_div[] = {
  982. { .parent = &div_core_ck, .rates = div2_1to2_rates },
  983. { .parent = NULL },
  984. };
  985. static struct clk l3_div_ck = {
  986. .name = "l3_div_ck",
  987. .parent = &div_core_ck,
  988. .clksel = l3_div_div,
  989. .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
  990. .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
  991. .ops = &clkops_null,
  992. .recalc = &omap2_clksel_recalc,
  993. .round_rate = &omap2_clksel_round_rate,
  994. .set_rate = &omap2_clksel_set_rate,
  995. };
  996. static const struct clksel l4_div_div[] = {
  997. { .parent = &l3_div_ck, .rates = div2_1to2_rates },
  998. { .parent = NULL },
  999. };
  1000. static struct clk l4_div_ck = {
  1001. .name = "l4_div_ck",
  1002. .parent = &l3_div_ck,
  1003. .clksel = l4_div_div,
  1004. .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
  1005. .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
  1006. .ops = &clkops_null,
  1007. .recalc = &omap2_clksel_recalc,
  1008. .round_rate = &omap2_clksel_round_rate,
  1009. .set_rate = &omap2_clksel_set_rate,
  1010. };
  1011. static struct clk lp_clk_div_ck = {
  1012. .name = "lp_clk_div_ck",
  1013. .parent = &dpll_abe_m2x2_ck,
  1014. .ops = &clkops_null,
  1015. .recalc = &followparent_recalc,
  1016. };
  1017. static const struct clksel l4_wkup_clk_mux_sel[] = {
  1018. { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
  1019. { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
  1020. { .parent = NULL },
  1021. };
  1022. static struct clk l4_wkup_clk_mux_ck = {
  1023. .name = "l4_wkup_clk_mux_ck",
  1024. .parent = &sys_clkin_ck,
  1025. .clksel = l4_wkup_clk_mux_sel,
  1026. .init = &omap2_init_clksel_parent,
  1027. .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
  1028. .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
  1029. .ops = &clkops_null,
  1030. .recalc = &omap2_clksel_recalc,
  1031. };
  1032. static const struct clksel per_abe_nc_fclk_div[] = {
  1033. { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
  1034. { .parent = NULL },
  1035. };
  1036. static struct clk per_abe_nc_fclk = {
  1037. .name = "per_abe_nc_fclk",
  1038. .parent = &dpll_abe_m2_ck,
  1039. .clksel = per_abe_nc_fclk_div,
  1040. .clksel_reg = OMAP4430_CM_SCALE_FCLK,
  1041. .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
  1042. .ops = &clkops_null,
  1043. .recalc = &omap2_clksel_recalc,
  1044. .round_rate = &omap2_clksel_round_rate,
  1045. .set_rate = &omap2_clksel_set_rate,
  1046. };
  1047. static const struct clksel mcasp2_fclk_sel[] = {
  1048. { .parent = &func_96m_fclk, .rates = div_1_0_rates },
  1049. { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
  1050. { .parent = NULL },
  1051. };
  1052. static struct clk mcasp2_fclk = {
  1053. .name = "mcasp2_fclk",
  1054. .parent = &func_96m_fclk,
  1055. .ops = &clkops_null,
  1056. .recalc = &followparent_recalc,
  1057. };
  1058. static struct clk mcasp3_fclk = {
  1059. .name = "mcasp3_fclk",
  1060. .parent = &func_96m_fclk,
  1061. .ops = &clkops_null,
  1062. .recalc = &followparent_recalc,
  1063. };
  1064. static struct clk ocp_abe_iclk = {
  1065. .name = "ocp_abe_iclk",
  1066. .parent = &aess_fclk,
  1067. .ops = &clkops_null,
  1068. .recalc = &followparent_recalc,
  1069. };
  1070. static struct clk per_abe_24m_fclk = {
  1071. .name = "per_abe_24m_fclk",
  1072. .parent = &dpll_abe_m2_ck,
  1073. .ops = &clkops_null,
  1074. .recalc = &followparent_recalc,
  1075. };
  1076. static const struct clksel pmd_stm_clock_mux_sel[] = {
  1077. { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
  1078. { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
  1079. { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
  1080. { .parent = NULL },
  1081. };
  1082. static struct clk pmd_stm_clock_mux_ck = {
  1083. .name = "pmd_stm_clock_mux_ck",
  1084. .parent = &sys_clkin_ck,
  1085. .ops = &clkops_null,
  1086. .recalc = &followparent_recalc,
  1087. };
  1088. static struct clk pmd_trace_clk_mux_ck = {
  1089. .name = "pmd_trace_clk_mux_ck",
  1090. .parent = &sys_clkin_ck,
  1091. .ops = &clkops_null,
  1092. .recalc = &followparent_recalc,
  1093. };
  1094. static const struct clksel syc_clk_div_div[] = {
  1095. { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
  1096. { .parent = NULL },
  1097. };
  1098. static struct clk syc_clk_div_ck = {
  1099. .name = "syc_clk_div_ck",
  1100. .parent = &sys_clkin_ck,
  1101. .clksel = syc_clk_div_div,
  1102. .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
  1103. .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
  1104. .ops = &clkops_null,
  1105. .recalc = &omap2_clksel_recalc,
  1106. .round_rate = &omap2_clksel_round_rate,
  1107. .set_rate = &omap2_clksel_set_rate,
  1108. };
  1109. /* Leaf clocks controlled by modules */
  1110. static struct clk aes1_fck = {
  1111. .name = "aes1_fck",
  1112. .ops = &clkops_omap2_dflt,
  1113. .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
  1114. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1115. .clkdm_name = "l4_secure_clkdm",
  1116. .parent = &l3_div_ck,
  1117. .recalc = &followparent_recalc,
  1118. };
  1119. static struct clk aes2_fck = {
  1120. .name = "aes2_fck",
  1121. .ops = &clkops_omap2_dflt,
  1122. .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
  1123. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1124. .clkdm_name = "l4_secure_clkdm",
  1125. .parent = &l3_div_ck,
  1126. .recalc = &followparent_recalc,
  1127. };
  1128. static struct clk aess_fck = {
  1129. .name = "aess_fck",
  1130. .ops = &clkops_omap2_dflt,
  1131. .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
  1132. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1133. .clkdm_name = "abe_clkdm",
  1134. .parent = &aess_fclk,
  1135. .recalc = &followparent_recalc,
  1136. };
  1137. static struct clk bandgap_fclk = {
  1138. .name = "bandgap_fclk",
  1139. .ops = &clkops_omap2_dflt,
  1140. .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
  1141. .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
  1142. .clkdm_name = "l4_wkup_clkdm",
  1143. .parent = &sys_32k_ck,
  1144. .recalc = &followparent_recalc,
  1145. };
  1146. static struct clk des3des_fck = {
  1147. .name = "des3des_fck",
  1148. .ops = &clkops_omap2_dflt,
  1149. .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
  1150. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1151. .clkdm_name = "l4_secure_clkdm",
  1152. .parent = &l4_div_ck,
  1153. .recalc = &followparent_recalc,
  1154. };
  1155. static const struct clksel dmic_sync_mux_sel[] = {
  1156. { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
  1157. { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
  1158. { .parent = &func_24m_clk, .rates = div_1_2_rates },
  1159. { .parent = NULL },
  1160. };
  1161. static struct clk dmic_sync_mux_ck = {
  1162. .name = "dmic_sync_mux_ck",
  1163. .parent = &abe_24m_fclk,
  1164. .clksel = dmic_sync_mux_sel,
  1165. .init = &omap2_init_clksel_parent,
  1166. .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
  1167. .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
  1168. .ops = &clkops_null,
  1169. .recalc = &omap2_clksel_recalc,
  1170. };
  1171. static const struct clksel func_dmic_abe_gfclk_sel[] = {
  1172. { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
  1173. { .parent = &pad_clks_ck, .rates = div_1_1_rates },
  1174. { .parent = &slimbus_clk, .rates = div_1_2_rates },
  1175. { .parent = NULL },
  1176. };
  1177. /* Merged func_dmic_abe_gfclk into dmic */
  1178. static struct clk dmic_fck = {
  1179. .name = "dmic_fck",
  1180. .parent = &dmic_sync_mux_ck,
  1181. .clksel = func_dmic_abe_gfclk_sel,
  1182. .init = &omap2_init_clksel_parent,
  1183. .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
  1184. .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
  1185. .ops = &clkops_omap2_dflt,
  1186. .recalc = &omap2_clksel_recalc,
  1187. .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
  1188. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1189. .clkdm_name = "abe_clkdm",
  1190. };
  1191. static struct clk dsp_fck = {
  1192. .name = "dsp_fck",
  1193. .ops = &clkops_omap2_dflt,
  1194. .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
  1195. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1196. .clkdm_name = "tesla_clkdm",
  1197. .parent = &dpll_iva_m4_ck,
  1198. .recalc = &followparent_recalc,
  1199. };
  1200. static struct clk dss_sys_clk = {
  1201. .name = "dss_sys_clk",
  1202. .ops = &clkops_omap2_dflt,
  1203. .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
  1204. .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
  1205. .clkdm_name = "l3_dss_clkdm",
  1206. .parent = &syc_clk_div_ck,
  1207. .recalc = &followparent_recalc,
  1208. };
  1209. static struct clk dss_tv_clk = {
  1210. .name = "dss_tv_clk",
  1211. .ops = &clkops_omap2_dflt,
  1212. .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
  1213. .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
  1214. .clkdm_name = "l3_dss_clkdm",
  1215. .parent = &extalt_clkin_ck,
  1216. .recalc = &followparent_recalc,
  1217. };
  1218. static struct clk dss_dss_clk = {
  1219. .name = "dss_dss_clk",
  1220. .ops = &clkops_omap2_dflt,
  1221. .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
  1222. .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
  1223. .clkdm_name = "l3_dss_clkdm",
  1224. .parent = &dpll_per_m5_ck,
  1225. .recalc = &followparent_recalc,
  1226. };
  1227. static struct clk dss_48mhz_clk = {
  1228. .name = "dss_48mhz_clk",
  1229. .ops = &clkops_omap2_dflt,
  1230. .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
  1231. .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
  1232. .clkdm_name = "l3_dss_clkdm",
  1233. .parent = &func_48mc_fclk,
  1234. .recalc = &followparent_recalc,
  1235. };
  1236. static struct clk dss_fck = {
  1237. .name = "dss_fck",
  1238. .ops = &clkops_omap2_dflt,
  1239. .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
  1240. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1241. .clkdm_name = "l3_dss_clkdm",
  1242. .parent = &l3_div_ck,
  1243. .recalc = &followparent_recalc,
  1244. };
  1245. static struct clk efuse_ctrl_cust_fck = {
  1246. .name = "efuse_ctrl_cust_fck",
  1247. .ops = &clkops_omap2_dflt,
  1248. .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
  1249. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1250. .clkdm_name = "l4_cefuse_clkdm",
  1251. .parent = &sys_clkin_ck,
  1252. .recalc = &followparent_recalc,
  1253. };
  1254. static struct clk emif1_fck = {
  1255. .name = "emif1_fck",
  1256. .ops = &clkops_omap2_dflt,
  1257. .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
  1258. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1259. .flags = ENABLE_ON_INIT,
  1260. .clkdm_name = "l3_emif_clkdm",
  1261. .parent = &ddrphy_ck,
  1262. .recalc = &followparent_recalc,
  1263. };
  1264. static struct clk emif2_fck = {
  1265. .name = "emif2_fck",
  1266. .ops = &clkops_omap2_dflt,
  1267. .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
  1268. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1269. .flags = ENABLE_ON_INIT,
  1270. .clkdm_name = "l3_emif_clkdm",
  1271. .parent = &ddrphy_ck,
  1272. .recalc = &followparent_recalc,
  1273. };
  1274. static const struct clksel fdif_fclk_div[] = {
  1275. { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
  1276. { .parent = NULL },
  1277. };
  1278. /* Merged fdif_fclk into fdif */
  1279. static struct clk fdif_fck = {
  1280. .name = "fdif_fck",
  1281. .parent = &dpll_per_m4_ck,
  1282. .clksel = fdif_fclk_div,
  1283. .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
  1284. .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
  1285. .ops = &clkops_omap2_dflt,
  1286. .recalc = &omap2_clksel_recalc,
  1287. .round_rate = &omap2_clksel_round_rate,
  1288. .set_rate = &omap2_clksel_set_rate,
  1289. .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
  1290. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1291. .clkdm_name = "iss_clkdm",
  1292. };
  1293. static struct clk fpka_fck = {
  1294. .name = "fpka_fck",
  1295. .ops = &clkops_omap2_dflt,
  1296. .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
  1297. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1298. .clkdm_name = "l4_secure_clkdm",
  1299. .parent = &l4_div_ck,
  1300. .recalc = &followparent_recalc,
  1301. };
  1302. static struct clk gpio1_dbclk = {
  1303. .name = "gpio1_dbclk",
  1304. .ops = &clkops_omap2_dflt,
  1305. .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
  1306. .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
  1307. .clkdm_name = "l4_wkup_clkdm",
  1308. .parent = &sys_32k_ck,
  1309. .recalc = &followparent_recalc,
  1310. };
  1311. static struct clk gpio1_ick = {
  1312. .name = "gpio1_ick",
  1313. .ops = &clkops_omap2_dflt,
  1314. .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
  1315. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1316. .clkdm_name = "l4_wkup_clkdm",
  1317. .parent = &l4_wkup_clk_mux_ck,
  1318. .recalc = &followparent_recalc,
  1319. };
  1320. static struct clk gpio2_dbclk = {
  1321. .name = "gpio2_dbclk",
  1322. .ops = &clkops_omap2_dflt,
  1323. .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
  1324. .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
  1325. .clkdm_name = "l4_per_clkdm",
  1326. .parent = &sys_32k_ck,
  1327. .recalc = &followparent_recalc,
  1328. };
  1329. static struct clk gpio2_ick = {
  1330. .name = "gpio2_ick",
  1331. .ops = &clkops_omap2_dflt,
  1332. .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
  1333. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1334. .clkdm_name = "l4_per_clkdm",
  1335. .parent = &l4_div_ck,
  1336. .recalc = &followparent_recalc,
  1337. };
  1338. static struct clk gpio3_dbclk = {
  1339. .name = "gpio3_dbclk",
  1340. .ops = &clkops_omap2_dflt,
  1341. .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
  1342. .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
  1343. .clkdm_name = "l4_per_clkdm",
  1344. .parent = &sys_32k_ck,
  1345. .recalc = &followparent_recalc,
  1346. };
  1347. static struct clk gpio3_ick = {
  1348. .name = "gpio3_ick",
  1349. .ops = &clkops_omap2_dflt,
  1350. .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
  1351. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1352. .clkdm_name = "l4_per_clkdm",
  1353. .parent = &l4_div_ck,
  1354. .recalc = &followparent_recalc,
  1355. };
  1356. static struct clk gpio4_dbclk = {
  1357. .name = "gpio4_dbclk",
  1358. .ops = &clkops_omap2_dflt,
  1359. .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
  1360. .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
  1361. .clkdm_name = "l4_per_clkdm",
  1362. .parent = &sys_32k_ck,
  1363. .recalc = &followparent_recalc,
  1364. };
  1365. static struct clk gpio4_ick = {
  1366. .name = "gpio4_ick",
  1367. .ops = &clkops_omap2_dflt,
  1368. .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
  1369. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1370. .clkdm_name = "l4_per_clkdm",
  1371. .parent = &l4_div_ck,
  1372. .recalc = &followparent_recalc,
  1373. };
  1374. static struct clk gpio5_dbclk = {
  1375. .name = "gpio5_dbclk",
  1376. .ops = &clkops_omap2_dflt,
  1377. .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
  1378. .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
  1379. .clkdm_name = "l4_per_clkdm",
  1380. .parent = &sys_32k_ck,
  1381. .recalc = &followparent_recalc,
  1382. };
  1383. static struct clk gpio5_ick = {
  1384. .name = "gpio5_ick",
  1385. .ops = &clkops_omap2_dflt,
  1386. .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
  1387. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1388. .clkdm_name = "l4_per_clkdm",
  1389. .parent = &l4_div_ck,
  1390. .recalc = &followparent_recalc,
  1391. };
  1392. static struct clk gpio6_dbclk = {
  1393. .name = "gpio6_dbclk",
  1394. .ops = &clkops_omap2_dflt,
  1395. .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
  1396. .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
  1397. .clkdm_name = "l4_per_clkdm",
  1398. .parent = &sys_32k_ck,
  1399. .recalc = &followparent_recalc,
  1400. };
  1401. static struct clk gpio6_ick = {
  1402. .name = "gpio6_ick",
  1403. .ops = &clkops_omap2_dflt,
  1404. .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
  1405. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1406. .clkdm_name = "l4_per_clkdm",
  1407. .parent = &l4_div_ck,
  1408. .recalc = &followparent_recalc,
  1409. };
  1410. static struct clk gpmc_ick = {
  1411. .name = "gpmc_ick",
  1412. .ops = &clkops_omap2_dflt,
  1413. .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
  1414. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1415. .clkdm_name = "l3_2_clkdm",
  1416. .parent = &l3_div_ck,
  1417. .recalc = &followparent_recalc,
  1418. };
  1419. static const struct clksel sgx_clk_mux_sel[] = {
  1420. { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
  1421. { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
  1422. { .parent = NULL },
  1423. };
  1424. /* Merged sgx_clk_mux into gpu */
  1425. static struct clk gpu_fck = {
  1426. .name = "gpu_fck",
  1427. .parent = &dpll_core_m7_ck,
  1428. .clksel = sgx_clk_mux_sel,
  1429. .init = &omap2_init_clksel_parent,
  1430. .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
  1431. .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
  1432. .ops = &clkops_omap2_dflt,
  1433. .recalc = &omap2_clksel_recalc,
  1434. .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
  1435. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1436. .clkdm_name = "l3_gfx_clkdm",
  1437. };
  1438. static struct clk hdq1w_fck = {
  1439. .name = "hdq1w_fck",
  1440. .ops = &clkops_omap2_dflt,
  1441. .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
  1442. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1443. .clkdm_name = "l4_per_clkdm",
  1444. .parent = &func_12m_fclk,
  1445. .recalc = &followparent_recalc,
  1446. };
  1447. static const struct clksel hsi_fclk_div[] = {
  1448. { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
  1449. { .parent = NULL },
  1450. };
  1451. /* Merged hsi_fclk into hsi */
  1452. static struct clk hsi_fck = {
  1453. .name = "hsi_fck",
  1454. .parent = &dpll_per_m2x2_ck,
  1455. .clksel = hsi_fclk_div,
  1456. .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
  1457. .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
  1458. .ops = &clkops_omap2_dflt,
  1459. .recalc = &omap2_clksel_recalc,
  1460. .round_rate = &omap2_clksel_round_rate,
  1461. .set_rate = &omap2_clksel_set_rate,
  1462. .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
  1463. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1464. .clkdm_name = "l3_init_clkdm",
  1465. };
  1466. static struct clk i2c1_fck = {
  1467. .name = "i2c1_fck",
  1468. .ops = &clkops_omap2_dflt,
  1469. .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
  1470. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1471. .clkdm_name = "l4_per_clkdm",
  1472. .parent = &func_96m_fclk,
  1473. .recalc = &followparent_recalc,
  1474. };
  1475. static struct clk i2c2_fck = {
  1476. .name = "i2c2_fck",
  1477. .ops = &clkops_omap2_dflt,
  1478. .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
  1479. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1480. .clkdm_name = "l4_per_clkdm",
  1481. .parent = &func_96m_fclk,
  1482. .recalc = &followparent_recalc,
  1483. };
  1484. static struct clk i2c3_fck = {
  1485. .name = "i2c3_fck",
  1486. .ops = &clkops_omap2_dflt,
  1487. .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
  1488. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1489. .clkdm_name = "l4_per_clkdm",
  1490. .parent = &func_96m_fclk,
  1491. .recalc = &followparent_recalc,
  1492. };
  1493. static struct clk i2c4_fck = {
  1494. .name = "i2c4_fck",
  1495. .ops = &clkops_omap2_dflt,
  1496. .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
  1497. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1498. .clkdm_name = "l4_per_clkdm",
  1499. .parent = &func_96m_fclk,
  1500. .recalc = &followparent_recalc,
  1501. };
  1502. static struct clk ipu_fck = {
  1503. .name = "ipu_fck",
  1504. .ops = &clkops_omap2_dflt,
  1505. .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
  1506. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1507. .clkdm_name = "ducati_clkdm",
  1508. .parent = &ducati_clk_mux_ck,
  1509. .recalc = &followparent_recalc,
  1510. };
  1511. static struct clk iss_ctrlclk = {
  1512. .name = "iss_ctrlclk",
  1513. .ops = &clkops_omap2_dflt,
  1514. .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
  1515. .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
  1516. .clkdm_name = "iss_clkdm",
  1517. .parent = &func_96m_fclk,
  1518. .recalc = &followparent_recalc,
  1519. };
  1520. static struct clk iss_fck = {
  1521. .name = "iss_fck",
  1522. .ops = &clkops_omap2_dflt,
  1523. .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
  1524. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1525. .clkdm_name = "iss_clkdm",
  1526. .parent = &ducati_clk_mux_ck,
  1527. .recalc = &followparent_recalc,
  1528. };
  1529. static struct clk iva_fck = {
  1530. .name = "iva_fck",
  1531. .ops = &clkops_omap2_dflt,
  1532. .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
  1533. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1534. .clkdm_name = "ivahd_clkdm",
  1535. .parent = &dpll_iva_m5_ck,
  1536. .recalc = &followparent_recalc,
  1537. };
  1538. static struct clk kbd_fck = {
  1539. .name = "kbd_fck",
  1540. .ops = &clkops_omap2_dflt,
  1541. .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
  1542. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1543. .clkdm_name = "l4_wkup_clkdm",
  1544. .parent = &sys_32k_ck,
  1545. .recalc = &followparent_recalc,
  1546. };
  1547. static struct clk l3_instr_ick = {
  1548. .name = "l3_instr_ick",
  1549. .ops = &clkops_omap2_dflt,
  1550. .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
  1551. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1552. .clkdm_name = "l3_instr_clkdm",
  1553. .parent = &l3_div_ck,
  1554. .recalc = &followparent_recalc,
  1555. };
  1556. static struct clk l3_main_3_ick = {
  1557. .name = "l3_main_3_ick",
  1558. .ops = &clkops_omap2_dflt,
  1559. .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
  1560. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1561. .clkdm_name = "l3_instr_clkdm",
  1562. .parent = &l3_div_ck,
  1563. .recalc = &followparent_recalc,
  1564. };
  1565. static struct clk mcasp_sync_mux_ck = {
  1566. .name = "mcasp_sync_mux_ck",
  1567. .parent = &abe_24m_fclk,
  1568. .clksel = dmic_sync_mux_sel,
  1569. .init = &omap2_init_clksel_parent,
  1570. .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
  1571. .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
  1572. .ops = &clkops_null,
  1573. .recalc = &omap2_clksel_recalc,
  1574. };
  1575. static const struct clksel func_mcasp_abe_gfclk_sel[] = {
  1576. { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
  1577. { .parent = &pad_clks_ck, .rates = div_1_1_rates },
  1578. { .parent = &slimbus_clk, .rates = div_1_2_rates },
  1579. { .parent = NULL },
  1580. };
  1581. /* Merged func_mcasp_abe_gfclk into mcasp */
  1582. static struct clk mcasp_fck = {
  1583. .name = "mcasp_fck",
  1584. .parent = &mcasp_sync_mux_ck,
  1585. .clksel = func_mcasp_abe_gfclk_sel,
  1586. .init = &omap2_init_clksel_parent,
  1587. .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
  1588. .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
  1589. .ops = &clkops_omap2_dflt,
  1590. .recalc = &omap2_clksel_recalc,
  1591. .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
  1592. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1593. .clkdm_name = "abe_clkdm",
  1594. };
  1595. static struct clk mcbsp1_sync_mux_ck = {
  1596. .name = "mcbsp1_sync_mux_ck",
  1597. .parent = &abe_24m_fclk,
  1598. .clksel = dmic_sync_mux_sel,
  1599. .init = &omap2_init_clksel_parent,
  1600. .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
  1601. .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
  1602. .ops = &clkops_null,
  1603. .recalc = &omap2_clksel_recalc,
  1604. };
  1605. static const struct clksel func_mcbsp1_gfclk_sel[] = {
  1606. { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
  1607. { .parent = &pad_clks_ck, .rates = div_1_1_rates },
  1608. { .parent = &slimbus_clk, .rates = div_1_2_rates },
  1609. { .parent = NULL },
  1610. };
  1611. /* Merged func_mcbsp1_gfclk into mcbsp1 */
  1612. static struct clk mcbsp1_fck = {
  1613. .name = "mcbsp1_fck",
  1614. .parent = &mcbsp1_sync_mux_ck,
  1615. .clksel = func_mcbsp1_gfclk_sel,
  1616. .init = &omap2_init_clksel_parent,
  1617. .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
  1618. .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
  1619. .ops = &clkops_omap2_dflt,
  1620. .recalc = &omap2_clksel_recalc,
  1621. .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
  1622. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1623. .clkdm_name = "abe_clkdm",
  1624. };
  1625. static struct clk mcbsp2_sync_mux_ck = {
  1626. .name = "mcbsp2_sync_mux_ck",
  1627. .parent = &abe_24m_fclk,
  1628. .clksel = dmic_sync_mux_sel,
  1629. .init = &omap2_init_clksel_parent,
  1630. .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
  1631. .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
  1632. .ops = &clkops_null,
  1633. .recalc = &omap2_clksel_recalc,
  1634. };
  1635. static const struct clksel func_mcbsp2_gfclk_sel[] = {
  1636. { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
  1637. { .parent = &pad_clks_ck, .rates = div_1_1_rates },
  1638. { .parent = &slimbus_clk, .rates = div_1_2_rates },
  1639. { .parent = NULL },
  1640. };
  1641. /* Merged func_mcbsp2_gfclk into mcbsp2 */
  1642. static struct clk mcbsp2_fck = {
  1643. .name = "mcbsp2_fck",
  1644. .parent = &mcbsp2_sync_mux_ck,
  1645. .clksel = func_mcbsp2_gfclk_sel,
  1646. .init = &omap2_init_clksel_parent,
  1647. .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
  1648. .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
  1649. .ops = &clkops_omap2_dflt,
  1650. .recalc = &omap2_clksel_recalc,
  1651. .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
  1652. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1653. .clkdm_name = "abe_clkdm",
  1654. };
  1655. static struct clk mcbsp3_sync_mux_ck = {
  1656. .name = "mcbsp3_sync_mux_ck",
  1657. .parent = &abe_24m_fclk,
  1658. .clksel = dmic_sync_mux_sel,
  1659. .init = &omap2_init_clksel_parent,
  1660. .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
  1661. .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
  1662. .ops = &clkops_null,
  1663. .recalc = &omap2_clksel_recalc,
  1664. };
  1665. static const struct clksel func_mcbsp3_gfclk_sel[] = {
  1666. { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
  1667. { .parent = &pad_clks_ck, .rates = div_1_1_rates },
  1668. { .parent = &slimbus_clk, .rates = div_1_2_rates },
  1669. { .parent = NULL },
  1670. };
  1671. /* Merged func_mcbsp3_gfclk into mcbsp3 */
  1672. static struct clk mcbsp3_fck = {
  1673. .name = "mcbsp3_fck",
  1674. .parent = &mcbsp3_sync_mux_ck,
  1675. .clksel = func_mcbsp3_gfclk_sel,
  1676. .init = &omap2_init_clksel_parent,
  1677. .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
  1678. .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
  1679. .ops = &clkops_omap2_dflt,
  1680. .recalc = &omap2_clksel_recalc,
  1681. .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
  1682. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1683. .clkdm_name = "abe_clkdm",
  1684. };
  1685. static struct clk mcbsp4_sync_mux_ck = {
  1686. .name = "mcbsp4_sync_mux_ck",
  1687. .parent = &func_96m_fclk,
  1688. .clksel = mcasp2_fclk_sel,
  1689. .init = &omap2_init_clksel_parent,
  1690. .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
  1691. .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
  1692. .ops = &clkops_null,
  1693. .recalc = &omap2_clksel_recalc,
  1694. };
  1695. static const struct clksel per_mcbsp4_gfclk_sel[] = {
  1696. { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
  1697. { .parent = &pad_clks_ck, .rates = div_1_1_rates },
  1698. { .parent = NULL },
  1699. };
  1700. /* Merged per_mcbsp4_gfclk into mcbsp4 */
  1701. static struct clk mcbsp4_fck = {
  1702. .name = "mcbsp4_fck",
  1703. .parent = &mcbsp4_sync_mux_ck,
  1704. .clksel = per_mcbsp4_gfclk_sel,
  1705. .init = &omap2_init_clksel_parent,
  1706. .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
  1707. .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
  1708. .ops = &clkops_omap2_dflt,
  1709. .recalc = &omap2_clksel_recalc,
  1710. .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
  1711. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1712. .clkdm_name = "l4_per_clkdm",
  1713. };
  1714. static struct clk mcpdm_fck = {
  1715. .name = "mcpdm_fck",
  1716. .ops = &clkops_omap2_dflt,
  1717. .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
  1718. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1719. .clkdm_name = "abe_clkdm",
  1720. .parent = &pad_clks_ck,
  1721. .recalc = &followparent_recalc,
  1722. };
  1723. static struct clk mcspi1_fck = {
  1724. .name = "mcspi1_fck",
  1725. .ops = &clkops_omap2_dflt,
  1726. .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
  1727. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1728. .clkdm_name = "l4_per_clkdm",
  1729. .parent = &func_48m_fclk,
  1730. .recalc = &followparent_recalc,
  1731. };
  1732. static struct clk mcspi2_fck = {
  1733. .name = "mcspi2_fck",
  1734. .ops = &clkops_omap2_dflt,
  1735. .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
  1736. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1737. .clkdm_name = "l4_per_clkdm",
  1738. .parent = &func_48m_fclk,
  1739. .recalc = &followparent_recalc,
  1740. };
  1741. static struct clk mcspi3_fck = {
  1742. .name = "mcspi3_fck",
  1743. .ops = &clkops_omap2_dflt,
  1744. .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
  1745. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1746. .clkdm_name = "l4_per_clkdm",
  1747. .parent = &func_48m_fclk,
  1748. .recalc = &followparent_recalc,
  1749. };
  1750. static struct clk mcspi4_fck = {
  1751. .name = "mcspi4_fck",
  1752. .ops = &clkops_omap2_dflt,
  1753. .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
  1754. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1755. .clkdm_name = "l4_per_clkdm",
  1756. .parent = &func_48m_fclk,
  1757. .recalc = &followparent_recalc,
  1758. };
  1759. /* Merged hsmmc1_fclk into mmc1 */
  1760. static struct clk mmc1_fck = {
  1761. .name = "mmc1_fck",
  1762. .parent = &func_64m_fclk,
  1763. .clksel = hsmmc6_fclk_sel,
  1764. .init = &omap2_init_clksel_parent,
  1765. .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
  1766. .clksel_mask = OMAP4430_CLKSEL_MASK,
  1767. .ops = &clkops_omap2_dflt,
  1768. .recalc = &omap2_clksel_recalc,
  1769. .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
  1770. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1771. .clkdm_name = "l3_init_clkdm",
  1772. };
  1773. /* Merged hsmmc2_fclk into mmc2 */
  1774. static struct clk mmc2_fck = {
  1775. .name = "mmc2_fck",
  1776. .parent = &func_64m_fclk,
  1777. .clksel = hsmmc6_fclk_sel,
  1778. .init = &omap2_init_clksel_parent,
  1779. .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
  1780. .clksel_mask = OMAP4430_CLKSEL_MASK,
  1781. .ops = &clkops_omap2_dflt,
  1782. .recalc = &omap2_clksel_recalc,
  1783. .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
  1784. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1785. .clkdm_name = "l3_init_clkdm",
  1786. };
  1787. static struct clk mmc3_fck = {
  1788. .name = "mmc3_fck",
  1789. .ops = &clkops_omap2_dflt,
  1790. .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
  1791. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1792. .clkdm_name = "l4_per_clkdm",
  1793. .parent = &func_48m_fclk,
  1794. .recalc = &followparent_recalc,
  1795. };
  1796. static struct clk mmc4_fck = {
  1797. .name = "mmc4_fck",
  1798. .ops = &clkops_omap2_dflt,
  1799. .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
  1800. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1801. .clkdm_name = "l4_per_clkdm",
  1802. .parent = &func_48m_fclk,
  1803. .recalc = &followparent_recalc,
  1804. };
  1805. static struct clk mmc5_fck = {
  1806. .name = "mmc5_fck",
  1807. .ops = &clkops_omap2_dflt,
  1808. .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
  1809. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1810. .clkdm_name = "l4_per_clkdm",
  1811. .parent = &func_48m_fclk,
  1812. .recalc = &followparent_recalc,
  1813. };
  1814. static struct clk ocp2scp_usb_phy_phy_48m = {
  1815. .name = "ocp2scp_usb_phy_phy_48m",
  1816. .ops = &clkops_omap2_dflt,
  1817. .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
  1818. .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
  1819. .clkdm_name = "l3_init_clkdm",
  1820. .parent = &func_48m_fclk,
  1821. .recalc = &followparent_recalc,
  1822. };
  1823. static struct clk ocp2scp_usb_phy_ick = {
  1824. .name = "ocp2scp_usb_phy_ick",
  1825. .ops = &clkops_omap2_dflt,
  1826. .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
  1827. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1828. .clkdm_name = "l3_init_clkdm",
  1829. .parent = &l4_div_ck,
  1830. .recalc = &followparent_recalc,
  1831. };
  1832. static struct clk ocp_wp_noc_ick = {
  1833. .name = "ocp_wp_noc_ick",
  1834. .ops = &clkops_omap2_dflt,
  1835. .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
  1836. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1837. .clkdm_name = "l3_instr_clkdm",
  1838. .parent = &l3_div_ck,
  1839. .recalc = &followparent_recalc,
  1840. };
  1841. static struct clk rng_ick = {
  1842. .name = "rng_ick",
  1843. .ops = &clkops_omap2_dflt,
  1844. .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
  1845. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1846. .clkdm_name = "l4_secure_clkdm",
  1847. .parent = &l4_div_ck,
  1848. .recalc = &followparent_recalc,
  1849. };
  1850. static struct clk sha2md5_fck = {
  1851. .name = "sha2md5_fck",
  1852. .ops = &clkops_omap2_dflt,
  1853. .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
  1854. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1855. .clkdm_name = "l4_secure_clkdm",
  1856. .parent = &l3_div_ck,
  1857. .recalc = &followparent_recalc,
  1858. };
  1859. static struct clk sl2if_ick = {
  1860. .name = "sl2if_ick",
  1861. .ops = &clkops_omap2_dflt,
  1862. .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
  1863. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  1864. .clkdm_name = "ivahd_clkdm",
  1865. .parent = &dpll_iva_m5_ck,
  1866. .recalc = &followparent_recalc,
  1867. };
  1868. static struct clk slimbus1_fclk_1 = {
  1869. .name = "slimbus1_fclk_1",
  1870. .ops = &clkops_omap2_dflt,
  1871. .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
  1872. .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
  1873. .clkdm_name = "abe_clkdm",
  1874. .parent = &func_24m_clk,
  1875. .recalc = &followparent_recalc,
  1876. };
  1877. static struct clk slimbus1_fclk_0 = {
  1878. .name = "slimbus1_fclk_0",
  1879. .ops = &clkops_omap2_dflt,
  1880. .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
  1881. .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
  1882. .clkdm_name = "abe_clkdm",
  1883. .parent = &abe_24m_fclk,
  1884. .recalc = &followparent_recalc,
  1885. };
  1886. static struct clk slimbus1_fclk_2 = {
  1887. .name = "slimbus1_fclk_2",
  1888. .ops = &clkops_omap2_dflt,
  1889. .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
  1890. .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
  1891. .clkdm_name = "abe_clkdm",
  1892. .parent = &pad_clks_ck,
  1893. .recalc = &followparent_recalc,
  1894. };
  1895. static struct clk slimbus1_slimbus_clk = {
  1896. .name = "slimbus1_slimbus_clk",
  1897. .ops = &clkops_omap2_dflt,
  1898. .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
  1899. .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
  1900. .clkdm_name = "abe_clkdm",
  1901. .parent = &slimbus_clk,
  1902. .recalc = &followparent_recalc,
  1903. };
  1904. static struct clk slimbus1_fck = {
  1905. .name = "slimbus1_fck",
  1906. .ops = &clkops_omap2_dflt,
  1907. .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
  1908. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1909. .clkdm_name = "abe_clkdm",
  1910. .parent = &ocp_abe_iclk,
  1911. .recalc = &followparent_recalc,
  1912. };
  1913. static struct clk slimbus2_fclk_1 = {
  1914. .name = "slimbus2_fclk_1",
  1915. .ops = &clkops_omap2_dflt,
  1916. .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
  1917. .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
  1918. .clkdm_name = "l4_per_clkdm",
  1919. .parent = &per_abe_24m_fclk,
  1920. .recalc = &followparent_recalc,
  1921. };
  1922. static struct clk slimbus2_fclk_0 = {
  1923. .name = "slimbus2_fclk_0",
  1924. .ops = &clkops_omap2_dflt,
  1925. .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
  1926. .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
  1927. .clkdm_name = "l4_per_clkdm",
  1928. .parent = &func_24mc_fclk,
  1929. .recalc = &followparent_recalc,
  1930. };
  1931. static struct clk slimbus2_slimbus_clk = {
  1932. .name = "slimbus2_slimbus_clk",
  1933. .ops = &clkops_omap2_dflt,
  1934. .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
  1935. .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
  1936. .clkdm_name = "l4_per_clkdm",
  1937. .parent = &pad_slimbus_core_clks_ck,
  1938. .recalc = &followparent_recalc,
  1939. };
  1940. static struct clk slimbus2_fck = {
  1941. .name = "slimbus2_fck",
  1942. .ops = &clkops_omap2_dflt,
  1943. .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
  1944. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1945. .clkdm_name = "l4_per_clkdm",
  1946. .parent = &l4_div_ck,
  1947. .recalc = &followparent_recalc,
  1948. };
  1949. static struct clk smartreflex_core_fck = {
  1950. .name = "smartreflex_core_fck",
  1951. .ops = &clkops_omap2_dflt,
  1952. .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
  1953. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1954. .clkdm_name = "l4_ao_clkdm",
  1955. .parent = &l4_wkup_clk_mux_ck,
  1956. .recalc = &followparent_recalc,
  1957. };
  1958. static struct clk smartreflex_iva_fck = {
  1959. .name = "smartreflex_iva_fck",
  1960. .ops = &clkops_omap2_dflt,
  1961. .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
  1962. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1963. .clkdm_name = "l4_ao_clkdm",
  1964. .parent = &l4_wkup_clk_mux_ck,
  1965. .recalc = &followparent_recalc,
  1966. };
  1967. static struct clk smartreflex_mpu_fck = {
  1968. .name = "smartreflex_mpu_fck",
  1969. .ops = &clkops_omap2_dflt,
  1970. .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
  1971. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1972. .clkdm_name = "l4_ao_clkdm",
  1973. .parent = &l4_wkup_clk_mux_ck,
  1974. .recalc = &followparent_recalc,
  1975. };
  1976. /* Merged dmt1_clk_mux into timer1 */
  1977. static struct clk timer1_fck = {
  1978. .name = "timer1_fck",
  1979. .parent = &sys_clkin_ck,
  1980. .clksel = abe_dpll_bypass_clk_mux_sel,
  1981. .init = &omap2_init_clksel_parent,
  1982. .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
  1983. .clksel_mask = OMAP4430_CLKSEL_MASK,
  1984. .ops = &clkops_omap2_dflt,
  1985. .recalc = &omap2_clksel_recalc,
  1986. .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
  1987. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  1988. .clkdm_name = "l4_wkup_clkdm",
  1989. };
  1990. /* Merged cm2_dm10_mux into timer10 */
  1991. static struct clk timer10_fck = {
  1992. .name = "timer10_fck",
  1993. .parent = &sys_clkin_ck,
  1994. .clksel = abe_dpll_bypass_clk_mux_sel,
  1995. .init = &omap2_init_clksel_parent,
  1996. .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
  1997. .clksel_mask = OMAP4430_CLKSEL_MASK,
  1998. .ops = &clkops_omap2_dflt,
  1999. .recalc = &omap2_clksel_recalc,
  2000. .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
  2001. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2002. .clkdm_name = "l4_per_clkdm",
  2003. };
  2004. /* Merged cm2_dm11_mux into timer11 */
  2005. static struct clk timer11_fck = {
  2006. .name = "timer11_fck",
  2007. .parent = &sys_clkin_ck,
  2008. .clksel = abe_dpll_bypass_clk_mux_sel,
  2009. .init = &omap2_init_clksel_parent,
  2010. .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
  2011. .clksel_mask = OMAP4430_CLKSEL_MASK,
  2012. .ops = &clkops_omap2_dflt,
  2013. .recalc = &omap2_clksel_recalc,
  2014. .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
  2015. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2016. .clkdm_name = "l4_per_clkdm",
  2017. };
  2018. /* Merged cm2_dm2_mux into timer2 */
  2019. static struct clk timer2_fck = {
  2020. .name = "timer2_fck",
  2021. .parent = &sys_clkin_ck,
  2022. .clksel = abe_dpll_bypass_clk_mux_sel,
  2023. .init = &omap2_init_clksel_parent,
  2024. .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
  2025. .clksel_mask = OMAP4430_CLKSEL_MASK,
  2026. .ops = &clkops_omap2_dflt,
  2027. .recalc = &omap2_clksel_recalc,
  2028. .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
  2029. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2030. .clkdm_name = "l4_per_clkdm",
  2031. };
  2032. /* Merged cm2_dm3_mux into timer3 */
  2033. static struct clk timer3_fck = {
  2034. .name = "timer3_fck",
  2035. .parent = &sys_clkin_ck,
  2036. .clksel = abe_dpll_bypass_clk_mux_sel,
  2037. .init = &omap2_init_clksel_parent,
  2038. .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
  2039. .clksel_mask = OMAP4430_CLKSEL_MASK,
  2040. .ops = &clkops_omap2_dflt,
  2041. .recalc = &omap2_clksel_recalc,
  2042. .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
  2043. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2044. .clkdm_name = "l4_per_clkdm",
  2045. };
  2046. /* Merged cm2_dm4_mux into timer4 */
  2047. static struct clk timer4_fck = {
  2048. .name = "timer4_fck",
  2049. .parent = &sys_clkin_ck,
  2050. .clksel = abe_dpll_bypass_clk_mux_sel,
  2051. .init = &omap2_init_clksel_parent,
  2052. .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
  2053. .clksel_mask = OMAP4430_CLKSEL_MASK,
  2054. .ops = &clkops_omap2_dflt,
  2055. .recalc = &omap2_clksel_recalc,
  2056. .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
  2057. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2058. .clkdm_name = "l4_per_clkdm",
  2059. };
  2060. static const struct clksel timer5_sync_mux_sel[] = {
  2061. { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
  2062. { .parent = &sys_32k_ck, .rates = div_1_1_rates },
  2063. { .parent = NULL },
  2064. };
  2065. /* Merged timer5_sync_mux into timer5 */
  2066. static struct clk timer5_fck = {
  2067. .name = "timer5_fck",
  2068. .parent = &syc_clk_div_ck,
  2069. .clksel = timer5_sync_mux_sel,
  2070. .init = &omap2_init_clksel_parent,
  2071. .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
  2072. .clksel_mask = OMAP4430_CLKSEL_MASK,
  2073. .ops = &clkops_omap2_dflt,
  2074. .recalc = &omap2_clksel_recalc,
  2075. .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
  2076. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2077. .clkdm_name = "abe_clkdm",
  2078. };
  2079. /* Merged timer6_sync_mux into timer6 */
  2080. static struct clk timer6_fck = {
  2081. .name = "timer6_fck",
  2082. .parent = &syc_clk_div_ck,
  2083. .clksel = timer5_sync_mux_sel,
  2084. .init = &omap2_init_clksel_parent,
  2085. .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
  2086. .clksel_mask = OMAP4430_CLKSEL_MASK,
  2087. .ops = &clkops_omap2_dflt,
  2088. .recalc = &omap2_clksel_recalc,
  2089. .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
  2090. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2091. .clkdm_name = "abe_clkdm",
  2092. };
  2093. /* Merged timer7_sync_mux into timer7 */
  2094. static struct clk timer7_fck = {
  2095. .name = "timer7_fck",
  2096. .parent = &syc_clk_div_ck,
  2097. .clksel = timer5_sync_mux_sel,
  2098. .init = &omap2_init_clksel_parent,
  2099. .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
  2100. .clksel_mask = OMAP4430_CLKSEL_MASK,
  2101. .ops = &clkops_omap2_dflt,
  2102. .recalc = &omap2_clksel_recalc,
  2103. .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
  2104. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2105. .clkdm_name = "abe_clkdm",
  2106. };
  2107. /* Merged timer8_sync_mux into timer8 */
  2108. static struct clk timer8_fck = {
  2109. .name = "timer8_fck",
  2110. .parent = &syc_clk_div_ck,
  2111. .clksel = timer5_sync_mux_sel,
  2112. .init = &omap2_init_clksel_parent,
  2113. .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
  2114. .clksel_mask = OMAP4430_CLKSEL_MASK,
  2115. .ops = &clkops_omap2_dflt,
  2116. .recalc = &omap2_clksel_recalc,
  2117. .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
  2118. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2119. .clkdm_name = "abe_clkdm",
  2120. };
  2121. /* Merged cm2_dm9_mux into timer9 */
  2122. static struct clk timer9_fck = {
  2123. .name = "timer9_fck",
  2124. .parent = &sys_clkin_ck,
  2125. .clksel = abe_dpll_bypass_clk_mux_sel,
  2126. .init = &omap2_init_clksel_parent,
  2127. .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
  2128. .clksel_mask = OMAP4430_CLKSEL_MASK,
  2129. .ops = &clkops_omap2_dflt,
  2130. .recalc = &omap2_clksel_recalc,
  2131. .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
  2132. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2133. .clkdm_name = "l4_per_clkdm",
  2134. };
  2135. static struct clk uart1_fck = {
  2136. .name = "uart1_fck",
  2137. .ops = &clkops_omap2_dflt,
  2138. .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
  2139. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2140. .clkdm_name = "l4_per_clkdm",
  2141. .parent = &func_48m_fclk,
  2142. .recalc = &followparent_recalc,
  2143. };
  2144. static struct clk uart2_fck = {
  2145. .name = "uart2_fck",
  2146. .ops = &clkops_omap2_dflt,
  2147. .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
  2148. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2149. .clkdm_name = "l4_per_clkdm",
  2150. .parent = &func_48m_fclk,
  2151. .recalc = &followparent_recalc,
  2152. };
  2153. static struct clk uart3_fck = {
  2154. .name = "uart3_fck",
  2155. .ops = &clkops_omap2_dflt,
  2156. .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
  2157. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2158. .clkdm_name = "l4_per_clkdm",
  2159. .parent = &func_48m_fclk,
  2160. .recalc = &followparent_recalc,
  2161. };
  2162. static struct clk uart4_fck = {
  2163. .name = "uart4_fck",
  2164. .ops = &clkops_omap2_dflt,
  2165. .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
  2166. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2167. .clkdm_name = "l4_per_clkdm",
  2168. .parent = &func_48m_fclk,
  2169. .recalc = &followparent_recalc,
  2170. };
  2171. static struct clk usb_host_fs_fck = {
  2172. .name = "usb_host_fs_fck",
  2173. .ops = &clkops_omap2_dflt,
  2174. .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
  2175. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2176. .clkdm_name = "l3_init_clkdm",
  2177. .parent = &func_48mc_fclk,
  2178. .recalc = &followparent_recalc,
  2179. };
  2180. static struct clk usb_host_hs_utmi_p3_clk = {
  2181. .name = "usb_host_hs_utmi_p3_clk",
  2182. .ops = &clkops_omap2_dflt,
  2183. .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2184. .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
  2185. .clkdm_name = "l3_init_clkdm",
  2186. .parent = &init_60m_fclk,
  2187. .recalc = &followparent_recalc,
  2188. };
  2189. static struct clk usb_host_hs_hsic60m_p1_clk = {
  2190. .name = "usb_host_hs_hsic60m_p1_clk",
  2191. .ops = &clkops_omap2_dflt,
  2192. .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2193. .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
  2194. .clkdm_name = "l3_init_clkdm",
  2195. .parent = &init_60m_fclk,
  2196. .recalc = &followparent_recalc,
  2197. };
  2198. static struct clk usb_host_hs_hsic60m_p2_clk = {
  2199. .name = "usb_host_hs_hsic60m_p2_clk",
  2200. .ops = &clkops_omap2_dflt,
  2201. .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2202. .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
  2203. .clkdm_name = "l3_init_clkdm",
  2204. .parent = &init_60m_fclk,
  2205. .recalc = &followparent_recalc,
  2206. };
  2207. static const struct clksel utmi_p1_gfclk_sel[] = {
  2208. { .parent = &init_60m_fclk, .rates = div_1_0_rates },
  2209. { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
  2210. { .parent = NULL },
  2211. };
  2212. static struct clk utmi_p1_gfclk = {
  2213. .name = "utmi_p1_gfclk",
  2214. .parent = &init_60m_fclk,
  2215. .clksel = utmi_p1_gfclk_sel,
  2216. .init = &omap2_init_clksel_parent,
  2217. .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2218. .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
  2219. .ops = &clkops_null,
  2220. .recalc = &omap2_clksel_recalc,
  2221. };
  2222. static struct clk usb_host_hs_utmi_p1_clk = {
  2223. .name = "usb_host_hs_utmi_p1_clk",
  2224. .ops = &clkops_omap2_dflt,
  2225. .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2226. .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
  2227. .clkdm_name = "l3_init_clkdm",
  2228. .parent = &utmi_p1_gfclk,
  2229. .recalc = &followparent_recalc,
  2230. };
  2231. static const struct clksel utmi_p2_gfclk_sel[] = {
  2232. { .parent = &init_60m_fclk, .rates = div_1_0_rates },
  2233. { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
  2234. { .parent = NULL },
  2235. };
  2236. static struct clk utmi_p2_gfclk = {
  2237. .name = "utmi_p2_gfclk",
  2238. .parent = &init_60m_fclk,
  2239. .clksel = utmi_p2_gfclk_sel,
  2240. .init = &omap2_init_clksel_parent,
  2241. .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2242. .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
  2243. .ops = &clkops_null,
  2244. .recalc = &omap2_clksel_recalc,
  2245. };
  2246. static struct clk usb_host_hs_utmi_p2_clk = {
  2247. .name = "usb_host_hs_utmi_p2_clk",
  2248. .ops = &clkops_omap2_dflt,
  2249. .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2250. .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
  2251. .clkdm_name = "l3_init_clkdm",
  2252. .parent = &utmi_p2_gfclk,
  2253. .recalc = &followparent_recalc,
  2254. };
  2255. static struct clk usb_host_hs_hsic480m_p1_clk = {
  2256. .name = "usb_host_hs_hsic480m_p1_clk",
  2257. .ops = &clkops_omap2_dflt,
  2258. .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2259. .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
  2260. .clkdm_name = "l3_init_clkdm",
  2261. .parent = &dpll_usb_m2_ck,
  2262. .recalc = &followparent_recalc,
  2263. };
  2264. static struct clk usb_host_hs_hsic480m_p2_clk = {
  2265. .name = "usb_host_hs_hsic480m_p2_clk",
  2266. .ops = &clkops_omap2_dflt,
  2267. .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2268. .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
  2269. .clkdm_name = "l3_init_clkdm",
  2270. .parent = &dpll_usb_m2_ck,
  2271. .recalc = &followparent_recalc,
  2272. };
  2273. static struct clk usb_host_hs_func48mclk = {
  2274. .name = "usb_host_hs_func48mclk",
  2275. .ops = &clkops_omap2_dflt,
  2276. .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2277. .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
  2278. .clkdm_name = "l3_init_clkdm",
  2279. .parent = &func_48mc_fclk,
  2280. .recalc = &followparent_recalc,
  2281. };
  2282. static struct clk usb_host_hs_fck = {
  2283. .name = "usb_host_hs_fck",
  2284. .ops = &clkops_omap2_dflt,
  2285. .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
  2286. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2287. .clkdm_name = "l3_init_clkdm",
  2288. .parent = &init_60m_fclk,
  2289. .recalc = &followparent_recalc,
  2290. };
  2291. static const struct clksel otg_60m_gfclk_sel[] = {
  2292. { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
  2293. { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
  2294. { .parent = NULL },
  2295. };
  2296. static struct clk otg_60m_gfclk = {
  2297. .name = "otg_60m_gfclk",
  2298. .parent = &utmi_phy_clkout_ck,
  2299. .clksel = otg_60m_gfclk_sel,
  2300. .init = &omap2_init_clksel_parent,
  2301. .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
  2302. .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
  2303. .ops = &clkops_null,
  2304. .recalc = &omap2_clksel_recalc,
  2305. };
  2306. static struct clk usb_otg_hs_xclk = {
  2307. .name = "usb_otg_hs_xclk",
  2308. .ops = &clkops_omap2_dflt,
  2309. .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
  2310. .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
  2311. .clkdm_name = "l3_init_clkdm",
  2312. .parent = &otg_60m_gfclk,
  2313. .recalc = &followparent_recalc,
  2314. };
  2315. static struct clk usb_otg_hs_ick = {
  2316. .name = "usb_otg_hs_ick",
  2317. .ops = &clkops_omap2_dflt,
  2318. .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
  2319. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  2320. .clkdm_name = "l3_init_clkdm",
  2321. .parent = &l3_div_ck,
  2322. .recalc = &followparent_recalc,
  2323. };
  2324. static struct clk usb_phy_cm_clk32k = {
  2325. .name = "usb_phy_cm_clk32k",
  2326. .ops = &clkops_omap2_dflt,
  2327. .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
  2328. .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
  2329. .clkdm_name = "l4_ao_clkdm",
  2330. .parent = &sys_32k_ck,
  2331. .recalc = &followparent_recalc,
  2332. };
  2333. static struct clk usb_tll_hs_usb_ch2_clk = {
  2334. .name = "usb_tll_hs_usb_ch2_clk",
  2335. .ops = &clkops_omap2_dflt,
  2336. .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
  2337. .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
  2338. .clkdm_name = "l3_init_clkdm",
  2339. .parent = &init_60m_fclk,
  2340. .recalc = &followparent_recalc,
  2341. };
  2342. static struct clk usb_tll_hs_usb_ch0_clk = {
  2343. .name = "usb_tll_hs_usb_ch0_clk",
  2344. .ops = &clkops_omap2_dflt,
  2345. .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
  2346. .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
  2347. .clkdm_name = "l3_init_clkdm",
  2348. .parent = &init_60m_fclk,
  2349. .recalc = &followparent_recalc,
  2350. };
  2351. static struct clk usb_tll_hs_usb_ch1_clk = {
  2352. .name = "usb_tll_hs_usb_ch1_clk",
  2353. .ops = &clkops_omap2_dflt,
  2354. .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
  2355. .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
  2356. .clkdm_name = "l3_init_clkdm",
  2357. .parent = &init_60m_fclk,
  2358. .recalc = &followparent_recalc,
  2359. };
  2360. static struct clk usb_tll_hs_ick = {
  2361. .name = "usb_tll_hs_ick",
  2362. .ops = &clkops_omap2_dflt,
  2363. .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
  2364. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  2365. .clkdm_name = "l3_init_clkdm",
  2366. .parent = &l4_div_ck,
  2367. .recalc = &followparent_recalc,
  2368. };
  2369. static const struct clksel_rate div2_14to18_rates[] = {
  2370. { .div = 14, .val = 0, .flags = RATE_IN_4430 },
  2371. { .div = 18, .val = 1, .flags = RATE_IN_4430 },
  2372. { .div = 0 },
  2373. };
  2374. static const struct clksel usim_fclk_div[] = {
  2375. { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
  2376. { .parent = NULL },
  2377. };
  2378. static struct clk usim_ck = {
  2379. .name = "usim_ck",
  2380. .parent = &dpll_per_m4_ck,
  2381. .clksel = usim_fclk_div,
  2382. .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
  2383. .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
  2384. .ops = &clkops_null,
  2385. .recalc = &omap2_clksel_recalc,
  2386. .round_rate = &omap2_clksel_round_rate,
  2387. .set_rate = &omap2_clksel_set_rate,
  2388. };
  2389. static struct clk usim_fclk = {
  2390. .name = "usim_fclk",
  2391. .ops = &clkops_omap2_dflt,
  2392. .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
  2393. .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
  2394. .clkdm_name = "l4_wkup_clkdm",
  2395. .parent = &usim_ck,
  2396. .recalc = &followparent_recalc,
  2397. };
  2398. static struct clk usim_fck = {
  2399. .name = "usim_fck",
  2400. .ops = &clkops_omap2_dflt,
  2401. .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
  2402. .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
  2403. .clkdm_name = "l4_wkup_clkdm",
  2404. .parent = &sys_32k_ck,
  2405. .recalc = &followparent_recalc,
  2406. };
  2407. static struct clk wd_timer2_fck = {
  2408. .name = "wd_timer2_fck",
  2409. .ops = &clkops_omap2_dflt,
  2410. .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
  2411. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2412. .clkdm_name = "l4_wkup_clkdm",
  2413. .parent = &sys_32k_ck,
  2414. .recalc = &followparent_recalc,
  2415. };
  2416. static struct clk wd_timer3_fck = {
  2417. .name = "wd_timer3_fck",
  2418. .ops = &clkops_omap2_dflt,
  2419. .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
  2420. .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
  2421. .clkdm_name = "abe_clkdm",
  2422. .parent = &sys_32k_ck,
  2423. .recalc = &followparent_recalc,
  2424. };
  2425. /* Remaining optional clocks */
  2426. static const struct clksel stm_clk_div_div[] = {
  2427. { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
  2428. { .parent = NULL },
  2429. };
  2430. static struct clk stm_clk_div_ck = {
  2431. .name = "stm_clk_div_ck",
  2432. .parent = &pmd_stm_clock_mux_ck,
  2433. .clksel = stm_clk_div_div,
  2434. .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
  2435. .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
  2436. .ops = &clkops_null,
  2437. .recalc = &omap2_clksel_recalc,
  2438. .round_rate = &omap2_clksel_round_rate,
  2439. .set_rate = &omap2_clksel_set_rate,
  2440. };
  2441. static const struct clksel trace_clk_div_div[] = {
  2442. { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
  2443. { .parent = NULL },
  2444. };
  2445. static struct clk trace_clk_div_ck = {
  2446. .name = "trace_clk_div_ck",
  2447. .parent = &pmd_trace_clk_mux_ck,
  2448. .clksel = trace_clk_div_div,
  2449. .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
  2450. .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
  2451. .ops = &clkops_null,
  2452. .recalc = &omap2_clksel_recalc,
  2453. .round_rate = &omap2_clksel_round_rate,
  2454. .set_rate = &omap2_clksel_set_rate,
  2455. };
  2456. /*
  2457. * clkdev
  2458. */
  2459. static struct omap_clk omap44xx_clks[] = {
  2460. CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
  2461. CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
  2462. CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
  2463. CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
  2464. CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
  2465. CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
  2466. CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
  2467. CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
  2468. CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
  2469. CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
  2470. CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
  2471. CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
  2472. CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
  2473. CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
  2474. CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
  2475. CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
  2476. CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
  2477. CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
  2478. CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
  2479. CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
  2480. CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
  2481. CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
  2482. CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
  2483. CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
  2484. CLK(NULL, "abe_clk", &abe_clk, CK_443X),
  2485. CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
  2486. CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X),
  2487. CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
  2488. CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
  2489. CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X),
  2490. CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
  2491. CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
  2492. CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
  2493. CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X),
  2494. CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
  2495. CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
  2496. CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
  2497. CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X),
  2498. CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
  2499. CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
  2500. CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X),
  2501. CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X),
  2502. CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
  2503. CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
  2504. CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X),
  2505. CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X),
  2506. CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
  2507. CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
  2508. CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
  2509. CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
  2510. CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
  2511. CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
  2512. CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
  2513. CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X),
  2514. CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X),
  2515. CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X),
  2516. CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X),
  2517. CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X),
  2518. CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
  2519. CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
  2520. CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
  2521. CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
  2522. CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
  2523. CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
  2524. CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
  2525. CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
  2526. CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
  2527. CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
  2528. CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
  2529. CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
  2530. CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
  2531. CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
  2532. CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
  2533. CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
  2534. CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
  2535. CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
  2536. CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
  2537. CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
  2538. CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
  2539. CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
  2540. CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
  2541. CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
  2542. CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
  2543. CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
  2544. CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
  2545. CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
  2546. CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
  2547. CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
  2548. CLK(NULL, "aess_fck", &aess_fck, CK_443X),
  2549. CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
  2550. CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
  2551. CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
  2552. CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
  2553. CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
  2554. CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
  2555. CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
  2556. CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
  2557. CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
  2558. CLK(NULL, "dss_fck", &dss_fck, CK_443X),
  2559. CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
  2560. CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
  2561. CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
  2562. CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
  2563. CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
  2564. CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X),
  2565. CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
  2566. CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X),
  2567. CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
  2568. CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X),
  2569. CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
  2570. CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X),
  2571. CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
  2572. CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X),
  2573. CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
  2574. CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X),
  2575. CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
  2576. CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
  2577. CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
  2578. CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
  2579. CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
  2580. CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
  2581. CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
  2582. CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
  2583. CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
  2584. CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
  2585. CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
  2586. CLK(NULL, "iss_fck", &iss_fck, CK_443X),
  2587. CLK(NULL, "iva_fck", &iva_fck, CK_443X),
  2588. CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
  2589. CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
  2590. CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
  2591. CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
  2592. CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
  2593. CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
  2594. CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X),
  2595. CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
  2596. CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X),
  2597. CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
  2598. CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
  2599. CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
  2600. CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
  2601. CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
  2602. CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
  2603. CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
  2604. CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
  2605. CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
  2606. CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X),
  2607. CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X),
  2608. CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
  2609. CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
  2610. CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
  2611. CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
  2612. CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
  2613. CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
  2614. CLK("omap_rng", "ick", &rng_ick, CK_443X),
  2615. CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
  2616. CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
  2617. CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
  2618. CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
  2619. CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
  2620. CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
  2621. CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
  2622. CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
  2623. CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
  2624. CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
  2625. CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
  2626. CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
  2627. CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
  2628. CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
  2629. CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
  2630. CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
  2631. CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
  2632. CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
  2633. CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
  2634. CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
  2635. CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
  2636. CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
  2637. CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
  2638. CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
  2639. CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
  2640. CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
  2641. CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
  2642. CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
  2643. CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
  2644. CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
  2645. CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
  2646. CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
  2647. CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
  2648. CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
  2649. CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
  2650. CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
  2651. CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
  2652. CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
  2653. CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
  2654. CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
  2655. CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
  2656. CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
  2657. CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
  2658. CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X),
  2659. CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
  2660. CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
  2661. CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
  2662. CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
  2663. CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
  2664. CLK(NULL, "usim_ck", &usim_ck, CK_443X),
  2665. CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
  2666. CLK(NULL, "usim_fck", &usim_fck, CK_443X),
  2667. CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
  2668. CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
  2669. CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
  2670. CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
  2671. CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
  2672. CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
  2673. CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
  2674. CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
  2675. CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
  2676. CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
  2677. CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
  2678. CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
  2679. CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
  2680. CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
  2681. CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
  2682. CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
  2683. CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X),
  2684. CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
  2685. CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
  2686. CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
  2687. CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
  2688. CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
  2689. CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
  2690. CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
  2691. CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
  2692. CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
  2693. CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
  2694. CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
  2695. CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
  2696. CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
  2697. CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
  2698. CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
  2699. CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
  2700. CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
  2701. CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
  2702. CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
  2703. CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
  2704. CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
  2705. };
  2706. int __init omap4xxx_clk_init(void)
  2707. {
  2708. struct omap_clk *c;
  2709. u32 cpu_clkflg;
  2710. if (cpu_is_omap44xx()) {
  2711. cpu_mask = RATE_IN_4430;
  2712. cpu_clkflg = CK_443X;
  2713. }
  2714. clk_init(&omap2_clk_functions);
  2715. for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
  2716. c++)
  2717. clk_preinit(c->lk.clk);
  2718. for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
  2719. c++)
  2720. if (c->cpu & cpu_clkflg) {
  2721. clkdev_add(&c->lk);
  2722. clk_register(c->lk.clk);
  2723. omap2_init_clk_clkdm(c->lk.clk);
  2724. }
  2725. recalculate_root_clocks();
  2726. /*
  2727. * Only enable those clocks we will need, let the drivers
  2728. * enable other clocks as necessary
  2729. */
  2730. clk_enable_init_clocks();
  2731. return 0;
  2732. }