clock2430_data.c 60 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/clock2430_data.c
  3. *
  4. * Copyright (C) 2005-2009 Texas Instruments, Inc.
  5. * Copyright (C) 2004-2010 Nokia Corporation
  6. *
  7. * Contacts:
  8. * Richard Woodruff <r-woodruff2@ti.com>
  9. * Paul Walmsley
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/clk.h>
  17. #include <linux/list.h>
  18. #include <plat/clkdev_omap.h>
  19. #include "clock.h"
  20. #include "clock2xxx.h"
  21. #include "opp2xxx.h"
  22. #include "prm.h"
  23. #include "cm.h"
  24. #include "prm-regbits-24xx.h"
  25. #include "cm-regbits-24xx.h"
  26. #include "sdrc.h"
  27. #include "control.h"
  28. #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
  29. /*
  30. * 2430 clock tree.
  31. *
  32. * NOTE:In many cases here we are assigning a 'default' parent. In many
  33. * cases the parent is selectable. The get/set parent calls will also
  34. * switch sources.
  35. *
  36. * Many some clocks say always_enabled, but they can be auto idled for
  37. * power savings. They will always be available upon clock request.
  38. *
  39. * Several sources are given initial rates which may be wrong, this will
  40. * be fixed up in the init func.
  41. *
  42. * Things are broadly separated below by clock domains. It is
  43. * noteworthy that most periferals have dependencies on multiple clock
  44. * domains. Many get their interface clocks from the L4 domain, but get
  45. * functional clocks from fixed sources or other core domain derived
  46. * clocks.
  47. */
  48. /* Base external input clocks */
  49. static struct clk func_32k_ck = {
  50. .name = "func_32k_ck",
  51. .ops = &clkops_null,
  52. .rate = 32000,
  53. .clkdm_name = "wkup_clkdm",
  54. };
  55. static struct clk secure_32k_ck = {
  56. .name = "secure_32k_ck",
  57. .ops = &clkops_null,
  58. .rate = 32768,
  59. .clkdm_name = "wkup_clkdm",
  60. };
  61. /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
  62. static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
  63. .name = "osc_ck",
  64. .ops = &clkops_oscck,
  65. .clkdm_name = "wkup_clkdm",
  66. .recalc = &omap2_osc_clk_recalc,
  67. };
  68. /* Without modem likely 12MHz, with modem likely 13MHz */
  69. static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
  70. .name = "sys_ck", /* ~ ref_clk also */
  71. .ops = &clkops_null,
  72. .parent = &osc_ck,
  73. .clkdm_name = "wkup_clkdm",
  74. .recalc = &omap2xxx_sys_clk_recalc,
  75. };
  76. static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
  77. .name = "alt_ck",
  78. .ops = &clkops_null,
  79. .rate = 54000000,
  80. .clkdm_name = "wkup_clkdm",
  81. };
  82. /* Optional external clock input for McBSP CLKS */
  83. static struct clk mcbsp_clks = {
  84. .name = "mcbsp_clks",
  85. .ops = &clkops_null,
  86. };
  87. /*
  88. * Analog domain root source clocks
  89. */
  90. /* dpll_ck, is broken out in to special cases through clksel */
  91. /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
  92. * deal with this
  93. */
  94. static struct dpll_data dpll_dd = {
  95. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  96. .mult_mask = OMAP24XX_DPLL_MULT_MASK,
  97. .div1_mask = OMAP24XX_DPLL_DIV_MASK,
  98. .clk_bypass = &sys_ck,
  99. .clk_ref = &sys_ck,
  100. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  101. .enable_mask = OMAP24XX_EN_DPLL_MASK,
  102. .max_multiplier = 1023,
  103. .min_divider = 1,
  104. .max_divider = 16,
  105. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  106. };
  107. /*
  108. * XXX Cannot add round_rate here yet, as this is still a composite clock,
  109. * not just a DPLL
  110. */
  111. static struct clk dpll_ck = {
  112. .name = "dpll_ck",
  113. .ops = &clkops_null,
  114. .parent = &sys_ck, /* Can be func_32k also */
  115. .dpll_data = &dpll_dd,
  116. .clkdm_name = "wkup_clkdm",
  117. .recalc = &omap2_dpllcore_recalc,
  118. .set_rate = &omap2_reprogram_dpllcore,
  119. };
  120. static struct clk apll96_ck = {
  121. .name = "apll96_ck",
  122. .ops = &clkops_apll96,
  123. .parent = &sys_ck,
  124. .rate = 96000000,
  125. .flags = ENABLE_ON_INIT,
  126. .clkdm_name = "wkup_clkdm",
  127. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  128. .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
  129. };
  130. static struct clk apll54_ck = {
  131. .name = "apll54_ck",
  132. .ops = &clkops_apll54,
  133. .parent = &sys_ck,
  134. .rate = 54000000,
  135. .flags = ENABLE_ON_INIT,
  136. .clkdm_name = "wkup_clkdm",
  137. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  138. .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
  139. };
  140. /*
  141. * PRCM digital base sources
  142. */
  143. /* func_54m_ck */
  144. static const struct clksel_rate func_54m_apll54_rates[] = {
  145. { .div = 1, .val = 0, .flags = RATE_IN_24XX },
  146. { .div = 0 },
  147. };
  148. static const struct clksel_rate func_54m_alt_rates[] = {
  149. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  150. { .div = 0 },
  151. };
  152. static const struct clksel func_54m_clksel[] = {
  153. { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
  154. { .parent = &alt_ck, .rates = func_54m_alt_rates, },
  155. { .parent = NULL },
  156. };
  157. static struct clk func_54m_ck = {
  158. .name = "func_54m_ck",
  159. .ops = &clkops_null,
  160. .parent = &apll54_ck, /* can also be alt_clk */
  161. .clkdm_name = "wkup_clkdm",
  162. .init = &omap2_init_clksel_parent,
  163. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  164. .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
  165. .clksel = func_54m_clksel,
  166. .recalc = &omap2_clksel_recalc,
  167. };
  168. static struct clk core_ck = {
  169. .name = "core_ck",
  170. .ops = &clkops_null,
  171. .parent = &dpll_ck, /* can also be 32k */
  172. .clkdm_name = "wkup_clkdm",
  173. .recalc = &followparent_recalc,
  174. };
  175. /* func_96m_ck */
  176. static const struct clksel_rate func_96m_apll96_rates[] = {
  177. { .div = 1, .val = 0, .flags = RATE_IN_24XX },
  178. { .div = 0 },
  179. };
  180. static const struct clksel_rate func_96m_alt_rates[] = {
  181. { .div = 1, .val = 1, .flags = RATE_IN_243X },
  182. { .div = 0 },
  183. };
  184. static const struct clksel func_96m_clksel[] = {
  185. { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
  186. { .parent = &alt_ck, .rates = func_96m_alt_rates },
  187. { .parent = NULL }
  188. };
  189. static struct clk func_96m_ck = {
  190. .name = "func_96m_ck",
  191. .ops = &clkops_null,
  192. .parent = &apll96_ck,
  193. .clkdm_name = "wkup_clkdm",
  194. .init = &omap2_init_clksel_parent,
  195. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  196. .clksel_mask = OMAP2430_96M_SOURCE_MASK,
  197. .clksel = func_96m_clksel,
  198. .recalc = &omap2_clksel_recalc,
  199. };
  200. /* func_48m_ck */
  201. static const struct clksel_rate func_48m_apll96_rates[] = {
  202. { .div = 2, .val = 0, .flags = RATE_IN_24XX },
  203. { .div = 0 },
  204. };
  205. static const struct clksel_rate func_48m_alt_rates[] = {
  206. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  207. { .div = 0 },
  208. };
  209. static const struct clksel func_48m_clksel[] = {
  210. { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
  211. { .parent = &alt_ck, .rates = func_48m_alt_rates },
  212. { .parent = NULL }
  213. };
  214. static struct clk func_48m_ck = {
  215. .name = "func_48m_ck",
  216. .ops = &clkops_null,
  217. .parent = &apll96_ck, /* 96M or Alt */
  218. .clkdm_name = "wkup_clkdm",
  219. .init = &omap2_init_clksel_parent,
  220. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  221. .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
  222. .clksel = func_48m_clksel,
  223. .recalc = &omap2_clksel_recalc,
  224. .round_rate = &omap2_clksel_round_rate,
  225. .set_rate = &omap2_clksel_set_rate
  226. };
  227. static struct clk func_12m_ck = {
  228. .name = "func_12m_ck",
  229. .ops = &clkops_null,
  230. .parent = &func_48m_ck,
  231. .fixed_div = 4,
  232. .clkdm_name = "wkup_clkdm",
  233. .recalc = &omap_fixed_divisor_recalc,
  234. };
  235. /* Secure timer, only available in secure mode */
  236. static struct clk wdt1_osc_ck = {
  237. .name = "ck_wdt1_osc",
  238. .ops = &clkops_null, /* RMK: missing? */
  239. .parent = &osc_ck,
  240. .recalc = &followparent_recalc,
  241. };
  242. /*
  243. * The common_clkout* clksel_rate structs are common to
  244. * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
  245. * sys_clkout2_* are 2420-only, so the
  246. * clksel_rate flags fields are inaccurate for those clocks. This is
  247. * harmless since access to those clocks are gated by the struct clk
  248. * flags fields, which mark them as 2420-only.
  249. */
  250. static const struct clksel_rate common_clkout_src_core_rates[] = {
  251. { .div = 1, .val = 0, .flags = RATE_IN_24XX },
  252. { .div = 0 }
  253. };
  254. static const struct clksel_rate common_clkout_src_sys_rates[] = {
  255. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  256. { .div = 0 }
  257. };
  258. static const struct clksel_rate common_clkout_src_96m_rates[] = {
  259. { .div = 1, .val = 2, .flags = RATE_IN_24XX },
  260. { .div = 0 }
  261. };
  262. static const struct clksel_rate common_clkout_src_54m_rates[] = {
  263. { .div = 1, .val = 3, .flags = RATE_IN_24XX },
  264. { .div = 0 }
  265. };
  266. static const struct clksel common_clkout_src_clksel[] = {
  267. { .parent = &core_ck, .rates = common_clkout_src_core_rates },
  268. { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
  269. { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
  270. { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
  271. { .parent = NULL }
  272. };
  273. static struct clk sys_clkout_src = {
  274. .name = "sys_clkout_src",
  275. .ops = &clkops_omap2_dflt,
  276. .parent = &func_54m_ck,
  277. .clkdm_name = "wkup_clkdm",
  278. .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
  279. .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
  280. .init = &omap2_init_clksel_parent,
  281. .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
  282. .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
  283. .clksel = common_clkout_src_clksel,
  284. .recalc = &omap2_clksel_recalc,
  285. .round_rate = &omap2_clksel_round_rate,
  286. .set_rate = &omap2_clksel_set_rate
  287. };
  288. static const struct clksel_rate common_clkout_rates[] = {
  289. { .div = 1, .val = 0, .flags = RATE_IN_24XX },
  290. { .div = 2, .val = 1, .flags = RATE_IN_24XX },
  291. { .div = 4, .val = 2, .flags = RATE_IN_24XX },
  292. { .div = 8, .val = 3, .flags = RATE_IN_24XX },
  293. { .div = 16, .val = 4, .flags = RATE_IN_24XX },
  294. { .div = 0 },
  295. };
  296. static const struct clksel sys_clkout_clksel[] = {
  297. { .parent = &sys_clkout_src, .rates = common_clkout_rates },
  298. { .parent = NULL }
  299. };
  300. static struct clk sys_clkout = {
  301. .name = "sys_clkout",
  302. .ops = &clkops_null,
  303. .parent = &sys_clkout_src,
  304. .clkdm_name = "wkup_clkdm",
  305. .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
  306. .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
  307. .clksel = sys_clkout_clksel,
  308. .recalc = &omap2_clksel_recalc,
  309. .round_rate = &omap2_clksel_round_rate,
  310. .set_rate = &omap2_clksel_set_rate
  311. };
  312. static struct clk emul_ck = {
  313. .name = "emul_ck",
  314. .ops = &clkops_omap2_dflt,
  315. .parent = &func_54m_ck,
  316. .clkdm_name = "wkup_clkdm",
  317. .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
  318. .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
  319. .recalc = &followparent_recalc,
  320. };
  321. /*
  322. * MPU clock domain
  323. * Clocks:
  324. * MPU_FCLK, MPU_ICLK
  325. * INT_M_FCLK, INT_M_I_CLK
  326. *
  327. * - Individual clocks are hardware managed.
  328. * - Base divider comes from: CM_CLKSEL_MPU
  329. *
  330. */
  331. static const struct clksel_rate mpu_core_rates[] = {
  332. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  333. { .div = 2, .val = 2, .flags = RATE_IN_24XX },
  334. { .div = 0 },
  335. };
  336. static const struct clksel mpu_clksel[] = {
  337. { .parent = &core_ck, .rates = mpu_core_rates },
  338. { .parent = NULL }
  339. };
  340. static struct clk mpu_ck = { /* Control cpu */
  341. .name = "mpu_ck",
  342. .ops = &clkops_null,
  343. .parent = &core_ck,
  344. .clkdm_name = "mpu_clkdm",
  345. .init = &omap2_init_clksel_parent,
  346. .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
  347. .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
  348. .clksel = mpu_clksel,
  349. .recalc = &omap2_clksel_recalc,
  350. };
  351. /*
  352. * DSP (2430-IVA2.1) clock domain
  353. * Clocks:
  354. * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
  355. *
  356. * Won't be too specific here. The core clock comes into this block
  357. * it is divided then tee'ed. One branch goes directly to xyz enable
  358. * controls. The other branch gets further divided by 2 then possibly
  359. * routed into a synchronizer and out of clocks abc.
  360. */
  361. static const struct clksel_rate dsp_fck_core_rates[] = {
  362. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  363. { .div = 2, .val = 2, .flags = RATE_IN_24XX },
  364. { .div = 3, .val = 3, .flags = RATE_IN_24XX },
  365. { .div = 4, .val = 4, .flags = RATE_IN_24XX },
  366. { .div = 0 },
  367. };
  368. static const struct clksel dsp_fck_clksel[] = {
  369. { .parent = &core_ck, .rates = dsp_fck_core_rates },
  370. { .parent = NULL }
  371. };
  372. static struct clk dsp_fck = {
  373. .name = "dsp_fck",
  374. .ops = &clkops_omap2_dflt_wait,
  375. .parent = &core_ck,
  376. .clkdm_name = "dsp_clkdm",
  377. .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
  378. .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
  379. .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
  380. .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
  381. .clksel = dsp_fck_clksel,
  382. .recalc = &omap2_clksel_recalc,
  383. };
  384. /* DSP interface clock */
  385. static const struct clksel_rate dsp_irate_ick_rates[] = {
  386. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  387. { .div = 2, .val = 2, .flags = RATE_IN_24XX },
  388. { .div = 3, .val = 3, .flags = RATE_IN_243X },
  389. { .div = 0 },
  390. };
  391. static const struct clksel dsp_irate_ick_clksel[] = {
  392. { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
  393. { .parent = NULL }
  394. };
  395. /* This clock does not exist as such in the TRM. */
  396. static struct clk dsp_irate_ick = {
  397. .name = "dsp_irate_ick",
  398. .ops = &clkops_null,
  399. .parent = &dsp_fck,
  400. .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
  401. .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
  402. .clksel = dsp_irate_ick_clksel,
  403. .recalc = &omap2_clksel_recalc,
  404. };
  405. /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
  406. static struct clk iva2_1_ick = {
  407. .name = "iva2_1_ick",
  408. .ops = &clkops_omap2_dflt_wait,
  409. .parent = &dsp_irate_ick,
  410. .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
  411. .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
  412. };
  413. /*
  414. * L3 clock domain
  415. * L3 clocks are used for both interface and functional clocks to
  416. * multiple entities. Some of these clocks are completely managed
  417. * by hardware, and some others allow software control. Hardware
  418. * managed ones general are based on directly CLK_REQ signals and
  419. * various auto idle settings. The functional spec sets many of these
  420. * as 'tie-high' for their enables.
  421. *
  422. * I-CLOCKS:
  423. * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
  424. * CAM, HS-USB.
  425. * F-CLOCK
  426. * SSI.
  427. *
  428. * GPMC memories and SDRC have timing and clock sensitive registers which
  429. * may very well need notification when the clock changes. Currently for low
  430. * operating points, these are taken care of in sleep.S.
  431. */
  432. static const struct clksel_rate core_l3_core_rates[] = {
  433. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  434. { .div = 4, .val = 4, .flags = RATE_IN_24XX },
  435. { .div = 6, .val = 6, .flags = RATE_IN_24XX },
  436. { .div = 0 }
  437. };
  438. static const struct clksel core_l3_clksel[] = {
  439. { .parent = &core_ck, .rates = core_l3_core_rates },
  440. { .parent = NULL }
  441. };
  442. static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
  443. .name = "core_l3_ck",
  444. .ops = &clkops_null,
  445. .parent = &core_ck,
  446. .clkdm_name = "core_l3_clkdm",
  447. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
  448. .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
  449. .clksel = core_l3_clksel,
  450. .recalc = &omap2_clksel_recalc,
  451. };
  452. /* usb_l4_ick */
  453. static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
  454. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  455. { .div = 2, .val = 2, .flags = RATE_IN_24XX },
  456. { .div = 4, .val = 4, .flags = RATE_IN_24XX },
  457. { .div = 0 }
  458. };
  459. static const struct clksel usb_l4_ick_clksel[] = {
  460. { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
  461. { .parent = NULL },
  462. };
  463. /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
  464. static struct clk usb_l4_ick = { /* FS-USB interface clock */
  465. .name = "usb_l4_ick",
  466. .ops = &clkops_omap2_dflt_wait,
  467. .parent = &core_l3_ck,
  468. .clkdm_name = "core_l4_clkdm",
  469. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  470. .enable_bit = OMAP24XX_EN_USB_SHIFT,
  471. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
  472. .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
  473. .clksel = usb_l4_ick_clksel,
  474. .recalc = &omap2_clksel_recalc,
  475. };
  476. /*
  477. * L4 clock management domain
  478. *
  479. * This domain contains lots of interface clocks from the L4 interface, some
  480. * functional clocks. Fixed APLL functional source clocks are managed in
  481. * this domain.
  482. */
  483. static const struct clksel_rate l4_core_l3_rates[] = {
  484. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  485. { .div = 2, .val = 2, .flags = RATE_IN_24XX },
  486. { .div = 0 }
  487. };
  488. static const struct clksel l4_clksel[] = {
  489. { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
  490. { .parent = NULL }
  491. };
  492. static struct clk l4_ck = { /* used both as an ick and fck */
  493. .name = "l4_ck",
  494. .ops = &clkops_null,
  495. .parent = &core_l3_ck,
  496. .clkdm_name = "core_l4_clkdm",
  497. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
  498. .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
  499. .clksel = l4_clksel,
  500. .recalc = &omap2_clksel_recalc,
  501. };
  502. /*
  503. * SSI is in L3 management domain, its direct parent is core not l3,
  504. * many core power domain entities are grouped into the L3 clock
  505. * domain.
  506. * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
  507. *
  508. * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
  509. */
  510. static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
  511. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  512. { .div = 2, .val = 2, .flags = RATE_IN_24XX },
  513. { .div = 3, .val = 3, .flags = RATE_IN_24XX },
  514. { .div = 4, .val = 4, .flags = RATE_IN_24XX },
  515. { .div = 5, .val = 5, .flags = RATE_IN_243X },
  516. { .div = 0 }
  517. };
  518. static const struct clksel ssi_ssr_sst_fck_clksel[] = {
  519. { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
  520. { .parent = NULL }
  521. };
  522. static struct clk ssi_ssr_sst_fck = {
  523. .name = "ssi_fck",
  524. .ops = &clkops_omap2_dflt_wait,
  525. .parent = &core_ck,
  526. .clkdm_name = "core_l3_clkdm",
  527. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  528. .enable_bit = OMAP24XX_EN_SSI_SHIFT,
  529. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
  530. .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
  531. .clksel = ssi_ssr_sst_fck_clksel,
  532. .recalc = &omap2_clksel_recalc,
  533. };
  534. /*
  535. * Presumably this is the same as SSI_ICLK.
  536. * TRM contradicts itself on what clockdomain SSI_ICLK is in
  537. */
  538. static struct clk ssi_l4_ick = {
  539. .name = "ssi_l4_ick",
  540. .ops = &clkops_omap2_dflt_wait,
  541. .parent = &l4_ck,
  542. .clkdm_name = "core_l4_clkdm",
  543. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  544. .enable_bit = OMAP24XX_EN_SSI_SHIFT,
  545. .recalc = &followparent_recalc,
  546. };
  547. /*
  548. * GFX clock domain
  549. * Clocks:
  550. * GFX_FCLK, GFX_ICLK
  551. * GFX_CG1(2d), GFX_CG2(3d)
  552. *
  553. * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
  554. * The 2d and 3d clocks run at a hardware determined
  555. * divided value of fclk.
  556. *
  557. */
  558. /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
  559. static const struct clksel gfx_fck_clksel[] = {
  560. { .parent = &core_l3_ck, .rates = gfx_l3_rates },
  561. { .parent = NULL },
  562. };
  563. static struct clk gfx_3d_fck = {
  564. .name = "gfx_3d_fck",
  565. .ops = &clkops_omap2_dflt_wait,
  566. .parent = &core_l3_ck,
  567. .clkdm_name = "gfx_clkdm",
  568. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
  569. .enable_bit = OMAP24XX_EN_3D_SHIFT,
  570. .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
  571. .clksel_mask = OMAP_CLKSEL_GFX_MASK,
  572. .clksel = gfx_fck_clksel,
  573. .recalc = &omap2_clksel_recalc,
  574. .round_rate = &omap2_clksel_round_rate,
  575. .set_rate = &omap2_clksel_set_rate
  576. };
  577. static struct clk gfx_2d_fck = {
  578. .name = "gfx_2d_fck",
  579. .ops = &clkops_omap2_dflt_wait,
  580. .parent = &core_l3_ck,
  581. .clkdm_name = "gfx_clkdm",
  582. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
  583. .enable_bit = OMAP24XX_EN_2D_SHIFT,
  584. .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
  585. .clksel_mask = OMAP_CLKSEL_GFX_MASK,
  586. .clksel = gfx_fck_clksel,
  587. .recalc = &omap2_clksel_recalc,
  588. };
  589. static struct clk gfx_ick = {
  590. .name = "gfx_ick", /* From l3 */
  591. .ops = &clkops_omap2_dflt_wait,
  592. .parent = &core_l3_ck,
  593. .clkdm_name = "gfx_clkdm",
  594. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
  595. .enable_bit = OMAP_EN_GFX_SHIFT,
  596. .recalc = &followparent_recalc,
  597. };
  598. /*
  599. * Modem clock domain (2430)
  600. * CLOCKS:
  601. * MDM_OSC_CLK
  602. * MDM_ICLK
  603. * These clocks are usable in chassis mode only.
  604. */
  605. static const struct clksel_rate mdm_ick_core_rates[] = {
  606. { .div = 1, .val = 1, .flags = RATE_IN_243X },
  607. { .div = 4, .val = 4, .flags = RATE_IN_243X },
  608. { .div = 6, .val = 6, .flags = RATE_IN_243X },
  609. { .div = 9, .val = 9, .flags = RATE_IN_243X },
  610. { .div = 0 }
  611. };
  612. static const struct clksel mdm_ick_clksel[] = {
  613. { .parent = &core_ck, .rates = mdm_ick_core_rates },
  614. { .parent = NULL }
  615. };
  616. static struct clk mdm_ick = { /* used both as a ick and fck */
  617. .name = "mdm_ick",
  618. .ops = &clkops_omap2_dflt_wait,
  619. .parent = &core_ck,
  620. .clkdm_name = "mdm_clkdm",
  621. .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
  622. .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
  623. .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
  624. .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
  625. .clksel = mdm_ick_clksel,
  626. .recalc = &omap2_clksel_recalc,
  627. };
  628. static struct clk mdm_osc_ck = {
  629. .name = "mdm_osc_ck",
  630. .ops = &clkops_omap2_dflt_wait,
  631. .parent = &osc_ck,
  632. .clkdm_name = "mdm_clkdm",
  633. .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
  634. .enable_bit = OMAP2430_EN_OSC_SHIFT,
  635. .recalc = &followparent_recalc,
  636. };
  637. /*
  638. * DSS clock domain
  639. * CLOCKs:
  640. * DSS_L4_ICLK, DSS_L3_ICLK,
  641. * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
  642. *
  643. * DSS is both initiator and target.
  644. */
  645. /* XXX Add RATE_NOT_VALIDATED */
  646. static const struct clksel_rate dss1_fck_sys_rates[] = {
  647. { .div = 1, .val = 0, .flags = RATE_IN_24XX },
  648. { .div = 0 }
  649. };
  650. static const struct clksel_rate dss1_fck_core_rates[] = {
  651. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  652. { .div = 2, .val = 2, .flags = RATE_IN_24XX },
  653. { .div = 3, .val = 3, .flags = RATE_IN_24XX },
  654. { .div = 4, .val = 4, .flags = RATE_IN_24XX },
  655. { .div = 5, .val = 5, .flags = RATE_IN_24XX },
  656. { .div = 6, .val = 6, .flags = RATE_IN_24XX },
  657. { .div = 8, .val = 8, .flags = RATE_IN_24XX },
  658. { .div = 9, .val = 9, .flags = RATE_IN_24XX },
  659. { .div = 12, .val = 12, .flags = RATE_IN_24XX },
  660. { .div = 16, .val = 16, .flags = RATE_IN_24XX },
  661. { .div = 0 }
  662. };
  663. static const struct clksel dss1_fck_clksel[] = {
  664. { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
  665. { .parent = &core_ck, .rates = dss1_fck_core_rates },
  666. { .parent = NULL },
  667. };
  668. static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
  669. .name = "dss_ick",
  670. .ops = &clkops_omap2_dflt,
  671. .parent = &l4_ck, /* really both l3 and l4 */
  672. .clkdm_name = "dss_clkdm",
  673. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  674. .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
  675. .recalc = &followparent_recalc,
  676. };
  677. static struct clk dss1_fck = {
  678. .name = "dss1_fck",
  679. .ops = &clkops_omap2_dflt,
  680. .parent = &core_ck, /* Core or sys */
  681. .clkdm_name = "dss_clkdm",
  682. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  683. .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
  684. .init = &omap2_init_clksel_parent,
  685. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
  686. .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
  687. .clksel = dss1_fck_clksel,
  688. .recalc = &omap2_clksel_recalc,
  689. };
  690. static const struct clksel_rate dss2_fck_sys_rates[] = {
  691. { .div = 1, .val = 0, .flags = RATE_IN_24XX },
  692. { .div = 0 }
  693. };
  694. static const struct clksel_rate dss2_fck_48m_rates[] = {
  695. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  696. { .div = 0 }
  697. };
  698. static const struct clksel dss2_fck_clksel[] = {
  699. { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
  700. { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
  701. { .parent = NULL }
  702. };
  703. static struct clk dss2_fck = { /* Alt clk used in power management */
  704. .name = "dss2_fck",
  705. .ops = &clkops_omap2_dflt,
  706. .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
  707. .clkdm_name = "dss_clkdm",
  708. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  709. .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
  710. .init = &omap2_init_clksel_parent,
  711. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
  712. .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
  713. .clksel = dss2_fck_clksel,
  714. .recalc = &followparent_recalc,
  715. };
  716. static struct clk dss_54m_fck = { /* Alt clk used in power management */
  717. .name = "dss_54m_fck", /* 54m tv clk */
  718. .ops = &clkops_omap2_dflt_wait,
  719. .parent = &func_54m_ck,
  720. .clkdm_name = "dss_clkdm",
  721. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  722. .enable_bit = OMAP24XX_EN_TV_SHIFT,
  723. .recalc = &followparent_recalc,
  724. };
  725. /*
  726. * CORE power domain ICLK & FCLK defines.
  727. * Many of the these can have more than one possible parent. Entries
  728. * here will likely have an L4 interface parent, and may have multiple
  729. * functional clock parents.
  730. */
  731. static const struct clksel_rate gpt_alt_rates[] = {
  732. { .div = 1, .val = 2, .flags = RATE_IN_24XX },
  733. { .div = 0 }
  734. };
  735. static const struct clksel omap24xx_gpt_clksel[] = {
  736. { .parent = &func_32k_ck, .rates = gpt_32k_rates },
  737. { .parent = &sys_ck, .rates = gpt_sys_rates },
  738. { .parent = &alt_ck, .rates = gpt_alt_rates },
  739. { .parent = NULL },
  740. };
  741. static struct clk gpt1_ick = {
  742. .name = "gpt1_ick",
  743. .ops = &clkops_omap2_dflt_wait,
  744. .parent = &l4_ck,
  745. .clkdm_name = "core_l4_clkdm",
  746. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  747. .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
  748. .recalc = &followparent_recalc,
  749. };
  750. static struct clk gpt1_fck = {
  751. .name = "gpt1_fck",
  752. .ops = &clkops_omap2_dflt_wait,
  753. .parent = &func_32k_ck,
  754. .clkdm_name = "core_l4_clkdm",
  755. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  756. .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
  757. .init = &omap2_init_clksel_parent,
  758. .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
  759. .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
  760. .clksel = omap24xx_gpt_clksel,
  761. .recalc = &omap2_clksel_recalc,
  762. .round_rate = &omap2_clksel_round_rate,
  763. .set_rate = &omap2_clksel_set_rate
  764. };
  765. static struct clk gpt2_ick = {
  766. .name = "gpt2_ick",
  767. .ops = &clkops_omap2_dflt_wait,
  768. .parent = &l4_ck,
  769. .clkdm_name = "core_l4_clkdm",
  770. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  771. .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
  772. .recalc = &followparent_recalc,
  773. };
  774. static struct clk gpt2_fck = {
  775. .name = "gpt2_fck",
  776. .ops = &clkops_omap2_dflt_wait,
  777. .parent = &func_32k_ck,
  778. .clkdm_name = "core_l4_clkdm",
  779. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  780. .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
  781. .init = &omap2_init_clksel_parent,
  782. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  783. .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
  784. .clksel = omap24xx_gpt_clksel,
  785. .recalc = &omap2_clksel_recalc,
  786. };
  787. static struct clk gpt3_ick = {
  788. .name = "gpt3_ick",
  789. .ops = &clkops_omap2_dflt_wait,
  790. .parent = &l4_ck,
  791. .clkdm_name = "core_l4_clkdm",
  792. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  793. .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
  794. .recalc = &followparent_recalc,
  795. };
  796. static struct clk gpt3_fck = {
  797. .name = "gpt3_fck",
  798. .ops = &clkops_omap2_dflt_wait,
  799. .parent = &func_32k_ck,
  800. .clkdm_name = "core_l4_clkdm",
  801. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  802. .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
  803. .init = &omap2_init_clksel_parent,
  804. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  805. .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
  806. .clksel = omap24xx_gpt_clksel,
  807. .recalc = &omap2_clksel_recalc,
  808. };
  809. static struct clk gpt4_ick = {
  810. .name = "gpt4_ick",
  811. .ops = &clkops_omap2_dflt_wait,
  812. .parent = &l4_ck,
  813. .clkdm_name = "core_l4_clkdm",
  814. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  815. .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
  816. .recalc = &followparent_recalc,
  817. };
  818. static struct clk gpt4_fck = {
  819. .name = "gpt4_fck",
  820. .ops = &clkops_omap2_dflt_wait,
  821. .parent = &func_32k_ck,
  822. .clkdm_name = "core_l4_clkdm",
  823. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  824. .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
  825. .init = &omap2_init_clksel_parent,
  826. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  827. .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
  828. .clksel = omap24xx_gpt_clksel,
  829. .recalc = &omap2_clksel_recalc,
  830. };
  831. static struct clk gpt5_ick = {
  832. .name = "gpt5_ick",
  833. .ops = &clkops_omap2_dflt_wait,
  834. .parent = &l4_ck,
  835. .clkdm_name = "core_l4_clkdm",
  836. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  837. .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
  838. .recalc = &followparent_recalc,
  839. };
  840. static struct clk gpt5_fck = {
  841. .name = "gpt5_fck",
  842. .ops = &clkops_omap2_dflt_wait,
  843. .parent = &func_32k_ck,
  844. .clkdm_name = "core_l4_clkdm",
  845. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  846. .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
  847. .init = &omap2_init_clksel_parent,
  848. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  849. .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
  850. .clksel = omap24xx_gpt_clksel,
  851. .recalc = &omap2_clksel_recalc,
  852. };
  853. static struct clk gpt6_ick = {
  854. .name = "gpt6_ick",
  855. .ops = &clkops_omap2_dflt_wait,
  856. .parent = &l4_ck,
  857. .clkdm_name = "core_l4_clkdm",
  858. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  859. .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
  860. .recalc = &followparent_recalc,
  861. };
  862. static struct clk gpt6_fck = {
  863. .name = "gpt6_fck",
  864. .ops = &clkops_omap2_dflt_wait,
  865. .parent = &func_32k_ck,
  866. .clkdm_name = "core_l4_clkdm",
  867. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  868. .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
  869. .init = &omap2_init_clksel_parent,
  870. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  871. .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
  872. .clksel = omap24xx_gpt_clksel,
  873. .recalc = &omap2_clksel_recalc,
  874. };
  875. static struct clk gpt7_ick = {
  876. .name = "gpt7_ick",
  877. .ops = &clkops_omap2_dflt_wait,
  878. .parent = &l4_ck,
  879. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  880. .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
  881. .recalc = &followparent_recalc,
  882. };
  883. static struct clk gpt7_fck = {
  884. .name = "gpt7_fck",
  885. .ops = &clkops_omap2_dflt_wait,
  886. .parent = &func_32k_ck,
  887. .clkdm_name = "core_l4_clkdm",
  888. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  889. .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
  890. .init = &omap2_init_clksel_parent,
  891. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  892. .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
  893. .clksel = omap24xx_gpt_clksel,
  894. .recalc = &omap2_clksel_recalc,
  895. };
  896. static struct clk gpt8_ick = {
  897. .name = "gpt8_ick",
  898. .ops = &clkops_omap2_dflt_wait,
  899. .parent = &l4_ck,
  900. .clkdm_name = "core_l4_clkdm",
  901. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  902. .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
  903. .recalc = &followparent_recalc,
  904. };
  905. static struct clk gpt8_fck = {
  906. .name = "gpt8_fck",
  907. .ops = &clkops_omap2_dflt_wait,
  908. .parent = &func_32k_ck,
  909. .clkdm_name = "core_l4_clkdm",
  910. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  911. .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
  912. .init = &omap2_init_clksel_parent,
  913. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  914. .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
  915. .clksel = omap24xx_gpt_clksel,
  916. .recalc = &omap2_clksel_recalc,
  917. };
  918. static struct clk gpt9_ick = {
  919. .name = "gpt9_ick",
  920. .ops = &clkops_omap2_dflt_wait,
  921. .parent = &l4_ck,
  922. .clkdm_name = "core_l4_clkdm",
  923. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  924. .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
  925. .recalc = &followparent_recalc,
  926. };
  927. static struct clk gpt9_fck = {
  928. .name = "gpt9_fck",
  929. .ops = &clkops_omap2_dflt_wait,
  930. .parent = &func_32k_ck,
  931. .clkdm_name = "core_l4_clkdm",
  932. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  933. .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
  934. .init = &omap2_init_clksel_parent,
  935. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  936. .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
  937. .clksel = omap24xx_gpt_clksel,
  938. .recalc = &omap2_clksel_recalc,
  939. };
  940. static struct clk gpt10_ick = {
  941. .name = "gpt10_ick",
  942. .ops = &clkops_omap2_dflt_wait,
  943. .parent = &l4_ck,
  944. .clkdm_name = "core_l4_clkdm",
  945. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  946. .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
  947. .recalc = &followparent_recalc,
  948. };
  949. static struct clk gpt10_fck = {
  950. .name = "gpt10_fck",
  951. .ops = &clkops_omap2_dflt_wait,
  952. .parent = &func_32k_ck,
  953. .clkdm_name = "core_l4_clkdm",
  954. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  955. .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
  956. .init = &omap2_init_clksel_parent,
  957. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  958. .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
  959. .clksel = omap24xx_gpt_clksel,
  960. .recalc = &omap2_clksel_recalc,
  961. };
  962. static struct clk gpt11_ick = {
  963. .name = "gpt11_ick",
  964. .ops = &clkops_omap2_dflt_wait,
  965. .parent = &l4_ck,
  966. .clkdm_name = "core_l4_clkdm",
  967. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  968. .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
  969. .recalc = &followparent_recalc,
  970. };
  971. static struct clk gpt11_fck = {
  972. .name = "gpt11_fck",
  973. .ops = &clkops_omap2_dflt_wait,
  974. .parent = &func_32k_ck,
  975. .clkdm_name = "core_l4_clkdm",
  976. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  977. .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
  978. .init = &omap2_init_clksel_parent,
  979. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  980. .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
  981. .clksel = omap24xx_gpt_clksel,
  982. .recalc = &omap2_clksel_recalc,
  983. };
  984. static struct clk gpt12_ick = {
  985. .name = "gpt12_ick",
  986. .ops = &clkops_omap2_dflt_wait,
  987. .parent = &l4_ck,
  988. .clkdm_name = "core_l4_clkdm",
  989. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  990. .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
  991. .recalc = &followparent_recalc,
  992. };
  993. static struct clk gpt12_fck = {
  994. .name = "gpt12_fck",
  995. .ops = &clkops_omap2_dflt_wait,
  996. .parent = &secure_32k_ck,
  997. .clkdm_name = "core_l4_clkdm",
  998. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  999. .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
  1000. .init = &omap2_init_clksel_parent,
  1001. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
  1002. .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
  1003. .clksel = omap24xx_gpt_clksel,
  1004. .recalc = &omap2_clksel_recalc,
  1005. };
  1006. static struct clk mcbsp1_ick = {
  1007. .name = "mcbsp1_ick",
  1008. .ops = &clkops_omap2_dflt_wait,
  1009. .parent = &l4_ck,
  1010. .clkdm_name = "core_l4_clkdm",
  1011. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1012. .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
  1013. .recalc = &followparent_recalc,
  1014. };
  1015. static const struct clksel_rate common_mcbsp_96m_rates[] = {
  1016. { .div = 1, .val = 0, .flags = RATE_IN_24XX },
  1017. { .div = 0 }
  1018. };
  1019. static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
  1020. { .div = 1, .val = 1, .flags = RATE_IN_24XX },
  1021. { .div = 0 }
  1022. };
  1023. static const struct clksel mcbsp_fck_clksel[] = {
  1024. { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
  1025. { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
  1026. { .parent = NULL }
  1027. };
  1028. static struct clk mcbsp1_fck = {
  1029. .name = "mcbsp1_fck",
  1030. .ops = &clkops_omap2_dflt_wait,
  1031. .parent = &func_96m_ck,
  1032. .init = &omap2_init_clksel_parent,
  1033. .clkdm_name = "core_l4_clkdm",
  1034. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1035. .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
  1036. .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
  1037. .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
  1038. .clksel = mcbsp_fck_clksel,
  1039. .recalc = &omap2_clksel_recalc,
  1040. };
  1041. static struct clk mcbsp2_ick = {
  1042. .name = "mcbsp2_ick",
  1043. .ops = &clkops_omap2_dflt_wait,
  1044. .parent = &l4_ck,
  1045. .clkdm_name = "core_l4_clkdm",
  1046. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1047. .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
  1048. .recalc = &followparent_recalc,
  1049. };
  1050. static struct clk mcbsp2_fck = {
  1051. .name = "mcbsp2_fck",
  1052. .ops = &clkops_omap2_dflt_wait,
  1053. .parent = &func_96m_ck,
  1054. .init = &omap2_init_clksel_parent,
  1055. .clkdm_name = "core_l4_clkdm",
  1056. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1057. .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
  1058. .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
  1059. .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
  1060. .clksel = mcbsp_fck_clksel,
  1061. .recalc = &omap2_clksel_recalc,
  1062. };
  1063. static struct clk mcbsp3_ick = {
  1064. .name = "mcbsp3_ick",
  1065. .ops = &clkops_omap2_dflt_wait,
  1066. .parent = &l4_ck,
  1067. .clkdm_name = "core_l4_clkdm",
  1068. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1069. .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
  1070. .recalc = &followparent_recalc,
  1071. };
  1072. static struct clk mcbsp3_fck = {
  1073. .name = "mcbsp3_fck",
  1074. .ops = &clkops_omap2_dflt_wait,
  1075. .parent = &func_96m_ck,
  1076. .init = &omap2_init_clksel_parent,
  1077. .clkdm_name = "core_l4_clkdm",
  1078. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1079. .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
  1080. .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
  1081. .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
  1082. .clksel = mcbsp_fck_clksel,
  1083. .recalc = &omap2_clksel_recalc,
  1084. };
  1085. static struct clk mcbsp4_ick = {
  1086. .name = "mcbsp4_ick",
  1087. .ops = &clkops_omap2_dflt_wait,
  1088. .parent = &l4_ck,
  1089. .clkdm_name = "core_l4_clkdm",
  1090. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1091. .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
  1092. .recalc = &followparent_recalc,
  1093. };
  1094. static struct clk mcbsp4_fck = {
  1095. .name = "mcbsp4_fck",
  1096. .ops = &clkops_omap2_dflt_wait,
  1097. .parent = &func_96m_ck,
  1098. .init = &omap2_init_clksel_parent,
  1099. .clkdm_name = "core_l4_clkdm",
  1100. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1101. .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
  1102. .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
  1103. .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
  1104. .clksel = mcbsp_fck_clksel,
  1105. .recalc = &omap2_clksel_recalc,
  1106. };
  1107. static struct clk mcbsp5_ick = {
  1108. .name = "mcbsp5_ick",
  1109. .ops = &clkops_omap2_dflt_wait,
  1110. .parent = &l4_ck,
  1111. .clkdm_name = "core_l4_clkdm",
  1112. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1113. .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
  1114. .recalc = &followparent_recalc,
  1115. };
  1116. static struct clk mcbsp5_fck = {
  1117. .name = "mcbsp5_fck",
  1118. .ops = &clkops_omap2_dflt_wait,
  1119. .parent = &func_96m_ck,
  1120. .init = &omap2_init_clksel_parent,
  1121. .clkdm_name = "core_l4_clkdm",
  1122. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1123. .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
  1124. .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
  1125. .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
  1126. .clksel = mcbsp_fck_clksel,
  1127. .recalc = &omap2_clksel_recalc,
  1128. };
  1129. static struct clk mcspi1_ick = {
  1130. .name = "mcspi1_ick",
  1131. .ops = &clkops_omap2_dflt_wait,
  1132. .parent = &l4_ck,
  1133. .clkdm_name = "core_l4_clkdm",
  1134. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1135. .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
  1136. .recalc = &followparent_recalc,
  1137. };
  1138. static struct clk mcspi1_fck = {
  1139. .name = "mcspi1_fck",
  1140. .ops = &clkops_omap2_dflt_wait,
  1141. .parent = &func_48m_ck,
  1142. .clkdm_name = "core_l4_clkdm",
  1143. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1144. .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
  1145. .recalc = &followparent_recalc,
  1146. };
  1147. static struct clk mcspi2_ick = {
  1148. .name = "mcspi2_ick",
  1149. .ops = &clkops_omap2_dflt_wait,
  1150. .parent = &l4_ck,
  1151. .clkdm_name = "core_l4_clkdm",
  1152. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1153. .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
  1154. .recalc = &followparent_recalc,
  1155. };
  1156. static struct clk mcspi2_fck = {
  1157. .name = "mcspi2_fck",
  1158. .ops = &clkops_omap2_dflt_wait,
  1159. .parent = &func_48m_ck,
  1160. .clkdm_name = "core_l4_clkdm",
  1161. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1162. .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
  1163. .recalc = &followparent_recalc,
  1164. };
  1165. static struct clk mcspi3_ick = {
  1166. .name = "mcspi3_ick",
  1167. .ops = &clkops_omap2_dflt_wait,
  1168. .parent = &l4_ck,
  1169. .clkdm_name = "core_l4_clkdm",
  1170. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1171. .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
  1172. .recalc = &followparent_recalc,
  1173. };
  1174. static struct clk mcspi3_fck = {
  1175. .name = "mcspi3_fck",
  1176. .ops = &clkops_omap2_dflt_wait,
  1177. .parent = &func_48m_ck,
  1178. .clkdm_name = "core_l4_clkdm",
  1179. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1180. .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
  1181. .recalc = &followparent_recalc,
  1182. };
  1183. static struct clk uart1_ick = {
  1184. .name = "uart1_ick",
  1185. .ops = &clkops_omap2_dflt_wait,
  1186. .parent = &l4_ck,
  1187. .clkdm_name = "core_l4_clkdm",
  1188. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1189. .enable_bit = OMAP24XX_EN_UART1_SHIFT,
  1190. .recalc = &followparent_recalc,
  1191. };
  1192. static struct clk uart1_fck = {
  1193. .name = "uart1_fck",
  1194. .ops = &clkops_omap2_dflt_wait,
  1195. .parent = &func_48m_ck,
  1196. .clkdm_name = "core_l4_clkdm",
  1197. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1198. .enable_bit = OMAP24XX_EN_UART1_SHIFT,
  1199. .recalc = &followparent_recalc,
  1200. };
  1201. static struct clk uart2_ick = {
  1202. .name = "uart2_ick",
  1203. .ops = &clkops_omap2_dflt_wait,
  1204. .parent = &l4_ck,
  1205. .clkdm_name = "core_l4_clkdm",
  1206. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1207. .enable_bit = OMAP24XX_EN_UART2_SHIFT,
  1208. .recalc = &followparent_recalc,
  1209. };
  1210. static struct clk uart2_fck = {
  1211. .name = "uart2_fck",
  1212. .ops = &clkops_omap2_dflt_wait,
  1213. .parent = &func_48m_ck,
  1214. .clkdm_name = "core_l4_clkdm",
  1215. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1216. .enable_bit = OMAP24XX_EN_UART2_SHIFT,
  1217. .recalc = &followparent_recalc,
  1218. };
  1219. static struct clk uart3_ick = {
  1220. .name = "uart3_ick",
  1221. .ops = &clkops_omap2_dflt_wait,
  1222. .parent = &l4_ck,
  1223. .clkdm_name = "core_l4_clkdm",
  1224. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1225. .enable_bit = OMAP24XX_EN_UART3_SHIFT,
  1226. .recalc = &followparent_recalc,
  1227. };
  1228. static struct clk uart3_fck = {
  1229. .name = "uart3_fck",
  1230. .ops = &clkops_omap2_dflt_wait,
  1231. .parent = &func_48m_ck,
  1232. .clkdm_name = "core_l4_clkdm",
  1233. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1234. .enable_bit = OMAP24XX_EN_UART3_SHIFT,
  1235. .recalc = &followparent_recalc,
  1236. };
  1237. static struct clk gpios_ick = {
  1238. .name = "gpios_ick",
  1239. .ops = &clkops_omap2_dflt_wait,
  1240. .parent = &l4_ck,
  1241. .clkdm_name = "core_l4_clkdm",
  1242. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  1243. .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
  1244. .recalc = &followparent_recalc,
  1245. };
  1246. static struct clk gpios_fck = {
  1247. .name = "gpios_fck",
  1248. .ops = &clkops_omap2_dflt_wait,
  1249. .parent = &func_32k_ck,
  1250. .clkdm_name = "wkup_clkdm",
  1251. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  1252. .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
  1253. .recalc = &followparent_recalc,
  1254. };
  1255. static struct clk mpu_wdt_ick = {
  1256. .name = "mpu_wdt_ick",
  1257. .ops = &clkops_omap2_dflt_wait,
  1258. .parent = &l4_ck,
  1259. .clkdm_name = "core_l4_clkdm",
  1260. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  1261. .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
  1262. .recalc = &followparent_recalc,
  1263. };
  1264. static struct clk mpu_wdt_fck = {
  1265. .name = "mpu_wdt_fck",
  1266. .ops = &clkops_omap2_dflt_wait,
  1267. .parent = &func_32k_ck,
  1268. .clkdm_name = "wkup_clkdm",
  1269. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  1270. .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
  1271. .recalc = &followparent_recalc,
  1272. };
  1273. static struct clk sync_32k_ick = {
  1274. .name = "sync_32k_ick",
  1275. .ops = &clkops_omap2_dflt_wait,
  1276. .parent = &l4_ck,
  1277. .flags = ENABLE_ON_INIT,
  1278. .clkdm_name = "core_l4_clkdm",
  1279. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  1280. .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
  1281. .recalc = &followparent_recalc,
  1282. };
  1283. static struct clk wdt1_ick = {
  1284. .name = "wdt1_ick",
  1285. .ops = &clkops_omap2_dflt_wait,
  1286. .parent = &l4_ck,
  1287. .clkdm_name = "core_l4_clkdm",
  1288. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  1289. .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
  1290. .recalc = &followparent_recalc,
  1291. };
  1292. static struct clk omapctrl_ick = {
  1293. .name = "omapctrl_ick",
  1294. .ops = &clkops_omap2_dflt_wait,
  1295. .parent = &l4_ck,
  1296. .flags = ENABLE_ON_INIT,
  1297. .clkdm_name = "core_l4_clkdm",
  1298. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  1299. .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
  1300. .recalc = &followparent_recalc,
  1301. };
  1302. static struct clk icr_ick = {
  1303. .name = "icr_ick",
  1304. .ops = &clkops_omap2_dflt_wait,
  1305. .parent = &l4_ck,
  1306. .clkdm_name = "core_l4_clkdm",
  1307. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  1308. .enable_bit = OMAP2430_EN_ICR_SHIFT,
  1309. .recalc = &followparent_recalc,
  1310. };
  1311. static struct clk cam_ick = {
  1312. .name = "cam_ick",
  1313. .ops = &clkops_omap2_dflt,
  1314. .parent = &l4_ck,
  1315. .clkdm_name = "core_l4_clkdm",
  1316. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1317. .enable_bit = OMAP24XX_EN_CAM_SHIFT,
  1318. .recalc = &followparent_recalc,
  1319. };
  1320. /*
  1321. * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
  1322. * split into two separate clocks, since the parent clocks are different
  1323. * and the clockdomains are also different.
  1324. */
  1325. static struct clk cam_fck = {
  1326. .name = "cam_fck",
  1327. .ops = &clkops_omap2_dflt,
  1328. .parent = &func_96m_ck,
  1329. .clkdm_name = "core_l3_clkdm",
  1330. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1331. .enable_bit = OMAP24XX_EN_CAM_SHIFT,
  1332. .recalc = &followparent_recalc,
  1333. };
  1334. static struct clk mailboxes_ick = {
  1335. .name = "mailboxes_ick",
  1336. .ops = &clkops_omap2_dflt_wait,
  1337. .parent = &l4_ck,
  1338. .clkdm_name = "core_l4_clkdm",
  1339. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1340. .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
  1341. .recalc = &followparent_recalc,
  1342. };
  1343. static struct clk wdt4_ick = {
  1344. .name = "wdt4_ick",
  1345. .ops = &clkops_omap2_dflt_wait,
  1346. .parent = &l4_ck,
  1347. .clkdm_name = "core_l4_clkdm",
  1348. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1349. .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
  1350. .recalc = &followparent_recalc,
  1351. };
  1352. static struct clk wdt4_fck = {
  1353. .name = "wdt4_fck",
  1354. .ops = &clkops_omap2_dflt_wait,
  1355. .parent = &func_32k_ck,
  1356. .clkdm_name = "core_l4_clkdm",
  1357. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1358. .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
  1359. .recalc = &followparent_recalc,
  1360. };
  1361. static struct clk mspro_ick = {
  1362. .name = "mspro_ick",
  1363. .ops = &clkops_omap2_dflt_wait,
  1364. .parent = &l4_ck,
  1365. .clkdm_name = "core_l4_clkdm",
  1366. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1367. .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
  1368. .recalc = &followparent_recalc,
  1369. };
  1370. static struct clk mspro_fck = {
  1371. .name = "mspro_fck",
  1372. .ops = &clkops_omap2_dflt_wait,
  1373. .parent = &func_96m_ck,
  1374. .clkdm_name = "core_l4_clkdm",
  1375. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1376. .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
  1377. .recalc = &followparent_recalc,
  1378. };
  1379. static struct clk fac_ick = {
  1380. .name = "fac_ick",
  1381. .ops = &clkops_omap2_dflt_wait,
  1382. .parent = &l4_ck,
  1383. .clkdm_name = "core_l4_clkdm",
  1384. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1385. .enable_bit = OMAP24XX_EN_FAC_SHIFT,
  1386. .recalc = &followparent_recalc,
  1387. };
  1388. static struct clk fac_fck = {
  1389. .name = "fac_fck",
  1390. .ops = &clkops_omap2_dflt_wait,
  1391. .parent = &func_12m_ck,
  1392. .clkdm_name = "core_l4_clkdm",
  1393. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1394. .enable_bit = OMAP24XX_EN_FAC_SHIFT,
  1395. .recalc = &followparent_recalc,
  1396. };
  1397. static struct clk hdq_ick = {
  1398. .name = "hdq_ick",
  1399. .ops = &clkops_omap2_dflt_wait,
  1400. .parent = &l4_ck,
  1401. .clkdm_name = "core_l4_clkdm",
  1402. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1403. .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
  1404. .recalc = &followparent_recalc,
  1405. };
  1406. static struct clk hdq_fck = {
  1407. .name = "hdq_fck",
  1408. .ops = &clkops_omap2_dflt_wait,
  1409. .parent = &func_12m_ck,
  1410. .clkdm_name = "core_l4_clkdm",
  1411. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1412. .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
  1413. .recalc = &followparent_recalc,
  1414. };
  1415. /*
  1416. * XXX This is marked as a 2420-only define, but it claims to be present
  1417. * on 2430 also. Double-check.
  1418. */
  1419. static struct clk i2c2_ick = {
  1420. .name = "i2c2_ick",
  1421. .ops = &clkops_omap2_dflt_wait,
  1422. .parent = &l4_ck,
  1423. .clkdm_name = "core_l4_clkdm",
  1424. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1425. .enable_bit = OMAP2420_EN_I2C2_SHIFT,
  1426. .recalc = &followparent_recalc,
  1427. };
  1428. static struct clk i2chs2_fck = {
  1429. .name = "i2chs2_fck",
  1430. .ops = &clkops_omap2430_i2chs_wait,
  1431. .parent = &func_96m_ck,
  1432. .clkdm_name = "core_l4_clkdm",
  1433. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1434. .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
  1435. .recalc = &followparent_recalc,
  1436. };
  1437. /*
  1438. * XXX This is marked as a 2420-only define, but it claims to be present
  1439. * on 2430 also. Double-check.
  1440. */
  1441. static struct clk i2c1_ick = {
  1442. .name = "i2c1_ick",
  1443. .ops = &clkops_omap2_dflt_wait,
  1444. .parent = &l4_ck,
  1445. .clkdm_name = "core_l4_clkdm",
  1446. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1447. .enable_bit = OMAP2420_EN_I2C1_SHIFT,
  1448. .recalc = &followparent_recalc,
  1449. };
  1450. static struct clk i2chs1_fck = {
  1451. .name = "i2chs1_fck",
  1452. .ops = &clkops_omap2430_i2chs_wait,
  1453. .parent = &func_96m_ck,
  1454. .clkdm_name = "core_l4_clkdm",
  1455. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1456. .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
  1457. .recalc = &followparent_recalc,
  1458. };
  1459. static struct clk gpmc_fck = {
  1460. .name = "gpmc_fck",
  1461. .ops = &clkops_null, /* RMK: missing? */
  1462. .parent = &core_l3_ck,
  1463. .flags = ENABLE_ON_INIT,
  1464. .clkdm_name = "core_l3_clkdm",
  1465. .recalc = &followparent_recalc,
  1466. };
  1467. static struct clk sdma_fck = {
  1468. .name = "sdma_fck",
  1469. .ops = &clkops_null, /* RMK: missing? */
  1470. .parent = &core_l3_ck,
  1471. .clkdm_name = "core_l3_clkdm",
  1472. .recalc = &followparent_recalc,
  1473. };
  1474. static struct clk sdma_ick = {
  1475. .name = "sdma_ick",
  1476. .ops = &clkops_null, /* RMK: missing? */
  1477. .parent = &l4_ck,
  1478. .clkdm_name = "core_l3_clkdm",
  1479. .recalc = &followparent_recalc,
  1480. };
  1481. static struct clk sdrc_ick = {
  1482. .name = "sdrc_ick",
  1483. .ops = &clkops_omap2_dflt_wait,
  1484. .parent = &l4_ck,
  1485. .flags = ENABLE_ON_INIT,
  1486. .clkdm_name = "core_l4_clkdm",
  1487. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
  1488. .enable_bit = OMAP2430_EN_SDRC_SHIFT,
  1489. .recalc = &followparent_recalc,
  1490. };
  1491. static struct clk des_ick = {
  1492. .name = "des_ick",
  1493. .ops = &clkops_omap2_dflt_wait,
  1494. .parent = &l4_ck,
  1495. .clkdm_name = "core_l4_clkdm",
  1496. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
  1497. .enable_bit = OMAP24XX_EN_DES_SHIFT,
  1498. .recalc = &followparent_recalc,
  1499. };
  1500. static struct clk sha_ick = {
  1501. .name = "sha_ick",
  1502. .ops = &clkops_omap2_dflt_wait,
  1503. .parent = &l4_ck,
  1504. .clkdm_name = "core_l4_clkdm",
  1505. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
  1506. .enable_bit = OMAP24XX_EN_SHA_SHIFT,
  1507. .recalc = &followparent_recalc,
  1508. };
  1509. static struct clk rng_ick = {
  1510. .name = "rng_ick",
  1511. .ops = &clkops_omap2_dflt_wait,
  1512. .parent = &l4_ck,
  1513. .clkdm_name = "core_l4_clkdm",
  1514. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
  1515. .enable_bit = OMAP24XX_EN_RNG_SHIFT,
  1516. .recalc = &followparent_recalc,
  1517. };
  1518. static struct clk aes_ick = {
  1519. .name = "aes_ick",
  1520. .ops = &clkops_omap2_dflt_wait,
  1521. .parent = &l4_ck,
  1522. .clkdm_name = "core_l4_clkdm",
  1523. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
  1524. .enable_bit = OMAP24XX_EN_AES_SHIFT,
  1525. .recalc = &followparent_recalc,
  1526. };
  1527. static struct clk pka_ick = {
  1528. .name = "pka_ick",
  1529. .ops = &clkops_omap2_dflt_wait,
  1530. .parent = &l4_ck,
  1531. .clkdm_name = "core_l4_clkdm",
  1532. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
  1533. .enable_bit = OMAP24XX_EN_PKA_SHIFT,
  1534. .recalc = &followparent_recalc,
  1535. };
  1536. static struct clk usb_fck = {
  1537. .name = "usb_fck",
  1538. .ops = &clkops_omap2_dflt_wait,
  1539. .parent = &func_48m_ck,
  1540. .clkdm_name = "core_l3_clkdm",
  1541. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1542. .enable_bit = OMAP24XX_EN_USB_SHIFT,
  1543. .recalc = &followparent_recalc,
  1544. };
  1545. static struct clk usbhs_ick = {
  1546. .name = "usbhs_ick",
  1547. .ops = &clkops_omap2_dflt_wait,
  1548. .parent = &core_l3_ck,
  1549. .clkdm_name = "core_l3_clkdm",
  1550. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1551. .enable_bit = OMAP2430_EN_USBHS_SHIFT,
  1552. .recalc = &followparent_recalc,
  1553. };
  1554. static struct clk mmchs1_ick = {
  1555. .name = "mmchs1_ick",
  1556. .ops = &clkops_omap2_dflt_wait,
  1557. .parent = &l4_ck,
  1558. .clkdm_name = "core_l4_clkdm",
  1559. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1560. .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
  1561. .recalc = &followparent_recalc,
  1562. };
  1563. static struct clk mmchs1_fck = {
  1564. .name = "mmchs1_fck",
  1565. .ops = &clkops_omap2_dflt_wait,
  1566. .parent = &func_96m_ck,
  1567. .clkdm_name = "core_l3_clkdm",
  1568. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1569. .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
  1570. .recalc = &followparent_recalc,
  1571. };
  1572. static struct clk mmchs2_ick = {
  1573. .name = "mmchs2_ick",
  1574. .ops = &clkops_omap2_dflt_wait,
  1575. .parent = &l4_ck,
  1576. .clkdm_name = "core_l4_clkdm",
  1577. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1578. .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
  1579. .recalc = &followparent_recalc,
  1580. };
  1581. static struct clk mmchs2_fck = {
  1582. .name = "mmchs2_fck",
  1583. .ops = &clkops_omap2_dflt_wait,
  1584. .parent = &func_96m_ck,
  1585. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1586. .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
  1587. .recalc = &followparent_recalc,
  1588. };
  1589. static struct clk gpio5_ick = {
  1590. .name = "gpio5_ick",
  1591. .ops = &clkops_omap2_dflt_wait,
  1592. .parent = &l4_ck,
  1593. .clkdm_name = "core_l4_clkdm",
  1594. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1595. .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
  1596. .recalc = &followparent_recalc,
  1597. };
  1598. static struct clk gpio5_fck = {
  1599. .name = "gpio5_fck",
  1600. .ops = &clkops_omap2_dflt_wait,
  1601. .parent = &func_32k_ck,
  1602. .clkdm_name = "core_l4_clkdm",
  1603. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1604. .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
  1605. .recalc = &followparent_recalc,
  1606. };
  1607. static struct clk mdm_intc_ick = {
  1608. .name = "mdm_intc_ick",
  1609. .ops = &clkops_omap2_dflt_wait,
  1610. .parent = &l4_ck,
  1611. .clkdm_name = "core_l4_clkdm",
  1612. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1613. .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
  1614. .recalc = &followparent_recalc,
  1615. };
  1616. static struct clk mmchsdb1_fck = {
  1617. .name = "mmchsdb1_fck",
  1618. .ops = &clkops_omap2_dflt_wait,
  1619. .parent = &func_32k_ck,
  1620. .clkdm_name = "core_l4_clkdm",
  1621. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1622. .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
  1623. .recalc = &followparent_recalc,
  1624. };
  1625. static struct clk mmchsdb2_fck = {
  1626. .name = "mmchsdb2_fck",
  1627. .ops = &clkops_omap2_dflt_wait,
  1628. .parent = &func_32k_ck,
  1629. .clkdm_name = "core_l4_clkdm",
  1630. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
  1631. .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
  1632. .recalc = &followparent_recalc,
  1633. };
  1634. /*
  1635. * This clock is a composite clock which does entire set changes then
  1636. * forces a rebalance. It keys on the MPU speed, but it really could
  1637. * be any key speed part of a set in the rate table.
  1638. *
  1639. * to really change a set, you need memory table sets which get changed
  1640. * in sram, pre-notifiers & post notifiers, changing the top set, without
  1641. * having low level display recalc's won't work... this is why dpm notifiers
  1642. * work, isr's off, walk a list of clocks already _off_ and not messing with
  1643. * the bus.
  1644. *
  1645. * This clock should have no parent. It embodies the entire upper level
  1646. * active set. A parent will mess up some of the init also.
  1647. */
  1648. static struct clk virt_prcm_set = {
  1649. .name = "virt_prcm_set",
  1650. .ops = &clkops_null,
  1651. .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
  1652. .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
  1653. .set_rate = &omap2_select_table_rate,
  1654. .round_rate = &omap2_round_to_table_rate,
  1655. };
  1656. /*
  1657. * clkdev integration
  1658. */
  1659. static struct omap_clk omap2430_clks[] = {
  1660. /* external root sources */
  1661. CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
  1662. CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
  1663. CLK(NULL, "osc_ck", &osc_ck, CK_243X),
  1664. CLK(NULL, "sys_ck", &sys_ck, CK_243X),
  1665. CLK(NULL, "alt_ck", &alt_ck, CK_243X),
  1666. CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X),
  1667. CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X),
  1668. CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X),
  1669. CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X),
  1670. CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X),
  1671. CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
  1672. /* internal analog sources */
  1673. CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
  1674. CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
  1675. CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
  1676. /* internal prcm root sources */
  1677. CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
  1678. CLK(NULL, "core_ck", &core_ck, CK_243X),
  1679. CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X),
  1680. CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X),
  1681. CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X),
  1682. CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X),
  1683. CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X),
  1684. CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
  1685. CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
  1686. CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
  1687. CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
  1688. CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
  1689. CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
  1690. CLK(NULL, "emul_ck", &emul_ck, CK_243X),
  1691. /* mpu domain clocks */
  1692. CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
  1693. /* dsp domain clocks */
  1694. CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
  1695. CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X),
  1696. CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
  1697. /* GFX domain clocks */
  1698. CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
  1699. CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
  1700. CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
  1701. /* Modem domain clocks */
  1702. CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
  1703. CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
  1704. /* DSS domain clocks */
  1705. CLK("omapdss", "ick", &dss_ick, CK_243X),
  1706. CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X),
  1707. CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X),
  1708. CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X),
  1709. /* L3 domain clocks */
  1710. CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
  1711. CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
  1712. CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
  1713. /* L4 domain clocks */
  1714. CLK(NULL, "l4_ck", &l4_ck, CK_243X),
  1715. CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
  1716. /* virtual meta-group clock */
  1717. CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
  1718. /* general l4 interface ck, multi-parent functional clk */
  1719. CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
  1720. CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
  1721. CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
  1722. CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
  1723. CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
  1724. CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
  1725. CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
  1726. CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
  1727. CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
  1728. CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
  1729. CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
  1730. CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
  1731. CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
  1732. CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
  1733. CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
  1734. CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
  1735. CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
  1736. CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
  1737. CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
  1738. CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
  1739. CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
  1740. CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
  1741. CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
  1742. CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
  1743. CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
  1744. CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X),
  1745. CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
  1746. CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X),
  1747. CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
  1748. CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
  1749. CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
  1750. CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
  1751. CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
  1752. CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
  1753. CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
  1754. CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X),
  1755. CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
  1756. CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X),
  1757. CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
  1758. CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
  1759. CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
  1760. CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
  1761. CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
  1762. CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
  1763. CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
  1764. CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
  1765. CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
  1766. CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
  1767. CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
  1768. CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X),
  1769. CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
  1770. CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
  1771. CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
  1772. CLK(NULL, "icr_ick", &icr_ick, CK_243X),
  1773. CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
  1774. CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
  1775. CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
  1776. CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
  1777. CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
  1778. CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
  1779. CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
  1780. CLK(NULL, "fac_ick", &fac_ick, CK_243X),
  1781. CLK(NULL, "fac_fck", &fac_fck, CK_243X),
  1782. CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
  1783. CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
  1784. CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X),
  1785. CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
  1786. CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X),
  1787. CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
  1788. CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
  1789. CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
  1790. CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
  1791. CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
  1792. CLK(NULL, "des_ick", &des_ick, CK_243X),
  1793. CLK("omap-sham", "ick", &sha_ick, CK_243X),
  1794. CLK("omap_rng", "ick", &rng_ick, CK_243X),
  1795. CLK("omap-aes", "ick", &aes_ick, CK_243X),
  1796. CLK(NULL, "pka_ick", &pka_ick, CK_243X),
  1797. CLK(NULL, "usb_fck", &usb_fck, CK_243X),
  1798. CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
  1799. CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
  1800. CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
  1801. CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
  1802. CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
  1803. CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
  1804. CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
  1805. CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
  1806. CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
  1807. CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
  1808. };
  1809. /*
  1810. * init code
  1811. */
  1812. int __init omap2430_clk_init(void)
  1813. {
  1814. const struct prcm_config *prcm;
  1815. struct omap_clk *c;
  1816. u32 clkrate;
  1817. prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
  1818. cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
  1819. cpu_mask = RATE_IN_243X;
  1820. rate_table = omap2430_rate_table;
  1821. clk_init(&omap2_clk_functions);
  1822. for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
  1823. c++)
  1824. clk_preinit(c->lk.clk);
  1825. osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
  1826. propagate_rate(&osc_ck);
  1827. sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
  1828. propagate_rate(&sys_ck);
  1829. for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
  1830. c++) {
  1831. clkdev_add(&c->lk);
  1832. clk_register(c->lk.clk);
  1833. omap2_init_clk_clkdm(c->lk.clk);
  1834. }
  1835. /* Check the MPU rate set by bootloader */
  1836. clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
  1837. for (prcm = rate_table; prcm->mpu_speed; prcm++) {
  1838. if (!(prcm->flags & cpu_mask))
  1839. continue;
  1840. if (prcm->xtal_speed != sys_ck.rate)
  1841. continue;
  1842. if (prcm->dpll_speed <= clkrate)
  1843. break;
  1844. }
  1845. curr_prcm_set = prcm;
  1846. recalculate_root_clocks();
  1847. pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
  1848. (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
  1849. (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
  1850. /*
  1851. * Only enable those clocks we will need, let the drivers
  1852. * enable other clocks as necessary
  1853. */
  1854. clk_enable_init_clocks();
  1855. /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
  1856. vclk = clk_get(NULL, "virt_prcm_set");
  1857. sclk = clk_get(NULL, "sys_ck");
  1858. dclk = clk_get(NULL, "dpll_ck");
  1859. return 0;
  1860. }