iommu.h 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15. * 02110-1301, USA.
  16. */
  17. #ifndef MSM_IOMMU_H
  18. #define MSM_IOMMU_H
  19. #include <linux/interrupt.h>
  20. /* Maximum number of Machine IDs that we are allowing to be mapped to the same
  21. * context bank. The number of MIDs mapped to the same CB does not affect
  22. * performance, but there is a practical limit on how many distinct MIDs may
  23. * be present. These mappings are typically determined at design time and are
  24. * not expected to change at run time.
  25. */
  26. #define MAX_NUM_MIDS 16
  27. /**
  28. * struct msm_iommu_dev - a single IOMMU hardware instance
  29. * name Human-readable name given to this IOMMU HW instance
  30. * clk_rate Rate to set for this IOMMU's clock, if applicable to this
  31. * particular IOMMU. 0 means don't set a rate.
  32. * -1 means it is an AXI clock with no valid rate
  33. *
  34. */
  35. struct msm_iommu_dev {
  36. const char *name;
  37. int clk_rate;
  38. };
  39. /**
  40. * struct msm_iommu_ctx_dev - an IOMMU context bank instance
  41. * name Human-readable name given to this context bank
  42. * num Index of this context bank within the hardware
  43. * mids List of Machine IDs that are to be mapped into this context
  44. * bank, terminated by -1. The MID is a set of signals on the
  45. * AXI bus that identifies the function associated with a specific
  46. * memory request. (See ARM spec).
  47. */
  48. struct msm_iommu_ctx_dev {
  49. const char *name;
  50. int num;
  51. int mids[MAX_NUM_MIDS];
  52. };
  53. /**
  54. * struct msm_iommu_drvdata - A single IOMMU hardware instance
  55. * @base: IOMMU config port base address (VA)
  56. * @irq: Interrupt number
  57. *
  58. * A msm_iommu_drvdata holds the global driver data about a single piece
  59. * of an IOMMU hardware instance.
  60. */
  61. struct msm_iommu_drvdata {
  62. void __iomem *base;
  63. int irq;
  64. };
  65. /**
  66. * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
  67. * @num: Hardware context number of this context
  68. * @pdev: Platform device associated wit this HW instance
  69. * @attached_elm: List element for domains to track which devices are
  70. * attached to them
  71. *
  72. * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
  73. * within each IOMMU hardware instance
  74. */
  75. struct msm_iommu_ctx_drvdata {
  76. int num;
  77. struct platform_device *pdev;
  78. struct list_head attached_elm;
  79. };
  80. /*
  81. * Look up an IOMMU context device by its context name. NULL if none found.
  82. * Useful for testing and drivers that do not yet fully have IOMMU stuff in
  83. * their platform devices.
  84. */
  85. struct device *msm_iommu_get_ctx(const char *ctx_name);
  86. /*
  87. * Interrupt handler for the IOMMU context fault interrupt. Hooking the
  88. * interrupt is not supported in the API yet, but this will print an error
  89. * message and dump useful IOMMU registers.
  90. */
  91. irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
  92. #endif