board-msm8x60.c 2.7 KB

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  1. /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15. * 02110-1301, USA.
  16. *
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/io.h>
  21. #include <linux/irq.h>
  22. #include <asm/mach-types.h>
  23. #include <asm/mach/arch.h>
  24. #include <asm/hardware/gic.h>
  25. #include <mach/board.h>
  26. #include <mach/msm_iomap.h>
  27. void __iomem *gic_cpu_base_addr;
  28. unsigned long clk_get_max_axi_khz(void)
  29. {
  30. return 0;
  31. }
  32. static void __init msm8x60_map_io(void)
  33. {
  34. msm_map_msm8x60_io();
  35. }
  36. static void __init msm8x60_init_irq(void)
  37. {
  38. unsigned int i;
  39. gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
  40. gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
  41. gic_cpu_init(0, MSM_QGIC_CPU_BASE);
  42. /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
  43. writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
  44. /* RUMI does not adhere to GIC spec by enabling STIs by default.
  45. * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
  46. */
  47. if (!machine_is_msm8x60_sim())
  48. writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
  49. /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
  50. * as they are configured as level, which does not play nice with
  51. * handle_percpu_irq.
  52. */
  53. for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
  54. if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
  55. set_irq_handler(i, handle_percpu_irq);
  56. }
  57. }
  58. static void __init msm8x60_init(void)
  59. {
  60. }
  61. MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
  62. .map_io = msm8x60_map_io,
  63. .init_irq = msm8x60_init_irq,
  64. .init_machine = msm8x60_init,
  65. .timer = &msm_timer,
  66. MACHINE_END
  67. MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
  68. .map_io = msm8x60_map_io,
  69. .init_irq = msm8x60_init_irq,
  70. .init_machine = msm8x60_init,
  71. .timer = &msm_timer,
  72. MACHINE_END
  73. MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
  74. .map_io = msm8x60_map_io,
  75. .init_irq = msm8x60_init_irq,
  76. .init_machine = msm8x60_init,
  77. .timer = &msm_timer,
  78. MACHINE_END
  79. MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
  80. .map_io = msm8x60_map_io,
  81. .init_irq = msm8x60_init_irq,
  82. .init_machine = msm8x60_init,
  83. .timer = &msm_timer,
  84. MACHINE_END