sdio_chip.h 4.3 KB

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  1. /*
  2. * Copyright (c) 2011 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _BRCMFMAC_SDIO_CHIP_H_
  17. #define _BRCMFMAC_SDIO_CHIP_H_
  18. /*
  19. * Core reg address translation.
  20. * Both macro's returns a 32 bits byte address on the backplane bus.
  21. */
  22. #define CORE_CC_REG(base, field) \
  23. (base + offsetof(struct chipcregs, field))
  24. #define CORE_BUS_REG(base, field) \
  25. (base + offsetof(struct sdpcmd_regs, field))
  26. #define CORE_SB(base, field) \
  27. (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
  28. /* SDIO function 1 register CHIPCLKCSR */
  29. /* Force ALP request to backplane */
  30. #define SBSDIO_FORCE_ALP 0x01
  31. /* Force HT request to backplane */
  32. #define SBSDIO_FORCE_HT 0x02
  33. /* Force ILP request to backplane */
  34. #define SBSDIO_FORCE_ILP 0x04
  35. /* Make ALP ready (power up xtal) */
  36. #define SBSDIO_ALP_AVAIL_REQ 0x08
  37. /* Make HT ready (power up PLL) */
  38. #define SBSDIO_HT_AVAIL_REQ 0x10
  39. /* Squelch clock requests from HW */
  40. #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
  41. /* Status: ALP is ready */
  42. #define SBSDIO_ALP_AVAIL 0x40
  43. /* Status: HT is ready */
  44. #define SBSDIO_HT_AVAIL 0x80
  45. #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
  46. #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
  47. #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
  48. #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
  49. #define SBSDIO_CLKAV(regval, alponly) \
  50. (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
  51. #define BRCMF_MAX_CORENUM 6
  52. struct chip_core_info {
  53. u16 id;
  54. u16 rev;
  55. u32 base;
  56. u32 wrapbase;
  57. u32 caps;
  58. u32 cib;
  59. };
  60. struct chip_info {
  61. u32 chip;
  62. u32 chiprev;
  63. u32 socitype;
  64. /* core info */
  65. /* always put chipcommon core at 0, bus core at 1 */
  66. struct chip_core_info c_inf[BRCMF_MAX_CORENUM];
  67. u32 pmurev;
  68. u32 pmucaps;
  69. u32 ramsize;
  70. bool (*iscoreup)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
  71. u16 coreid);
  72. u32 (*corerev)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
  73. u16 coreid);
  74. void (*coredisable)(struct brcmf_sdio_dev *sdiodev,
  75. struct chip_info *ci, u16 coreid);
  76. void (*resetcore)(struct brcmf_sdio_dev *sdiodev,
  77. struct chip_info *ci, u16 coreid);
  78. };
  79. struct sbconfig {
  80. u32 PAD[2];
  81. u32 sbipsflag; /* initiator port ocp slave flag */
  82. u32 PAD[3];
  83. u32 sbtpsflag; /* target port ocp slave flag */
  84. u32 PAD[11];
  85. u32 sbtmerrloga; /* (sonics >= 2.3) */
  86. u32 PAD;
  87. u32 sbtmerrlog; /* (sonics >= 2.3) */
  88. u32 PAD[3];
  89. u32 sbadmatch3; /* address match3 */
  90. u32 PAD;
  91. u32 sbadmatch2; /* address match2 */
  92. u32 PAD;
  93. u32 sbadmatch1; /* address match1 */
  94. u32 PAD[7];
  95. u32 sbimstate; /* initiator agent state */
  96. u32 sbintvec; /* interrupt mask */
  97. u32 sbtmstatelow; /* target state */
  98. u32 sbtmstatehigh; /* target state */
  99. u32 sbbwa0; /* bandwidth allocation table0 */
  100. u32 PAD;
  101. u32 sbimconfiglow; /* initiator configuration */
  102. u32 sbimconfighigh; /* initiator configuration */
  103. u32 sbadmatch0; /* address match0 */
  104. u32 PAD;
  105. u32 sbtmconfiglow; /* target configuration */
  106. u32 sbtmconfighigh; /* target configuration */
  107. u32 sbbconfig; /* broadcast configuration */
  108. u32 PAD;
  109. u32 sbbstate; /* broadcast state */
  110. u32 PAD[3];
  111. u32 sbactcnfg; /* activate configuration */
  112. u32 PAD[3];
  113. u32 sbflagst; /* current sbflags */
  114. u32 PAD[3];
  115. u32 sbidlow; /* identification */
  116. u32 sbidhigh; /* identification */
  117. };
  118. extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
  119. struct chip_info **ci_ptr, u32 regs);
  120. extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr);
  121. extern void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
  122. struct chip_info *ci,
  123. u32 drivestrength);
  124. extern u8 brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid);
  125. #endif /* _BRCMFMAC_SDIO_CHIP_H_ */