debug.h 8.0 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef DEBUG_H
  17. #define DEBUG_H
  18. #include "hw.h"
  19. #include "rc.h"
  20. #include "dfs_debug.h"
  21. struct ath_txq;
  22. struct ath_buf;
  23. #ifdef CONFIG_ATH9K_DEBUGFS
  24. #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
  25. #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
  26. #else
  27. #define TX_STAT_INC(q, c) do { } while (0)
  28. #define RESET_STAT_INC(sc, type) do { } while (0)
  29. #endif
  30. #ifdef CONFIG_ATH9K_DEBUGFS
  31. /**
  32. * struct ath_interrupt_stats - Contains statistics about interrupts
  33. * @total: Total no. of interrupts generated so far
  34. * @rxok: RX with no errors
  35. * @rxlp: RX with low priority RX
  36. * @rxhp: RX with high priority, uapsd only
  37. * @rxeol: RX with no more RXDESC available
  38. * @rxorn: RX FIFO overrun
  39. * @txok: TX completed at the requested rate
  40. * @txurn: TX FIFO underrun
  41. * @mib: MIB regs reaching its threshold
  42. * @rxphyerr: RX with phy errors
  43. * @rx_keycache_miss: RX with key cache misses
  44. * @swba: Software Beacon Alert
  45. * @bmiss: Beacon Miss
  46. * @bnr: Beacon Not Ready
  47. * @cst: Carrier Sense TImeout
  48. * @gtt: Global TX Timeout
  49. * @tim: RX beacon TIM occurrence
  50. * @cabend: RX End of CAB traffic
  51. * @dtimsync: DTIM sync lossage
  52. * @dtim: RX Beacon with DTIM
  53. * @bb_watchdog: Baseband watchdog
  54. * @tsfoor: TSF out of range, indicates that the corrected TSF received
  55. * from a beacon differs from the PCU's internal TSF by more than a
  56. * (programmable) threshold
  57. */
  58. struct ath_interrupt_stats {
  59. u32 total;
  60. u32 rxok;
  61. u32 rxlp;
  62. u32 rxhp;
  63. u32 rxeol;
  64. u32 rxorn;
  65. u32 txok;
  66. u32 txeol;
  67. u32 txurn;
  68. u32 mib;
  69. u32 rxphyerr;
  70. u32 rx_keycache_miss;
  71. u32 swba;
  72. u32 bmiss;
  73. u32 bnr;
  74. u32 cst;
  75. u32 gtt;
  76. u32 tim;
  77. u32 cabend;
  78. u32 dtimsync;
  79. u32 dtim;
  80. u32 bb_watchdog;
  81. u32 tsfoor;
  82. };
  83. /**
  84. * struct ath_tx_stats - Statistics about TX
  85. * @tx_pkts_all: No. of total frames transmitted, including ones that
  86. may have had errors.
  87. * @tx_bytes_all: No. of total bytes transmitted, including ones that
  88. may have had errors.
  89. * @queued: Total MPDUs (non-aggr) queued
  90. * @completed: Total MPDUs (non-aggr) completed
  91. * @a_aggr: Total no. of aggregates queued
  92. * @a_queued_hw: Total AMPDUs queued to hardware
  93. * @a_queued_sw: Total AMPDUs queued to software queues
  94. * @a_completed: Total AMPDUs completed
  95. * @a_retries: No. of AMPDUs retried (SW)
  96. * @a_xretries: No. of AMPDUs dropped due to xretries
  97. * @fifo_underrun: FIFO underrun occurrences
  98. Valid only for:
  99. - non-aggregate condition.
  100. - first packet of aggregate.
  101. * @xtxop: No. of frames filtered because of TXOP limit
  102. * @timer_exp: Transmit timer expiry
  103. * @desc_cfg_err: Descriptor configuration errors
  104. * @data_urn: TX data underrun errors
  105. * @delim_urn: TX delimiter underrun errors
  106. * @puttxbuf: Number of times hardware was given txbuf to write.
  107. * @txstart: Number of times hardware was told to start tx.
  108. * @txprocdesc: Number of times tx descriptor was processed
  109. * @txfailed: Out-of-memory or other errors in xmit path.
  110. */
  111. struct ath_tx_stats {
  112. u32 tx_pkts_all;
  113. u32 tx_bytes_all;
  114. u32 queued;
  115. u32 completed;
  116. u32 xretries;
  117. u32 a_aggr;
  118. u32 a_queued_hw;
  119. u32 a_queued_sw;
  120. u32 a_completed;
  121. u32 a_retries;
  122. u32 a_xretries;
  123. u32 fifo_underrun;
  124. u32 xtxop;
  125. u32 timer_exp;
  126. u32 desc_cfg_err;
  127. u32 data_underrun;
  128. u32 delim_underrun;
  129. u32 puttxbuf;
  130. u32 txstart;
  131. u32 txprocdesc;
  132. u32 txfailed;
  133. };
  134. #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
  135. /**
  136. * struct ath_rx_stats - RX Statistics
  137. * @rx_pkts_all: No. of total frames received, including ones that
  138. may have had errors.
  139. * @rx_bytes_all: No. of total bytes received, including ones that
  140. may have had errors.
  141. * @crc_err: No. of frames with incorrect CRC value
  142. * @decrypt_crc_err: No. of frames whose CRC check failed after
  143. decryption process completed
  144. * @phy_err: No. of frames whose reception failed because the PHY
  145. encountered an error
  146. * @mic_err: No. of frames with incorrect TKIP MIC verification failure
  147. * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
  148. * @post_delim_crc_err: Post-Frame delimiter CRC error detections
  149. * @decrypt_busy_err: Decryption interruptions counter
  150. * @phy_err_stats: Individual PHY error statistics
  151. * @rx_len_err: No. of frames discarded due to bad length.
  152. * @rx_oom_err: No. of frames dropped due to OOM issues.
  153. * @rx_rate_err: No. of frames dropped due to rate errors.
  154. * @rx_too_many_frags_err: Frames dropped due to too-many-frags received.
  155. * @rx_drop_rxflush: No. of frames dropped due to RX-FLUSH.
  156. * @rx_beacons: No. of beacons received.
  157. * @rx_frags: No. of rx-fragements received.
  158. */
  159. struct ath_rx_stats {
  160. u32 rx_pkts_all;
  161. u32 rx_bytes_all;
  162. u32 crc_err;
  163. u32 decrypt_crc_err;
  164. u32 phy_err;
  165. u32 mic_err;
  166. u32 pre_delim_crc_err;
  167. u32 post_delim_crc_err;
  168. u32 decrypt_busy_err;
  169. u32 phy_err_stats[ATH9K_PHYERR_MAX];
  170. u32 rx_len_err;
  171. u32 rx_oom_err;
  172. u32 rx_rate_err;
  173. u32 rx_too_many_frags_err;
  174. u32 rx_drop_rxflush;
  175. u32 rx_beacons;
  176. u32 rx_frags;
  177. };
  178. enum ath_reset_type {
  179. RESET_TYPE_BB_HANG,
  180. RESET_TYPE_BB_WATCHDOG,
  181. RESET_TYPE_FATAL_INT,
  182. RESET_TYPE_TX_ERROR,
  183. RESET_TYPE_TX_HANG,
  184. RESET_TYPE_PLL_HANG,
  185. RESET_TYPE_MAC_HANG,
  186. __RESET_TYPE_MAX
  187. };
  188. struct ath_stats {
  189. struct ath_interrupt_stats istats;
  190. struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
  191. struct ath_rx_stats rxstats;
  192. struct ath_dfs_stats dfs_stats;
  193. u32 reset[__RESET_TYPE_MAX];
  194. };
  195. #define ATH_DBG_MAX_SAMPLES 10
  196. struct ath_dbg_bb_mac_samp {
  197. u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
  198. u32 pcu_obs, pcu_cr, noise;
  199. struct {
  200. u64 jiffies;
  201. int8_t rssi_ctl0;
  202. int8_t rssi_ctl1;
  203. int8_t rssi_ctl2;
  204. int8_t rssi_ext0;
  205. int8_t rssi_ext1;
  206. int8_t rssi_ext2;
  207. int8_t rssi;
  208. bool isok;
  209. u8 rts_fail_cnt;
  210. u8 data_fail_cnt;
  211. u8 rateindex;
  212. u8 qid;
  213. u8 tid;
  214. u32 ba_low;
  215. u32 ba_high;
  216. } ts[ATH_DBG_MAX_SAMPLES];
  217. struct {
  218. u64 jiffies;
  219. int8_t rssi_ctl0;
  220. int8_t rssi_ctl1;
  221. int8_t rssi_ctl2;
  222. int8_t rssi_ext0;
  223. int8_t rssi_ext1;
  224. int8_t rssi_ext2;
  225. int8_t rssi;
  226. bool is_mybeacon;
  227. u8 antenna;
  228. u8 rate;
  229. } rs[ATH_DBG_MAX_SAMPLES];
  230. struct ath_cycle_counters cc;
  231. struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
  232. };
  233. struct ath9k_debug {
  234. struct dentry *debugfs_phy;
  235. u32 regidx;
  236. struct ath_stats stats;
  237. #ifdef CONFIG_ATH9K_MAC_DEBUG
  238. spinlock_t samp_lock;
  239. struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
  240. u8 sampidx;
  241. u8 tsidx;
  242. u8 rsidx;
  243. #endif
  244. };
  245. int ath9k_init_debug(struct ath_hw *ah);
  246. void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
  247. void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
  248. struct ath_tx_status *ts, struct ath_txq *txq,
  249. unsigned int flags);
  250. void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
  251. #else
  252. #define RX_STAT_INC(c) /* NOP */
  253. static inline int ath9k_init_debug(struct ath_hw *ah)
  254. {
  255. return 0;
  256. }
  257. static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
  258. enum ath9k_int status)
  259. {
  260. }
  261. static inline void ath_debug_stat_tx(struct ath_softc *sc,
  262. struct ath_buf *bf,
  263. struct ath_tx_status *ts,
  264. struct ath_txq *txq,
  265. unsigned int flags)
  266. {
  267. }
  268. static inline void ath_debug_stat_rx(struct ath_softc *sc,
  269. struct ath_rx_status *rs)
  270. {
  271. }
  272. #endif /* CONFIG_ATH9K_DEBUGFS */
  273. #ifdef CONFIG_ATH9K_MAC_DEBUG
  274. void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
  275. #else
  276. static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
  277. {
  278. }
  279. #endif
  280. #endif /* DEBUG_H */