Home Explore Help
Register Sign In
phyus
/
linux-vybrid_public
8
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: ae40eb1ef3
Branches Tags
linux-vybrid_pu...
/
include
/
asm-m32r
/
m32r.h

m32r.h 4.7 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140 
  1. #ifndef _ASM_M32R_M32R_H_
    2. 

  2. #define _ASM_M32R_M32R_H_
    3. 

  3. 

  4. /*
    5. 

  5.  * Renesas M32R processor
    6. 

  6.  *
    7. 

  7.  * Copyright (C) 2003, 2004  Renesas Technology Corp.
    8. 

  8.  */
    9. 

  9. 

  10. 

  11. /* Chip type */
    12. 

  12. #if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP)
    13. 

  13. #include <asm/m32r_mp_fpga.h>
    14. 

  14. #elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
    15. 

  15. 	|| defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
    16. 

  16.         || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
    17. 

  17. #include <asm/m32102.h>
    18. 

  18. #endif
    19. 

  19. 

  20. /* Platform type */
    21. 

  21. #if defined(CONFIG_PLAT_M32700UT)
    22. 

  22. #include <asm/m32700ut/m32700ut_pld.h>
    23. 

  23. #include <asm/m32700ut/m32700ut_lan.h>
    24. 

  24. #include <asm/m32700ut/m32700ut_lcd.h>
    25. 

  25. #endif  /* CONFIG_PLAT_M32700UT */
    26. 

  26. 

  27. #if defined(CONFIG_PLAT_OPSPUT)
    28. 

  28. #include <asm/opsput/opsput_pld.h>
    29. 

  29. #include <asm/opsput/opsput_lan.h>
    30. 

  30. #include <asm/opsput/opsput_lcd.h>
    31. 

  31. #endif  /* CONFIG_PLAT_OPSPUT */
    32. 

  32. 

  33. #if defined(CONFIG_PLAT_MAPPI2)
    34. 

  34. #include <asm/mappi2/mappi2_pld.h>
    35. 

  35. #endif	/* CONFIG_PLAT_MAPPI2 */
    36. 

  36. 

  37. #if defined(CONFIG_PLAT_MAPPI3)
    38. 

  38. #include <asm/mappi3/mappi3_pld.h>
    39. 

  39. #endif	/* CONFIG_PLAT_MAPPI3 */
    40. 

  40. 

  41. #if defined(CONFIG_PLAT_USRV)
    42. 

  42. #include <asm/m32700ut/m32700ut_pld.h>
    43. 

  43. #endif
    44. 

  44. 

  45. #if defined(CONFIG_PLAT_M32104UT)
    46. 

  46. #include <asm/m32104ut/m32104ut_pld.h>
    47. 

  47. #endif  /* CONFIG_PLAT_M32104 */
    48. 

  48. 

  49. /*
    50. 

  50.  * M32R Register
    51. 

  51.  */
    52. 

  52. 

  53. /*
    54. 

  54.  * MMU Register
    55. 

  55.  */
    56. 

  56. 

  57. #define MMU_REG_BASE	(0xffff0000)
    58. 

  58. #define ITLB_BASE	(0xfe000000)
    59. 

  59. #define DTLB_BASE	(0xfe000800)
    60. 

  60. 

  61. #define NR_TLB_ENTRIES	CONFIG_TLB_ENTRIES
    62. 

  62. 

  63. #define MATM	MMU_REG_BASE		/* MMU Address Translation Mode
    64. 

  64. 					   Register */
    65. 

  65. #define MPSZ	(0x04 + MMU_REG_BASE)	/* MMU Page Size Designation Register */
    66. 

  66. #define MASID	(0x08 + MMU_REG_BASE)	/* MMU Address Space ID Register */
    67. 

  67. #define MESTS	(0x0c + MMU_REG_BASE)	/* MMU Exception Status Register */
    68. 

  68. #define MDEVA	(0x10 + MMU_REG_BASE)	/* MMU Operand Exception Virtual
    69. 

  69. 					   Address Register */
    70. 

  70. #define MDEVP	(0x14 + MMU_REG_BASE)	/* MMU Operand Exception Virtual Page
    71. 

  71. 					   Number Register */
    72. 

  72. #define MPTB	(0x18 + MMU_REG_BASE)	/* MMU Page Table Base Register */
    73. 

  73. #define MSVA	(0x20 + MMU_REG_BASE)	/* MMU Search Virtual Address
    74. 

  74. 					   Register */
    75. 

  75. #define MTOP	(0x24 + MMU_REG_BASE)	/* MMU TLB Operation Register */
    76. 

  76. #define MIDXI	(0x28 + MMU_REG_BASE)	/* MMU Index Register for
    77. 

  77. 					   Instruciton */
    78. 

  78. #define MIDXD	(0x2c + MMU_REG_BASE)	/* MMU Index Register for Operand */
    79. 

  79. 

  80. #define MATM_offset	(MATM - MMU_REG_BASE)
    81. 

  81. #define MPSZ_offset	(MPSZ - MMU_REG_BASE)
    82. 

  82. #define MASID_offset	(MASID - MMU_REG_BASE)
    83. 

  83. #define MESTS_offset	(MESTS - MMU_REG_BASE)
    84. 

  84. #define MDEVA_offset	(MDEVA - MMU_REG_BASE)
    85. 

  85. #define MDEVP_offset	(MDEVP - MMU_REG_BASE)
    86. 

  86. #define MPTB_offset	(MPTB - MMU_REG_BASE)
    87. 

  87. #define MSVA_offset	(MSVA - MMU_REG_BASE)
    88. 

  88. #define MTOP_offset	(MTOP - MMU_REG_BASE)
    89. 

  89. #define MIDXI_offset	(MIDXI - MMU_REG_BASE)
    90. 

  90. #define MIDXD_offset	(MIDXD - MMU_REG_BASE)
    91. 

  91. 

  92. #define MESTS_IT	(1 << 0)	/* Instruction TLB miss */
    93. 

  93. #define MESTS_IA	(1 << 1)	/* Instruction Access Exception */
    94. 

  94. #define MESTS_DT	(1 << 4)	/* Operand TLB miss */
    95. 

  95. #define MESTS_DA	(1 << 5)	/* Operand Access Exception */
    96. 

  96. #define MESTS_DRW	(1 << 6)	/* Operand Write Exception Flag */
    97. 

  97. 

  98. /*
    99. 

  99.  * PSW (Processor Status Word)
    100. 

  100.  */
    101. 

  101. 

  102. /* PSW bit */
    103. 

  103. #define M32R_PSW_BIT_SM   (7)    /* Stack Mode */
    104. 

  104. #define M32R_PSW_BIT_IE   (6)    /* Interrupt Enable */
    105. 

  105. #define M32R_PSW_BIT_PM   (3)    /* Processor Mode [0:Supervisor,1:User] */
    106. 

  106. #define M32R_PSW_BIT_C    (0)    /* Condition */
    107. 

  107. #define M32R_PSW_BIT_BSM  (7+8)  /* Backup Stack Mode */
    108. 

  108. #define M32R_PSW_BIT_BIE  (6+8)  /* Backup Interrupt Enable */
    109. 

  109. #define M32R_PSW_BIT_BPM  (3+8)  /* Backup Processor Mode */
    110. 

  110. #define M32R_PSW_BIT_BC   (0+8)  /* Backup Condition */
    111. 

  111. 

  112. /* PSW bit map */
    113. 

  113. #define M32R_PSW_SM   (1UL<< M32R_PSW_BIT_SM)   /* Stack Mode */
    114. 

  114. #define M32R_PSW_IE   (1UL<< M32R_PSW_BIT_IE)   /* Interrupt Enable */
    115. 

  115. #define M32R_PSW_PM   (1UL<< M32R_PSW_BIT_PM)   /* Processor Mode */
    116. 

  116. #define M32R_PSW_C    (1UL<< M32R_PSW_BIT_C)    /* Condition */
    117. 

  117. #define M32R_PSW_BSM  (1UL<< M32R_PSW_BIT_BSM)  /* Backup Stack Mode */
    118. 

  118. #define M32R_PSW_BIE  (1UL<< M32R_PSW_BIT_BIE)  /* Backup Interrupt Enable */
    119. 

  119. #define M32R_PSW_BPM  (1UL<< M32R_PSW_BIT_BPM)  /* Backup Processor Mode */
    120. 

  120. #define M32R_PSW_BC   (1UL<< M32R_PSW_BIT_BC)   /* Backup Condition */
    121. 

  121. 

  122. /*
    123. 

  123.  * Direct address to SFR
    124. 

  124.  */
    125. 

  125. 

  126. #include <asm/page.h>
    127. 

  127. #ifdef CONFIG_MMU
    128. 

  128. #define NONCACHE_OFFSET  (__PAGE_OFFSET + 0x20000000)
    129. 

  129. #else
    130. 

  130. #define NONCACHE_OFFSET  __PAGE_OFFSET
    131. 

  131. #endif /* CONFIG_MMU */
    132. 

  132. 

  133. #define M32R_ICU_ISTS_ADDR  M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET
    134. 

  134. #define M32R_ICU_IPICR_ADDR  M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET
    135. 

  135. #define M32R_ICU_IMASK_ADDR  M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET
    136. 

  136. #define M32R_FPGA_CPU_NAME_ADDR  M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET
    137. 

  137. #define M32R_FPGA_MODEL_ID_ADDR  M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET
    138. 

  138. #define M32R_FPGA_VERSION_ADDR   M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET
    139. 

  139. 

  140. #endif /* _ASM_M32R_M32R_H_ */
    141.