tlb_uv.c 21 KB

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  1. /*
  2. * SGI UltraViolet TLB flush routines.
  3. *
  4. * (c) 2008 Cliff Wickman <cpw@sgi.com>, SGI.
  5. *
  6. * This code is released under the GNU General Public License version 2 or
  7. * later.
  8. */
  9. #include <linux/seq_file.h>
  10. #include <linux/proc_fs.h>
  11. #include <linux/kernel.h>
  12. #include <asm/mmu_context.h>
  13. #include <asm/uv/uv.h>
  14. #include <asm/uv/uv_mmrs.h>
  15. #include <asm/uv/uv_hub.h>
  16. #include <asm/uv/uv_bau.h>
  17. #include <asm/genapic.h>
  18. #include <asm/idle.h>
  19. #include <asm/tsc.h>
  20. #include <asm/irq_vectors.h>
  21. #include <mach_apic.h>
  22. static struct bau_control **uv_bau_table_bases __read_mostly;
  23. static int uv_bau_retry_limit __read_mostly;
  24. /* position of pnode (which is nasid>>1): */
  25. static int uv_nshift __read_mostly;
  26. static unsigned long uv_mmask __read_mostly;
  27. static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
  28. static DEFINE_PER_CPU(struct bau_control, bau_control);
  29. /*
  30. * Free a software acknowledge hardware resource by clearing its Pending
  31. * bit. This will return a reply to the sender.
  32. * If the message has timed out, a reply has already been sent by the
  33. * hardware but the resource has not been released. In that case our
  34. * clear of the Timeout bit (as well) will free the resource. No reply will
  35. * be sent (the hardware will only do one reply per message).
  36. */
  37. static void uv_reply_to_message(int resource,
  38. struct bau_payload_queue_entry *msg,
  39. struct bau_msg_status *msp)
  40. {
  41. unsigned long dw;
  42. dw = (1 << (resource + UV_SW_ACK_NPENDING)) | (1 << resource);
  43. msg->replied_to = 1;
  44. msg->sw_ack_vector = 0;
  45. if (msp)
  46. msp->seen_by.bits = 0;
  47. uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
  48. }
  49. /*
  50. * Do all the things a cpu should do for a TLB shootdown message.
  51. * Other cpu's may come here at the same time for this message.
  52. */
  53. static void uv_bau_process_message(struct bau_payload_queue_entry *msg,
  54. int msg_slot, int sw_ack_slot)
  55. {
  56. unsigned long this_cpu_mask;
  57. struct bau_msg_status *msp;
  58. int cpu;
  59. msp = __get_cpu_var(bau_control).msg_statuses + msg_slot;
  60. cpu = uv_blade_processor_id();
  61. msg->number_of_cpus =
  62. uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id()));
  63. this_cpu_mask = 1UL << cpu;
  64. if (msp->seen_by.bits & this_cpu_mask)
  65. return;
  66. atomic_or_long(&msp->seen_by.bits, this_cpu_mask);
  67. if (msg->replied_to == 1)
  68. return;
  69. if (msg->address == TLB_FLUSH_ALL) {
  70. local_flush_tlb();
  71. __get_cpu_var(ptcstats).alltlb++;
  72. } else {
  73. __flush_tlb_one(msg->address);
  74. __get_cpu_var(ptcstats).onetlb++;
  75. }
  76. __get_cpu_var(ptcstats).requestee++;
  77. atomic_inc_short(&msg->acknowledge_count);
  78. if (msg->number_of_cpus == msg->acknowledge_count)
  79. uv_reply_to_message(sw_ack_slot, msg, msp);
  80. }
  81. /*
  82. * Examine the payload queue on one distribution node to see
  83. * which messages have not been seen, and which cpu(s) have not seen them.
  84. *
  85. * Returns the number of cpu's that have not responded.
  86. */
  87. static int uv_examine_destination(struct bau_control *bau_tablesp, int sender)
  88. {
  89. struct bau_payload_queue_entry *msg;
  90. struct bau_msg_status *msp;
  91. int count = 0;
  92. int i;
  93. int j;
  94. for (msg = bau_tablesp->va_queue_first, i = 0; i < DEST_Q_SIZE;
  95. msg++, i++) {
  96. if ((msg->sending_cpu == sender) && (!msg->replied_to)) {
  97. msp = bau_tablesp->msg_statuses + i;
  98. printk(KERN_DEBUG
  99. "blade %d: address:%#lx %d of %d, not cpu(s): ",
  100. i, msg->address, msg->acknowledge_count,
  101. msg->number_of_cpus);
  102. for (j = 0; j < msg->number_of_cpus; j++) {
  103. if (!((1L << j) & msp->seen_by.bits)) {
  104. count++;
  105. printk("%d ", j);
  106. }
  107. }
  108. printk("\n");
  109. }
  110. }
  111. return count;
  112. }
  113. /*
  114. * Examine the payload queue on all the distribution nodes to see
  115. * which messages have not been seen, and which cpu(s) have not seen them.
  116. *
  117. * Returns the number of cpu's that have not responded.
  118. */
  119. static int uv_examine_destinations(struct bau_target_nodemask *distribution)
  120. {
  121. int sender;
  122. int i;
  123. int count = 0;
  124. sender = smp_processor_id();
  125. for (i = 0; i < sizeof(struct bau_target_nodemask) * BITSPERBYTE; i++) {
  126. if (!bau_node_isset(i, distribution))
  127. continue;
  128. count += uv_examine_destination(uv_bau_table_bases[i], sender);
  129. }
  130. return count;
  131. }
  132. /*
  133. * wait for completion of a broadcast message
  134. *
  135. * return COMPLETE, RETRY or GIVEUP
  136. */
  137. static int uv_wait_completion(struct bau_desc *bau_desc,
  138. unsigned long mmr_offset, int right_shift)
  139. {
  140. int exams = 0;
  141. long destination_timeouts = 0;
  142. long source_timeouts = 0;
  143. unsigned long descriptor_status;
  144. while ((descriptor_status = (((unsigned long)
  145. uv_read_local_mmr(mmr_offset) >>
  146. right_shift) & UV_ACT_STATUS_MASK)) !=
  147. DESC_STATUS_IDLE) {
  148. if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) {
  149. source_timeouts++;
  150. if (source_timeouts > SOURCE_TIMEOUT_LIMIT)
  151. source_timeouts = 0;
  152. __get_cpu_var(ptcstats).s_retry++;
  153. return FLUSH_RETRY;
  154. }
  155. /*
  156. * spin here looking for progress at the destinations
  157. */
  158. if (descriptor_status == DESC_STATUS_DESTINATION_TIMEOUT) {
  159. destination_timeouts++;
  160. if (destination_timeouts > DESTINATION_TIMEOUT_LIMIT) {
  161. /*
  162. * returns number of cpus not responding
  163. */
  164. if (uv_examine_destinations
  165. (&bau_desc->distribution) == 0) {
  166. __get_cpu_var(ptcstats).d_retry++;
  167. return FLUSH_RETRY;
  168. }
  169. exams++;
  170. if (exams >= uv_bau_retry_limit) {
  171. printk(KERN_DEBUG
  172. "uv_flush_tlb_others");
  173. printk("giving up on cpu %d\n",
  174. smp_processor_id());
  175. return FLUSH_GIVEUP;
  176. }
  177. /*
  178. * delays can hang the simulator
  179. udelay(1000);
  180. */
  181. destination_timeouts = 0;
  182. }
  183. }
  184. }
  185. return FLUSH_COMPLETE;
  186. }
  187. /**
  188. * uv_flush_send_and_wait
  189. *
  190. * Send a broadcast and wait for a broadcast message to complete.
  191. *
  192. * The flush_mask contains the cpus the broadcast was sent to.
  193. *
  194. * Returns NULL if all remote flushing was done. The mask is zeroed.
  195. * Returns @flush_mask if some remote flushing remains to be done. The
  196. * mask will have some bits still set.
  197. */
  198. const struct cpumask *uv_flush_send_and_wait(int cpu, int this_blade,
  199. struct bau_desc *bau_desc,
  200. struct cpumask *flush_mask)
  201. {
  202. int completion_status = 0;
  203. int right_shift;
  204. int tries = 0;
  205. int blade;
  206. int bit;
  207. unsigned long mmr_offset;
  208. unsigned long index;
  209. cycles_t time1;
  210. cycles_t time2;
  211. if (cpu < UV_CPUS_PER_ACT_STATUS) {
  212. mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
  213. right_shift = cpu * UV_ACT_STATUS_SIZE;
  214. } else {
  215. mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
  216. right_shift =
  217. ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
  218. }
  219. time1 = get_cycles();
  220. do {
  221. tries++;
  222. index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) |
  223. cpu;
  224. uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
  225. completion_status = uv_wait_completion(bau_desc, mmr_offset,
  226. right_shift);
  227. } while (completion_status == FLUSH_RETRY);
  228. time2 = get_cycles();
  229. __get_cpu_var(ptcstats).sflush += (time2 - time1);
  230. if (tries > 1)
  231. __get_cpu_var(ptcstats).retriesok++;
  232. if (completion_status == FLUSH_GIVEUP) {
  233. /*
  234. * Cause the caller to do an IPI-style TLB shootdown on
  235. * the cpu's, all of which are still in the mask.
  236. */
  237. __get_cpu_var(ptcstats).ptc_i++;
  238. return 0;
  239. }
  240. /*
  241. * Success, so clear the remote cpu's from the mask so we don't
  242. * use the IPI method of shootdown on them.
  243. */
  244. for_each_cpu(bit, flush_mask) {
  245. blade = uv_cpu_to_blade_id(bit);
  246. if (blade == this_blade)
  247. continue;
  248. cpumask_clear_cpu(bit, flush_mask);
  249. }
  250. if (!cpumask_empty(flush_mask))
  251. return flush_mask;
  252. return NULL;
  253. }
  254. /**
  255. * uv_flush_tlb_others - globally purge translation cache of a virtual
  256. * address or all TLB's
  257. * @cpumask: mask of all cpu's in which the address is to be removed
  258. * @mm: mm_struct containing virtual address range
  259. * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
  260. * @cpu: the current cpu
  261. *
  262. * This is the entry point for initiating any UV global TLB shootdown.
  263. *
  264. * Purges the translation caches of all specified processors of the given
  265. * virtual address, or purges all TLB's on specified processors.
  266. *
  267. * The caller has derived the cpumask from the mm_struct. This function
  268. * is called only if there are bits set in the mask. (e.g. flush_tlb_page())
  269. *
  270. * The cpumask is converted into a nodemask of the nodes containing
  271. * the cpus.
  272. *
  273. * Note that this function should be called with preemption disabled.
  274. *
  275. * Returns NULL if all remote flushing was done.
  276. * Returns pointer to cpumask if some remote flushing remains to be
  277. * done. The returned pointer is valid till preemption is re-enabled.
  278. */
  279. const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
  280. struct mm_struct *mm,
  281. unsigned long va, unsigned int cpu)
  282. {
  283. static DEFINE_PER_CPU(cpumask_t, flush_tlb_mask);
  284. struct cpumask *flush_mask = &__get_cpu_var(flush_tlb_mask);
  285. int i;
  286. int bit;
  287. int blade;
  288. int uv_cpu;
  289. int this_blade;
  290. int locals = 0;
  291. struct bau_desc *bau_desc;
  292. WARN_ON(!in_atomic());
  293. cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
  294. uv_cpu = uv_blade_processor_id();
  295. this_blade = uv_numa_blade_id();
  296. bau_desc = __get_cpu_var(bau_control).descriptor_base;
  297. bau_desc += UV_ITEMS_PER_DESCRIPTOR * uv_cpu;
  298. bau_nodes_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
  299. i = 0;
  300. for_each_cpu(bit, flush_mask) {
  301. blade = uv_cpu_to_blade_id(bit);
  302. BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1));
  303. if (blade == this_blade) {
  304. locals++;
  305. continue;
  306. }
  307. bau_node_set(blade, &bau_desc->distribution);
  308. i++;
  309. }
  310. if (i == 0) {
  311. /*
  312. * no off_node flushing; return status for local node
  313. */
  314. if (locals)
  315. return flush_mask;
  316. else
  317. return NULL;
  318. }
  319. __get_cpu_var(ptcstats).requestor++;
  320. __get_cpu_var(ptcstats).ntargeted += i;
  321. bau_desc->payload.address = va;
  322. bau_desc->payload.sending_cpu = cpu;
  323. return uv_flush_send_and_wait(uv_cpu, this_blade, bau_desc, flush_mask);
  324. }
  325. /*
  326. * The BAU message interrupt comes here. (registered by set_intr_gate)
  327. * See entry_64.S
  328. *
  329. * We received a broadcast assist message.
  330. *
  331. * Interrupts may have been disabled; this interrupt could represent
  332. * the receipt of several messages.
  333. *
  334. * All cores/threads on this node get this interrupt.
  335. * The last one to see it does the s/w ack.
  336. * (the resource will not be freed until noninterruptable cpus see this
  337. * interrupt; hardware will timeout the s/w ack and reply ERROR)
  338. */
  339. void uv_bau_message_interrupt(struct pt_regs *regs)
  340. {
  341. struct bau_payload_queue_entry *va_queue_first;
  342. struct bau_payload_queue_entry *va_queue_last;
  343. struct bau_payload_queue_entry *msg;
  344. struct pt_regs *old_regs = set_irq_regs(regs);
  345. cycles_t time1;
  346. cycles_t time2;
  347. int msg_slot;
  348. int sw_ack_slot;
  349. int fw;
  350. int count = 0;
  351. unsigned long local_pnode;
  352. ack_APIC_irq();
  353. exit_idle();
  354. irq_enter();
  355. time1 = get_cycles();
  356. local_pnode = uv_blade_to_pnode(uv_numa_blade_id());
  357. va_queue_first = __get_cpu_var(bau_control).va_queue_first;
  358. va_queue_last = __get_cpu_var(bau_control).va_queue_last;
  359. msg = __get_cpu_var(bau_control).bau_msg_head;
  360. while (msg->sw_ack_vector) {
  361. count++;
  362. fw = msg->sw_ack_vector;
  363. msg_slot = msg - va_queue_first;
  364. sw_ack_slot = ffs(fw) - 1;
  365. uv_bau_process_message(msg, msg_slot, sw_ack_slot);
  366. msg++;
  367. if (msg > va_queue_last)
  368. msg = va_queue_first;
  369. __get_cpu_var(bau_control).bau_msg_head = msg;
  370. }
  371. if (!count)
  372. __get_cpu_var(ptcstats).nomsg++;
  373. else if (count > 1)
  374. __get_cpu_var(ptcstats).multmsg++;
  375. time2 = get_cycles();
  376. __get_cpu_var(ptcstats).dflush += (time2 - time1);
  377. irq_exit();
  378. set_irq_regs(old_regs);
  379. }
  380. static void uv_enable_timeouts(void)
  381. {
  382. int i;
  383. int blade;
  384. int last_blade;
  385. int pnode;
  386. int cur_cpu = 0;
  387. unsigned long apicid;
  388. last_blade = -1;
  389. for_each_online_node(i) {
  390. blade = uv_node_to_blade_id(i);
  391. if (blade == last_blade)
  392. continue;
  393. last_blade = blade;
  394. apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
  395. pnode = uv_blade_to_pnode(blade);
  396. cur_cpu += uv_blade_nr_possible_cpus(i);
  397. }
  398. }
  399. static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset)
  400. {
  401. if (*offset < num_possible_cpus())
  402. return offset;
  403. return NULL;
  404. }
  405. static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
  406. {
  407. (*offset)++;
  408. if (*offset < num_possible_cpus())
  409. return offset;
  410. return NULL;
  411. }
  412. static void uv_ptc_seq_stop(struct seq_file *file, void *data)
  413. {
  414. }
  415. /*
  416. * Display the statistics thru /proc
  417. * data points to the cpu number
  418. */
  419. static int uv_ptc_seq_show(struct seq_file *file, void *data)
  420. {
  421. struct ptc_stats *stat;
  422. int cpu;
  423. cpu = *(loff_t *)data;
  424. if (!cpu) {
  425. seq_printf(file,
  426. "# cpu requestor requestee one all sretry dretry ptc_i ");
  427. seq_printf(file,
  428. "sw_ack sflush dflush sok dnomsg dmult starget\n");
  429. }
  430. if (cpu < num_possible_cpus() && cpu_online(cpu)) {
  431. stat = &per_cpu(ptcstats, cpu);
  432. seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld ",
  433. cpu, stat->requestor,
  434. stat->requestee, stat->onetlb, stat->alltlb,
  435. stat->s_retry, stat->d_retry, stat->ptc_i);
  436. seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n",
  437. uv_read_global_mmr64(uv_blade_to_pnode
  438. (uv_cpu_to_blade_id(cpu)),
  439. UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
  440. stat->sflush, stat->dflush,
  441. stat->retriesok, stat->nomsg,
  442. stat->multmsg, stat->ntargeted);
  443. }
  444. return 0;
  445. }
  446. /*
  447. * 0: display meaning of the statistics
  448. * >0: retry limit
  449. */
  450. static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
  451. size_t count, loff_t *data)
  452. {
  453. long newmode;
  454. char optstr[64];
  455. if (count == 0 || count > sizeof(optstr))
  456. return -EINVAL;
  457. if (copy_from_user(optstr, user, count))
  458. return -EFAULT;
  459. optstr[count - 1] = '\0';
  460. if (strict_strtoul(optstr, 10, &newmode) < 0) {
  461. printk(KERN_DEBUG "%s is invalid\n", optstr);
  462. return -EINVAL;
  463. }
  464. if (newmode == 0) {
  465. printk(KERN_DEBUG "# cpu: cpu number\n");
  466. printk(KERN_DEBUG
  467. "requestor: times this cpu was the flush requestor\n");
  468. printk(KERN_DEBUG
  469. "requestee: times this cpu was requested to flush its TLBs\n");
  470. printk(KERN_DEBUG
  471. "one: times requested to flush a single address\n");
  472. printk(KERN_DEBUG
  473. "all: times requested to flush all TLB's\n");
  474. printk(KERN_DEBUG
  475. "sretry: number of retries of source-side timeouts\n");
  476. printk(KERN_DEBUG
  477. "dretry: number of retries of destination-side timeouts\n");
  478. printk(KERN_DEBUG
  479. "ptc_i: times UV fell through to IPI-style flushes\n");
  480. printk(KERN_DEBUG
  481. "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
  482. printk(KERN_DEBUG
  483. "sflush_us: cycles spent in uv_flush_tlb_others()\n");
  484. printk(KERN_DEBUG
  485. "dflush_us: cycles spent in handling flush requests\n");
  486. printk(KERN_DEBUG "sok: successes on retry\n");
  487. printk(KERN_DEBUG "dnomsg: interrupts with no message\n");
  488. printk(KERN_DEBUG
  489. "dmult: interrupts with multiple messages\n");
  490. printk(KERN_DEBUG "starget: nodes targeted\n");
  491. } else {
  492. uv_bau_retry_limit = newmode;
  493. printk(KERN_DEBUG "timeout retry limit:%d\n",
  494. uv_bau_retry_limit);
  495. }
  496. return count;
  497. }
  498. static const struct seq_operations uv_ptc_seq_ops = {
  499. .start = uv_ptc_seq_start,
  500. .next = uv_ptc_seq_next,
  501. .stop = uv_ptc_seq_stop,
  502. .show = uv_ptc_seq_show
  503. };
  504. static int uv_ptc_proc_open(struct inode *inode, struct file *file)
  505. {
  506. return seq_open(file, &uv_ptc_seq_ops);
  507. }
  508. static const struct file_operations proc_uv_ptc_operations = {
  509. .open = uv_ptc_proc_open,
  510. .read = seq_read,
  511. .write = uv_ptc_proc_write,
  512. .llseek = seq_lseek,
  513. .release = seq_release,
  514. };
  515. static int __init uv_ptc_init(void)
  516. {
  517. struct proc_dir_entry *proc_uv_ptc;
  518. if (!is_uv_system())
  519. return 0;
  520. proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL);
  521. if (!proc_uv_ptc) {
  522. printk(KERN_ERR "unable to create %s proc entry\n",
  523. UV_PTC_BASENAME);
  524. return -EINVAL;
  525. }
  526. proc_uv_ptc->proc_fops = &proc_uv_ptc_operations;
  527. return 0;
  528. }
  529. /*
  530. * begin the initialization of the per-blade control structures
  531. */
  532. static struct bau_control * __init uv_table_bases_init(int blade, int node)
  533. {
  534. int i;
  535. struct bau_msg_status *msp;
  536. struct bau_control *bau_tabp;
  537. bau_tabp =
  538. kmalloc_node(sizeof(struct bau_control), GFP_KERNEL, node);
  539. BUG_ON(!bau_tabp);
  540. bau_tabp->msg_statuses =
  541. kmalloc_node(sizeof(struct bau_msg_status) *
  542. DEST_Q_SIZE, GFP_KERNEL, node);
  543. BUG_ON(!bau_tabp->msg_statuses);
  544. for (i = 0, msp = bau_tabp->msg_statuses; i < DEST_Q_SIZE; i++, msp++)
  545. bau_cpubits_clear(&msp->seen_by, (int)
  546. uv_blade_nr_possible_cpus(blade));
  547. uv_bau_table_bases[blade] = bau_tabp;
  548. return bau_tabp;
  549. }
  550. /*
  551. * finish the initialization of the per-blade control structures
  552. */
  553. static void __init
  554. uv_table_bases_finish(int blade, int node, int cur_cpu,
  555. struct bau_control *bau_tablesp,
  556. struct bau_desc *adp)
  557. {
  558. struct bau_control *bcp;
  559. int i;
  560. for (i = cur_cpu; i < cur_cpu + uv_blade_nr_possible_cpus(blade); i++) {
  561. bcp = (struct bau_control *)&per_cpu(bau_control, i);
  562. bcp->bau_msg_head = bau_tablesp->va_queue_first;
  563. bcp->va_queue_first = bau_tablesp->va_queue_first;
  564. bcp->va_queue_last = bau_tablesp->va_queue_last;
  565. bcp->msg_statuses = bau_tablesp->msg_statuses;
  566. bcp->descriptor_base = adp;
  567. }
  568. }
  569. /*
  570. * initialize the sending side's sending buffers
  571. */
  572. static struct bau_desc * __init
  573. uv_activation_descriptor_init(int node, int pnode)
  574. {
  575. int i;
  576. unsigned long pa;
  577. unsigned long m;
  578. unsigned long n;
  579. unsigned long mmr_image;
  580. struct bau_desc *adp;
  581. struct bau_desc *ad2;
  582. adp = (struct bau_desc *)
  583. kmalloc_node(16384, GFP_KERNEL, node);
  584. BUG_ON(!adp);
  585. pa = __pa((unsigned long)adp);
  586. n = pa >> uv_nshift;
  587. m = pa & uv_mmask;
  588. mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE);
  589. if (mmr_image) {
  590. uv_write_global_mmr64(pnode, (unsigned long)
  591. UVH_LB_BAU_SB_DESCRIPTOR_BASE,
  592. (n << UV_DESC_BASE_PNODE_SHIFT | m));
  593. }
  594. for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) {
  595. memset(ad2, 0, sizeof(struct bau_desc));
  596. ad2->header.sw_ack_flag = 1;
  597. ad2->header.base_dest_nodeid =
  598. uv_blade_to_pnode(uv_cpu_to_blade_id(0));
  599. ad2->header.command = UV_NET_ENDPOINT_INTD;
  600. ad2->header.int_both = 1;
  601. /*
  602. * all others need to be set to zero:
  603. * fairness chaining multilevel count replied_to
  604. */
  605. }
  606. return adp;
  607. }
  608. /*
  609. * initialize the destination side's receiving buffers
  610. */
  611. static struct bau_payload_queue_entry * __init
  612. uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp)
  613. {
  614. struct bau_payload_queue_entry *pqp;
  615. char *cp;
  616. pqp = (struct bau_payload_queue_entry *) kmalloc_node(
  617. (DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry),
  618. GFP_KERNEL, node);
  619. BUG_ON(!pqp);
  620. cp = (char *)pqp + 31;
  621. pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
  622. bau_tablesp->va_queue_first = pqp;
  623. uv_write_global_mmr64(pnode,
  624. UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
  625. ((unsigned long)pnode <<
  626. UV_PAYLOADQ_PNODE_SHIFT) |
  627. uv_physnodeaddr(pqp));
  628. uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
  629. uv_physnodeaddr(pqp));
  630. bau_tablesp->va_queue_last = pqp + (DEST_Q_SIZE - 1);
  631. uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
  632. (unsigned long)
  633. uv_physnodeaddr(bau_tablesp->va_queue_last));
  634. memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE);
  635. return pqp;
  636. }
  637. /*
  638. * Initialization of each UV blade's structures
  639. */
  640. static int __init uv_init_blade(int blade, int node, int cur_cpu)
  641. {
  642. int pnode;
  643. unsigned long pa;
  644. unsigned long apicid;
  645. struct bau_desc *adp;
  646. struct bau_payload_queue_entry *pqp;
  647. struct bau_control *bau_tablesp;
  648. bau_tablesp = uv_table_bases_init(blade, node);
  649. pnode = uv_blade_to_pnode(blade);
  650. adp = uv_activation_descriptor_init(node, pnode);
  651. pqp = uv_payload_queue_init(node, pnode, bau_tablesp);
  652. uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp);
  653. /*
  654. * the below initialization can't be in firmware because the
  655. * messaging IRQ will be determined by the OS
  656. */
  657. apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
  658. pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG);
  659. if ((pa & 0xff) != UV_BAU_MESSAGE) {
  660. uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
  661. ((apicid << 32) | UV_BAU_MESSAGE));
  662. }
  663. return 0;
  664. }
  665. /*
  666. * Initialization of BAU-related structures
  667. */
  668. static int __init uv_bau_init(void)
  669. {
  670. int blade;
  671. int node;
  672. int nblades;
  673. int last_blade;
  674. int cur_cpu = 0;
  675. if (!is_uv_system())
  676. return 0;
  677. uv_bau_retry_limit = 1;
  678. uv_nshift = uv_hub_info->n_val;
  679. uv_mmask = (1UL << uv_hub_info->n_val) - 1;
  680. nblades = 0;
  681. last_blade = -1;
  682. for_each_online_node(node) {
  683. blade = uv_node_to_blade_id(node);
  684. if (blade == last_blade)
  685. continue;
  686. last_blade = blade;
  687. nblades++;
  688. }
  689. uv_bau_table_bases = (struct bau_control **)
  690. kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL);
  691. BUG_ON(!uv_bau_table_bases);
  692. last_blade = -1;
  693. for_each_online_node(node) {
  694. blade = uv_node_to_blade_id(node);
  695. if (blade == last_blade)
  696. continue;
  697. last_blade = blade;
  698. uv_init_blade(blade, node, cur_cpu);
  699. cur_cpu += uv_blade_nr_possible_cpus(blade);
  700. }
  701. alloc_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);
  702. uv_enable_timeouts();
  703. return 0;
  704. }
  705. __initcall(uv_bau_init);
  706. __initcall(uv_ptc_init);