at91sam9263.dtsi 7.0 KB

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  1. /*
  2. * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
  3. *
  4. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5. *
  6. * Licensed under GPLv2 only.
  7. */
  8. /include/ "skeleton.dtsi"
  9. / {
  10. model = "Atmel AT91SAM9263 family SoC";
  11. compatible = "atmel,at91sam9263";
  12. interrupt-parent = <&aic>;
  13. aliases {
  14. serial0 = &dbgu;
  15. serial1 = &usart0;
  16. serial2 = &usart1;
  17. serial3 = &usart2;
  18. gpio0 = &pioA;
  19. gpio1 = &pioB;
  20. gpio2 = &pioC;
  21. gpio3 = &pioD;
  22. gpio4 = &pioE;
  23. tcb0 = &tcb0;
  24. i2c0 = &i2c0;
  25. };
  26. cpus {
  27. cpu@0 {
  28. compatible = "arm,arm926ejs";
  29. };
  30. };
  31. memory {
  32. reg = <0x20000000 0x08000000>;
  33. };
  34. ahb {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. ranges;
  39. apb {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges;
  44. aic: interrupt-controller@fffff000 {
  45. #interrupt-cells = <3>;
  46. compatible = "atmel,at91rm9200-aic";
  47. interrupt-controller;
  48. reg = <0xfffff000 0x200>;
  49. atmel,external-irqs = <30 31>;
  50. };
  51. pmc: pmc@fffffc00 {
  52. compatible = "atmel,at91rm9200-pmc";
  53. reg = <0xfffffc00 0x100>;
  54. };
  55. ramc: ramc@ffffe200 {
  56. compatible = "atmel,at91sam9260-sdramc";
  57. reg = <0xffffe200 0x200
  58. 0xffffe800 0x200>;
  59. };
  60. pit: timer@fffffd30 {
  61. compatible = "atmel,at91sam9260-pit";
  62. reg = <0xfffffd30 0xf>;
  63. interrupts = <1 4 7>;
  64. };
  65. tcb0: timer@fff7c000 {
  66. compatible = "atmel,at91rm9200-tcb";
  67. reg = <0xfff7c000 0x100>;
  68. interrupts = <19 4 0>;
  69. };
  70. rstc@fffffd00 {
  71. compatible = "atmel,at91sam9260-rstc";
  72. reg = <0xfffffd00 0x10>;
  73. };
  74. shdwc@fffffd10 {
  75. compatible = "atmel,at91sam9260-shdwc";
  76. reg = <0xfffffd10 0x10>;
  77. };
  78. pinctrl@fffff200 {
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  82. ranges = <0xfffff200 0xfffff200 0xa00>;
  83. atmel,mux-mask = <
  84. /* A B */
  85. 0xfffffffb 0xffffe07f /* pioA */
  86. 0x0007ffff 0x39072fff /* pioB */
  87. 0xffffffff 0x3ffffff8 /* pioC */
  88. 0xfffffbff 0xffffffff /* pioD */
  89. 0xffe00fff 0xfbfcff00 /* pioE */
  90. >;
  91. /* shared pinctrl settings */
  92. dbgu {
  93. pinctrl_dbgu: dbgu-0 {
  94. atmel,pins =
  95. <2 30 0x1 0x0 /* PC30 periph A */
  96. 2 31 0x1 0x1>; /* PC31 periph with pullup */
  97. };
  98. };
  99. uart0 {
  100. pinctrl_uart0: uart0-0 {
  101. atmel,pins =
  102. <0 26 0x1 0x1 /* PA26 periph A with pullup */
  103. 0 27 0x1 0x0>; /* PA27 periph A */
  104. };
  105. pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  106. atmel,pins =
  107. <0 28 0x1 0x0 /* PA28 periph A */
  108. 0 29 0x1 0x0>; /* PA29 periph A */
  109. };
  110. };
  111. uart1 {
  112. pinctrl_uart1: uart1-0 {
  113. atmel,pins =
  114. <3 0 0x1 0x1 /* PD0 periph A with pullup */
  115. 3 1 0x1 0x0>; /* PD1 periph A */
  116. };
  117. pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
  118. atmel,pins =
  119. <3 7 0x2 0x0 /* PD7 periph B */
  120. 3 8 0x2 0x0>; /* PD8 periph B */
  121. };
  122. };
  123. uart2 {
  124. pinctrl_uart2: uart2-0 {
  125. atmel,pins =
  126. <3 2 0x1 0x1 /* PD2 periph A with pullup */
  127. 3 3 0x1 0x0>; /* PD3 periph A */
  128. };
  129. pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  130. atmel,pins =
  131. <3 5 0x2 0x0 /* PD5 periph B */
  132. 4 6 0x2 0x0>; /* PD6 periph B */
  133. };
  134. };
  135. nand {
  136. pinctrl_nand: nand-0 {
  137. atmel,pins =
  138. <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
  139. 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
  140. };
  141. };
  142. pioA: gpio@fffff200 {
  143. compatible = "atmel,at91rm9200-gpio";
  144. reg = <0xfffff200 0x200>;
  145. interrupts = <2 4 1>;
  146. #gpio-cells = <2>;
  147. gpio-controller;
  148. interrupt-controller;
  149. #interrupt-cells = <2>;
  150. };
  151. pioB: gpio@fffff400 {
  152. compatible = "atmel,at91rm9200-gpio";
  153. reg = <0xfffff400 0x200>;
  154. interrupts = <3 4 1>;
  155. #gpio-cells = <2>;
  156. gpio-controller;
  157. interrupt-controller;
  158. #interrupt-cells = <2>;
  159. };
  160. pioC: gpio@fffff600 {
  161. compatible = "atmel,at91rm9200-gpio";
  162. reg = <0xfffff600 0x200>;
  163. interrupts = <4 4 1>;
  164. #gpio-cells = <2>;
  165. gpio-controller;
  166. interrupt-controller;
  167. #interrupt-cells = <2>;
  168. };
  169. pioD: gpio@fffff800 {
  170. compatible = "atmel,at91rm9200-gpio";
  171. reg = <0xfffff800 0x200>;
  172. interrupts = <4 4 1>;
  173. #gpio-cells = <2>;
  174. gpio-controller;
  175. interrupt-controller;
  176. #interrupt-cells = <2>;
  177. };
  178. pioE: gpio@fffffa00 {
  179. compatible = "atmel,at91rm9200-gpio";
  180. reg = <0xfffffa00 0x200>;
  181. interrupts = <4 4 1>;
  182. #gpio-cells = <2>;
  183. gpio-controller;
  184. interrupt-controller;
  185. #interrupt-cells = <2>;
  186. };
  187. };
  188. dbgu: serial@ffffee00 {
  189. compatible = "atmel,at91sam9260-usart";
  190. reg = <0xffffee00 0x200>;
  191. interrupts = <1 4 7>;
  192. pinctrl-names = "default";
  193. pinctrl-0 = <&pinctrl_dbgu>;
  194. status = "disabled";
  195. };
  196. usart0: serial@fff8c000 {
  197. compatible = "atmel,at91sam9260-usart";
  198. reg = <0xfff8c000 0x200>;
  199. interrupts = <7 4 5>;
  200. atmel,use-dma-rx;
  201. atmel,use-dma-tx;
  202. pinctrl-names = "default";
  203. pinctrl-0 = <&pinctrl_uart0>;
  204. status = "disabled";
  205. };
  206. usart1: serial@fff90000 {
  207. compatible = "atmel,at91sam9260-usart";
  208. reg = <0xfff90000 0x200>;
  209. interrupts = <8 4 5>;
  210. atmel,use-dma-rx;
  211. atmel,use-dma-tx;
  212. pinctrl-names = "default";
  213. pinctrl-0 = <&pinctrl_uart1>;
  214. status = "disabled";
  215. };
  216. usart2: serial@fff94000 {
  217. compatible = "atmel,at91sam9260-usart";
  218. reg = <0xfff94000 0x200>;
  219. interrupts = <9 4 5>;
  220. atmel,use-dma-rx;
  221. atmel,use-dma-tx;
  222. pinctrl-names = "default";
  223. pinctrl-0 = <&pinctrl_uart2>;
  224. status = "disabled";
  225. };
  226. macb0: ethernet@fffbc000 {
  227. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  228. reg = <0xfffbc000 0x100>;
  229. interrupts = <21 4 3>;
  230. status = "disabled";
  231. };
  232. usb1: gadget@fff78000 {
  233. compatible = "atmel,at91rm9200-udc";
  234. reg = <0xfff78000 0x4000>;
  235. interrupts = <24 4 2>;
  236. status = "disabled";
  237. };
  238. i2c0: i2c@fff88000 {
  239. compatible = "atmel,at91sam9263-i2c";
  240. reg = <0xfff88000 0x100>;
  241. interrupts = <13 4 6>;
  242. #address-cells = <1>;
  243. #size-cells = <0>;
  244. status = "disabled";
  245. };
  246. };
  247. nand0: nand@40000000 {
  248. compatible = "atmel,at91rm9200-nand";
  249. #address-cells = <1>;
  250. #size-cells = <1>;
  251. reg = <0x40000000 0x10000000
  252. 0xffffe000 0x200
  253. >;
  254. atmel,nand-addr-offset = <21>;
  255. atmel,nand-cmd-offset = <22>;
  256. pinctrl-names = "default";
  257. pinctrl-0 = <&pinctrl_nand>;
  258. gpios = <&pioA 22 0
  259. &pioD 15 0
  260. 0
  261. >;
  262. status = "disabled";
  263. };
  264. usb0: ohci@00a00000 {
  265. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  266. reg = <0x00a00000 0x100000>;
  267. interrupts = <29 4 2>;
  268. status = "disabled";
  269. };
  270. };
  271. i2c@0 {
  272. compatible = "i2c-gpio";
  273. gpios = <&pioB 4 0 /* sda */
  274. &pioB 5 0 /* scl */
  275. >;
  276. i2c-gpio,sda-open-drain;
  277. i2c-gpio,scl-open-drain;
  278. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. status = "disabled";
  282. };
  283. };