dmaengine.c 30 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47. #include <linux/dma-mapping.h>
  48. #include <linux/init.h>
  49. #include <linux/module.h>
  50. #include <linux/mm.h>
  51. #include <linux/device.h>
  52. #include <linux/dmaengine.h>
  53. #include <linux/hardirq.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/percpu.h>
  56. #include <linux/rcupdate.h>
  57. #include <linux/mutex.h>
  58. #include <linux/jiffies.h>
  59. #include <linux/rculist.h>
  60. #include <linux/idr.h>
  61. #include <linux/slab.h>
  62. #include <linux/acpi.h>
  63. #include <linux/acpi_dma.h>
  64. #include <linux/of_dma.h>
  65. static DEFINE_MUTEX(dma_list_mutex);
  66. static DEFINE_IDR(dma_idr);
  67. static LIST_HEAD(dma_device_list);
  68. static long dmaengine_ref_count;
  69. /* --- sysfs implementation --- */
  70. /**
  71. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  72. * @dev - device node
  73. *
  74. * Must be called under dma_list_mutex
  75. */
  76. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  77. {
  78. struct dma_chan_dev *chan_dev;
  79. chan_dev = container_of(dev, typeof(*chan_dev), device);
  80. return chan_dev->chan;
  81. }
  82. static ssize_t memcpy_count_show(struct device *dev,
  83. struct device_attribute *attr, char *buf)
  84. {
  85. struct dma_chan *chan;
  86. unsigned long count = 0;
  87. int i;
  88. int err;
  89. mutex_lock(&dma_list_mutex);
  90. chan = dev_to_dma_chan(dev);
  91. if (chan) {
  92. for_each_possible_cpu(i)
  93. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  94. err = sprintf(buf, "%lu\n", count);
  95. } else
  96. err = -ENODEV;
  97. mutex_unlock(&dma_list_mutex);
  98. return err;
  99. }
  100. static DEVICE_ATTR_RO(memcpy_count);
  101. static ssize_t bytes_transferred_show(struct device *dev,
  102. struct device_attribute *attr, char *buf)
  103. {
  104. struct dma_chan *chan;
  105. unsigned long count = 0;
  106. int i;
  107. int err;
  108. mutex_lock(&dma_list_mutex);
  109. chan = dev_to_dma_chan(dev);
  110. if (chan) {
  111. for_each_possible_cpu(i)
  112. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  113. err = sprintf(buf, "%lu\n", count);
  114. } else
  115. err = -ENODEV;
  116. mutex_unlock(&dma_list_mutex);
  117. return err;
  118. }
  119. static DEVICE_ATTR_RO(bytes_transferred);
  120. static ssize_t in_use_show(struct device *dev, struct device_attribute *attr,
  121. char *buf)
  122. {
  123. struct dma_chan *chan;
  124. int err;
  125. mutex_lock(&dma_list_mutex);
  126. chan = dev_to_dma_chan(dev);
  127. if (chan)
  128. err = sprintf(buf, "%d\n", chan->client_count);
  129. else
  130. err = -ENODEV;
  131. mutex_unlock(&dma_list_mutex);
  132. return err;
  133. }
  134. static DEVICE_ATTR_RO(in_use);
  135. static struct attribute *dma_dev_attrs[] = {
  136. &dev_attr_memcpy_count.attr,
  137. &dev_attr_bytes_transferred.attr,
  138. &dev_attr_in_use.attr,
  139. NULL,
  140. };
  141. ATTRIBUTE_GROUPS(dma_dev);
  142. static void chan_dev_release(struct device *dev)
  143. {
  144. struct dma_chan_dev *chan_dev;
  145. chan_dev = container_of(dev, typeof(*chan_dev), device);
  146. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  147. mutex_lock(&dma_list_mutex);
  148. idr_remove(&dma_idr, chan_dev->dev_id);
  149. mutex_unlock(&dma_list_mutex);
  150. kfree(chan_dev->idr_ref);
  151. }
  152. kfree(chan_dev);
  153. }
  154. static struct class dma_devclass = {
  155. .name = "dma",
  156. .dev_groups = dma_dev_groups,
  157. .dev_release = chan_dev_release,
  158. };
  159. /* --- client and device registration --- */
  160. #define dma_device_satisfies_mask(device, mask) \
  161. __dma_device_satisfies_mask((device), &(mask))
  162. static int
  163. __dma_device_satisfies_mask(struct dma_device *device,
  164. const dma_cap_mask_t *want)
  165. {
  166. dma_cap_mask_t has;
  167. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  168. DMA_TX_TYPE_END);
  169. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  170. }
  171. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  172. {
  173. return chan->device->dev->driver->owner;
  174. }
  175. /**
  176. * balance_ref_count - catch up the channel reference count
  177. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  178. *
  179. * balance_ref_count must be called under dma_list_mutex
  180. */
  181. static void balance_ref_count(struct dma_chan *chan)
  182. {
  183. struct module *owner = dma_chan_to_owner(chan);
  184. while (chan->client_count < dmaengine_ref_count) {
  185. __module_get(owner);
  186. chan->client_count++;
  187. }
  188. }
  189. /**
  190. * dma_chan_get - try to grab a dma channel's parent driver module
  191. * @chan - channel to grab
  192. *
  193. * Must be called under dma_list_mutex
  194. */
  195. static int dma_chan_get(struct dma_chan *chan)
  196. {
  197. int err = -ENODEV;
  198. struct module *owner = dma_chan_to_owner(chan);
  199. if (chan->client_count) {
  200. __module_get(owner);
  201. err = 0;
  202. } else if (try_module_get(owner))
  203. err = 0;
  204. if (err == 0)
  205. chan->client_count++;
  206. /* allocate upon first client reference */
  207. if (chan->client_count == 1 && err == 0) {
  208. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  209. if (desc_cnt < 0) {
  210. err = desc_cnt;
  211. chan->client_count = 0;
  212. module_put(owner);
  213. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  214. balance_ref_count(chan);
  215. }
  216. return err;
  217. }
  218. /**
  219. * dma_chan_put - drop a reference to a dma channel's parent driver module
  220. * @chan - channel to release
  221. *
  222. * Must be called under dma_list_mutex
  223. */
  224. static void dma_chan_put(struct dma_chan *chan)
  225. {
  226. if (!chan->client_count)
  227. return; /* this channel failed alloc_chan_resources */
  228. chan->client_count--;
  229. module_put(dma_chan_to_owner(chan));
  230. if (chan->client_count == 0)
  231. chan->device->device_free_chan_resources(chan);
  232. }
  233. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  234. {
  235. enum dma_status status;
  236. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  237. dma_async_issue_pending(chan);
  238. do {
  239. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  240. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  241. pr_err("%s: timeout!\n", __func__);
  242. return DMA_ERROR;
  243. }
  244. if (status != DMA_IN_PROGRESS)
  245. break;
  246. cpu_relax();
  247. } while (1);
  248. return status;
  249. }
  250. EXPORT_SYMBOL(dma_sync_wait);
  251. /**
  252. * dma_cap_mask_all - enable iteration over all operation types
  253. */
  254. static dma_cap_mask_t dma_cap_mask_all;
  255. /**
  256. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  257. * @chan - associated channel for this entry
  258. */
  259. struct dma_chan_tbl_ent {
  260. struct dma_chan *chan;
  261. };
  262. /**
  263. * channel_table - percpu lookup table for memory-to-memory offload providers
  264. */
  265. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  266. static int __init dma_channel_table_init(void)
  267. {
  268. enum dma_transaction_type cap;
  269. int err = 0;
  270. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  271. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  272. * but are not associated with an operation so they do not need
  273. * an entry in the channel_table
  274. */
  275. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  276. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  277. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  278. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  279. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  280. if (!channel_table[cap]) {
  281. err = -ENOMEM;
  282. break;
  283. }
  284. }
  285. if (err) {
  286. pr_err("initialization failure\n");
  287. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  288. if (channel_table[cap])
  289. free_percpu(channel_table[cap]);
  290. }
  291. return err;
  292. }
  293. arch_initcall(dma_channel_table_init);
  294. /**
  295. * dma_find_channel - find a channel to carry out the operation
  296. * @tx_type: transaction type
  297. */
  298. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  299. {
  300. return this_cpu_read(channel_table[tx_type]->chan);
  301. }
  302. EXPORT_SYMBOL(dma_find_channel);
  303. /*
  304. * net_dma_find_channel - find a channel for net_dma
  305. * net_dma has alignment requirements
  306. */
  307. struct dma_chan *net_dma_find_channel(void)
  308. {
  309. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  310. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  311. return NULL;
  312. return chan;
  313. }
  314. EXPORT_SYMBOL(net_dma_find_channel);
  315. /**
  316. * dma_issue_pending_all - flush all pending operations across all channels
  317. */
  318. void dma_issue_pending_all(void)
  319. {
  320. struct dma_device *device;
  321. struct dma_chan *chan;
  322. rcu_read_lock();
  323. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  324. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  325. continue;
  326. list_for_each_entry(chan, &device->channels, device_node)
  327. if (chan->client_count)
  328. device->device_issue_pending(chan);
  329. }
  330. rcu_read_unlock();
  331. }
  332. EXPORT_SYMBOL(dma_issue_pending_all);
  333. /**
  334. * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu
  335. */
  336. static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
  337. {
  338. int node = dev_to_node(chan->device->dev);
  339. return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node));
  340. }
  341. /**
  342. * min_chan - returns the channel with min count and in the same numa-node as the cpu
  343. * @cap: capability to match
  344. * @cpu: cpu index which the channel should be close to
  345. *
  346. * If some channels are close to the given cpu, the one with the lowest
  347. * reference count is returned. Otherwise, cpu is ignored and only the
  348. * reference count is taken into account.
  349. * Must be called under dma_list_mutex.
  350. */
  351. static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
  352. {
  353. struct dma_device *device;
  354. struct dma_chan *chan;
  355. struct dma_chan *min = NULL;
  356. struct dma_chan *localmin = NULL;
  357. list_for_each_entry(device, &dma_device_list, global_node) {
  358. if (!dma_has_cap(cap, device->cap_mask) ||
  359. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  360. continue;
  361. list_for_each_entry(chan, &device->channels, device_node) {
  362. if (!chan->client_count)
  363. continue;
  364. if (!min || chan->table_count < min->table_count)
  365. min = chan;
  366. if (dma_chan_is_local(chan, cpu))
  367. if (!localmin ||
  368. chan->table_count < localmin->table_count)
  369. localmin = chan;
  370. }
  371. }
  372. chan = localmin ? localmin : min;
  373. if (chan)
  374. chan->table_count++;
  375. return chan;
  376. }
  377. /**
  378. * dma_channel_rebalance - redistribute the available channels
  379. *
  380. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  381. * operation type) in the SMP case, and operation isolation (avoid
  382. * multi-tasking channels) in the non-SMP case. Must be called under
  383. * dma_list_mutex.
  384. */
  385. static void dma_channel_rebalance(void)
  386. {
  387. struct dma_chan *chan;
  388. struct dma_device *device;
  389. int cpu;
  390. int cap;
  391. /* undo the last distribution */
  392. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  393. for_each_possible_cpu(cpu)
  394. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  395. list_for_each_entry(device, &dma_device_list, global_node) {
  396. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  397. continue;
  398. list_for_each_entry(chan, &device->channels, device_node)
  399. chan->table_count = 0;
  400. }
  401. /* don't populate the channel_table if no clients are available */
  402. if (!dmaengine_ref_count)
  403. return;
  404. /* redistribute available channels */
  405. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  406. for_each_online_cpu(cpu) {
  407. chan = min_chan(cap, cpu);
  408. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  409. }
  410. }
  411. static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
  412. struct dma_device *dev,
  413. dma_filter_fn fn, void *fn_param)
  414. {
  415. struct dma_chan *chan;
  416. if (!__dma_device_satisfies_mask(dev, mask)) {
  417. pr_debug("%s: wrong capabilities\n", __func__);
  418. return NULL;
  419. }
  420. /* devices with multiple channels need special handling as we need to
  421. * ensure that all channels are either private or public.
  422. */
  423. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  424. list_for_each_entry(chan, &dev->channels, device_node) {
  425. /* some channels are already publicly allocated */
  426. if (chan->client_count)
  427. return NULL;
  428. }
  429. list_for_each_entry(chan, &dev->channels, device_node) {
  430. if (chan->client_count) {
  431. pr_debug("%s: %s busy\n",
  432. __func__, dma_chan_name(chan));
  433. continue;
  434. }
  435. if (fn && !fn(chan, fn_param)) {
  436. pr_debug("%s: %s filter said false\n",
  437. __func__, dma_chan_name(chan));
  438. continue;
  439. }
  440. return chan;
  441. }
  442. return NULL;
  443. }
  444. /**
  445. * dma_request_slave_channel - try to get specific channel exclusively
  446. * @chan: target channel
  447. */
  448. struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
  449. {
  450. int err = -EBUSY;
  451. /* lock against __dma_request_channel */
  452. mutex_lock(&dma_list_mutex);
  453. if (chan->client_count == 0) {
  454. err = dma_chan_get(chan);
  455. if (err)
  456. pr_debug("%s: failed to get %s: (%d)\n",
  457. __func__, dma_chan_name(chan), err);
  458. } else
  459. chan = NULL;
  460. mutex_unlock(&dma_list_mutex);
  461. return chan;
  462. }
  463. EXPORT_SYMBOL_GPL(dma_get_slave_channel);
  464. /**
  465. * __dma_request_channel - try to allocate an exclusive channel
  466. * @mask: capabilities that the channel must satisfy
  467. * @fn: optional callback to disposition available channels
  468. * @fn_param: opaque parameter to pass to dma_filter_fn
  469. */
  470. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  471. dma_filter_fn fn, void *fn_param)
  472. {
  473. struct dma_device *device, *_d;
  474. struct dma_chan *chan = NULL;
  475. int err;
  476. /* Find a channel */
  477. mutex_lock(&dma_list_mutex);
  478. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  479. chan = private_candidate(mask, device, fn, fn_param);
  480. if (chan) {
  481. /* Found a suitable channel, try to grab, prep, and
  482. * return it. We first set DMA_PRIVATE to disable
  483. * balance_ref_count as this channel will not be
  484. * published in the general-purpose allocator
  485. */
  486. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  487. device->privatecnt++;
  488. err = dma_chan_get(chan);
  489. if (err == -ENODEV) {
  490. pr_debug("%s: %s module removed\n",
  491. __func__, dma_chan_name(chan));
  492. list_del_rcu(&device->global_node);
  493. } else if (err)
  494. pr_debug("%s: failed to get %s: (%d)\n",
  495. __func__, dma_chan_name(chan), err);
  496. else
  497. break;
  498. if (--device->privatecnt == 0)
  499. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  500. chan = NULL;
  501. }
  502. }
  503. mutex_unlock(&dma_list_mutex);
  504. pr_debug("%s: %s (%s)\n",
  505. __func__,
  506. chan ? "success" : "fail",
  507. chan ? dma_chan_name(chan) : NULL);
  508. return chan;
  509. }
  510. EXPORT_SYMBOL_GPL(__dma_request_channel);
  511. /**
  512. * dma_request_slave_channel - try to allocate an exclusive slave channel
  513. * @dev: pointer to client device structure
  514. * @name: slave channel name
  515. */
  516. struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
  517. {
  518. /* If device-tree is present get slave info from here */
  519. if (dev->of_node)
  520. return of_dma_request_slave_channel(dev->of_node, name);
  521. /* If device was enumerated by ACPI get slave info from here */
  522. if (ACPI_HANDLE(dev))
  523. return acpi_dma_request_slave_chan_by_name(dev, name);
  524. return NULL;
  525. }
  526. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  527. void dma_release_channel(struct dma_chan *chan)
  528. {
  529. mutex_lock(&dma_list_mutex);
  530. WARN_ONCE(chan->client_count != 1,
  531. "chan reference count %d != 1\n", chan->client_count);
  532. dma_chan_put(chan);
  533. /* drop PRIVATE cap enabled by __dma_request_channel() */
  534. if (--chan->device->privatecnt == 0)
  535. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  536. mutex_unlock(&dma_list_mutex);
  537. }
  538. EXPORT_SYMBOL_GPL(dma_release_channel);
  539. /**
  540. * dmaengine_get - register interest in dma_channels
  541. */
  542. void dmaengine_get(void)
  543. {
  544. struct dma_device *device, *_d;
  545. struct dma_chan *chan;
  546. int err;
  547. mutex_lock(&dma_list_mutex);
  548. dmaengine_ref_count++;
  549. /* try to grab channels */
  550. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  551. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  552. continue;
  553. list_for_each_entry(chan, &device->channels, device_node) {
  554. err = dma_chan_get(chan);
  555. if (err == -ENODEV) {
  556. /* module removed before we could use it */
  557. list_del_rcu(&device->global_node);
  558. break;
  559. } else if (err)
  560. pr_debug("%s: failed to get %s: (%d)\n",
  561. __func__, dma_chan_name(chan), err);
  562. }
  563. }
  564. /* if this is the first reference and there were channels
  565. * waiting we need to rebalance to get those channels
  566. * incorporated into the channel table
  567. */
  568. if (dmaengine_ref_count == 1)
  569. dma_channel_rebalance();
  570. mutex_unlock(&dma_list_mutex);
  571. }
  572. EXPORT_SYMBOL(dmaengine_get);
  573. /**
  574. * dmaengine_put - let dma drivers be removed when ref_count == 0
  575. */
  576. void dmaengine_put(void)
  577. {
  578. struct dma_device *device;
  579. struct dma_chan *chan;
  580. mutex_lock(&dma_list_mutex);
  581. dmaengine_ref_count--;
  582. BUG_ON(dmaengine_ref_count < 0);
  583. /* drop channel references */
  584. list_for_each_entry(device, &dma_device_list, global_node) {
  585. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  586. continue;
  587. list_for_each_entry(chan, &device->channels, device_node)
  588. dma_chan_put(chan);
  589. }
  590. mutex_unlock(&dma_list_mutex);
  591. }
  592. EXPORT_SYMBOL(dmaengine_put);
  593. static bool device_has_all_tx_types(struct dma_device *device)
  594. {
  595. /* A device that satisfies this test has channels that will never cause
  596. * an async_tx channel switch event as all possible operation types can
  597. * be handled.
  598. */
  599. #ifdef CONFIG_ASYNC_TX_DMA
  600. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  601. return false;
  602. #endif
  603. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  604. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  605. return false;
  606. #endif
  607. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  608. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  609. return false;
  610. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  611. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  612. return false;
  613. #endif
  614. #endif
  615. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  616. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  617. return false;
  618. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  619. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  620. return false;
  621. #endif
  622. #endif
  623. return true;
  624. }
  625. static int get_dma_id(struct dma_device *device)
  626. {
  627. int rc;
  628. mutex_lock(&dma_list_mutex);
  629. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  630. if (rc >= 0)
  631. device->dev_id = rc;
  632. mutex_unlock(&dma_list_mutex);
  633. return rc < 0 ? rc : 0;
  634. }
  635. /**
  636. * dma_async_device_register - registers DMA devices found
  637. * @device: &dma_device
  638. */
  639. int dma_async_device_register(struct dma_device *device)
  640. {
  641. int chancnt = 0, rc;
  642. struct dma_chan* chan;
  643. atomic_t *idr_ref;
  644. if (!device)
  645. return -ENODEV;
  646. /* validate device routines */
  647. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  648. !device->device_prep_dma_memcpy);
  649. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  650. !device->device_prep_dma_xor);
  651. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  652. !device->device_prep_dma_xor_val);
  653. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  654. !device->device_prep_dma_pq);
  655. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  656. !device->device_prep_dma_pq_val);
  657. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  658. !device->device_prep_dma_interrupt);
  659. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  660. !device->device_prep_dma_sg);
  661. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  662. !device->device_prep_dma_cyclic);
  663. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  664. !device->device_control);
  665. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  666. !device->device_prep_interleaved_dma);
  667. BUG_ON(!device->device_alloc_chan_resources);
  668. BUG_ON(!device->device_free_chan_resources);
  669. BUG_ON(!device->device_tx_status);
  670. BUG_ON(!device->device_issue_pending);
  671. BUG_ON(!device->dev);
  672. /* note: this only matters in the
  673. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  674. */
  675. if (device_has_all_tx_types(device))
  676. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  677. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  678. if (!idr_ref)
  679. return -ENOMEM;
  680. rc = get_dma_id(device);
  681. if (rc != 0) {
  682. kfree(idr_ref);
  683. return rc;
  684. }
  685. atomic_set(idr_ref, 0);
  686. /* represent channels in sysfs. Probably want devs too */
  687. list_for_each_entry(chan, &device->channels, device_node) {
  688. rc = -ENOMEM;
  689. chan->local = alloc_percpu(typeof(*chan->local));
  690. if (chan->local == NULL)
  691. goto err_out;
  692. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  693. if (chan->dev == NULL) {
  694. free_percpu(chan->local);
  695. chan->local = NULL;
  696. goto err_out;
  697. }
  698. chan->chan_id = chancnt++;
  699. chan->dev->device.class = &dma_devclass;
  700. chan->dev->device.parent = device->dev;
  701. chan->dev->chan = chan;
  702. chan->dev->idr_ref = idr_ref;
  703. chan->dev->dev_id = device->dev_id;
  704. atomic_inc(idr_ref);
  705. dev_set_name(&chan->dev->device, "dma%dchan%d",
  706. device->dev_id, chan->chan_id);
  707. rc = device_register(&chan->dev->device);
  708. if (rc) {
  709. free_percpu(chan->local);
  710. chan->local = NULL;
  711. kfree(chan->dev);
  712. atomic_dec(idr_ref);
  713. goto err_out;
  714. }
  715. chan->client_count = 0;
  716. }
  717. device->chancnt = chancnt;
  718. mutex_lock(&dma_list_mutex);
  719. /* take references on public channels */
  720. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  721. list_for_each_entry(chan, &device->channels, device_node) {
  722. /* if clients are already waiting for channels we need
  723. * to take references on their behalf
  724. */
  725. if (dma_chan_get(chan) == -ENODEV) {
  726. /* note we can only get here for the first
  727. * channel as the remaining channels are
  728. * guaranteed to get a reference
  729. */
  730. rc = -ENODEV;
  731. mutex_unlock(&dma_list_mutex);
  732. goto err_out;
  733. }
  734. }
  735. list_add_tail_rcu(&device->global_node, &dma_device_list);
  736. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  737. device->privatecnt++; /* Always private */
  738. dma_channel_rebalance();
  739. mutex_unlock(&dma_list_mutex);
  740. return 0;
  741. err_out:
  742. /* if we never registered a channel just release the idr */
  743. if (atomic_read(idr_ref) == 0) {
  744. mutex_lock(&dma_list_mutex);
  745. idr_remove(&dma_idr, device->dev_id);
  746. mutex_unlock(&dma_list_mutex);
  747. kfree(idr_ref);
  748. return rc;
  749. }
  750. list_for_each_entry(chan, &device->channels, device_node) {
  751. if (chan->local == NULL)
  752. continue;
  753. mutex_lock(&dma_list_mutex);
  754. chan->dev->chan = NULL;
  755. mutex_unlock(&dma_list_mutex);
  756. device_unregister(&chan->dev->device);
  757. free_percpu(chan->local);
  758. }
  759. return rc;
  760. }
  761. EXPORT_SYMBOL(dma_async_device_register);
  762. /**
  763. * dma_async_device_unregister - unregister a DMA device
  764. * @device: &dma_device
  765. *
  766. * This routine is called by dma driver exit routines, dmaengine holds module
  767. * references to prevent it being called while channels are in use.
  768. */
  769. void dma_async_device_unregister(struct dma_device *device)
  770. {
  771. struct dma_chan *chan;
  772. mutex_lock(&dma_list_mutex);
  773. list_del_rcu(&device->global_node);
  774. dma_channel_rebalance();
  775. mutex_unlock(&dma_list_mutex);
  776. list_for_each_entry(chan, &device->channels, device_node) {
  777. WARN_ONCE(chan->client_count,
  778. "%s called while %d clients hold a reference\n",
  779. __func__, chan->client_count);
  780. mutex_lock(&dma_list_mutex);
  781. chan->dev->chan = NULL;
  782. mutex_unlock(&dma_list_mutex);
  783. device_unregister(&chan->dev->device);
  784. free_percpu(chan->local);
  785. }
  786. }
  787. EXPORT_SYMBOL(dma_async_device_unregister);
  788. /**
  789. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  790. * @chan: DMA channel to offload copy to
  791. * @dest: destination address (virtual)
  792. * @src: source address (virtual)
  793. * @len: length
  794. *
  795. * Both @dest and @src must be mappable to a bus address according to the
  796. * DMA mapping API rules for streaming mappings.
  797. * Both @dest and @src must stay memory resident (kernel memory or locked
  798. * user space pages).
  799. */
  800. dma_cookie_t
  801. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  802. void *src, size_t len)
  803. {
  804. struct dma_device *dev = chan->device;
  805. struct dma_async_tx_descriptor *tx;
  806. dma_addr_t dma_dest, dma_src;
  807. dma_cookie_t cookie;
  808. unsigned long flags;
  809. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  810. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  811. flags = DMA_CTRL_ACK |
  812. DMA_COMPL_SRC_UNMAP_SINGLE |
  813. DMA_COMPL_DEST_UNMAP_SINGLE;
  814. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  815. if (!tx) {
  816. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  817. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  818. return -ENOMEM;
  819. }
  820. tx->callback = NULL;
  821. cookie = tx->tx_submit(tx);
  822. preempt_disable();
  823. __this_cpu_add(chan->local->bytes_transferred, len);
  824. __this_cpu_inc(chan->local->memcpy_count);
  825. preempt_enable();
  826. return cookie;
  827. }
  828. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  829. /**
  830. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  831. * @chan: DMA channel to offload copy to
  832. * @page: destination page
  833. * @offset: offset in page to copy to
  834. * @kdata: source address (virtual)
  835. * @len: length
  836. *
  837. * Both @page/@offset and @kdata must be mappable to a bus address according
  838. * to the DMA mapping API rules for streaming mappings.
  839. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  840. * locked user space pages)
  841. */
  842. dma_cookie_t
  843. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  844. unsigned int offset, void *kdata, size_t len)
  845. {
  846. struct dma_device *dev = chan->device;
  847. struct dma_async_tx_descriptor *tx;
  848. dma_addr_t dma_dest, dma_src;
  849. dma_cookie_t cookie;
  850. unsigned long flags;
  851. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  852. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  853. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  854. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  855. if (!tx) {
  856. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  857. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  858. return -ENOMEM;
  859. }
  860. tx->callback = NULL;
  861. cookie = tx->tx_submit(tx);
  862. preempt_disable();
  863. __this_cpu_add(chan->local->bytes_transferred, len);
  864. __this_cpu_inc(chan->local->memcpy_count);
  865. preempt_enable();
  866. return cookie;
  867. }
  868. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  869. /**
  870. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  871. * @chan: DMA channel to offload copy to
  872. * @dest_pg: destination page
  873. * @dest_off: offset in page to copy to
  874. * @src_pg: source page
  875. * @src_off: offset in page to copy from
  876. * @len: length
  877. *
  878. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  879. * address according to the DMA mapping API rules for streaming mappings.
  880. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  881. * (kernel memory or locked user space pages).
  882. */
  883. dma_cookie_t
  884. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  885. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  886. size_t len)
  887. {
  888. struct dma_device *dev = chan->device;
  889. struct dma_async_tx_descriptor *tx;
  890. dma_addr_t dma_dest, dma_src;
  891. dma_cookie_t cookie;
  892. unsigned long flags;
  893. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  894. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  895. DMA_FROM_DEVICE);
  896. flags = DMA_CTRL_ACK;
  897. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  898. if (!tx) {
  899. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  900. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  901. return -ENOMEM;
  902. }
  903. tx->callback = NULL;
  904. cookie = tx->tx_submit(tx);
  905. preempt_disable();
  906. __this_cpu_add(chan->local->bytes_transferred, len);
  907. __this_cpu_inc(chan->local->memcpy_count);
  908. preempt_enable();
  909. return cookie;
  910. }
  911. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  912. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  913. struct dma_chan *chan)
  914. {
  915. tx->chan = chan;
  916. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  917. spin_lock_init(&tx->lock);
  918. #endif
  919. }
  920. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  921. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  922. * @tx: in-flight transaction to wait on
  923. */
  924. enum dma_status
  925. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  926. {
  927. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  928. if (!tx)
  929. return DMA_COMPLETE;
  930. while (tx->cookie == -EBUSY) {
  931. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  932. pr_err("%s timeout waiting for descriptor submission\n",
  933. __func__);
  934. return DMA_ERROR;
  935. }
  936. cpu_relax();
  937. }
  938. return dma_sync_wait(tx->chan, tx->cookie);
  939. }
  940. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  941. /* dma_run_dependencies - helper routine for dma drivers to process
  942. * (start) dependent operations on their target channel
  943. * @tx: transaction with dependencies
  944. */
  945. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  946. {
  947. struct dma_async_tx_descriptor *dep = txd_next(tx);
  948. struct dma_async_tx_descriptor *dep_next;
  949. struct dma_chan *chan;
  950. if (!dep)
  951. return;
  952. /* we'll submit tx->next now, so clear the link */
  953. txd_clear_next(tx);
  954. chan = dep->chan;
  955. /* keep submitting up until a channel switch is detected
  956. * in that case we will be called again as a result of
  957. * processing the interrupt from async_tx_channel_switch
  958. */
  959. for (; dep; dep = dep_next) {
  960. txd_lock(dep);
  961. txd_clear_parent(dep);
  962. dep_next = txd_next(dep);
  963. if (dep_next && dep_next->chan == chan)
  964. txd_clear_next(dep); /* ->next will be submitted */
  965. else
  966. dep_next = NULL; /* submit current dep and terminate */
  967. txd_unlock(dep);
  968. dep->tx_submit(dep);
  969. }
  970. chan->device->device_issue_pending(chan);
  971. }
  972. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  973. static int __init dma_bus_init(void)
  974. {
  975. return class_register(&dma_devclass);
  976. }
  977. arch_initcall(dma_bus_init);