rt61pci.c 75 KB

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  1. /*
  2. Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt61pci
  19. Abstract: rt61pci device specific routines.
  20. Supported chipsets: RT2561, RT2561s, RT2661.
  21. */
  22. /*
  23. * Set enviroment defines for rt2x00.h
  24. */
  25. #define DRV_NAME "rt61pci"
  26. #include <linux/delay.h>
  27. #include <linux/etherdevice.h>
  28. #include <linux/init.h>
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/pci.h>
  32. #include <linux/eeprom_93cx6.h>
  33. #include "rt2x00.h"
  34. #include "rt2x00pci.h"
  35. #include "rt61pci.h"
  36. /*
  37. * Register access.
  38. * BBP and RF register require indirect register access,
  39. * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  40. * These indirect registers work with busy bits,
  41. * and we will try maximal REGISTER_BUSY_COUNT times to access
  42. * the register while taking a REGISTER_BUSY_DELAY us delay
  43. * between each attampt. When the busy bit is still set at that time,
  44. * the access attempt is considered to have failed,
  45. * and we will print an error.
  46. */
  47. static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  48. {
  49. u32 reg;
  50. unsigned int i;
  51. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  52. rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
  53. if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
  54. break;
  55. udelay(REGISTER_BUSY_DELAY);
  56. }
  57. return reg;
  58. }
  59. static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  60. const unsigned int word, const u8 value)
  61. {
  62. u32 reg;
  63. /*
  64. * Wait until the BBP becomes ready.
  65. */
  66. reg = rt61pci_bbp_check(rt2x00dev);
  67. if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  68. ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
  69. return;
  70. }
  71. /*
  72. * Write the data into the BBP.
  73. */
  74. reg = 0;
  75. rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  76. rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  77. rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  78. rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  79. rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  80. }
  81. static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
  82. const unsigned int word, u8 *value)
  83. {
  84. u32 reg;
  85. /*
  86. * Wait until the BBP becomes ready.
  87. */
  88. reg = rt61pci_bbp_check(rt2x00dev);
  89. if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  90. ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
  91. return;
  92. }
  93. /*
  94. * Write the request into the BBP.
  95. */
  96. reg = 0;
  97. rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  98. rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  99. rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
  100. rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  101. /*
  102. * Wait until the BBP becomes ready.
  103. */
  104. reg = rt61pci_bbp_check(rt2x00dev);
  105. if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  106. ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
  107. *value = 0xff;
  108. return;
  109. }
  110. *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
  111. }
  112. static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
  113. const unsigned int word, const u32 value)
  114. {
  115. u32 reg;
  116. unsigned int i;
  117. if (!word)
  118. return;
  119. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  120. rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
  121. if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
  122. goto rf_write;
  123. udelay(REGISTER_BUSY_DELAY);
  124. }
  125. ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
  126. return;
  127. rf_write:
  128. reg = 0;
  129. rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
  130. rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
  131. rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
  132. rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
  133. rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
  134. rt2x00_rf_write(rt2x00dev, word, value);
  135. }
  136. static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
  137. const u8 command, const u8 token,
  138. const u8 arg0, const u8 arg1)
  139. {
  140. u32 reg;
  141. rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
  142. if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
  143. ERROR(rt2x00dev, "mcu request error. "
  144. "Request 0x%02x failed for token 0x%02x.\n",
  145. command, token);
  146. return;
  147. }
  148. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
  149. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
  150. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
  151. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
  152. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
  153. rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
  154. rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
  155. rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
  156. rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
  157. }
  158. static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  159. {
  160. struct rt2x00_dev *rt2x00dev = eeprom->data;
  161. u32 reg;
  162. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  163. eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
  164. eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
  165. eeprom->reg_data_clock =
  166. !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
  167. eeprom->reg_chip_select =
  168. !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
  169. }
  170. static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  171. {
  172. struct rt2x00_dev *rt2x00dev = eeprom->data;
  173. u32 reg = 0;
  174. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
  175. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
  176. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
  177. !!eeprom->reg_data_clock);
  178. rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
  179. !!eeprom->reg_chip_select);
  180. rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
  181. }
  182. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  183. #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
  184. static void rt61pci_read_csr(const struct rt2x00_dev *rt2x00dev,
  185. const unsigned int word, u32 *data)
  186. {
  187. rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
  188. }
  189. static void rt61pci_write_csr(const struct rt2x00_dev *rt2x00dev,
  190. const unsigned int word, u32 data)
  191. {
  192. rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
  193. }
  194. static const struct rt2x00debug rt61pci_rt2x00debug = {
  195. .owner = THIS_MODULE,
  196. .csr = {
  197. .read = rt61pci_read_csr,
  198. .write = rt61pci_write_csr,
  199. .word_size = sizeof(u32),
  200. .word_count = CSR_REG_SIZE / sizeof(u32),
  201. },
  202. .eeprom = {
  203. .read = rt2x00_eeprom_read,
  204. .write = rt2x00_eeprom_write,
  205. .word_size = sizeof(u16),
  206. .word_count = EEPROM_SIZE / sizeof(u16),
  207. },
  208. .bbp = {
  209. .read = rt61pci_bbp_read,
  210. .write = rt61pci_bbp_write,
  211. .word_size = sizeof(u8),
  212. .word_count = BBP_SIZE / sizeof(u8),
  213. },
  214. .rf = {
  215. .read = rt2x00_rf_read,
  216. .write = rt61pci_rf_write,
  217. .word_size = sizeof(u32),
  218. .word_count = RF_SIZE / sizeof(u32),
  219. },
  220. };
  221. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  222. #ifdef CONFIG_RT61PCI_RFKILL
  223. static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  224. {
  225. u32 reg;
  226. rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
  227. return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
  228. }
  229. #else
  230. #define rt61pci_rfkill_poll NULL
  231. #endif /* CONFIG_RT61PCI_RFKILL */
  232. /*
  233. * Configuration handlers.
  234. */
  235. static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
  236. {
  237. u32 tmp;
  238. tmp = le32_to_cpu(mac[1]);
  239. rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
  240. mac[1] = cpu_to_le32(tmp);
  241. rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
  242. (2 * sizeof(__le32)));
  243. }
  244. static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
  245. {
  246. u32 tmp;
  247. tmp = le32_to_cpu(bssid[1]);
  248. rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
  249. bssid[1] = cpu_to_le32(tmp);
  250. rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
  251. (2 * sizeof(__le32)));
  252. }
  253. static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
  254. const int tsf_sync)
  255. {
  256. u32 reg;
  257. /*
  258. * Clear current synchronisation setup.
  259. * For the Beacon base registers we only need to clear
  260. * the first byte since that byte contains the VALID and OWNER
  261. * bits which (when set to 0) will invalidate the entire beacon.
  262. */
  263. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
  264. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
  265. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
  266. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
  267. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
  268. /*
  269. * Enable synchronisation.
  270. */
  271. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  272. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
  273. rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
  274. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
  275. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
  276. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  277. }
  278. static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
  279. const int short_preamble,
  280. const int ack_timeout,
  281. const int ack_consume_time)
  282. {
  283. u32 reg;
  284. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  285. rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
  286. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  287. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  288. rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
  289. !!short_preamble);
  290. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  291. }
  292. static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
  293. const int basic_rate_mask)
  294. {
  295. rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
  296. }
  297. static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
  298. struct rf_channel *rf, const int txpower)
  299. {
  300. u8 r3;
  301. u8 r94;
  302. u8 smart;
  303. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
  304. rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
  305. smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
  306. rt2x00_rf(&rt2x00dev->chip, RF2527));
  307. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  308. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
  309. rt61pci_bbp_write(rt2x00dev, 3, r3);
  310. r94 = 6;
  311. if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
  312. r94 += txpower - MAX_TXPOWER;
  313. else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
  314. r94 += txpower;
  315. rt61pci_bbp_write(rt2x00dev, 94, r94);
  316. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  317. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  318. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  319. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  320. udelay(200);
  321. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  322. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  323. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
  324. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  325. udelay(200);
  326. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  327. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  328. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  329. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  330. msleep(1);
  331. }
  332. static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
  333. const int txpower)
  334. {
  335. struct rf_channel rf;
  336. rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
  337. rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
  338. rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
  339. rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
  340. rt61pci_config_channel(rt2x00dev, &rf, txpower);
  341. }
  342. static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
  343. struct antenna_setup *ant)
  344. {
  345. u8 r3;
  346. u8 r4;
  347. u8 r77;
  348. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  349. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  350. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  351. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
  352. !rt2x00_rf(&rt2x00dev->chip, RF5225));
  353. switch (ant->rx) {
  354. case ANTENNA_SW_DIVERSITY:
  355. case ANTENNA_HW_DIVERSITY:
  356. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
  357. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
  358. !!(rt2x00dev->curr_hwmode != HWMODE_A));
  359. break;
  360. case ANTENNA_A:
  361. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
  362. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
  363. if (rt2x00dev->curr_hwmode == HWMODE_A)
  364. rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
  365. else
  366. rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
  367. break;
  368. case ANTENNA_B:
  369. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
  370. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
  371. if (rt2x00dev->curr_hwmode == HWMODE_A)
  372. rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
  373. else
  374. rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
  375. break;
  376. }
  377. rt61pci_bbp_write(rt2x00dev, 77, r77);
  378. rt61pci_bbp_write(rt2x00dev, 3, r3);
  379. rt61pci_bbp_write(rt2x00dev, 4, r4);
  380. }
  381. static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
  382. struct antenna_setup *ant)
  383. {
  384. u8 r3;
  385. u8 r4;
  386. u8 r77;
  387. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  388. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  389. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  390. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
  391. !rt2x00_rf(&rt2x00dev->chip, RF2527));
  392. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
  393. !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
  394. switch (ant->rx) {
  395. case ANTENNA_SW_DIVERSITY:
  396. case ANTENNA_HW_DIVERSITY:
  397. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
  398. break;
  399. case ANTENNA_A:
  400. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
  401. rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
  402. break;
  403. case ANTENNA_B:
  404. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
  405. rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
  406. break;
  407. }
  408. rt61pci_bbp_write(rt2x00dev, 77, r77);
  409. rt61pci_bbp_write(rt2x00dev, 3, r3);
  410. rt61pci_bbp_write(rt2x00dev, 4, r4);
  411. }
  412. static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
  413. const int p1, const int p2)
  414. {
  415. u32 reg;
  416. rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
  417. if (p1 != 0xff) {
  418. rt2x00_set_field32(&reg, MAC_CSR13_BIT4, !!p1);
  419. rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
  420. rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
  421. }
  422. if (p2 != 0xff) {
  423. rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
  424. rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
  425. rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
  426. }
  427. }
  428. static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
  429. struct antenna_setup *ant)
  430. {
  431. u16 eeprom;
  432. u8 r3;
  433. u8 r4;
  434. u8 r77;
  435. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  436. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  437. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  438. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  439. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
  440. if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
  441. rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
  442. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
  443. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 1);
  444. rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
  445. } else if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) {
  446. if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED) >= 2) {
  447. rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
  448. rt61pci_bbp_write(rt2x00dev, 77, r77);
  449. }
  450. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
  451. rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
  452. } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
  453. rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
  454. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
  455. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
  456. switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
  457. case 0:
  458. rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
  459. break;
  460. case 1:
  461. rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
  462. break;
  463. case 2:
  464. rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
  465. break;
  466. case 3:
  467. rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
  468. break;
  469. }
  470. } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
  471. !rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
  472. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
  473. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
  474. switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
  475. case 0:
  476. rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
  477. rt61pci_bbp_write(rt2x00dev, 77, r77);
  478. rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
  479. break;
  480. case 1:
  481. rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
  482. rt61pci_bbp_write(rt2x00dev, 77, r77);
  483. rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
  484. break;
  485. case 2:
  486. rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
  487. rt61pci_bbp_write(rt2x00dev, 77, r77);
  488. rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
  489. break;
  490. case 3:
  491. rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
  492. rt61pci_bbp_write(rt2x00dev, 77, r77);
  493. rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
  494. break;
  495. }
  496. }
  497. rt61pci_bbp_write(rt2x00dev, 3, r3);
  498. rt61pci_bbp_write(rt2x00dev, 4, r4);
  499. }
  500. struct antenna_sel {
  501. u8 word;
  502. /*
  503. * value[0] -> non-LNA
  504. * value[1] -> LNA
  505. */
  506. u8 value[2];
  507. };
  508. static const struct antenna_sel antenna_sel_a[] = {
  509. { 96, { 0x58, 0x78 } },
  510. { 104, { 0x38, 0x48 } },
  511. { 75, { 0xfe, 0x80 } },
  512. { 86, { 0xfe, 0x80 } },
  513. { 88, { 0xfe, 0x80 } },
  514. { 35, { 0x60, 0x60 } },
  515. { 97, { 0x58, 0x58 } },
  516. { 98, { 0x58, 0x58 } },
  517. };
  518. static const struct antenna_sel antenna_sel_bg[] = {
  519. { 96, { 0x48, 0x68 } },
  520. { 104, { 0x2c, 0x3c } },
  521. { 75, { 0xfe, 0x80 } },
  522. { 86, { 0xfe, 0x80 } },
  523. { 88, { 0xfe, 0x80 } },
  524. { 35, { 0x50, 0x50 } },
  525. { 97, { 0x48, 0x48 } },
  526. { 98, { 0x48, 0x48 } },
  527. };
  528. static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
  529. struct antenna_setup *ant)
  530. {
  531. const struct antenna_sel *sel;
  532. unsigned int lna;
  533. unsigned int i;
  534. u32 reg;
  535. rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
  536. if (rt2x00dev->curr_hwmode == HWMODE_A) {
  537. sel = antenna_sel_a;
  538. lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  539. rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
  540. rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
  541. } else {
  542. sel = antenna_sel_bg;
  543. lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  544. rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
  545. rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
  546. }
  547. for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
  548. rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
  549. rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
  550. if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
  551. rt2x00_rf(&rt2x00dev->chip, RF5325))
  552. rt61pci_config_antenna_5x(rt2x00dev, ant);
  553. else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
  554. rt61pci_config_antenna_2x(rt2x00dev, ant);
  555. else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
  556. if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
  557. rt61pci_config_antenna_2x(rt2x00dev, ant);
  558. else
  559. rt61pci_config_antenna_2529(rt2x00dev, ant);
  560. }
  561. }
  562. static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
  563. struct rt2x00lib_conf *libconf)
  564. {
  565. u32 reg;
  566. rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
  567. rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
  568. rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
  569. rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
  570. rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
  571. rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
  572. rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
  573. rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
  574. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  575. rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
  576. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  577. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  578. rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
  579. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  580. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  581. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
  582. libconf->conf->beacon_int * 16);
  583. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  584. }
  585. static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
  586. const unsigned int flags,
  587. struct rt2x00lib_conf *libconf)
  588. {
  589. if (flags & CONFIG_UPDATE_PHYMODE)
  590. rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
  591. if (flags & CONFIG_UPDATE_CHANNEL)
  592. rt61pci_config_channel(rt2x00dev, &libconf->rf,
  593. libconf->conf->power_level);
  594. if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
  595. rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
  596. if (flags & CONFIG_UPDATE_ANTENNA)
  597. rt61pci_config_antenna(rt2x00dev, &libconf->ant);
  598. if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
  599. rt61pci_config_duration(rt2x00dev, libconf);
  600. }
  601. /*
  602. * LED functions.
  603. */
  604. static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
  605. {
  606. u32 reg;
  607. u16 led_reg;
  608. u8 arg0;
  609. u8 arg1;
  610. rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
  611. rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
  612. rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
  613. rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
  614. led_reg = rt2x00dev->led_reg;
  615. rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
  616. if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
  617. rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
  618. else
  619. rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
  620. arg0 = led_reg & 0xff;
  621. arg1 = (led_reg >> 8) & 0xff;
  622. rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
  623. }
  624. static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
  625. {
  626. u16 led_reg;
  627. u8 arg0;
  628. u8 arg1;
  629. led_reg = rt2x00dev->led_reg;
  630. rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
  631. rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
  632. rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
  633. arg0 = led_reg & 0xff;
  634. arg1 = (led_reg >> 8) & 0xff;
  635. rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
  636. }
  637. static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
  638. {
  639. u8 led;
  640. if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
  641. return;
  642. /*
  643. * Led handling requires a positive value for the rssi,
  644. * to do that correctly we need to add the correction.
  645. */
  646. rssi += rt2x00dev->rssi_offset;
  647. if (rssi <= 30)
  648. led = 0;
  649. else if (rssi <= 39)
  650. led = 1;
  651. else if (rssi <= 49)
  652. led = 2;
  653. else if (rssi <= 53)
  654. led = 3;
  655. else if (rssi <= 63)
  656. led = 4;
  657. else
  658. led = 5;
  659. rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
  660. }
  661. /*
  662. * Link tuning
  663. */
  664. static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
  665. struct link_qual *qual)
  666. {
  667. u32 reg;
  668. /*
  669. * Update FCS error count from register.
  670. */
  671. rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
  672. qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
  673. /*
  674. * Update False CCA count from register.
  675. */
  676. rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
  677. qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
  678. }
  679. static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
  680. {
  681. rt61pci_bbp_write(rt2x00dev, 17, 0x20);
  682. rt2x00dev->link.vgc_level = 0x20;
  683. }
  684. static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
  685. {
  686. int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
  687. u8 r17;
  688. u8 up_bound;
  689. u8 low_bound;
  690. /*
  691. * Update Led strength
  692. */
  693. rt61pci_activity_led(rt2x00dev, rssi);
  694. rt61pci_bbp_read(rt2x00dev, 17, &r17);
  695. /*
  696. * Determine r17 bounds.
  697. */
  698. if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
  699. low_bound = 0x28;
  700. up_bound = 0x48;
  701. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
  702. low_bound += 0x10;
  703. up_bound += 0x10;
  704. }
  705. } else {
  706. low_bound = 0x20;
  707. up_bound = 0x40;
  708. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
  709. low_bound += 0x10;
  710. up_bound += 0x10;
  711. }
  712. }
  713. /*
  714. * Special big-R17 for very short distance
  715. */
  716. if (rssi >= -35) {
  717. if (r17 != 0x60)
  718. rt61pci_bbp_write(rt2x00dev, 17, 0x60);
  719. return;
  720. }
  721. /*
  722. * Special big-R17 for short distance
  723. */
  724. if (rssi >= -58) {
  725. if (r17 != up_bound)
  726. rt61pci_bbp_write(rt2x00dev, 17, up_bound);
  727. return;
  728. }
  729. /*
  730. * Special big-R17 for middle-short distance
  731. */
  732. if (rssi >= -66) {
  733. low_bound += 0x10;
  734. if (r17 != low_bound)
  735. rt61pci_bbp_write(rt2x00dev, 17, low_bound);
  736. return;
  737. }
  738. /*
  739. * Special mid-R17 for middle distance
  740. */
  741. if (rssi >= -74) {
  742. low_bound += 0x08;
  743. if (r17 != low_bound)
  744. rt61pci_bbp_write(rt2x00dev, 17, low_bound);
  745. return;
  746. }
  747. /*
  748. * Special case: Change up_bound based on the rssi.
  749. * Lower up_bound when rssi is weaker then -74 dBm.
  750. */
  751. up_bound -= 2 * (-74 - rssi);
  752. if (low_bound > up_bound)
  753. up_bound = low_bound;
  754. if (r17 > up_bound) {
  755. rt61pci_bbp_write(rt2x00dev, 17, up_bound);
  756. return;
  757. }
  758. /*
  759. * r17 does not yet exceed upper limit, continue and base
  760. * the r17 tuning on the false CCA count.
  761. */
  762. if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
  763. if (++r17 > up_bound)
  764. r17 = up_bound;
  765. rt61pci_bbp_write(rt2x00dev, 17, r17);
  766. } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
  767. if (--r17 < low_bound)
  768. r17 = low_bound;
  769. rt61pci_bbp_write(rt2x00dev, 17, r17);
  770. }
  771. }
  772. /*
  773. * Firmware name function.
  774. */
  775. static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
  776. {
  777. char *fw_name;
  778. switch (rt2x00dev->chip.rt) {
  779. case RT2561:
  780. fw_name = FIRMWARE_RT2561;
  781. break;
  782. case RT2561s:
  783. fw_name = FIRMWARE_RT2561s;
  784. break;
  785. case RT2661:
  786. fw_name = FIRMWARE_RT2661;
  787. break;
  788. default:
  789. fw_name = NULL;
  790. break;
  791. }
  792. return fw_name;
  793. }
  794. /*
  795. * Initialization functions.
  796. */
  797. static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
  798. const size_t len)
  799. {
  800. int i;
  801. u32 reg;
  802. /*
  803. * Wait for stable hardware.
  804. */
  805. for (i = 0; i < 100; i++) {
  806. rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
  807. if (reg)
  808. break;
  809. msleep(1);
  810. }
  811. if (!reg) {
  812. ERROR(rt2x00dev, "Unstable hardware.\n");
  813. return -EBUSY;
  814. }
  815. /*
  816. * Prepare MCU and mailbox for firmware loading.
  817. */
  818. reg = 0;
  819. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
  820. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  821. rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
  822. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  823. rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
  824. /*
  825. * Write firmware to device.
  826. */
  827. reg = 0;
  828. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
  829. rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
  830. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  831. rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
  832. data, len);
  833. rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
  834. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  835. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
  836. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  837. for (i = 0; i < 100; i++) {
  838. rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
  839. if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
  840. break;
  841. msleep(1);
  842. }
  843. if (i == 100) {
  844. ERROR(rt2x00dev, "MCU Control register not ready.\n");
  845. return -EBUSY;
  846. }
  847. /*
  848. * Reset MAC and BBP registers.
  849. */
  850. reg = 0;
  851. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
  852. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
  853. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  854. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  855. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
  856. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
  857. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  858. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  859. rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
  860. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  861. return 0;
  862. }
  863. static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
  864. {
  865. struct data_ring *ring = rt2x00dev->rx;
  866. struct data_desc *rxd;
  867. unsigned int i;
  868. u32 word;
  869. memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
  870. for (i = 0; i < ring->stats.limit; i++) {
  871. rxd = ring->entry[i].priv;
  872. rt2x00_desc_read(rxd, 5, &word);
  873. rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
  874. ring->entry[i].data_dma);
  875. rt2x00_desc_write(rxd, 5, word);
  876. rt2x00_desc_read(rxd, 0, &word);
  877. rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
  878. rt2x00_desc_write(rxd, 0, word);
  879. }
  880. rt2x00_ring_index_clear(rt2x00dev->rx);
  881. }
  882. static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
  883. {
  884. struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
  885. struct data_desc *txd;
  886. unsigned int i;
  887. u32 word;
  888. memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
  889. for (i = 0; i < ring->stats.limit; i++) {
  890. txd = ring->entry[i].priv;
  891. rt2x00_desc_read(txd, 1, &word);
  892. rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
  893. rt2x00_desc_write(txd, 1, word);
  894. rt2x00_desc_read(txd, 5, &word);
  895. rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
  896. rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
  897. rt2x00_desc_write(txd, 5, word);
  898. rt2x00_desc_read(txd, 6, &word);
  899. rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
  900. ring->entry[i].data_dma);
  901. rt2x00_desc_write(txd, 6, word);
  902. rt2x00_desc_read(txd, 0, &word);
  903. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  904. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
  905. rt2x00_desc_write(txd, 0, word);
  906. }
  907. rt2x00_ring_index_clear(ring);
  908. }
  909. static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
  910. {
  911. u32 reg;
  912. /*
  913. * Initialize rings.
  914. */
  915. rt61pci_init_rxring(rt2x00dev);
  916. rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
  917. rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
  918. rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
  919. rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
  920. rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
  921. /*
  922. * Initialize registers.
  923. */
  924. rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
  925. rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
  926. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
  927. rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
  928. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
  929. rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
  930. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
  931. rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
  932. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
  933. rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
  934. rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
  935. rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
  936. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
  937. rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
  938. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
  939. 4);
  940. rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
  941. rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
  942. rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
  943. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
  944. rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
  945. rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
  946. rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
  947. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
  948. rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
  949. rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
  950. rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
  951. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
  952. rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
  953. rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
  954. rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
  955. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
  956. rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
  957. rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
  958. rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
  959. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
  960. rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
  961. rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
  962. rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE,
  963. rt2x00dev->rx->stats.limit);
  964. rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
  965. rt2x00dev->rx->desc_size / 4);
  966. rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
  967. rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
  968. rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
  969. rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
  970. rt2x00dev->rx->data_dma);
  971. rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
  972. rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
  973. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
  974. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
  975. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
  976. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
  977. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
  978. rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
  979. rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
  980. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
  981. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
  982. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
  983. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
  984. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
  985. rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
  986. rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
  987. rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
  988. rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
  989. return 0;
  990. }
  991. static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
  992. {
  993. u32 reg;
  994. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  995. rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
  996. rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
  997. rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
  998. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  999. rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
  1000. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
  1001. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
  1002. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
  1003. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
  1004. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
  1005. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
  1006. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
  1007. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
  1008. rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
  1009. /*
  1010. * CCK TXD BBP registers
  1011. */
  1012. rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
  1013. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
  1014. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
  1015. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
  1016. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
  1017. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
  1018. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
  1019. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
  1020. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
  1021. rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
  1022. /*
  1023. * OFDM TXD BBP registers
  1024. */
  1025. rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
  1026. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
  1027. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
  1028. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
  1029. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
  1030. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
  1031. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
  1032. rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
  1033. rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
  1034. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
  1035. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
  1036. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
  1037. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
  1038. rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
  1039. rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
  1040. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
  1041. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
  1042. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
  1043. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
  1044. rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
  1045. rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
  1046. rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
  1047. rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
  1048. rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
  1049. rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
  1050. rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
  1051. if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
  1052. return -EBUSY;
  1053. rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
  1054. /*
  1055. * Invalidate all Shared Keys (SEC_CSR0),
  1056. * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
  1057. */
  1058. rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
  1059. rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
  1060. rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
  1061. rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
  1062. rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
  1063. rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
  1064. rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
  1065. rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
  1066. rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
  1067. rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
  1068. rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
  1069. rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
  1070. rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
  1071. rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
  1072. rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
  1073. rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
  1074. rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
  1075. rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
  1076. /*
  1077. * We must clear the error counters.
  1078. * These registers are cleared on read,
  1079. * so we may pass a useless variable to store the value.
  1080. */
  1081. rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
  1082. rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
  1083. rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
  1084. /*
  1085. * Reset MAC and BBP registers.
  1086. */
  1087. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1088. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
  1089. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
  1090. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1091. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1092. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
  1093. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
  1094. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1095. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1096. rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
  1097. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1098. return 0;
  1099. }
  1100. static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
  1101. {
  1102. unsigned int i;
  1103. u16 eeprom;
  1104. u8 reg_id;
  1105. u8 value;
  1106. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1107. rt61pci_bbp_read(rt2x00dev, 0, &value);
  1108. if ((value != 0xff) && (value != 0x00))
  1109. goto continue_csr_init;
  1110. NOTICE(rt2x00dev, "Waiting for BBP register.\n");
  1111. udelay(REGISTER_BUSY_DELAY);
  1112. }
  1113. ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
  1114. return -EACCES;
  1115. continue_csr_init:
  1116. rt61pci_bbp_write(rt2x00dev, 3, 0x00);
  1117. rt61pci_bbp_write(rt2x00dev, 15, 0x30);
  1118. rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
  1119. rt61pci_bbp_write(rt2x00dev, 22, 0x38);
  1120. rt61pci_bbp_write(rt2x00dev, 23, 0x06);
  1121. rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
  1122. rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
  1123. rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
  1124. rt61pci_bbp_write(rt2x00dev, 34, 0x12);
  1125. rt61pci_bbp_write(rt2x00dev, 37, 0x07);
  1126. rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
  1127. rt61pci_bbp_write(rt2x00dev, 41, 0x60);
  1128. rt61pci_bbp_write(rt2x00dev, 53, 0x10);
  1129. rt61pci_bbp_write(rt2x00dev, 54, 0x18);
  1130. rt61pci_bbp_write(rt2x00dev, 60, 0x10);
  1131. rt61pci_bbp_write(rt2x00dev, 61, 0x04);
  1132. rt61pci_bbp_write(rt2x00dev, 62, 0x04);
  1133. rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
  1134. rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
  1135. rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
  1136. rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
  1137. rt61pci_bbp_write(rt2x00dev, 99, 0x00);
  1138. rt61pci_bbp_write(rt2x00dev, 102, 0x16);
  1139. rt61pci_bbp_write(rt2x00dev, 107, 0x04);
  1140. DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
  1141. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  1142. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  1143. if (eeprom != 0xffff && eeprom != 0x0000) {
  1144. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  1145. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  1146. DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
  1147. reg_id, value);
  1148. rt61pci_bbp_write(rt2x00dev, reg_id, value);
  1149. }
  1150. }
  1151. DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
  1152. return 0;
  1153. }
  1154. /*
  1155. * Device state switch handlers.
  1156. */
  1157. static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
  1158. enum dev_state state)
  1159. {
  1160. u32 reg;
  1161. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  1162. rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
  1163. state == STATE_RADIO_RX_OFF);
  1164. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  1165. }
  1166. static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  1167. enum dev_state state)
  1168. {
  1169. int mask = (state == STATE_RADIO_IRQ_OFF);
  1170. u32 reg;
  1171. /*
  1172. * When interrupts are being enabled, the interrupt registers
  1173. * should clear the register to assure a clean state.
  1174. */
  1175. if (state == STATE_RADIO_IRQ_ON) {
  1176. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  1177. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  1178. rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
  1179. rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
  1180. }
  1181. /*
  1182. * Only toggle the interrupts bits we are going to use.
  1183. * Non-checked interrupt bits are disabled by default.
  1184. */
  1185. rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
  1186. rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
  1187. rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
  1188. rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
  1189. rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
  1190. rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
  1191. rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
  1192. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
  1193. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
  1194. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
  1195. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
  1196. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
  1197. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
  1198. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
  1199. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
  1200. rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
  1201. }
  1202. static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  1203. {
  1204. u32 reg;
  1205. /*
  1206. * Initialize all registers.
  1207. */
  1208. if (rt61pci_init_rings(rt2x00dev) ||
  1209. rt61pci_init_registers(rt2x00dev) ||
  1210. rt61pci_init_bbp(rt2x00dev)) {
  1211. ERROR(rt2x00dev, "Register initialization failed.\n");
  1212. return -EIO;
  1213. }
  1214. /*
  1215. * Enable interrupts.
  1216. */
  1217. rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
  1218. /*
  1219. * Enable RX.
  1220. */
  1221. rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
  1222. rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
  1223. rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
  1224. /*
  1225. * Enable LED
  1226. */
  1227. rt61pci_enable_led(rt2x00dev);
  1228. return 0;
  1229. }
  1230. static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  1231. {
  1232. u32 reg;
  1233. /*
  1234. * Disable LED
  1235. */
  1236. rt61pci_disable_led(rt2x00dev);
  1237. rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
  1238. /*
  1239. * Disable synchronisation.
  1240. */
  1241. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
  1242. /*
  1243. * Cancel RX and TX.
  1244. */
  1245. rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
  1246. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
  1247. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
  1248. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
  1249. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
  1250. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
  1251. rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
  1252. /*
  1253. * Disable interrupts.
  1254. */
  1255. rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
  1256. }
  1257. static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
  1258. {
  1259. u32 reg;
  1260. unsigned int i;
  1261. char put_to_sleep;
  1262. char current_state;
  1263. put_to_sleep = (state != STATE_AWAKE);
  1264. rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
  1265. rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
  1266. rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
  1267. rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
  1268. /*
  1269. * Device is not guaranteed to be in the requested state yet.
  1270. * We must wait until the register indicates that the
  1271. * device has entered the correct state.
  1272. */
  1273. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1274. rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
  1275. current_state =
  1276. rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
  1277. if (current_state == !put_to_sleep)
  1278. return 0;
  1279. msleep(10);
  1280. }
  1281. NOTICE(rt2x00dev, "Device failed to enter state %d, "
  1282. "current device state %d.\n", !put_to_sleep, current_state);
  1283. return -EBUSY;
  1284. }
  1285. static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  1286. enum dev_state state)
  1287. {
  1288. int retval = 0;
  1289. switch (state) {
  1290. case STATE_RADIO_ON:
  1291. retval = rt61pci_enable_radio(rt2x00dev);
  1292. break;
  1293. case STATE_RADIO_OFF:
  1294. rt61pci_disable_radio(rt2x00dev);
  1295. break;
  1296. case STATE_RADIO_RX_ON:
  1297. case STATE_RADIO_RX_OFF:
  1298. rt61pci_toggle_rx(rt2x00dev, state);
  1299. break;
  1300. case STATE_DEEP_SLEEP:
  1301. case STATE_SLEEP:
  1302. case STATE_STANDBY:
  1303. case STATE_AWAKE:
  1304. retval = rt61pci_set_state(rt2x00dev, state);
  1305. break;
  1306. default:
  1307. retval = -ENOTSUPP;
  1308. break;
  1309. }
  1310. return retval;
  1311. }
  1312. /*
  1313. * TX descriptor initialization
  1314. */
  1315. static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
  1316. struct data_desc *txd,
  1317. struct txdata_entry_desc *desc,
  1318. struct ieee80211_hdr *ieee80211hdr,
  1319. unsigned int length,
  1320. struct ieee80211_tx_control *control)
  1321. {
  1322. u32 word;
  1323. /*
  1324. * Start writing the descriptor words.
  1325. */
  1326. rt2x00_desc_read(txd, 1, &word);
  1327. rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
  1328. rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
  1329. rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
  1330. rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
  1331. rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
  1332. rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
  1333. rt2x00_desc_write(txd, 1, word);
  1334. rt2x00_desc_read(txd, 2, &word);
  1335. rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
  1336. rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
  1337. rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
  1338. rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
  1339. rt2x00_desc_write(txd, 2, word);
  1340. rt2x00_desc_read(txd, 5, &word);
  1341. rt2x00_set_field32(&word, TXD_W5_TX_POWER,
  1342. TXPOWER_TO_DEV(control->power_level));
  1343. rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
  1344. rt2x00_desc_write(txd, 5, word);
  1345. rt2x00_desc_read(txd, 11, &word);
  1346. rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
  1347. rt2x00_desc_write(txd, 11, word);
  1348. rt2x00_desc_read(txd, 0, &word);
  1349. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
  1350. rt2x00_set_field32(&word, TXD_W0_VALID, 1);
  1351. rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
  1352. test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
  1353. rt2x00_set_field32(&word, TXD_W0_ACK,
  1354. !(control->flags & IEEE80211_TXCTL_NO_ACK));
  1355. rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
  1356. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
  1357. rt2x00_set_field32(&word, TXD_W0_OFDM,
  1358. test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
  1359. rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
  1360. rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
  1361. !!(control->flags &
  1362. IEEE80211_TXCTL_LONG_RETRY_LIMIT));
  1363. rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
  1364. rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
  1365. rt2x00_set_field32(&word, TXD_W0_BURST,
  1366. test_bit(ENTRY_TXD_BURST, &desc->flags));
  1367. rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
  1368. rt2x00_desc_write(txd, 0, word);
  1369. }
  1370. /*
  1371. * TX data initialization
  1372. */
  1373. static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
  1374. unsigned int queue)
  1375. {
  1376. u32 reg;
  1377. if (queue == IEEE80211_TX_QUEUE_BEACON) {
  1378. /*
  1379. * For Wi-Fi faily generated beacons between participating
  1380. * stations. Set TBTT phase adaptive adjustment step to 8us.
  1381. */
  1382. rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
  1383. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  1384. if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
  1385. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
  1386. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  1387. }
  1388. return;
  1389. }
  1390. rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
  1391. if (queue == IEEE80211_TX_QUEUE_DATA0)
  1392. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
  1393. else if (queue == IEEE80211_TX_QUEUE_DATA1)
  1394. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
  1395. else if (queue == IEEE80211_TX_QUEUE_DATA2)
  1396. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
  1397. else if (queue == IEEE80211_TX_QUEUE_DATA3)
  1398. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
  1399. else if (queue == IEEE80211_TX_QUEUE_DATA4)
  1400. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT, 1);
  1401. rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
  1402. }
  1403. /*
  1404. * RX control handlers
  1405. */
  1406. static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
  1407. {
  1408. u16 eeprom;
  1409. u8 offset;
  1410. u8 lna;
  1411. lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
  1412. switch (lna) {
  1413. case 3:
  1414. offset = 90;
  1415. break;
  1416. case 2:
  1417. offset = 74;
  1418. break;
  1419. case 1:
  1420. offset = 64;
  1421. break;
  1422. default:
  1423. return 0;
  1424. }
  1425. if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
  1426. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
  1427. offset += 14;
  1428. if (lna == 3 || lna == 2)
  1429. offset += 10;
  1430. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
  1431. offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
  1432. } else {
  1433. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
  1434. offset += 14;
  1435. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
  1436. offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
  1437. }
  1438. return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
  1439. }
  1440. static void rt61pci_fill_rxdone(struct data_entry *entry,
  1441. struct rxdata_entry_desc *desc)
  1442. {
  1443. struct data_desc *rxd = entry->priv;
  1444. u32 word0;
  1445. u32 word1;
  1446. rt2x00_desc_read(rxd, 0, &word0);
  1447. rt2x00_desc_read(rxd, 1, &word1);
  1448. desc->flags = 0;
  1449. if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
  1450. desc->flags |= RX_FLAG_FAILED_FCS_CRC;
  1451. /*
  1452. * Obtain the status about this packet.
  1453. */
  1454. desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
  1455. desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
  1456. desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
  1457. desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
  1458. return;
  1459. }
  1460. /*
  1461. * Interrupt functions.
  1462. */
  1463. static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
  1464. {
  1465. struct data_ring *ring;
  1466. struct data_entry *entry;
  1467. struct data_entry *entry_done;
  1468. struct data_desc *txd;
  1469. u32 word;
  1470. u32 reg;
  1471. u32 old_reg;
  1472. int type;
  1473. int index;
  1474. int tx_status;
  1475. int retry;
  1476. /*
  1477. * During each loop we will compare the freshly read
  1478. * STA_CSR4 register value with the value read from
  1479. * the previous loop. If the 2 values are equal then
  1480. * we should stop processing because the chance it
  1481. * quite big that the device has been unplugged and
  1482. * we risk going into an endless loop.
  1483. */
  1484. old_reg = 0;
  1485. while (1) {
  1486. rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
  1487. if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
  1488. break;
  1489. if (old_reg == reg)
  1490. break;
  1491. old_reg = reg;
  1492. /*
  1493. * Skip this entry when it contains an invalid
  1494. * ring identication number.
  1495. */
  1496. type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
  1497. ring = rt2x00lib_get_ring(rt2x00dev, type);
  1498. if (unlikely(!ring))
  1499. continue;
  1500. /*
  1501. * Skip this entry when it contains an invalid
  1502. * index number.
  1503. */
  1504. index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
  1505. if (unlikely(index >= ring->stats.limit))
  1506. continue;
  1507. entry = &ring->entry[index];
  1508. txd = entry->priv;
  1509. rt2x00_desc_read(txd, 0, &word);
  1510. if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1511. !rt2x00_get_field32(word, TXD_W0_VALID))
  1512. return;
  1513. entry_done = rt2x00_get_data_entry_done(ring);
  1514. while (entry != entry_done) {
  1515. /* Catch up. Just report any entries we missed as
  1516. * failed. */
  1517. WARNING(rt2x00dev,
  1518. "TX status report missed for entry %p\n",
  1519. entry_done);
  1520. rt2x00lib_txdone(entry_done, TX_FAIL_OTHER, 0);
  1521. entry_done = rt2x00_get_data_entry_done(ring);
  1522. }
  1523. /*
  1524. * Obtain the status about this packet.
  1525. */
  1526. tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
  1527. retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
  1528. rt2x00lib_txdone(entry, tx_status, retry);
  1529. /*
  1530. * Make this entry available for reuse.
  1531. */
  1532. entry->flags = 0;
  1533. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  1534. rt2x00_desc_write(txd, 0, word);
  1535. rt2x00_ring_index_done_inc(entry->ring);
  1536. /*
  1537. * If the data ring was full before the txdone handler
  1538. * we must make sure the packet queue in the mac80211 stack
  1539. * is reenabled when the txdone handler has finished.
  1540. */
  1541. if (!rt2x00_ring_full(ring))
  1542. ieee80211_wake_queue(rt2x00dev->hw,
  1543. entry->tx_status.control.queue);
  1544. }
  1545. }
  1546. static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
  1547. {
  1548. struct rt2x00_dev *rt2x00dev = dev_instance;
  1549. u32 reg_mcu;
  1550. u32 reg;
  1551. /*
  1552. * Get the interrupt sources & saved to local variable.
  1553. * Write register value back to clear pending interrupts.
  1554. */
  1555. rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
  1556. rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
  1557. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  1558. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  1559. if (!reg && !reg_mcu)
  1560. return IRQ_NONE;
  1561. if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
  1562. return IRQ_HANDLED;
  1563. /*
  1564. * Handle interrupts, walk through all bits
  1565. * and run the tasks, the bits are checked in order of
  1566. * priority.
  1567. */
  1568. /*
  1569. * 1 - Rx ring done interrupt.
  1570. */
  1571. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
  1572. rt2x00pci_rxdone(rt2x00dev);
  1573. /*
  1574. * 2 - Tx ring done interrupt.
  1575. */
  1576. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
  1577. rt61pci_txdone(rt2x00dev);
  1578. /*
  1579. * 3 - Handle MCU command done.
  1580. */
  1581. if (reg_mcu)
  1582. rt2x00pci_register_write(rt2x00dev,
  1583. M2H_CMD_DONE_CSR, 0xffffffff);
  1584. return IRQ_HANDLED;
  1585. }
  1586. /*
  1587. * Device probe functions.
  1588. */
  1589. static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1590. {
  1591. struct eeprom_93cx6 eeprom;
  1592. u32 reg;
  1593. u16 word;
  1594. u8 *mac;
  1595. s8 value;
  1596. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  1597. eeprom.data = rt2x00dev;
  1598. eeprom.register_read = rt61pci_eepromregister_read;
  1599. eeprom.register_write = rt61pci_eepromregister_write;
  1600. eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
  1601. PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
  1602. eeprom.reg_data_in = 0;
  1603. eeprom.reg_data_out = 0;
  1604. eeprom.reg_data_clock = 0;
  1605. eeprom.reg_chip_select = 0;
  1606. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  1607. EEPROM_SIZE / sizeof(u16));
  1608. /*
  1609. * Start validation of the data that has been read.
  1610. */
  1611. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1612. if (!is_valid_ether_addr(mac)) {
  1613. DECLARE_MAC_BUF(macbuf);
  1614. random_ether_addr(mac);
  1615. EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
  1616. }
  1617. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1618. if (word == 0xffff) {
  1619. rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
  1620. rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
  1621. ANTENNA_B);
  1622. rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
  1623. ANTENNA_B);
  1624. rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
  1625. rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
  1626. rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
  1627. rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
  1628. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1629. EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
  1630. }
  1631. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
  1632. if (word == 0xffff) {
  1633. rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
  1634. rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
  1635. rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
  1636. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
  1637. rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
  1638. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
  1639. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
  1640. EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
  1641. }
  1642. rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
  1643. if (word == 0xffff) {
  1644. rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
  1645. LED_MODE_DEFAULT);
  1646. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
  1647. EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
  1648. }
  1649. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
  1650. if (word == 0xffff) {
  1651. rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
  1652. rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
  1653. rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
  1654. EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
  1655. }
  1656. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
  1657. if (word == 0xffff) {
  1658. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
  1659. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
  1660. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
  1661. EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
  1662. } else {
  1663. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
  1664. if (value < -10 || value > 10)
  1665. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
  1666. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
  1667. if (value < -10 || value > 10)
  1668. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
  1669. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
  1670. }
  1671. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
  1672. if (word == 0xffff) {
  1673. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
  1674. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
  1675. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
  1676. EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
  1677. } else {
  1678. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
  1679. if (value < -10 || value > 10)
  1680. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
  1681. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
  1682. if (value < -10 || value > 10)
  1683. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
  1684. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
  1685. }
  1686. return 0;
  1687. }
  1688. static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1689. {
  1690. u32 reg;
  1691. u16 value;
  1692. u16 eeprom;
  1693. u16 device;
  1694. /*
  1695. * Read EEPROM word for configuration.
  1696. */
  1697. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1698. /*
  1699. * Identify RF chipset.
  1700. * To determine the RT chip we have to read the
  1701. * PCI header of the device.
  1702. */
  1703. pci_read_config_word(rt2x00dev_pci(rt2x00dev),
  1704. PCI_CONFIG_HEADER_DEVICE, &device);
  1705. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1706. rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
  1707. rt2x00_set_chip(rt2x00dev, device, value, reg);
  1708. if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
  1709. !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
  1710. !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
  1711. !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
  1712. ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
  1713. return -ENODEV;
  1714. }
  1715. /*
  1716. * Identify default antenna configuration.
  1717. */
  1718. rt2x00dev->default_ant.tx =
  1719. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
  1720. rt2x00dev->default_ant.rx =
  1721. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
  1722. /*
  1723. * Read the Frame type.
  1724. */
  1725. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
  1726. __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
  1727. /*
  1728. * Determine number of antenna's.
  1729. */
  1730. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
  1731. __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
  1732. /*
  1733. * Detect if this device has an hardware controlled radio.
  1734. */
  1735. #ifdef CONFIG_RT61PCI_RFKILL
  1736. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
  1737. __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
  1738. #endif /* CONFIG_RT61PCI_RFKILL */
  1739. /*
  1740. * Read frequency offset and RF programming sequence.
  1741. */
  1742. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
  1743. if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
  1744. __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
  1745. rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
  1746. /*
  1747. * Read external LNA informations.
  1748. */
  1749. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1750. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
  1751. __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  1752. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
  1753. __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  1754. /*
  1755. * Store led settings, for correct led behaviour.
  1756. * If the eeprom value is invalid,
  1757. * switch to default led mode.
  1758. */
  1759. rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
  1760. rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
  1761. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
  1762. rt2x00dev->led_mode);
  1763. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
  1764. rt2x00_get_field16(eeprom,
  1765. EEPROM_LED_POLARITY_GPIO_0));
  1766. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
  1767. rt2x00_get_field16(eeprom,
  1768. EEPROM_LED_POLARITY_GPIO_1));
  1769. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
  1770. rt2x00_get_field16(eeprom,
  1771. EEPROM_LED_POLARITY_GPIO_2));
  1772. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
  1773. rt2x00_get_field16(eeprom,
  1774. EEPROM_LED_POLARITY_GPIO_3));
  1775. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
  1776. rt2x00_get_field16(eeprom,
  1777. EEPROM_LED_POLARITY_GPIO_4));
  1778. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
  1779. rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
  1780. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
  1781. rt2x00_get_field16(eeprom,
  1782. EEPROM_LED_POLARITY_RDY_G));
  1783. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
  1784. rt2x00_get_field16(eeprom,
  1785. EEPROM_LED_POLARITY_RDY_A));
  1786. return 0;
  1787. }
  1788. /*
  1789. * RF value list for RF5225 & RF5325
  1790. * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
  1791. */
  1792. static const struct rf_channel rf_vals_noseq[] = {
  1793. { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
  1794. { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
  1795. { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
  1796. { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
  1797. { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
  1798. { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
  1799. { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
  1800. { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
  1801. { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
  1802. { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
  1803. { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
  1804. { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
  1805. { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
  1806. { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
  1807. /* 802.11 UNI / HyperLan 2 */
  1808. { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
  1809. { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
  1810. { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
  1811. { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
  1812. { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
  1813. { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
  1814. { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
  1815. { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
  1816. /* 802.11 HyperLan 2 */
  1817. { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
  1818. { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
  1819. { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
  1820. { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
  1821. { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
  1822. { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
  1823. { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
  1824. { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
  1825. { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
  1826. { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
  1827. /* 802.11 UNII */
  1828. { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
  1829. { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
  1830. { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
  1831. { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
  1832. { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
  1833. { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
  1834. /* MMAC(Japan)J52 ch 34,38,42,46 */
  1835. { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
  1836. { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
  1837. { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
  1838. { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
  1839. };
  1840. /*
  1841. * RF value list for RF5225 & RF5325
  1842. * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
  1843. */
  1844. static const struct rf_channel rf_vals_seq[] = {
  1845. { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
  1846. { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
  1847. { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
  1848. { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
  1849. { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
  1850. { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
  1851. { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
  1852. { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
  1853. { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
  1854. { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
  1855. { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
  1856. { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
  1857. { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
  1858. { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
  1859. /* 802.11 UNI / HyperLan 2 */
  1860. { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
  1861. { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
  1862. { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
  1863. { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
  1864. { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
  1865. { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
  1866. { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
  1867. { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
  1868. /* 802.11 HyperLan 2 */
  1869. { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
  1870. { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
  1871. { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
  1872. { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
  1873. { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
  1874. { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
  1875. { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
  1876. { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
  1877. { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
  1878. { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
  1879. /* 802.11 UNII */
  1880. { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
  1881. { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
  1882. { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
  1883. { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
  1884. { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
  1885. { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
  1886. /* MMAC(Japan)J52 ch 34,38,42,46 */
  1887. { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
  1888. { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
  1889. { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
  1890. { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
  1891. };
  1892. static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1893. {
  1894. struct hw_mode_spec *spec = &rt2x00dev->spec;
  1895. u8 *txpower;
  1896. unsigned int i;
  1897. /*
  1898. * Initialize all hw fields.
  1899. */
  1900. rt2x00dev->hw->flags =
  1901. IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  1902. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
  1903. rt2x00dev->hw->extra_tx_headroom = 0;
  1904. rt2x00dev->hw->max_signal = MAX_SIGNAL;
  1905. rt2x00dev->hw->max_rssi = MAX_RX_SSI;
  1906. rt2x00dev->hw->queues = 5;
  1907. SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
  1908. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  1909. rt2x00_eeprom_addr(rt2x00dev,
  1910. EEPROM_MAC_ADDR_0));
  1911. /*
  1912. * Convert tx_power array in eeprom.
  1913. */
  1914. txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
  1915. for (i = 0; i < 14; i++)
  1916. txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
  1917. /*
  1918. * Initialize hw_mode information.
  1919. */
  1920. spec->num_modes = 2;
  1921. spec->num_rates = 12;
  1922. spec->tx_power_a = NULL;
  1923. spec->tx_power_bg = txpower;
  1924. spec->tx_power_default = DEFAULT_TXPOWER;
  1925. if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
  1926. spec->num_channels = 14;
  1927. spec->channels = rf_vals_noseq;
  1928. } else {
  1929. spec->num_channels = 14;
  1930. spec->channels = rf_vals_seq;
  1931. }
  1932. if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
  1933. rt2x00_rf(&rt2x00dev->chip, RF5325)) {
  1934. spec->num_modes = 3;
  1935. spec->num_channels = ARRAY_SIZE(rf_vals_seq);
  1936. txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
  1937. for (i = 0; i < 14; i++)
  1938. txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
  1939. spec->tx_power_a = txpower;
  1940. }
  1941. }
  1942. static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
  1943. {
  1944. int retval;
  1945. /*
  1946. * Allocate eeprom data.
  1947. */
  1948. retval = rt61pci_validate_eeprom(rt2x00dev);
  1949. if (retval)
  1950. return retval;
  1951. retval = rt61pci_init_eeprom(rt2x00dev);
  1952. if (retval)
  1953. return retval;
  1954. /*
  1955. * Initialize hw specifications.
  1956. */
  1957. rt61pci_probe_hw_mode(rt2x00dev);
  1958. /*
  1959. * This device requires firmware
  1960. */
  1961. __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
  1962. /*
  1963. * Set the rssi offset.
  1964. */
  1965. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  1966. return 0;
  1967. }
  1968. /*
  1969. * IEEE80211 stack callback functions.
  1970. */
  1971. static void rt61pci_configure_filter(struct ieee80211_hw *hw,
  1972. unsigned int changed_flags,
  1973. unsigned int *total_flags,
  1974. int mc_count,
  1975. struct dev_addr_list *mc_list)
  1976. {
  1977. struct rt2x00_dev *rt2x00dev = hw->priv;
  1978. struct interface *intf = &rt2x00dev->interface;
  1979. u32 reg;
  1980. /*
  1981. * Mask off any flags we are going to ignore from
  1982. * the total_flags field.
  1983. */
  1984. *total_flags &=
  1985. FIF_ALLMULTI |
  1986. FIF_FCSFAIL |
  1987. FIF_PLCPFAIL |
  1988. FIF_CONTROL |
  1989. FIF_OTHER_BSS |
  1990. FIF_PROMISC_IN_BSS;
  1991. /*
  1992. * Apply some rules to the filters:
  1993. * - Some filters imply different filters to be set.
  1994. * - Some things we can't filter out at all.
  1995. * - Some filters are set based on interface type.
  1996. */
  1997. if (mc_count)
  1998. *total_flags |= FIF_ALLMULTI;
  1999. if (*total_flags & FIF_OTHER_BSS ||
  2000. *total_flags & FIF_PROMISC_IN_BSS)
  2001. *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
  2002. if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
  2003. *total_flags |= FIF_PROMISC_IN_BSS;
  2004. /*
  2005. * Check if there is any work left for us.
  2006. */
  2007. if (intf->filter == *total_flags)
  2008. return;
  2009. intf->filter = *total_flags;
  2010. /*
  2011. * Start configuration steps.
  2012. * Note that the version error will always be dropped
  2013. * and broadcast frames will always be accepted since
  2014. * there is no filter for it at this time.
  2015. */
  2016. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  2017. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
  2018. !(*total_flags & FIF_FCSFAIL));
  2019. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
  2020. !(*total_flags & FIF_PLCPFAIL));
  2021. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
  2022. !(*total_flags & FIF_CONTROL));
  2023. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
  2024. !(*total_flags & FIF_PROMISC_IN_BSS));
  2025. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
  2026. !(*total_flags & FIF_PROMISC_IN_BSS));
  2027. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
  2028. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
  2029. !(*total_flags & FIF_ALLMULTI));
  2030. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
  2031. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
  2032. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  2033. }
  2034. static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
  2035. u32 short_retry, u32 long_retry)
  2036. {
  2037. struct rt2x00_dev *rt2x00dev = hw->priv;
  2038. u32 reg;
  2039. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  2040. rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
  2041. rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
  2042. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  2043. return 0;
  2044. }
  2045. static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
  2046. {
  2047. struct rt2x00_dev *rt2x00dev = hw->priv;
  2048. u64 tsf;
  2049. u32 reg;
  2050. rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
  2051. tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
  2052. rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
  2053. tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
  2054. return tsf;
  2055. }
  2056. static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
  2057. {
  2058. struct rt2x00_dev *rt2x00dev = hw->priv;
  2059. rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
  2060. rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
  2061. }
  2062. static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  2063. struct ieee80211_tx_control *control)
  2064. {
  2065. struct rt2x00_dev *rt2x00dev = hw->priv;
  2066. /*
  2067. * Just in case the ieee80211 doesn't set this,
  2068. * but we need this queue set for the descriptor
  2069. * initialization.
  2070. */
  2071. control->queue = IEEE80211_TX_QUEUE_BEACON;
  2072. /*
  2073. * We need to append the descriptor in front of the
  2074. * beacon frame.
  2075. */
  2076. if (skb_headroom(skb) < TXD_DESC_SIZE) {
  2077. if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
  2078. dev_kfree_skb(skb);
  2079. return -ENOMEM;
  2080. }
  2081. }
  2082. /*
  2083. * First we create the beacon.
  2084. */
  2085. skb_push(skb, TXD_DESC_SIZE);
  2086. memset(skb->data, 0, TXD_DESC_SIZE);
  2087. rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
  2088. (struct ieee80211_hdr *)(skb->data +
  2089. TXD_DESC_SIZE),
  2090. skb->len - TXD_DESC_SIZE, control);
  2091. /*
  2092. * Write entire beacon with descriptor to register,
  2093. * and kick the beacon generator.
  2094. */
  2095. rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
  2096. skb->data, skb->len);
  2097. rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
  2098. return 0;
  2099. }
  2100. static const struct ieee80211_ops rt61pci_mac80211_ops = {
  2101. .tx = rt2x00mac_tx,
  2102. .start = rt2x00mac_start,
  2103. .stop = rt2x00mac_stop,
  2104. .add_interface = rt2x00mac_add_interface,
  2105. .remove_interface = rt2x00mac_remove_interface,
  2106. .config = rt2x00mac_config,
  2107. .config_interface = rt2x00mac_config_interface,
  2108. .configure_filter = rt61pci_configure_filter,
  2109. .get_stats = rt2x00mac_get_stats,
  2110. .set_retry_limit = rt61pci_set_retry_limit,
  2111. .erp_ie_changed = rt2x00mac_erp_ie_changed,
  2112. .conf_tx = rt2x00mac_conf_tx,
  2113. .get_tx_stats = rt2x00mac_get_tx_stats,
  2114. .get_tsf = rt61pci_get_tsf,
  2115. .reset_tsf = rt61pci_reset_tsf,
  2116. .beacon_update = rt61pci_beacon_update,
  2117. };
  2118. static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
  2119. .irq_handler = rt61pci_interrupt,
  2120. .probe_hw = rt61pci_probe_hw,
  2121. .get_firmware_name = rt61pci_get_firmware_name,
  2122. .load_firmware = rt61pci_load_firmware,
  2123. .initialize = rt2x00pci_initialize,
  2124. .uninitialize = rt2x00pci_uninitialize,
  2125. .set_device_state = rt61pci_set_device_state,
  2126. .rfkill_poll = rt61pci_rfkill_poll,
  2127. .link_stats = rt61pci_link_stats,
  2128. .reset_tuner = rt61pci_reset_tuner,
  2129. .link_tuner = rt61pci_link_tuner,
  2130. .write_tx_desc = rt61pci_write_tx_desc,
  2131. .write_tx_data = rt2x00pci_write_tx_data,
  2132. .kick_tx_queue = rt61pci_kick_tx_queue,
  2133. .fill_rxdone = rt61pci_fill_rxdone,
  2134. .config_mac_addr = rt61pci_config_mac_addr,
  2135. .config_bssid = rt61pci_config_bssid,
  2136. .config_type = rt61pci_config_type,
  2137. .config_preamble = rt61pci_config_preamble,
  2138. .config = rt61pci_config,
  2139. };
  2140. static const struct rt2x00_ops rt61pci_ops = {
  2141. .name = DRV_NAME,
  2142. .rxd_size = RXD_DESC_SIZE,
  2143. .txd_size = TXD_DESC_SIZE,
  2144. .eeprom_size = EEPROM_SIZE,
  2145. .rf_size = RF_SIZE,
  2146. .lib = &rt61pci_rt2x00_ops,
  2147. .hw = &rt61pci_mac80211_ops,
  2148. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  2149. .debugfs = &rt61pci_rt2x00debug,
  2150. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  2151. };
  2152. /*
  2153. * RT61pci module information.
  2154. */
  2155. static struct pci_device_id rt61pci_device_table[] = {
  2156. /* RT2561s */
  2157. { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
  2158. /* RT2561 v2 */
  2159. { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
  2160. /* RT2661 */
  2161. { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
  2162. { 0, }
  2163. };
  2164. MODULE_AUTHOR(DRV_PROJECT);
  2165. MODULE_VERSION(DRV_VERSION);
  2166. MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
  2167. MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
  2168. "PCI & PCMCIA chipset based cards");
  2169. MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
  2170. MODULE_FIRMWARE(FIRMWARE_RT2561);
  2171. MODULE_FIRMWARE(FIRMWARE_RT2561s);
  2172. MODULE_FIRMWARE(FIRMWARE_RT2661);
  2173. MODULE_LICENSE("GPL");
  2174. static struct pci_driver rt61pci_driver = {
  2175. .name = DRV_NAME,
  2176. .id_table = rt61pci_device_table,
  2177. .probe = rt2x00pci_probe,
  2178. .remove = __devexit_p(rt2x00pci_remove),
  2179. .suspend = rt2x00pci_suspend,
  2180. .resume = rt2x00pci_resume,
  2181. };
  2182. static int __init rt61pci_init(void)
  2183. {
  2184. return pci_register_driver(&rt61pci_driver);
  2185. }
  2186. static void __exit rt61pci_exit(void)
  2187. {
  2188. pci_unregister_driver(&rt61pci_driver);
  2189. }
  2190. module_init(rt61pci_init);
  2191. module_exit(rt61pci_exit);