wm8350-core.c 38 KB

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  1. /*
  2. * wm8350-core.c -- Device access for Wolfson WM8350
  3. *
  4. * Copyright 2007, 2008 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Liam Girdwood, Mark Brown
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/bug.h>
  18. #include <linux/device.h>
  19. #include <linux/delay.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/mfd/wm8350/core.h>
  23. #include <linux/mfd/wm8350/audio.h>
  24. #include <linux/mfd/wm8350/comparator.h>
  25. #include <linux/mfd/wm8350/gpio.h>
  26. #include <linux/mfd/wm8350/pmic.h>
  27. #include <linux/mfd/wm8350/rtc.h>
  28. #include <linux/mfd/wm8350/supply.h>
  29. #include <linux/mfd/wm8350/wdt.h>
  30. #define WM8350_UNLOCK_KEY 0x0013
  31. #define WM8350_LOCK_KEY 0x0000
  32. #define WM8350_CLOCK_CONTROL_1 0x28
  33. #define WM8350_AIF_TEST 0x74
  34. /* debug */
  35. #define WM8350_BUS_DEBUG 0
  36. #if WM8350_BUS_DEBUG
  37. #define dump(regs, src) do { \
  38. int i_; \
  39. u16 *src_ = src; \
  40. printk(KERN_DEBUG); \
  41. for (i_ = 0; i_ < regs; i_++) \
  42. printk(" 0x%4.4x", *src_++); \
  43. printk("\n"); \
  44. } while (0);
  45. #else
  46. #define dump(bytes, src)
  47. #endif
  48. #define WM8350_LOCK_DEBUG 0
  49. #if WM8350_LOCK_DEBUG
  50. #define ldbg(format, arg...) printk(format, ## arg)
  51. #else
  52. #define ldbg(format, arg...)
  53. #endif
  54. /*
  55. * WM8350 Device IO
  56. */
  57. static DEFINE_MUTEX(io_mutex);
  58. static DEFINE_MUTEX(reg_lock_mutex);
  59. static DEFINE_MUTEX(auxadc_mutex);
  60. /* Perform a physical read from the device.
  61. */
  62. static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
  63. u16 *dest)
  64. {
  65. int i, ret;
  66. int bytes = num_regs * 2;
  67. dev_dbg(wm8350->dev, "volatile read\n");
  68. ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
  69. for (i = reg; i < reg + num_regs; i++) {
  70. /* Cache is CPU endian */
  71. dest[i - reg] = be16_to_cpu(dest[i - reg]);
  72. /* Satisfy non-volatile bits from cache */
  73. dest[i - reg] &= wm8350_reg_io_map[i].vol;
  74. dest[i - reg] |= wm8350->reg_cache[i];
  75. /* Mask out non-readable bits */
  76. dest[i - reg] &= wm8350_reg_io_map[i].readable;
  77. }
  78. dump(num_regs, dest);
  79. return ret;
  80. }
  81. static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
  82. {
  83. int i;
  84. int end = reg + num_regs;
  85. int ret = 0;
  86. int bytes = num_regs * 2;
  87. if (wm8350->read_dev == NULL)
  88. return -ENODEV;
  89. if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
  90. dev_err(wm8350->dev, "invalid reg %x\n",
  91. reg + num_regs - 1);
  92. return -EINVAL;
  93. }
  94. dev_dbg(wm8350->dev,
  95. "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
  96. #if WM8350_BUS_DEBUG
  97. /* we can _safely_ read any register, but warn if read not supported */
  98. for (i = reg; i < end; i++) {
  99. if (!wm8350_reg_io_map[i].readable)
  100. dev_warn(wm8350->dev,
  101. "reg R%d is not readable\n", i);
  102. }
  103. #endif
  104. /* if any volatile registers are required, then read back all */
  105. for (i = reg; i < end; i++)
  106. if (wm8350_reg_io_map[i].vol)
  107. return wm8350_phys_read(wm8350, reg, num_regs, dest);
  108. /* no volatiles, then cache is good */
  109. dev_dbg(wm8350->dev, "cache read\n");
  110. memcpy(dest, &wm8350->reg_cache[reg], bytes);
  111. dump(num_regs, dest);
  112. return ret;
  113. }
  114. static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
  115. {
  116. if (reg == WM8350_SECURITY ||
  117. wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
  118. return 0;
  119. if ((reg == WM8350_GPIO_CONFIGURATION_I_O) ||
  120. (reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
  121. reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
  122. (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
  123. reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
  124. return 1;
  125. return 0;
  126. }
  127. static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
  128. {
  129. int i;
  130. int end = reg + num_regs;
  131. int bytes = num_regs * 2;
  132. if (wm8350->write_dev == NULL)
  133. return -ENODEV;
  134. if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
  135. dev_err(wm8350->dev, "invalid reg %x\n",
  136. reg + num_regs - 1);
  137. return -EINVAL;
  138. }
  139. /* it's generally not a good idea to write to RO or locked registers */
  140. for (i = reg; i < end; i++) {
  141. if (!wm8350_reg_io_map[i].writable) {
  142. dev_err(wm8350->dev,
  143. "attempted write to read only reg R%d\n", i);
  144. return -EINVAL;
  145. }
  146. if (is_reg_locked(wm8350, i)) {
  147. dev_err(wm8350->dev,
  148. "attempted write to locked reg R%d\n", i);
  149. return -EINVAL;
  150. }
  151. src[i - reg] &= wm8350_reg_io_map[i].writable;
  152. wm8350->reg_cache[i] =
  153. (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
  154. | src[i - reg];
  155. src[i - reg] = cpu_to_be16(src[i - reg]);
  156. }
  157. /* Actually write it out */
  158. return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
  159. }
  160. /*
  161. * Safe read, modify, write methods
  162. */
  163. int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
  164. {
  165. u16 data;
  166. int err;
  167. mutex_lock(&io_mutex);
  168. err = wm8350_read(wm8350, reg, 1, &data);
  169. if (err) {
  170. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  171. goto out;
  172. }
  173. data &= ~mask;
  174. err = wm8350_write(wm8350, reg, 1, &data);
  175. if (err)
  176. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  177. out:
  178. mutex_unlock(&io_mutex);
  179. return err;
  180. }
  181. EXPORT_SYMBOL_GPL(wm8350_clear_bits);
  182. int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
  183. {
  184. u16 data;
  185. int err;
  186. mutex_lock(&io_mutex);
  187. err = wm8350_read(wm8350, reg, 1, &data);
  188. if (err) {
  189. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  190. goto out;
  191. }
  192. data |= mask;
  193. err = wm8350_write(wm8350, reg, 1, &data);
  194. if (err)
  195. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  196. out:
  197. mutex_unlock(&io_mutex);
  198. return err;
  199. }
  200. EXPORT_SYMBOL_GPL(wm8350_set_bits);
  201. u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
  202. {
  203. u16 data;
  204. int err;
  205. mutex_lock(&io_mutex);
  206. err = wm8350_read(wm8350, reg, 1, &data);
  207. if (err)
  208. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  209. mutex_unlock(&io_mutex);
  210. return data;
  211. }
  212. EXPORT_SYMBOL_GPL(wm8350_reg_read);
  213. int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
  214. {
  215. int ret;
  216. u16 data = val;
  217. mutex_lock(&io_mutex);
  218. ret = wm8350_write(wm8350, reg, 1, &data);
  219. if (ret)
  220. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  221. mutex_unlock(&io_mutex);
  222. return ret;
  223. }
  224. EXPORT_SYMBOL_GPL(wm8350_reg_write);
  225. int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
  226. u16 *dest)
  227. {
  228. int err = 0;
  229. mutex_lock(&io_mutex);
  230. err = wm8350_read(wm8350, start_reg, regs, dest);
  231. if (err)
  232. dev_err(wm8350->dev, "block read starting from R%d failed\n",
  233. start_reg);
  234. mutex_unlock(&io_mutex);
  235. return err;
  236. }
  237. EXPORT_SYMBOL_GPL(wm8350_block_read);
  238. int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
  239. u16 *src)
  240. {
  241. int ret = 0;
  242. mutex_lock(&io_mutex);
  243. ret = wm8350_write(wm8350, start_reg, regs, src);
  244. if (ret)
  245. dev_err(wm8350->dev, "block write starting at R%d failed\n",
  246. start_reg);
  247. mutex_unlock(&io_mutex);
  248. return ret;
  249. }
  250. EXPORT_SYMBOL_GPL(wm8350_block_write);
  251. int wm8350_reg_lock(struct wm8350 *wm8350)
  252. {
  253. u16 key = WM8350_LOCK_KEY;
  254. int ret;
  255. ldbg(__func__);
  256. mutex_lock(&io_mutex);
  257. ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
  258. if (ret)
  259. dev_err(wm8350->dev, "lock failed\n");
  260. mutex_unlock(&io_mutex);
  261. return ret;
  262. }
  263. EXPORT_SYMBOL_GPL(wm8350_reg_lock);
  264. int wm8350_reg_unlock(struct wm8350 *wm8350)
  265. {
  266. u16 key = WM8350_UNLOCK_KEY;
  267. int ret;
  268. ldbg(__func__);
  269. mutex_lock(&io_mutex);
  270. ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
  271. if (ret)
  272. dev_err(wm8350->dev, "unlock failed\n");
  273. mutex_unlock(&io_mutex);
  274. return ret;
  275. }
  276. EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
  277. static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
  278. {
  279. mutex_lock(&wm8350->irq_mutex);
  280. if (wm8350->irq[irq].handler)
  281. wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data);
  282. else {
  283. dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n",
  284. irq);
  285. wm8350_mask_irq(wm8350, irq);
  286. }
  287. mutex_unlock(&wm8350->irq_mutex);
  288. }
  289. /*
  290. * wm8350_irq_worker actually handles the interrupts. Since all
  291. * interrupts are clear on read the IRQ line will be reasserted and
  292. * the physical IRQ will be handled again if another interrupt is
  293. * asserted while we run - in the normal course of events this is a
  294. * rare occurrence so we save I2C/SPI reads.
  295. */
  296. static void wm8350_irq_worker(struct work_struct *work)
  297. {
  298. struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work);
  299. u16 level_one, status1, status2, comp;
  300. /* TODO: Use block reads to improve performance? */
  301. level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
  302. & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
  303. status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1)
  304. & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK);
  305. status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2)
  306. & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK);
  307. comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS)
  308. & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK);
  309. /* over current */
  310. if (level_one & WM8350_OC_INT) {
  311. u16 oc;
  312. oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS);
  313. oc &= ~wm8350_reg_read(wm8350,
  314. WM8350_OVER_CURRENT_INT_STATUS_MASK);
  315. if (oc & WM8350_OC_LS_EINT) /* limit switch */
  316. wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS);
  317. }
  318. /* under voltage */
  319. if (level_one & WM8350_UV_INT) {
  320. u16 uv;
  321. uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS);
  322. uv &= ~wm8350_reg_read(wm8350,
  323. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK);
  324. if (uv & WM8350_UV_DC1_EINT)
  325. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1);
  326. if (uv & WM8350_UV_DC2_EINT)
  327. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2);
  328. if (uv & WM8350_UV_DC3_EINT)
  329. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3);
  330. if (uv & WM8350_UV_DC4_EINT)
  331. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4);
  332. if (uv & WM8350_UV_DC5_EINT)
  333. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5);
  334. if (uv & WM8350_UV_DC6_EINT)
  335. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6);
  336. if (uv & WM8350_UV_LDO1_EINT)
  337. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1);
  338. if (uv & WM8350_UV_LDO2_EINT)
  339. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2);
  340. if (uv & WM8350_UV_LDO3_EINT)
  341. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3);
  342. if (uv & WM8350_UV_LDO4_EINT)
  343. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4);
  344. }
  345. /* charger, RTC */
  346. if (status1) {
  347. if (status1 & WM8350_CHG_BAT_HOT_EINT)
  348. wm8350_irq_call_handler(wm8350,
  349. WM8350_IRQ_CHG_BAT_HOT);
  350. if (status1 & WM8350_CHG_BAT_COLD_EINT)
  351. wm8350_irq_call_handler(wm8350,
  352. WM8350_IRQ_CHG_BAT_COLD);
  353. if (status1 & WM8350_CHG_BAT_FAIL_EINT)
  354. wm8350_irq_call_handler(wm8350,
  355. WM8350_IRQ_CHG_BAT_FAIL);
  356. if (status1 & WM8350_CHG_TO_EINT)
  357. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO);
  358. if (status1 & WM8350_CHG_END_EINT)
  359. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END);
  360. if (status1 & WM8350_CHG_START_EINT)
  361. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START);
  362. if (status1 & WM8350_CHG_FAST_RDY_EINT)
  363. wm8350_irq_call_handler(wm8350,
  364. WM8350_IRQ_CHG_FAST_RDY);
  365. if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT)
  366. wm8350_irq_call_handler(wm8350,
  367. WM8350_IRQ_CHG_VBATT_LT_3P9);
  368. if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT)
  369. wm8350_irq_call_handler(wm8350,
  370. WM8350_IRQ_CHG_VBATT_LT_3P1);
  371. if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT)
  372. wm8350_irq_call_handler(wm8350,
  373. WM8350_IRQ_CHG_VBATT_LT_2P85);
  374. if (status1 & WM8350_RTC_ALM_EINT)
  375. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM);
  376. if (status1 & WM8350_RTC_SEC_EINT)
  377. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC);
  378. if (status1 & WM8350_RTC_PER_EINT)
  379. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER);
  380. }
  381. /* current sink, system, aux adc */
  382. if (status2) {
  383. if (status2 & WM8350_CS1_EINT)
  384. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1);
  385. if (status2 & WM8350_CS2_EINT)
  386. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2);
  387. if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT)
  388. wm8350_irq_call_handler(wm8350,
  389. WM8350_IRQ_SYS_HYST_COMP_FAIL);
  390. if (status2 & WM8350_SYS_CHIP_GT115_EINT)
  391. wm8350_irq_call_handler(wm8350,
  392. WM8350_IRQ_SYS_CHIP_GT115);
  393. if (status2 & WM8350_SYS_CHIP_GT140_EINT)
  394. wm8350_irq_call_handler(wm8350,
  395. WM8350_IRQ_SYS_CHIP_GT140);
  396. if (status2 & WM8350_SYS_WDOG_TO_EINT)
  397. wm8350_irq_call_handler(wm8350,
  398. WM8350_IRQ_SYS_WDOG_TO);
  399. if (status2 & WM8350_AUXADC_DATARDY_EINT)
  400. wm8350_irq_call_handler(wm8350,
  401. WM8350_IRQ_AUXADC_DATARDY);
  402. if (status2 & WM8350_AUXADC_DCOMP4_EINT)
  403. wm8350_irq_call_handler(wm8350,
  404. WM8350_IRQ_AUXADC_DCOMP4);
  405. if (status2 & WM8350_AUXADC_DCOMP3_EINT)
  406. wm8350_irq_call_handler(wm8350,
  407. WM8350_IRQ_AUXADC_DCOMP3);
  408. if (status2 & WM8350_AUXADC_DCOMP2_EINT)
  409. wm8350_irq_call_handler(wm8350,
  410. WM8350_IRQ_AUXADC_DCOMP2);
  411. if (status2 & WM8350_AUXADC_DCOMP1_EINT)
  412. wm8350_irq_call_handler(wm8350,
  413. WM8350_IRQ_AUXADC_DCOMP1);
  414. if (status2 & WM8350_USB_LIMIT_EINT)
  415. wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT);
  416. }
  417. /* wake, codec, ext */
  418. if (comp) {
  419. if (comp & WM8350_WKUP_OFF_STATE_EINT)
  420. wm8350_irq_call_handler(wm8350,
  421. WM8350_IRQ_WKUP_OFF_STATE);
  422. if (comp & WM8350_WKUP_HIB_STATE_EINT)
  423. wm8350_irq_call_handler(wm8350,
  424. WM8350_IRQ_WKUP_HIB_STATE);
  425. if (comp & WM8350_WKUP_CONV_FAULT_EINT)
  426. wm8350_irq_call_handler(wm8350,
  427. WM8350_IRQ_WKUP_CONV_FAULT);
  428. if (comp & WM8350_WKUP_WDOG_RST_EINT)
  429. wm8350_irq_call_handler(wm8350,
  430. WM8350_IRQ_WKUP_WDOG_RST);
  431. if (comp & WM8350_WKUP_GP_PWR_ON_EINT)
  432. wm8350_irq_call_handler(wm8350,
  433. WM8350_IRQ_WKUP_GP_PWR_ON);
  434. if (comp & WM8350_WKUP_ONKEY_EINT)
  435. wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY);
  436. if (comp & WM8350_WKUP_GP_WAKEUP_EINT)
  437. wm8350_irq_call_handler(wm8350,
  438. WM8350_IRQ_WKUP_GP_WAKEUP);
  439. if (comp & WM8350_CODEC_JCK_DET_L_EINT)
  440. wm8350_irq_call_handler(wm8350,
  441. WM8350_IRQ_CODEC_JCK_DET_L);
  442. if (comp & WM8350_CODEC_JCK_DET_R_EINT)
  443. wm8350_irq_call_handler(wm8350,
  444. WM8350_IRQ_CODEC_JCK_DET_R);
  445. if (comp & WM8350_CODEC_MICSCD_EINT)
  446. wm8350_irq_call_handler(wm8350,
  447. WM8350_IRQ_CODEC_MICSCD);
  448. if (comp & WM8350_CODEC_MICD_EINT)
  449. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD);
  450. if (comp & WM8350_EXT_USB_FB_EINT)
  451. wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB);
  452. if (comp & WM8350_EXT_WALL_FB_EINT)
  453. wm8350_irq_call_handler(wm8350,
  454. WM8350_IRQ_EXT_WALL_FB);
  455. if (comp & WM8350_EXT_BAT_FB_EINT)
  456. wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB);
  457. }
  458. if (level_one & WM8350_GP_INT) {
  459. int i;
  460. u16 gpio;
  461. gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS);
  462. gpio &= ~wm8350_reg_read(wm8350,
  463. WM8350_GPIO_INT_STATUS_MASK);
  464. for (i = 0; i < 12; i++) {
  465. if (gpio & (1 << i))
  466. wm8350_irq_call_handler(wm8350,
  467. WM8350_IRQ_GPIO(i));
  468. }
  469. }
  470. enable_irq(wm8350->chip_irq);
  471. }
  472. static irqreturn_t wm8350_irq(int irq, void *data)
  473. {
  474. struct wm8350 *wm8350 = data;
  475. disable_irq_nosync(irq);
  476. schedule_work(&wm8350->irq_work);
  477. return IRQ_HANDLED;
  478. }
  479. int wm8350_register_irq(struct wm8350 *wm8350, int irq,
  480. void (*handler) (struct wm8350 *, int, void *),
  481. void *data)
  482. {
  483. if (irq < 0 || irq > WM8350_NUM_IRQ || !handler)
  484. return -EINVAL;
  485. if (wm8350->irq[irq].handler)
  486. return -EBUSY;
  487. mutex_lock(&wm8350->irq_mutex);
  488. wm8350->irq[irq].handler = handler;
  489. wm8350->irq[irq].data = data;
  490. mutex_unlock(&wm8350->irq_mutex);
  491. return 0;
  492. }
  493. EXPORT_SYMBOL_GPL(wm8350_register_irq);
  494. int wm8350_free_irq(struct wm8350 *wm8350, int irq)
  495. {
  496. if (irq < 0 || irq > WM8350_NUM_IRQ)
  497. return -EINVAL;
  498. mutex_lock(&wm8350->irq_mutex);
  499. wm8350->irq[irq].handler = NULL;
  500. mutex_unlock(&wm8350->irq_mutex);
  501. return 0;
  502. }
  503. EXPORT_SYMBOL_GPL(wm8350_free_irq);
  504. int wm8350_mask_irq(struct wm8350 *wm8350, int irq)
  505. {
  506. switch (irq) {
  507. case WM8350_IRQ_CHG_BAT_HOT:
  508. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  509. WM8350_IM_CHG_BAT_HOT_EINT);
  510. case WM8350_IRQ_CHG_BAT_COLD:
  511. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  512. WM8350_IM_CHG_BAT_COLD_EINT);
  513. case WM8350_IRQ_CHG_BAT_FAIL:
  514. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  515. WM8350_IM_CHG_BAT_FAIL_EINT);
  516. case WM8350_IRQ_CHG_TO:
  517. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  518. WM8350_IM_CHG_TO_EINT);
  519. case WM8350_IRQ_CHG_END:
  520. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  521. WM8350_IM_CHG_END_EINT);
  522. case WM8350_IRQ_CHG_START:
  523. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  524. WM8350_IM_CHG_START_EINT);
  525. case WM8350_IRQ_CHG_FAST_RDY:
  526. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  527. WM8350_IM_CHG_FAST_RDY_EINT);
  528. case WM8350_IRQ_RTC_PER:
  529. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  530. WM8350_IM_RTC_PER_EINT);
  531. case WM8350_IRQ_RTC_SEC:
  532. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  533. WM8350_IM_RTC_SEC_EINT);
  534. case WM8350_IRQ_RTC_ALM:
  535. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  536. WM8350_IM_RTC_ALM_EINT);
  537. case WM8350_IRQ_CHG_VBATT_LT_3P9:
  538. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  539. WM8350_IM_CHG_VBATT_LT_3P9_EINT);
  540. case WM8350_IRQ_CHG_VBATT_LT_3P1:
  541. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  542. WM8350_IM_CHG_VBATT_LT_3P1_EINT);
  543. case WM8350_IRQ_CHG_VBATT_LT_2P85:
  544. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  545. WM8350_IM_CHG_VBATT_LT_2P85_EINT);
  546. case WM8350_IRQ_CS1:
  547. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  548. WM8350_IM_CS1_EINT);
  549. case WM8350_IRQ_CS2:
  550. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  551. WM8350_IM_CS2_EINT);
  552. case WM8350_IRQ_USB_LIMIT:
  553. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  554. WM8350_IM_USB_LIMIT_EINT);
  555. case WM8350_IRQ_AUXADC_DATARDY:
  556. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  557. WM8350_IM_AUXADC_DATARDY_EINT);
  558. case WM8350_IRQ_AUXADC_DCOMP4:
  559. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  560. WM8350_IM_AUXADC_DCOMP4_EINT);
  561. case WM8350_IRQ_AUXADC_DCOMP3:
  562. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  563. WM8350_IM_AUXADC_DCOMP3_EINT);
  564. case WM8350_IRQ_AUXADC_DCOMP2:
  565. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  566. WM8350_IM_AUXADC_DCOMP2_EINT);
  567. case WM8350_IRQ_AUXADC_DCOMP1:
  568. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  569. WM8350_IM_AUXADC_DCOMP1_EINT);
  570. case WM8350_IRQ_SYS_HYST_COMP_FAIL:
  571. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  572. WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
  573. case WM8350_IRQ_SYS_CHIP_GT115:
  574. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  575. WM8350_IM_SYS_CHIP_GT115_EINT);
  576. case WM8350_IRQ_SYS_CHIP_GT140:
  577. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  578. WM8350_IM_SYS_CHIP_GT140_EINT);
  579. case WM8350_IRQ_SYS_WDOG_TO:
  580. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  581. WM8350_IM_SYS_WDOG_TO_EINT);
  582. case WM8350_IRQ_UV_LDO4:
  583. return wm8350_set_bits(wm8350,
  584. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  585. WM8350_IM_UV_LDO4_EINT);
  586. case WM8350_IRQ_UV_LDO3:
  587. return wm8350_set_bits(wm8350,
  588. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  589. WM8350_IM_UV_LDO3_EINT);
  590. case WM8350_IRQ_UV_LDO2:
  591. return wm8350_set_bits(wm8350,
  592. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  593. WM8350_IM_UV_LDO2_EINT);
  594. case WM8350_IRQ_UV_LDO1:
  595. return wm8350_set_bits(wm8350,
  596. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  597. WM8350_IM_UV_LDO1_EINT);
  598. case WM8350_IRQ_UV_DC6:
  599. return wm8350_set_bits(wm8350,
  600. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  601. WM8350_IM_UV_DC6_EINT);
  602. case WM8350_IRQ_UV_DC5:
  603. return wm8350_set_bits(wm8350,
  604. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  605. WM8350_IM_UV_DC5_EINT);
  606. case WM8350_IRQ_UV_DC4:
  607. return wm8350_set_bits(wm8350,
  608. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  609. WM8350_IM_UV_DC4_EINT);
  610. case WM8350_IRQ_UV_DC3:
  611. return wm8350_set_bits(wm8350,
  612. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  613. WM8350_IM_UV_DC3_EINT);
  614. case WM8350_IRQ_UV_DC2:
  615. return wm8350_set_bits(wm8350,
  616. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  617. WM8350_IM_UV_DC2_EINT);
  618. case WM8350_IRQ_UV_DC1:
  619. return wm8350_set_bits(wm8350,
  620. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  621. WM8350_IM_UV_DC1_EINT);
  622. case WM8350_IRQ_OC_LS:
  623. return wm8350_set_bits(wm8350,
  624. WM8350_OVER_CURRENT_INT_STATUS_MASK,
  625. WM8350_IM_OC_LS_EINT);
  626. case WM8350_IRQ_EXT_USB_FB:
  627. return wm8350_set_bits(wm8350,
  628. WM8350_COMPARATOR_INT_STATUS_MASK,
  629. WM8350_IM_EXT_USB_FB_EINT);
  630. case WM8350_IRQ_EXT_WALL_FB:
  631. return wm8350_set_bits(wm8350,
  632. WM8350_COMPARATOR_INT_STATUS_MASK,
  633. WM8350_IM_EXT_WALL_FB_EINT);
  634. case WM8350_IRQ_EXT_BAT_FB:
  635. return wm8350_set_bits(wm8350,
  636. WM8350_COMPARATOR_INT_STATUS_MASK,
  637. WM8350_IM_EXT_BAT_FB_EINT);
  638. case WM8350_IRQ_CODEC_JCK_DET_L:
  639. return wm8350_set_bits(wm8350,
  640. WM8350_COMPARATOR_INT_STATUS_MASK,
  641. WM8350_IM_CODEC_JCK_DET_L_EINT);
  642. case WM8350_IRQ_CODEC_JCK_DET_R:
  643. return wm8350_set_bits(wm8350,
  644. WM8350_COMPARATOR_INT_STATUS_MASK,
  645. WM8350_IM_CODEC_JCK_DET_R_EINT);
  646. case WM8350_IRQ_CODEC_MICSCD:
  647. return wm8350_set_bits(wm8350,
  648. WM8350_COMPARATOR_INT_STATUS_MASK,
  649. WM8350_IM_CODEC_MICSCD_EINT);
  650. case WM8350_IRQ_CODEC_MICD:
  651. return wm8350_set_bits(wm8350,
  652. WM8350_COMPARATOR_INT_STATUS_MASK,
  653. WM8350_IM_CODEC_MICD_EINT);
  654. case WM8350_IRQ_WKUP_OFF_STATE:
  655. return wm8350_set_bits(wm8350,
  656. WM8350_COMPARATOR_INT_STATUS_MASK,
  657. WM8350_IM_WKUP_OFF_STATE_EINT);
  658. case WM8350_IRQ_WKUP_HIB_STATE:
  659. return wm8350_set_bits(wm8350,
  660. WM8350_COMPARATOR_INT_STATUS_MASK,
  661. WM8350_IM_WKUP_HIB_STATE_EINT);
  662. case WM8350_IRQ_WKUP_CONV_FAULT:
  663. return wm8350_set_bits(wm8350,
  664. WM8350_COMPARATOR_INT_STATUS_MASK,
  665. WM8350_IM_WKUP_CONV_FAULT_EINT);
  666. case WM8350_IRQ_WKUP_WDOG_RST:
  667. return wm8350_set_bits(wm8350,
  668. WM8350_COMPARATOR_INT_STATUS_MASK,
  669. WM8350_IM_WKUP_OFF_STATE_EINT);
  670. case WM8350_IRQ_WKUP_GP_PWR_ON:
  671. return wm8350_set_bits(wm8350,
  672. WM8350_COMPARATOR_INT_STATUS_MASK,
  673. WM8350_IM_WKUP_GP_PWR_ON_EINT);
  674. case WM8350_IRQ_WKUP_ONKEY:
  675. return wm8350_set_bits(wm8350,
  676. WM8350_COMPARATOR_INT_STATUS_MASK,
  677. WM8350_IM_WKUP_ONKEY_EINT);
  678. case WM8350_IRQ_WKUP_GP_WAKEUP:
  679. return wm8350_set_bits(wm8350,
  680. WM8350_COMPARATOR_INT_STATUS_MASK,
  681. WM8350_IM_WKUP_GP_WAKEUP_EINT);
  682. case WM8350_IRQ_GPIO(0):
  683. return wm8350_set_bits(wm8350,
  684. WM8350_GPIO_INT_STATUS_MASK,
  685. WM8350_IM_GP0_EINT);
  686. case WM8350_IRQ_GPIO(1):
  687. return wm8350_set_bits(wm8350,
  688. WM8350_GPIO_INT_STATUS_MASK,
  689. WM8350_IM_GP1_EINT);
  690. case WM8350_IRQ_GPIO(2):
  691. return wm8350_set_bits(wm8350,
  692. WM8350_GPIO_INT_STATUS_MASK,
  693. WM8350_IM_GP2_EINT);
  694. case WM8350_IRQ_GPIO(3):
  695. return wm8350_set_bits(wm8350,
  696. WM8350_GPIO_INT_STATUS_MASK,
  697. WM8350_IM_GP3_EINT);
  698. case WM8350_IRQ_GPIO(4):
  699. return wm8350_set_bits(wm8350,
  700. WM8350_GPIO_INT_STATUS_MASK,
  701. WM8350_IM_GP4_EINT);
  702. case WM8350_IRQ_GPIO(5):
  703. return wm8350_set_bits(wm8350,
  704. WM8350_GPIO_INT_STATUS_MASK,
  705. WM8350_IM_GP5_EINT);
  706. case WM8350_IRQ_GPIO(6):
  707. return wm8350_set_bits(wm8350,
  708. WM8350_GPIO_INT_STATUS_MASK,
  709. WM8350_IM_GP6_EINT);
  710. case WM8350_IRQ_GPIO(7):
  711. return wm8350_set_bits(wm8350,
  712. WM8350_GPIO_INT_STATUS_MASK,
  713. WM8350_IM_GP7_EINT);
  714. case WM8350_IRQ_GPIO(8):
  715. return wm8350_set_bits(wm8350,
  716. WM8350_GPIO_INT_STATUS_MASK,
  717. WM8350_IM_GP8_EINT);
  718. case WM8350_IRQ_GPIO(9):
  719. return wm8350_set_bits(wm8350,
  720. WM8350_GPIO_INT_STATUS_MASK,
  721. WM8350_IM_GP9_EINT);
  722. case WM8350_IRQ_GPIO(10):
  723. return wm8350_set_bits(wm8350,
  724. WM8350_GPIO_INT_STATUS_MASK,
  725. WM8350_IM_GP10_EINT);
  726. case WM8350_IRQ_GPIO(11):
  727. return wm8350_set_bits(wm8350,
  728. WM8350_GPIO_INT_STATUS_MASK,
  729. WM8350_IM_GP11_EINT);
  730. case WM8350_IRQ_GPIO(12):
  731. return wm8350_set_bits(wm8350,
  732. WM8350_GPIO_INT_STATUS_MASK,
  733. WM8350_IM_GP12_EINT);
  734. default:
  735. dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n",
  736. irq);
  737. return -EINVAL;
  738. }
  739. return 0;
  740. }
  741. EXPORT_SYMBOL_GPL(wm8350_mask_irq);
  742. int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
  743. {
  744. switch (irq) {
  745. case WM8350_IRQ_CHG_BAT_HOT:
  746. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  747. WM8350_IM_CHG_BAT_HOT_EINT);
  748. case WM8350_IRQ_CHG_BAT_COLD:
  749. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  750. WM8350_IM_CHG_BAT_COLD_EINT);
  751. case WM8350_IRQ_CHG_BAT_FAIL:
  752. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  753. WM8350_IM_CHG_BAT_FAIL_EINT);
  754. case WM8350_IRQ_CHG_TO:
  755. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  756. WM8350_IM_CHG_TO_EINT);
  757. case WM8350_IRQ_CHG_END:
  758. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  759. WM8350_IM_CHG_END_EINT);
  760. case WM8350_IRQ_CHG_START:
  761. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  762. WM8350_IM_CHG_START_EINT);
  763. case WM8350_IRQ_CHG_FAST_RDY:
  764. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  765. WM8350_IM_CHG_FAST_RDY_EINT);
  766. case WM8350_IRQ_RTC_PER:
  767. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  768. WM8350_IM_RTC_PER_EINT);
  769. case WM8350_IRQ_RTC_SEC:
  770. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  771. WM8350_IM_RTC_SEC_EINT);
  772. case WM8350_IRQ_RTC_ALM:
  773. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  774. WM8350_IM_RTC_ALM_EINT);
  775. case WM8350_IRQ_CHG_VBATT_LT_3P9:
  776. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  777. WM8350_IM_CHG_VBATT_LT_3P9_EINT);
  778. case WM8350_IRQ_CHG_VBATT_LT_3P1:
  779. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  780. WM8350_IM_CHG_VBATT_LT_3P1_EINT);
  781. case WM8350_IRQ_CHG_VBATT_LT_2P85:
  782. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  783. WM8350_IM_CHG_VBATT_LT_2P85_EINT);
  784. case WM8350_IRQ_CS1:
  785. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  786. WM8350_IM_CS1_EINT);
  787. case WM8350_IRQ_CS2:
  788. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  789. WM8350_IM_CS2_EINT);
  790. case WM8350_IRQ_USB_LIMIT:
  791. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  792. WM8350_IM_USB_LIMIT_EINT);
  793. case WM8350_IRQ_AUXADC_DATARDY:
  794. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  795. WM8350_IM_AUXADC_DATARDY_EINT);
  796. case WM8350_IRQ_AUXADC_DCOMP4:
  797. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  798. WM8350_IM_AUXADC_DCOMP4_EINT);
  799. case WM8350_IRQ_AUXADC_DCOMP3:
  800. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  801. WM8350_IM_AUXADC_DCOMP3_EINT);
  802. case WM8350_IRQ_AUXADC_DCOMP2:
  803. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  804. WM8350_IM_AUXADC_DCOMP2_EINT);
  805. case WM8350_IRQ_AUXADC_DCOMP1:
  806. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  807. WM8350_IM_AUXADC_DCOMP1_EINT);
  808. case WM8350_IRQ_SYS_HYST_COMP_FAIL:
  809. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  810. WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
  811. case WM8350_IRQ_SYS_CHIP_GT115:
  812. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  813. WM8350_IM_SYS_CHIP_GT115_EINT);
  814. case WM8350_IRQ_SYS_CHIP_GT140:
  815. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  816. WM8350_IM_SYS_CHIP_GT140_EINT);
  817. case WM8350_IRQ_SYS_WDOG_TO:
  818. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  819. WM8350_IM_SYS_WDOG_TO_EINT);
  820. case WM8350_IRQ_UV_LDO4:
  821. return wm8350_clear_bits(wm8350,
  822. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  823. WM8350_IM_UV_LDO4_EINT);
  824. case WM8350_IRQ_UV_LDO3:
  825. return wm8350_clear_bits(wm8350,
  826. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  827. WM8350_IM_UV_LDO3_EINT);
  828. case WM8350_IRQ_UV_LDO2:
  829. return wm8350_clear_bits(wm8350,
  830. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  831. WM8350_IM_UV_LDO2_EINT);
  832. case WM8350_IRQ_UV_LDO1:
  833. return wm8350_clear_bits(wm8350,
  834. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  835. WM8350_IM_UV_LDO1_EINT);
  836. case WM8350_IRQ_UV_DC6:
  837. return wm8350_clear_bits(wm8350,
  838. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  839. WM8350_IM_UV_DC6_EINT);
  840. case WM8350_IRQ_UV_DC5:
  841. return wm8350_clear_bits(wm8350,
  842. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  843. WM8350_IM_UV_DC5_EINT);
  844. case WM8350_IRQ_UV_DC4:
  845. return wm8350_clear_bits(wm8350,
  846. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  847. WM8350_IM_UV_DC4_EINT);
  848. case WM8350_IRQ_UV_DC3:
  849. return wm8350_clear_bits(wm8350,
  850. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  851. WM8350_IM_UV_DC3_EINT);
  852. case WM8350_IRQ_UV_DC2:
  853. return wm8350_clear_bits(wm8350,
  854. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  855. WM8350_IM_UV_DC2_EINT);
  856. case WM8350_IRQ_UV_DC1:
  857. return wm8350_clear_bits(wm8350,
  858. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  859. WM8350_IM_UV_DC1_EINT);
  860. case WM8350_IRQ_OC_LS:
  861. return wm8350_clear_bits(wm8350,
  862. WM8350_OVER_CURRENT_INT_STATUS_MASK,
  863. WM8350_IM_OC_LS_EINT);
  864. case WM8350_IRQ_EXT_USB_FB:
  865. return wm8350_clear_bits(wm8350,
  866. WM8350_COMPARATOR_INT_STATUS_MASK,
  867. WM8350_IM_EXT_USB_FB_EINT);
  868. case WM8350_IRQ_EXT_WALL_FB:
  869. return wm8350_clear_bits(wm8350,
  870. WM8350_COMPARATOR_INT_STATUS_MASK,
  871. WM8350_IM_EXT_WALL_FB_EINT);
  872. case WM8350_IRQ_EXT_BAT_FB:
  873. return wm8350_clear_bits(wm8350,
  874. WM8350_COMPARATOR_INT_STATUS_MASK,
  875. WM8350_IM_EXT_BAT_FB_EINT);
  876. case WM8350_IRQ_CODEC_JCK_DET_L:
  877. return wm8350_clear_bits(wm8350,
  878. WM8350_COMPARATOR_INT_STATUS_MASK,
  879. WM8350_IM_CODEC_JCK_DET_L_EINT);
  880. case WM8350_IRQ_CODEC_JCK_DET_R:
  881. return wm8350_clear_bits(wm8350,
  882. WM8350_COMPARATOR_INT_STATUS_MASK,
  883. WM8350_IM_CODEC_JCK_DET_R_EINT);
  884. case WM8350_IRQ_CODEC_MICSCD:
  885. return wm8350_clear_bits(wm8350,
  886. WM8350_COMPARATOR_INT_STATUS_MASK,
  887. WM8350_IM_CODEC_MICSCD_EINT);
  888. case WM8350_IRQ_CODEC_MICD:
  889. return wm8350_clear_bits(wm8350,
  890. WM8350_COMPARATOR_INT_STATUS_MASK,
  891. WM8350_IM_CODEC_MICD_EINT);
  892. case WM8350_IRQ_WKUP_OFF_STATE:
  893. return wm8350_clear_bits(wm8350,
  894. WM8350_COMPARATOR_INT_STATUS_MASK,
  895. WM8350_IM_WKUP_OFF_STATE_EINT);
  896. case WM8350_IRQ_WKUP_HIB_STATE:
  897. return wm8350_clear_bits(wm8350,
  898. WM8350_COMPARATOR_INT_STATUS_MASK,
  899. WM8350_IM_WKUP_HIB_STATE_EINT);
  900. case WM8350_IRQ_WKUP_CONV_FAULT:
  901. return wm8350_clear_bits(wm8350,
  902. WM8350_COMPARATOR_INT_STATUS_MASK,
  903. WM8350_IM_WKUP_CONV_FAULT_EINT);
  904. case WM8350_IRQ_WKUP_WDOG_RST:
  905. return wm8350_clear_bits(wm8350,
  906. WM8350_COMPARATOR_INT_STATUS_MASK,
  907. WM8350_IM_WKUP_OFF_STATE_EINT);
  908. case WM8350_IRQ_WKUP_GP_PWR_ON:
  909. return wm8350_clear_bits(wm8350,
  910. WM8350_COMPARATOR_INT_STATUS_MASK,
  911. WM8350_IM_WKUP_GP_PWR_ON_EINT);
  912. case WM8350_IRQ_WKUP_ONKEY:
  913. return wm8350_clear_bits(wm8350,
  914. WM8350_COMPARATOR_INT_STATUS_MASK,
  915. WM8350_IM_WKUP_ONKEY_EINT);
  916. case WM8350_IRQ_WKUP_GP_WAKEUP:
  917. return wm8350_clear_bits(wm8350,
  918. WM8350_COMPARATOR_INT_STATUS_MASK,
  919. WM8350_IM_WKUP_GP_WAKEUP_EINT);
  920. case WM8350_IRQ_GPIO(0):
  921. return wm8350_clear_bits(wm8350,
  922. WM8350_GPIO_INT_STATUS_MASK,
  923. WM8350_IM_GP0_EINT);
  924. case WM8350_IRQ_GPIO(1):
  925. return wm8350_clear_bits(wm8350,
  926. WM8350_GPIO_INT_STATUS_MASK,
  927. WM8350_IM_GP1_EINT);
  928. case WM8350_IRQ_GPIO(2):
  929. return wm8350_clear_bits(wm8350,
  930. WM8350_GPIO_INT_STATUS_MASK,
  931. WM8350_IM_GP2_EINT);
  932. case WM8350_IRQ_GPIO(3):
  933. return wm8350_clear_bits(wm8350,
  934. WM8350_GPIO_INT_STATUS_MASK,
  935. WM8350_IM_GP3_EINT);
  936. case WM8350_IRQ_GPIO(4):
  937. return wm8350_clear_bits(wm8350,
  938. WM8350_GPIO_INT_STATUS_MASK,
  939. WM8350_IM_GP4_EINT);
  940. case WM8350_IRQ_GPIO(5):
  941. return wm8350_clear_bits(wm8350,
  942. WM8350_GPIO_INT_STATUS_MASK,
  943. WM8350_IM_GP5_EINT);
  944. case WM8350_IRQ_GPIO(6):
  945. return wm8350_clear_bits(wm8350,
  946. WM8350_GPIO_INT_STATUS_MASK,
  947. WM8350_IM_GP6_EINT);
  948. case WM8350_IRQ_GPIO(7):
  949. return wm8350_clear_bits(wm8350,
  950. WM8350_GPIO_INT_STATUS_MASK,
  951. WM8350_IM_GP7_EINT);
  952. case WM8350_IRQ_GPIO(8):
  953. return wm8350_clear_bits(wm8350,
  954. WM8350_GPIO_INT_STATUS_MASK,
  955. WM8350_IM_GP8_EINT);
  956. case WM8350_IRQ_GPIO(9):
  957. return wm8350_clear_bits(wm8350,
  958. WM8350_GPIO_INT_STATUS_MASK,
  959. WM8350_IM_GP9_EINT);
  960. case WM8350_IRQ_GPIO(10):
  961. return wm8350_clear_bits(wm8350,
  962. WM8350_GPIO_INT_STATUS_MASK,
  963. WM8350_IM_GP10_EINT);
  964. case WM8350_IRQ_GPIO(11):
  965. return wm8350_clear_bits(wm8350,
  966. WM8350_GPIO_INT_STATUS_MASK,
  967. WM8350_IM_GP11_EINT);
  968. case WM8350_IRQ_GPIO(12):
  969. return wm8350_clear_bits(wm8350,
  970. WM8350_GPIO_INT_STATUS_MASK,
  971. WM8350_IM_GP12_EINT);
  972. default:
  973. dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n",
  974. irq);
  975. return -EINVAL;
  976. }
  977. return 0;
  978. }
  979. EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
  980. /*
  981. * Cache is always host endian.
  982. */
  983. static int wm8350_create_cache(struct wm8350 *wm8350, int mode)
  984. {
  985. int i, ret = 0;
  986. u16 value;
  987. const u16 *reg_map;
  988. switch (mode) {
  989. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
  990. case 0:
  991. reg_map = wm8350_mode0_defaults;
  992. break;
  993. #endif
  994. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
  995. case 1:
  996. reg_map = wm8350_mode1_defaults;
  997. break;
  998. #endif
  999. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
  1000. case 2:
  1001. reg_map = wm8350_mode2_defaults;
  1002. break;
  1003. #endif
  1004. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
  1005. case 3:
  1006. reg_map = wm8350_mode3_defaults;
  1007. break;
  1008. #endif
  1009. default:
  1010. dev_err(wm8350->dev, "Configuration mode %d not supported\n",
  1011. mode);
  1012. return -EINVAL;
  1013. }
  1014. wm8350->reg_cache =
  1015. kzalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
  1016. if (wm8350->reg_cache == NULL)
  1017. return -ENOMEM;
  1018. /* Read the initial cache state back from the device - this is
  1019. * a PMIC so the device many not be in a virgin state and we
  1020. * can't rely on the silicon values.
  1021. */
  1022. for (i = 0; i < WM8350_MAX_REGISTER; i++) {
  1023. /* audio register range */
  1024. if (wm8350_reg_io_map[i].readable &&
  1025. (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
  1026. ret = wm8350->read_dev(wm8350, i, 2, (char *)&value);
  1027. if (ret < 0) {
  1028. dev_err(wm8350->dev,
  1029. "failed to read initial cache value\n");
  1030. goto out;
  1031. }
  1032. value = be16_to_cpu(value);
  1033. value &= wm8350_reg_io_map[i].readable;
  1034. wm8350->reg_cache[i] = value;
  1035. } else
  1036. wm8350->reg_cache[i] = reg_map[i];
  1037. }
  1038. out:
  1039. return ret;
  1040. }
  1041. EXPORT_SYMBOL_GPL(wm8350_create_cache);
  1042. /*
  1043. * Register a client device. This is non-fatal since there is no need to
  1044. * fail the entire device init due to a single platform device failing.
  1045. */
  1046. static void wm8350_client_dev_register(struct wm8350 *wm8350,
  1047. const char *name,
  1048. struct platform_device **pdev)
  1049. {
  1050. int ret;
  1051. *pdev = platform_device_alloc(name, -1);
  1052. if (pdev == NULL) {
  1053. dev_err(wm8350->dev, "Failed to allocate %s\n", name);
  1054. return;
  1055. }
  1056. (*pdev)->dev.parent = wm8350->dev;
  1057. platform_set_drvdata(*pdev, wm8350);
  1058. ret = platform_device_add(*pdev);
  1059. if (ret != 0) {
  1060. dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
  1061. platform_device_put(*pdev);
  1062. *pdev = NULL;
  1063. }
  1064. }
  1065. int wm8350_device_init(struct wm8350 *wm8350, int irq,
  1066. struct wm8350_platform_data *pdata)
  1067. {
  1068. int ret = -EINVAL;
  1069. u16 id1, id2, mask, mode;
  1070. int i;
  1071. /* get WM8350 revision and config mode */
  1072. wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
  1073. wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
  1074. id1 = be16_to_cpu(id1);
  1075. id2 = be16_to_cpu(id2);
  1076. if (id1 == 0x6143) {
  1077. switch ((id2 & WM8350_CHIP_REV_MASK) >> 12) {
  1078. case WM8350_REV_E:
  1079. dev_info(wm8350->dev, "Found Rev E device\n");
  1080. wm8350->rev = WM8350_REV_E;
  1081. break;
  1082. case WM8350_REV_F:
  1083. dev_info(wm8350->dev, "Found Rev F device\n");
  1084. wm8350->rev = WM8350_REV_F;
  1085. break;
  1086. case WM8350_REV_G:
  1087. dev_info(wm8350->dev, "Found Rev G device\n");
  1088. wm8350->rev = WM8350_REV_G;
  1089. break;
  1090. default:
  1091. /* For safety we refuse to run on unknown hardware */
  1092. dev_info(wm8350->dev, "Found unknown rev\n");
  1093. ret = -ENODEV;
  1094. goto err;
  1095. }
  1096. } else {
  1097. dev_info(wm8350->dev, "Device with ID %x is not a WM8350\n",
  1098. id1);
  1099. ret = -ENODEV;
  1100. goto err;
  1101. }
  1102. mode = id2 & WM8350_CONF_STS_MASK >> 10;
  1103. mask = id2 & WM8350_CUST_ID_MASK;
  1104. dev_info(wm8350->dev, "Config mode %d, ROM mask %d\n", mode, mask);
  1105. ret = wm8350_create_cache(wm8350, mode);
  1106. if (ret < 0) {
  1107. printk(KERN_ERR "wm8350: failed to create register cache\n");
  1108. return ret;
  1109. }
  1110. if (pdata->init) {
  1111. ret = pdata->init(wm8350);
  1112. if (ret != 0) {
  1113. dev_err(wm8350->dev, "Platform init() failed: %d\n",
  1114. ret);
  1115. goto err;
  1116. }
  1117. }
  1118. mutex_init(&wm8350->irq_mutex);
  1119. INIT_WORK(&wm8350->irq_work, wm8350_irq_worker);
  1120. if (irq != NO_IRQ) {
  1121. ret = request_irq(irq, wm8350_irq, 0,
  1122. "wm8350", wm8350);
  1123. if (ret != 0) {
  1124. dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
  1125. ret);
  1126. goto err;
  1127. }
  1128. } else {
  1129. dev_err(wm8350->dev, "No IRQ configured\n");
  1130. goto err;
  1131. }
  1132. wm8350->chip_irq = irq;
  1133. wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
  1134. wm8350_client_dev_register(wm8350, "wm8350-codec",
  1135. &(wm8350->codec.pdev));
  1136. wm8350_client_dev_register(wm8350, "wm8350-gpio",
  1137. &(wm8350->gpio.pdev));
  1138. wm8350_client_dev_register(wm8350, "wm8350-power",
  1139. &(wm8350->power.pdev));
  1140. wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
  1141. wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
  1142. return 0;
  1143. err:
  1144. kfree(wm8350->reg_cache);
  1145. return ret;
  1146. }
  1147. EXPORT_SYMBOL_GPL(wm8350_device_init);
  1148. void wm8350_device_exit(struct wm8350 *wm8350)
  1149. {
  1150. int i;
  1151. for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
  1152. platform_device_unregister(wm8350->pmic.pdev[i]);
  1153. platform_device_unregister(wm8350->wdt.pdev);
  1154. platform_device_unregister(wm8350->rtc.pdev);
  1155. platform_device_unregister(wm8350->power.pdev);
  1156. platform_device_unregister(wm8350->gpio.pdev);
  1157. platform_device_unregister(wm8350->codec.pdev);
  1158. free_irq(wm8350->chip_irq, wm8350);
  1159. flush_work(&wm8350->irq_work);
  1160. kfree(wm8350->reg_cache);
  1161. }
  1162. EXPORT_SYMBOL_GPL(wm8350_device_exit);
  1163. MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
  1164. MODULE_LICENSE("GPL");