i915_debugfs.c 33 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150
  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "intel_drv.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #define DRM_I915_RING_DEBUG 1
  37. #if defined(CONFIG_DEBUG_FS)
  38. enum {
  39. ACTIVE_LIST,
  40. FLUSHING_LIST,
  41. INACTIVE_LIST,
  42. PINNED_LIST,
  43. DEFERRED_FREE_LIST,
  44. };
  45. enum {
  46. RENDER_RING,
  47. BSD_RING,
  48. BLT_RING,
  49. };
  50. static const char *yesno(int v)
  51. {
  52. return v ? "yes" : "no";
  53. }
  54. static int i915_capabilities(struct seq_file *m, void *data)
  55. {
  56. struct drm_info_node *node = (struct drm_info_node *) m->private;
  57. struct drm_device *dev = node->minor->dev;
  58. const struct intel_device_info *info = INTEL_INFO(dev);
  59. seq_printf(m, "gen: %d\n", info->gen);
  60. #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  61. B(is_mobile);
  62. B(is_i85x);
  63. B(is_i915g);
  64. B(is_i945gm);
  65. B(is_g33);
  66. B(need_gfx_hws);
  67. B(is_g4x);
  68. B(is_pineview);
  69. B(is_broadwater);
  70. B(is_crestline);
  71. B(has_fbc);
  72. B(has_rc6);
  73. B(has_pipe_cxsr);
  74. B(has_hotplug);
  75. B(cursor_needs_physical);
  76. B(has_overlay);
  77. B(overlay_needs_physical);
  78. B(supports_tv);
  79. B(has_bsd_ring);
  80. B(has_blt_ring);
  81. #undef B
  82. return 0;
  83. }
  84. static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
  85. {
  86. if (obj_priv->user_pin_count > 0)
  87. return "P";
  88. else if (obj_priv->pin_count > 0)
  89. return "p";
  90. else
  91. return " ";
  92. }
  93. static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
  94. {
  95. switch (obj_priv->tiling_mode) {
  96. default:
  97. case I915_TILING_NONE: return " ";
  98. case I915_TILING_X: return "X";
  99. case I915_TILING_Y: return "Y";
  100. }
  101. }
  102. static void
  103. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  104. {
  105. seq_printf(m, "%p: %s%s %8zd %08x %08x %d%s%s",
  106. &obj->base,
  107. get_pin_flag(obj),
  108. get_tiling_flag(obj),
  109. obj->base.size,
  110. obj->base.read_domains,
  111. obj->base.write_domain,
  112. obj->last_rendering_seqno,
  113. obj->dirty ? " dirty" : "",
  114. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  115. if (obj->base.name)
  116. seq_printf(m, " (name: %d)", obj->base.name);
  117. if (obj->fence_reg != I915_FENCE_REG_NONE)
  118. seq_printf(m, " (fence: %d)", obj->fence_reg);
  119. if (obj->gtt_space != NULL)
  120. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  121. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  122. if (obj->pin_mappable || obj->fault_mappable)
  123. seq_printf(m, " (mappable)");
  124. if (obj->ring != NULL)
  125. seq_printf(m, " (%s)", obj->ring->name);
  126. }
  127. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  128. {
  129. struct drm_info_node *node = (struct drm_info_node *) m->private;
  130. uintptr_t list = (uintptr_t) node->info_ent->data;
  131. struct list_head *head;
  132. struct drm_device *dev = node->minor->dev;
  133. drm_i915_private_t *dev_priv = dev->dev_private;
  134. struct drm_i915_gem_object *obj_priv;
  135. size_t total_obj_size, total_gtt_size;
  136. int count, ret;
  137. ret = mutex_lock_interruptible(&dev->struct_mutex);
  138. if (ret)
  139. return ret;
  140. switch (list) {
  141. case ACTIVE_LIST:
  142. seq_printf(m, "Active:\n");
  143. head = &dev_priv->mm.active_list;
  144. break;
  145. case INACTIVE_LIST:
  146. seq_printf(m, "Inactive:\n");
  147. head = &dev_priv->mm.inactive_list;
  148. break;
  149. case PINNED_LIST:
  150. seq_printf(m, "Pinned:\n");
  151. head = &dev_priv->mm.pinned_list;
  152. break;
  153. case FLUSHING_LIST:
  154. seq_printf(m, "Flushing:\n");
  155. head = &dev_priv->mm.flushing_list;
  156. break;
  157. case DEFERRED_FREE_LIST:
  158. seq_printf(m, "Deferred free:\n");
  159. head = &dev_priv->mm.deferred_free_list;
  160. break;
  161. default:
  162. mutex_unlock(&dev->struct_mutex);
  163. return -EINVAL;
  164. }
  165. total_obj_size = total_gtt_size = count = 0;
  166. list_for_each_entry(obj_priv, head, mm_list) {
  167. seq_printf(m, " ");
  168. describe_obj(m, obj_priv);
  169. seq_printf(m, "\n");
  170. total_obj_size += obj_priv->base.size;
  171. total_gtt_size += obj_priv->gtt_space->size;
  172. count++;
  173. }
  174. mutex_unlock(&dev->struct_mutex);
  175. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  176. count, total_obj_size, total_gtt_size);
  177. return 0;
  178. }
  179. static int i915_gem_object_info(struct seq_file *m, void* data)
  180. {
  181. struct drm_info_node *node = (struct drm_info_node *) m->private;
  182. struct drm_device *dev = node->minor->dev;
  183. struct drm_i915_private *dev_priv = dev->dev_private;
  184. int ret;
  185. ret = mutex_lock_interruptible(&dev->struct_mutex);
  186. if (ret)
  187. return ret;
  188. seq_printf(m, "%u objects\n", dev_priv->mm.object_count);
  189. seq_printf(m, "%zu object bytes\n", dev_priv->mm.object_memory);
  190. seq_printf(m, "%u pinned\n", dev_priv->mm.pin_count);
  191. seq_printf(m, "%zu pin bytes\n", dev_priv->mm.pin_memory);
  192. seq_printf(m, "%u mappable objects in gtt\n", dev_priv->mm.gtt_mappable_count);
  193. seq_printf(m, "%zu mappable gtt bytes\n", dev_priv->mm.gtt_mappable_memory);
  194. seq_printf(m, "%zu mappable gtt used bytes\n", dev_priv->mm.mappable_gtt_used);
  195. seq_printf(m, "%zu mappable gtt total\n", dev_priv->mm.mappable_gtt_total);
  196. seq_printf(m, "%u objects in gtt\n", dev_priv->mm.gtt_count);
  197. seq_printf(m, "%zu gtt bytes\n", dev_priv->mm.gtt_memory);
  198. seq_printf(m, "%zu gtt total\n", dev_priv->mm.gtt_total);
  199. mutex_unlock(&dev->struct_mutex);
  200. return 0;
  201. }
  202. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  203. {
  204. struct drm_info_node *node = (struct drm_info_node *) m->private;
  205. struct drm_device *dev = node->minor->dev;
  206. unsigned long flags;
  207. struct intel_crtc *crtc;
  208. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  209. const char *pipe = crtc->pipe ? "B" : "A";
  210. const char *plane = crtc->plane ? "B" : "A";
  211. struct intel_unpin_work *work;
  212. spin_lock_irqsave(&dev->event_lock, flags);
  213. work = crtc->unpin_work;
  214. if (work == NULL) {
  215. seq_printf(m, "No flip due on pipe %s (plane %s)\n",
  216. pipe, plane);
  217. } else {
  218. if (!work->pending) {
  219. seq_printf(m, "Flip queued on pipe %s (plane %s)\n",
  220. pipe, plane);
  221. } else {
  222. seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",
  223. pipe, plane);
  224. }
  225. if (work->enable_stall_check)
  226. seq_printf(m, "Stall check enabled, ");
  227. else
  228. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  229. seq_printf(m, "%d prepares\n", work->pending);
  230. if (work->old_fb_obj) {
  231. struct drm_i915_gem_object *obj_priv = to_intel_bo(work->old_fb_obj);
  232. if(obj_priv)
  233. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
  234. }
  235. if (work->pending_flip_obj) {
  236. struct drm_i915_gem_object *obj_priv = to_intel_bo(work->pending_flip_obj);
  237. if(obj_priv)
  238. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
  239. }
  240. }
  241. spin_unlock_irqrestore(&dev->event_lock, flags);
  242. }
  243. return 0;
  244. }
  245. static int i915_gem_request_info(struct seq_file *m, void *data)
  246. {
  247. struct drm_info_node *node = (struct drm_info_node *) m->private;
  248. struct drm_device *dev = node->minor->dev;
  249. drm_i915_private_t *dev_priv = dev->dev_private;
  250. struct drm_i915_gem_request *gem_request;
  251. int ret, count;
  252. ret = mutex_lock_interruptible(&dev->struct_mutex);
  253. if (ret)
  254. return ret;
  255. count = 0;
  256. if (!list_empty(&dev_priv->render_ring.request_list)) {
  257. seq_printf(m, "Render requests:\n");
  258. list_for_each_entry(gem_request,
  259. &dev_priv->render_ring.request_list,
  260. list) {
  261. seq_printf(m, " %d @ %d\n",
  262. gem_request->seqno,
  263. (int) (jiffies - gem_request->emitted_jiffies));
  264. }
  265. count++;
  266. }
  267. if (!list_empty(&dev_priv->bsd_ring.request_list)) {
  268. seq_printf(m, "BSD requests:\n");
  269. list_for_each_entry(gem_request,
  270. &dev_priv->bsd_ring.request_list,
  271. list) {
  272. seq_printf(m, " %d @ %d\n",
  273. gem_request->seqno,
  274. (int) (jiffies - gem_request->emitted_jiffies));
  275. }
  276. count++;
  277. }
  278. if (!list_empty(&dev_priv->blt_ring.request_list)) {
  279. seq_printf(m, "BLT requests:\n");
  280. list_for_each_entry(gem_request,
  281. &dev_priv->blt_ring.request_list,
  282. list) {
  283. seq_printf(m, " %d @ %d\n",
  284. gem_request->seqno,
  285. (int) (jiffies - gem_request->emitted_jiffies));
  286. }
  287. count++;
  288. }
  289. mutex_unlock(&dev->struct_mutex);
  290. if (count == 0)
  291. seq_printf(m, "No requests\n");
  292. return 0;
  293. }
  294. static void i915_ring_seqno_info(struct seq_file *m,
  295. struct intel_ring_buffer *ring)
  296. {
  297. if (ring->get_seqno) {
  298. seq_printf(m, "Current sequence (%s): %d\n",
  299. ring->name, ring->get_seqno(ring));
  300. seq_printf(m, "Waiter sequence (%s): %d\n",
  301. ring->name, ring->waiting_seqno);
  302. seq_printf(m, "IRQ sequence (%s): %d\n",
  303. ring->name, ring->irq_seqno);
  304. }
  305. }
  306. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  307. {
  308. struct drm_info_node *node = (struct drm_info_node *) m->private;
  309. struct drm_device *dev = node->minor->dev;
  310. drm_i915_private_t *dev_priv = dev->dev_private;
  311. int ret;
  312. ret = mutex_lock_interruptible(&dev->struct_mutex);
  313. if (ret)
  314. return ret;
  315. i915_ring_seqno_info(m, &dev_priv->render_ring);
  316. i915_ring_seqno_info(m, &dev_priv->bsd_ring);
  317. i915_ring_seqno_info(m, &dev_priv->blt_ring);
  318. mutex_unlock(&dev->struct_mutex);
  319. return 0;
  320. }
  321. static int i915_interrupt_info(struct seq_file *m, void *data)
  322. {
  323. struct drm_info_node *node = (struct drm_info_node *) m->private;
  324. struct drm_device *dev = node->minor->dev;
  325. drm_i915_private_t *dev_priv = dev->dev_private;
  326. int ret;
  327. ret = mutex_lock_interruptible(&dev->struct_mutex);
  328. if (ret)
  329. return ret;
  330. if (!HAS_PCH_SPLIT(dev)) {
  331. seq_printf(m, "Interrupt enable: %08x\n",
  332. I915_READ(IER));
  333. seq_printf(m, "Interrupt identity: %08x\n",
  334. I915_READ(IIR));
  335. seq_printf(m, "Interrupt mask: %08x\n",
  336. I915_READ(IMR));
  337. seq_printf(m, "Pipe A stat: %08x\n",
  338. I915_READ(PIPEASTAT));
  339. seq_printf(m, "Pipe B stat: %08x\n",
  340. I915_READ(PIPEBSTAT));
  341. } else {
  342. seq_printf(m, "North Display Interrupt enable: %08x\n",
  343. I915_READ(DEIER));
  344. seq_printf(m, "North Display Interrupt identity: %08x\n",
  345. I915_READ(DEIIR));
  346. seq_printf(m, "North Display Interrupt mask: %08x\n",
  347. I915_READ(DEIMR));
  348. seq_printf(m, "South Display Interrupt enable: %08x\n",
  349. I915_READ(SDEIER));
  350. seq_printf(m, "South Display Interrupt identity: %08x\n",
  351. I915_READ(SDEIIR));
  352. seq_printf(m, "South Display Interrupt mask: %08x\n",
  353. I915_READ(SDEIMR));
  354. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  355. I915_READ(GTIER));
  356. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  357. I915_READ(GTIIR));
  358. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  359. I915_READ(GTIMR));
  360. }
  361. seq_printf(m, "Interrupts received: %d\n",
  362. atomic_read(&dev_priv->irq_received));
  363. i915_ring_seqno_info(m, &dev_priv->render_ring);
  364. i915_ring_seqno_info(m, &dev_priv->bsd_ring);
  365. i915_ring_seqno_info(m, &dev_priv->blt_ring);
  366. mutex_unlock(&dev->struct_mutex);
  367. return 0;
  368. }
  369. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  370. {
  371. struct drm_info_node *node = (struct drm_info_node *) m->private;
  372. struct drm_device *dev = node->minor->dev;
  373. drm_i915_private_t *dev_priv = dev->dev_private;
  374. int i, ret;
  375. ret = mutex_lock_interruptible(&dev->struct_mutex);
  376. if (ret)
  377. return ret;
  378. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  379. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  380. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  381. struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
  382. seq_printf(m, "Fenced object[%2d] = ", i);
  383. if (obj == NULL)
  384. seq_printf(m, "unused");
  385. else
  386. describe_obj(m, to_intel_bo(obj));
  387. seq_printf(m, "\n");
  388. }
  389. mutex_unlock(&dev->struct_mutex);
  390. return 0;
  391. }
  392. static int i915_hws_info(struct seq_file *m, void *data)
  393. {
  394. struct drm_info_node *node = (struct drm_info_node *) m->private;
  395. struct drm_device *dev = node->minor->dev;
  396. drm_i915_private_t *dev_priv = dev->dev_private;
  397. struct intel_ring_buffer *ring;
  398. volatile u32 *hws;
  399. int i;
  400. switch ((uintptr_t)node->info_ent->data) {
  401. case RENDER_RING: ring = &dev_priv->render_ring; break;
  402. case BSD_RING: ring = &dev_priv->bsd_ring; break;
  403. case BLT_RING: ring = &dev_priv->blt_ring; break;
  404. default: return -EINVAL;
  405. }
  406. hws = (volatile u32 *)ring->status_page.page_addr;
  407. if (hws == NULL)
  408. return 0;
  409. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  410. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  411. i * 4,
  412. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  413. }
  414. return 0;
  415. }
  416. static void i915_dump_object(struct seq_file *m,
  417. struct io_mapping *mapping,
  418. struct drm_i915_gem_object *obj_priv)
  419. {
  420. int page, page_count, i;
  421. page_count = obj_priv->base.size / PAGE_SIZE;
  422. for (page = 0; page < page_count; page++) {
  423. u32 *mem = io_mapping_map_wc(mapping,
  424. obj_priv->gtt_offset + page * PAGE_SIZE);
  425. for (i = 0; i < PAGE_SIZE; i += 4)
  426. seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
  427. io_mapping_unmap(mem);
  428. }
  429. }
  430. static int i915_batchbuffer_info(struct seq_file *m, void *data)
  431. {
  432. struct drm_info_node *node = (struct drm_info_node *) m->private;
  433. struct drm_device *dev = node->minor->dev;
  434. drm_i915_private_t *dev_priv = dev->dev_private;
  435. struct drm_gem_object *obj;
  436. struct drm_i915_gem_object *obj_priv;
  437. int ret;
  438. ret = mutex_lock_interruptible(&dev->struct_mutex);
  439. if (ret)
  440. return ret;
  441. list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
  442. obj = &obj_priv->base;
  443. if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
  444. seq_printf(m, "--- gtt_offset = 0x%08x\n",
  445. obj_priv->gtt_offset);
  446. i915_dump_object(m, dev_priv->mm.gtt_mapping, obj_priv);
  447. }
  448. }
  449. mutex_unlock(&dev->struct_mutex);
  450. return 0;
  451. }
  452. static int i915_ringbuffer_data(struct seq_file *m, void *data)
  453. {
  454. struct drm_info_node *node = (struct drm_info_node *) m->private;
  455. struct drm_device *dev = node->minor->dev;
  456. drm_i915_private_t *dev_priv = dev->dev_private;
  457. struct intel_ring_buffer *ring;
  458. int ret;
  459. switch ((uintptr_t)node->info_ent->data) {
  460. case RENDER_RING: ring = &dev_priv->render_ring; break;
  461. case BSD_RING: ring = &dev_priv->bsd_ring; break;
  462. case BLT_RING: ring = &dev_priv->blt_ring; break;
  463. default: return -EINVAL;
  464. }
  465. ret = mutex_lock_interruptible(&dev->struct_mutex);
  466. if (ret)
  467. return ret;
  468. if (!ring->gem_object) {
  469. seq_printf(m, "No ringbuffer setup\n");
  470. } else {
  471. u8 *virt = ring->virtual_start;
  472. uint32_t off;
  473. for (off = 0; off < ring->size; off += 4) {
  474. uint32_t *ptr = (uint32_t *)(virt + off);
  475. seq_printf(m, "%08x : %08x\n", off, *ptr);
  476. }
  477. }
  478. mutex_unlock(&dev->struct_mutex);
  479. return 0;
  480. }
  481. static int i915_ringbuffer_info(struct seq_file *m, void *data)
  482. {
  483. struct drm_info_node *node = (struct drm_info_node *) m->private;
  484. struct drm_device *dev = node->minor->dev;
  485. drm_i915_private_t *dev_priv = dev->dev_private;
  486. struct intel_ring_buffer *ring;
  487. switch ((uintptr_t)node->info_ent->data) {
  488. case RENDER_RING: ring = &dev_priv->render_ring; break;
  489. case BSD_RING: ring = &dev_priv->bsd_ring; break;
  490. case BLT_RING: ring = &dev_priv->blt_ring; break;
  491. default: return -EINVAL;
  492. }
  493. if (ring->size == 0)
  494. return 0;
  495. seq_printf(m, "Ring %s:\n", ring->name);
  496. seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
  497. seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
  498. seq_printf(m, " Size : %08x\n", ring->size);
  499. seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
  500. seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
  501. seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
  502. return 0;
  503. }
  504. static const char *pin_flag(int pinned)
  505. {
  506. if (pinned > 0)
  507. return " P";
  508. else if (pinned < 0)
  509. return " p";
  510. else
  511. return "";
  512. }
  513. static const char *tiling_flag(int tiling)
  514. {
  515. switch (tiling) {
  516. default:
  517. case I915_TILING_NONE: return "";
  518. case I915_TILING_X: return " X";
  519. case I915_TILING_Y: return " Y";
  520. }
  521. }
  522. static const char *dirty_flag(int dirty)
  523. {
  524. return dirty ? " dirty" : "";
  525. }
  526. static const char *purgeable_flag(int purgeable)
  527. {
  528. return purgeable ? " purgeable" : "";
  529. }
  530. static int i915_error_state(struct seq_file *m, void *unused)
  531. {
  532. struct drm_info_node *node = (struct drm_info_node *) m->private;
  533. struct drm_device *dev = node->minor->dev;
  534. drm_i915_private_t *dev_priv = dev->dev_private;
  535. struct drm_i915_error_state *error;
  536. unsigned long flags;
  537. int i, page, offset, elt;
  538. spin_lock_irqsave(&dev_priv->error_lock, flags);
  539. if (!dev_priv->first_error) {
  540. seq_printf(m, "no error state collected\n");
  541. goto out;
  542. }
  543. error = dev_priv->first_error;
  544. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  545. error->time.tv_usec);
  546. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  547. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  548. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  549. if (INTEL_INFO(dev)->gen >= 6) {
  550. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  551. seq_printf(m, "Blitter command stream:\n");
  552. seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
  553. seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
  554. seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
  555. seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
  556. seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
  557. seq_printf(m, "Video (BSD) command stream:\n");
  558. seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
  559. seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
  560. seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
  561. seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
  562. seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
  563. }
  564. seq_printf(m, "Render command stream:\n");
  565. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
  566. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
  567. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
  568. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
  569. if (INTEL_INFO(dev)->gen >= 4) {
  570. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  571. seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
  572. }
  573. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
  574. seq_printf(m, " seqno: 0x%08x\n", error->seqno);
  575. if (error->active_bo_count) {
  576. seq_printf(m, "Buffers [%d]:\n", error->active_bo_count);
  577. for (i = 0; i < error->active_bo_count; i++) {
  578. seq_printf(m, " %08x %8zd %08x %08x %08x%s%s%s%s",
  579. error->active_bo[i].gtt_offset,
  580. error->active_bo[i].size,
  581. error->active_bo[i].read_domains,
  582. error->active_bo[i].write_domain,
  583. error->active_bo[i].seqno,
  584. pin_flag(error->active_bo[i].pinned),
  585. tiling_flag(error->active_bo[i].tiling),
  586. dirty_flag(error->active_bo[i].dirty),
  587. purgeable_flag(error->active_bo[i].purgeable));
  588. if (error->active_bo[i].name)
  589. seq_printf(m, " (name: %d)", error->active_bo[i].name);
  590. if (error->active_bo[i].fence_reg != I915_FENCE_REG_NONE)
  591. seq_printf(m, " (fence: %d)", error->active_bo[i].fence_reg);
  592. seq_printf(m, "\n");
  593. }
  594. }
  595. for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
  596. if (error->batchbuffer[i]) {
  597. struct drm_i915_error_object *obj = error->batchbuffer[i];
  598. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
  599. offset = 0;
  600. for (page = 0; page < obj->page_count; page++) {
  601. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  602. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  603. offset += 4;
  604. }
  605. }
  606. }
  607. }
  608. if (error->ringbuffer) {
  609. struct drm_i915_error_object *obj = error->ringbuffer;
  610. seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset);
  611. offset = 0;
  612. for (page = 0; page < obj->page_count; page++) {
  613. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  614. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  615. offset += 4;
  616. }
  617. }
  618. }
  619. if (error->overlay)
  620. intel_overlay_print_error_state(m, error->overlay);
  621. out:
  622. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  623. return 0;
  624. }
  625. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  626. {
  627. struct drm_info_node *node = (struct drm_info_node *) m->private;
  628. struct drm_device *dev = node->minor->dev;
  629. drm_i915_private_t *dev_priv = dev->dev_private;
  630. u16 crstanddelay = I915_READ16(CRSTANDVID);
  631. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  632. return 0;
  633. }
  634. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  635. {
  636. struct drm_info_node *node = (struct drm_info_node *) m->private;
  637. struct drm_device *dev = node->minor->dev;
  638. drm_i915_private_t *dev_priv = dev->dev_private;
  639. u16 rgvswctl = I915_READ16(MEMSWCTL);
  640. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  641. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  642. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  643. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  644. MEMSTAT_VID_SHIFT);
  645. seq_printf(m, "Current P-state: %d\n",
  646. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  647. return 0;
  648. }
  649. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  650. {
  651. struct drm_info_node *node = (struct drm_info_node *) m->private;
  652. struct drm_device *dev = node->minor->dev;
  653. drm_i915_private_t *dev_priv = dev->dev_private;
  654. u32 delayfreq;
  655. int i;
  656. for (i = 0; i < 16; i++) {
  657. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  658. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  659. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  660. }
  661. return 0;
  662. }
  663. static inline int MAP_TO_MV(int map)
  664. {
  665. return 1250 - (map * 25);
  666. }
  667. static int i915_inttoext_table(struct seq_file *m, void *unused)
  668. {
  669. struct drm_info_node *node = (struct drm_info_node *) m->private;
  670. struct drm_device *dev = node->minor->dev;
  671. drm_i915_private_t *dev_priv = dev->dev_private;
  672. u32 inttoext;
  673. int i;
  674. for (i = 1; i <= 32; i++) {
  675. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  676. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  677. }
  678. return 0;
  679. }
  680. static int i915_drpc_info(struct seq_file *m, void *unused)
  681. {
  682. struct drm_info_node *node = (struct drm_info_node *) m->private;
  683. struct drm_device *dev = node->minor->dev;
  684. drm_i915_private_t *dev_priv = dev->dev_private;
  685. u32 rgvmodectl = I915_READ(MEMMODECTL);
  686. u32 rstdbyctl = I915_READ(MCHBAR_RENDER_STANDBY);
  687. u16 crstandvid = I915_READ16(CRSTANDVID);
  688. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  689. "yes" : "no");
  690. seq_printf(m, "Boost freq: %d\n",
  691. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  692. MEMMODE_BOOST_FREQ_SHIFT);
  693. seq_printf(m, "HW control enabled: %s\n",
  694. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  695. seq_printf(m, "SW control enabled: %s\n",
  696. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  697. seq_printf(m, "Gated voltage change: %s\n",
  698. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  699. seq_printf(m, "Starting frequency: P%d\n",
  700. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  701. seq_printf(m, "Max P-state: P%d\n",
  702. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  703. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  704. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  705. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  706. seq_printf(m, "Render standby enabled: %s\n",
  707. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  708. return 0;
  709. }
  710. static int i915_fbc_status(struct seq_file *m, void *unused)
  711. {
  712. struct drm_info_node *node = (struct drm_info_node *) m->private;
  713. struct drm_device *dev = node->minor->dev;
  714. drm_i915_private_t *dev_priv = dev->dev_private;
  715. if (!I915_HAS_FBC(dev)) {
  716. seq_printf(m, "FBC unsupported on this chipset\n");
  717. return 0;
  718. }
  719. if (intel_fbc_enabled(dev)) {
  720. seq_printf(m, "FBC enabled\n");
  721. } else {
  722. seq_printf(m, "FBC disabled: ");
  723. switch (dev_priv->no_fbc_reason) {
  724. case FBC_NO_OUTPUT:
  725. seq_printf(m, "no outputs");
  726. break;
  727. case FBC_STOLEN_TOO_SMALL:
  728. seq_printf(m, "not enough stolen memory");
  729. break;
  730. case FBC_UNSUPPORTED_MODE:
  731. seq_printf(m, "mode not supported");
  732. break;
  733. case FBC_MODE_TOO_LARGE:
  734. seq_printf(m, "mode too large");
  735. break;
  736. case FBC_BAD_PLANE:
  737. seq_printf(m, "FBC unsupported on plane");
  738. break;
  739. case FBC_NOT_TILED:
  740. seq_printf(m, "scanout buffer not tiled");
  741. break;
  742. case FBC_MULTIPLE_PIPES:
  743. seq_printf(m, "multiple pipes are enabled");
  744. break;
  745. default:
  746. seq_printf(m, "unknown reason");
  747. }
  748. seq_printf(m, "\n");
  749. }
  750. return 0;
  751. }
  752. static int i915_sr_status(struct seq_file *m, void *unused)
  753. {
  754. struct drm_info_node *node = (struct drm_info_node *) m->private;
  755. struct drm_device *dev = node->minor->dev;
  756. drm_i915_private_t *dev_priv = dev->dev_private;
  757. bool sr_enabled = false;
  758. if (IS_GEN5(dev))
  759. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  760. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  761. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  762. else if (IS_I915GM(dev))
  763. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  764. else if (IS_PINEVIEW(dev))
  765. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  766. seq_printf(m, "self-refresh: %s\n",
  767. sr_enabled ? "enabled" : "disabled");
  768. return 0;
  769. }
  770. static int i915_emon_status(struct seq_file *m, void *unused)
  771. {
  772. struct drm_info_node *node = (struct drm_info_node *) m->private;
  773. struct drm_device *dev = node->minor->dev;
  774. drm_i915_private_t *dev_priv = dev->dev_private;
  775. unsigned long temp, chipset, gfx;
  776. int ret;
  777. ret = mutex_lock_interruptible(&dev->struct_mutex);
  778. if (ret)
  779. return ret;
  780. temp = i915_mch_val(dev_priv);
  781. chipset = i915_chipset_val(dev_priv);
  782. gfx = i915_gfx_val(dev_priv);
  783. mutex_unlock(&dev->struct_mutex);
  784. seq_printf(m, "GMCH temp: %ld\n", temp);
  785. seq_printf(m, "Chipset power: %ld\n", chipset);
  786. seq_printf(m, "GFX power: %ld\n", gfx);
  787. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  788. return 0;
  789. }
  790. static int i915_gfxec(struct seq_file *m, void *unused)
  791. {
  792. struct drm_info_node *node = (struct drm_info_node *) m->private;
  793. struct drm_device *dev = node->minor->dev;
  794. drm_i915_private_t *dev_priv = dev->dev_private;
  795. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  796. return 0;
  797. }
  798. static int i915_opregion(struct seq_file *m, void *unused)
  799. {
  800. struct drm_info_node *node = (struct drm_info_node *) m->private;
  801. struct drm_device *dev = node->minor->dev;
  802. drm_i915_private_t *dev_priv = dev->dev_private;
  803. struct intel_opregion *opregion = &dev_priv->opregion;
  804. int ret;
  805. ret = mutex_lock_interruptible(&dev->struct_mutex);
  806. if (ret)
  807. return ret;
  808. if (opregion->header)
  809. seq_write(m, opregion->header, OPREGION_SIZE);
  810. mutex_unlock(&dev->struct_mutex);
  811. return 0;
  812. }
  813. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  814. {
  815. struct drm_info_node *node = (struct drm_info_node *) m->private;
  816. struct drm_device *dev = node->minor->dev;
  817. drm_i915_private_t *dev_priv = dev->dev_private;
  818. struct intel_fbdev *ifbdev;
  819. struct intel_framebuffer *fb;
  820. int ret;
  821. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  822. if (ret)
  823. return ret;
  824. ifbdev = dev_priv->fbdev;
  825. fb = to_intel_framebuffer(ifbdev->helper.fb);
  826. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  827. fb->base.width,
  828. fb->base.height,
  829. fb->base.depth,
  830. fb->base.bits_per_pixel);
  831. describe_obj(m, to_intel_bo(fb->obj));
  832. seq_printf(m, "\n");
  833. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  834. if (&fb->base == ifbdev->helper.fb)
  835. continue;
  836. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  837. fb->base.width,
  838. fb->base.height,
  839. fb->base.depth,
  840. fb->base.bits_per_pixel);
  841. describe_obj(m, to_intel_bo(fb->obj));
  842. seq_printf(m, "\n");
  843. }
  844. mutex_unlock(&dev->mode_config.mutex);
  845. return 0;
  846. }
  847. static int
  848. i915_wedged_open(struct inode *inode,
  849. struct file *filp)
  850. {
  851. filp->private_data = inode->i_private;
  852. return 0;
  853. }
  854. static ssize_t
  855. i915_wedged_read(struct file *filp,
  856. char __user *ubuf,
  857. size_t max,
  858. loff_t *ppos)
  859. {
  860. struct drm_device *dev = filp->private_data;
  861. drm_i915_private_t *dev_priv = dev->dev_private;
  862. char buf[80];
  863. int len;
  864. len = snprintf(buf, sizeof (buf),
  865. "wedged : %d\n",
  866. atomic_read(&dev_priv->mm.wedged));
  867. if (len > sizeof (buf))
  868. len = sizeof (buf);
  869. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  870. }
  871. static ssize_t
  872. i915_wedged_write(struct file *filp,
  873. const char __user *ubuf,
  874. size_t cnt,
  875. loff_t *ppos)
  876. {
  877. struct drm_device *dev = filp->private_data;
  878. drm_i915_private_t *dev_priv = dev->dev_private;
  879. char buf[20];
  880. int val = 1;
  881. if (cnt > 0) {
  882. if (cnt > sizeof (buf) - 1)
  883. return -EINVAL;
  884. if (copy_from_user(buf, ubuf, cnt))
  885. return -EFAULT;
  886. buf[cnt] = 0;
  887. val = simple_strtoul(buf, NULL, 0);
  888. }
  889. DRM_INFO("Manually setting wedged to %d\n", val);
  890. atomic_set(&dev_priv->mm.wedged, val);
  891. if (val) {
  892. wake_up_all(&dev_priv->irq_queue);
  893. queue_work(dev_priv->wq, &dev_priv->error_work);
  894. }
  895. return cnt;
  896. }
  897. static const struct file_operations i915_wedged_fops = {
  898. .owner = THIS_MODULE,
  899. .open = i915_wedged_open,
  900. .read = i915_wedged_read,
  901. .write = i915_wedged_write,
  902. .llseek = default_llseek,
  903. };
  904. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  905. * allocated we need to hook into the minor for release. */
  906. static int
  907. drm_add_fake_info_node(struct drm_minor *minor,
  908. struct dentry *ent,
  909. const void *key)
  910. {
  911. struct drm_info_node *node;
  912. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  913. if (node == NULL) {
  914. debugfs_remove(ent);
  915. return -ENOMEM;
  916. }
  917. node->minor = minor;
  918. node->dent = ent;
  919. node->info_ent = (void *) key;
  920. list_add(&node->list, &minor->debugfs_nodes.list);
  921. return 0;
  922. }
  923. static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
  924. {
  925. struct drm_device *dev = minor->dev;
  926. struct dentry *ent;
  927. ent = debugfs_create_file("i915_wedged",
  928. S_IRUGO | S_IWUSR,
  929. root, dev,
  930. &i915_wedged_fops);
  931. if (IS_ERR(ent))
  932. return PTR_ERR(ent);
  933. return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
  934. }
  935. static struct drm_info_list i915_debugfs_list[] = {
  936. {"i915_capabilities", i915_capabilities, 0, 0},
  937. {"i915_gem_objects", i915_gem_object_info, 0},
  938. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  939. {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
  940. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  941. {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
  942. {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
  943. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  944. {"i915_gem_request", i915_gem_request_info, 0},
  945. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  946. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  947. {"i915_gem_interrupt", i915_interrupt_info, 0},
  948. {"i915_gem_hws", i915_hws_info, 0, (void *)RENDER_RING},
  949. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BLT_RING},
  950. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)BSD_RING},
  951. {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RENDER_RING},
  952. {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RENDER_RING},
  953. {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BSD_RING},
  954. {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BSD_RING},
  955. {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BLT_RING},
  956. {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BLT_RING},
  957. {"i915_batchbuffers", i915_batchbuffer_info, 0},
  958. {"i915_error_state", i915_error_state, 0},
  959. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  960. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  961. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  962. {"i915_inttoext_table", i915_inttoext_table, 0},
  963. {"i915_drpc_info", i915_drpc_info, 0},
  964. {"i915_emon_status", i915_emon_status, 0},
  965. {"i915_gfxec", i915_gfxec, 0},
  966. {"i915_fbc_status", i915_fbc_status, 0},
  967. {"i915_sr_status", i915_sr_status, 0},
  968. {"i915_opregion", i915_opregion, 0},
  969. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  970. };
  971. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  972. int i915_debugfs_init(struct drm_minor *minor)
  973. {
  974. int ret;
  975. ret = i915_wedged_create(minor->debugfs_root, minor);
  976. if (ret)
  977. return ret;
  978. return drm_debugfs_create_files(i915_debugfs_list,
  979. I915_DEBUGFS_ENTRIES,
  980. minor->debugfs_root, minor);
  981. }
  982. void i915_debugfs_cleanup(struct drm_minor *minor)
  983. {
  984. drm_debugfs_remove_files(i915_debugfs_list,
  985. I915_DEBUGFS_ENTRIES, minor);
  986. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  987. 1, minor);
  988. }
  989. #endif /* CONFIG_DEBUG_FS */