rtsx_pcr.c 28 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21. */
  22. #include <linux/pci.h>
  23. #include <linux/module.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/highmem.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/delay.h>
  28. #include <linux/idr.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/mfd/core.h>
  31. #include <linux/mfd/rtsx_pci.h>
  32. #include <asm/unaligned.h>
  33. #include "rtsx_pcr.h"
  34. static bool msi_en = true;
  35. module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  36. MODULE_PARM_DESC(msi_en, "Enable MSI");
  37. static DEFINE_IDR(rtsx_pci_idr);
  38. static DEFINE_SPINLOCK(rtsx_pci_lock);
  39. static struct mfd_cell rtsx_pcr_cells[] = {
  40. [RTSX_SD_CARD] = {
  41. .name = DRV_NAME_RTSX_PCI_SDMMC,
  42. },
  43. [RTSX_MS_CARD] = {
  44. .name = DRV_NAME_RTSX_PCI_MS,
  45. },
  46. };
  47. static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
  48. { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  49. { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  50. { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  51. { 0, }
  52. };
  53. MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  54. void rtsx_pci_start_run(struct rtsx_pcr *pcr)
  55. {
  56. /* If pci device removed, don't queue idle work any more */
  57. if (pcr->remove_pci)
  58. return;
  59. if (pcr->state != PDEV_STAT_RUN) {
  60. pcr->state = PDEV_STAT_RUN;
  61. if (pcr->ops->enable_auto_blink)
  62. pcr->ops->enable_auto_blink(pcr);
  63. }
  64. mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
  65. }
  66. EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
  67. int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
  68. {
  69. int i;
  70. u32 val = HAIMR_WRITE_START;
  71. val |= (u32)(addr & 0x3FFF) << 16;
  72. val |= (u32)mask << 8;
  73. val |= (u32)data;
  74. rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  75. for (i = 0; i < MAX_RW_REG_CNT; i++) {
  76. val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  77. if ((val & HAIMR_TRANS_END) == 0) {
  78. if (data != (u8)val)
  79. return -EIO;
  80. return 0;
  81. }
  82. }
  83. return -ETIMEDOUT;
  84. }
  85. EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
  86. int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
  87. {
  88. u32 val = HAIMR_READ_START;
  89. int i;
  90. val |= (u32)(addr & 0x3FFF) << 16;
  91. rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  92. for (i = 0; i < MAX_RW_REG_CNT; i++) {
  93. val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  94. if ((val & HAIMR_TRANS_END) == 0)
  95. break;
  96. }
  97. if (i >= MAX_RW_REG_CNT)
  98. return -ETIMEDOUT;
  99. if (data)
  100. *data = (u8)(val & 0xFF);
  101. return 0;
  102. }
  103. EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
  104. int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
  105. {
  106. int err, i, finished = 0;
  107. u8 tmp;
  108. rtsx_pci_init_cmd(pcr);
  109. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
  110. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
  111. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
  112. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
  113. err = rtsx_pci_send_cmd(pcr, 100);
  114. if (err < 0)
  115. return err;
  116. for (i = 0; i < 100000; i++) {
  117. err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
  118. if (err < 0)
  119. return err;
  120. if (!(tmp & 0x80)) {
  121. finished = 1;
  122. break;
  123. }
  124. }
  125. if (!finished)
  126. return -ETIMEDOUT;
  127. return 0;
  128. }
  129. EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
  130. int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
  131. {
  132. int err, i, finished = 0;
  133. u16 data;
  134. u8 *ptr, tmp;
  135. rtsx_pci_init_cmd(pcr);
  136. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
  137. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
  138. err = rtsx_pci_send_cmd(pcr, 100);
  139. if (err < 0)
  140. return err;
  141. for (i = 0; i < 100000; i++) {
  142. err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
  143. if (err < 0)
  144. return err;
  145. if (!(tmp & 0x80)) {
  146. finished = 1;
  147. break;
  148. }
  149. }
  150. if (!finished)
  151. return -ETIMEDOUT;
  152. rtsx_pci_init_cmd(pcr);
  153. rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
  154. rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
  155. err = rtsx_pci_send_cmd(pcr, 100);
  156. if (err < 0)
  157. return err;
  158. ptr = rtsx_pci_get_cmd_data(pcr);
  159. data = ((u16)ptr[1] << 8) | ptr[0];
  160. if (val)
  161. *val = data;
  162. return 0;
  163. }
  164. EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
  165. void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
  166. {
  167. rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
  168. rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
  169. rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
  170. rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
  171. }
  172. EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
  173. void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
  174. u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
  175. {
  176. unsigned long flags;
  177. u32 val = 0;
  178. u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
  179. val |= (u32)(cmd_type & 0x03) << 30;
  180. val |= (u32)(reg_addr & 0x3FFF) << 16;
  181. val |= (u32)mask << 8;
  182. val |= (u32)data;
  183. spin_lock_irqsave(&pcr->lock, flags);
  184. ptr += pcr->ci;
  185. if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
  186. put_unaligned_le32(val, ptr);
  187. ptr++;
  188. pcr->ci++;
  189. }
  190. spin_unlock_irqrestore(&pcr->lock, flags);
  191. }
  192. EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
  193. void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
  194. {
  195. u32 val = 1 << 31;
  196. rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
  197. val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
  198. /* Hardware Auto Response */
  199. val |= 0x40000000;
  200. rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
  201. }
  202. EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
  203. int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
  204. {
  205. struct completion trans_done;
  206. u32 val = 1 << 31;
  207. long timeleft;
  208. unsigned long flags;
  209. int err = 0;
  210. spin_lock_irqsave(&pcr->lock, flags);
  211. /* set up data structures for the wakeup system */
  212. pcr->done = &trans_done;
  213. pcr->trans_result = TRANS_NOT_READY;
  214. init_completion(&trans_done);
  215. rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
  216. val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
  217. /* Hardware Auto Response */
  218. val |= 0x40000000;
  219. rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
  220. spin_unlock_irqrestore(&pcr->lock, flags);
  221. /* Wait for TRANS_OK_INT */
  222. timeleft = wait_for_completion_interruptible_timeout(
  223. &trans_done, msecs_to_jiffies(timeout));
  224. if (timeleft <= 0) {
  225. dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
  226. __func__, __LINE__);
  227. err = -ETIMEDOUT;
  228. goto finish_send_cmd;
  229. }
  230. spin_lock_irqsave(&pcr->lock, flags);
  231. if (pcr->trans_result == TRANS_RESULT_FAIL)
  232. err = -EINVAL;
  233. else if (pcr->trans_result == TRANS_RESULT_OK)
  234. err = 0;
  235. else if (pcr->trans_result == TRANS_NO_DEVICE)
  236. err = -ENODEV;
  237. spin_unlock_irqrestore(&pcr->lock, flags);
  238. finish_send_cmd:
  239. spin_lock_irqsave(&pcr->lock, flags);
  240. pcr->done = NULL;
  241. spin_unlock_irqrestore(&pcr->lock, flags);
  242. if ((err < 0) && (err != -ENODEV))
  243. rtsx_pci_stop_cmd(pcr);
  244. if (pcr->finish_me)
  245. complete(pcr->finish_me);
  246. return err;
  247. }
  248. EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
  249. static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
  250. dma_addr_t addr, unsigned int len, int end)
  251. {
  252. u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
  253. u64 val;
  254. u8 option = SG_VALID | SG_TRANS_DATA;
  255. dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
  256. (unsigned int)addr, len);
  257. if (end)
  258. option |= SG_END;
  259. val = ((u64)addr << 32) | ((u64)len << 12) | option;
  260. put_unaligned_le64(val, ptr);
  261. ptr++;
  262. pcr->sgi++;
  263. }
  264. int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  265. int num_sg, bool read, int timeout)
  266. {
  267. struct completion trans_done;
  268. u8 dir;
  269. int err = 0, i, count;
  270. long timeleft;
  271. unsigned long flags;
  272. struct scatterlist *sg;
  273. enum dma_data_direction dma_dir;
  274. u32 val;
  275. dma_addr_t addr;
  276. unsigned int len;
  277. dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
  278. /* don't transfer data during abort processing */
  279. if (pcr->remove_pci)
  280. return -EINVAL;
  281. if ((sglist == NULL) || (num_sg <= 0))
  282. return -EINVAL;
  283. if (read) {
  284. dir = DEVICE_TO_HOST;
  285. dma_dir = DMA_FROM_DEVICE;
  286. } else {
  287. dir = HOST_TO_DEVICE;
  288. dma_dir = DMA_TO_DEVICE;
  289. }
  290. count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
  291. if (count < 1) {
  292. dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
  293. return -EINVAL;
  294. }
  295. dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
  296. val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
  297. pcr->sgi = 0;
  298. for_each_sg(sglist, sg, count, i) {
  299. addr = sg_dma_address(sg);
  300. len = sg_dma_len(sg);
  301. rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
  302. }
  303. spin_lock_irqsave(&pcr->lock, flags);
  304. pcr->done = &trans_done;
  305. pcr->trans_result = TRANS_NOT_READY;
  306. init_completion(&trans_done);
  307. rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
  308. rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
  309. spin_unlock_irqrestore(&pcr->lock, flags);
  310. timeleft = wait_for_completion_interruptible_timeout(
  311. &trans_done, msecs_to_jiffies(timeout));
  312. if (timeleft <= 0) {
  313. dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
  314. __func__, __LINE__);
  315. err = -ETIMEDOUT;
  316. goto out;
  317. }
  318. spin_lock_irqsave(&pcr->lock, flags);
  319. if (pcr->trans_result == TRANS_RESULT_FAIL)
  320. err = -EINVAL;
  321. else if (pcr->trans_result == TRANS_NO_DEVICE)
  322. err = -ENODEV;
  323. spin_unlock_irqrestore(&pcr->lock, flags);
  324. out:
  325. spin_lock_irqsave(&pcr->lock, flags);
  326. pcr->done = NULL;
  327. spin_unlock_irqrestore(&pcr->lock, flags);
  328. dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
  329. if ((err < 0) && (err != -ENODEV))
  330. rtsx_pci_stop_cmd(pcr);
  331. if (pcr->finish_me)
  332. complete(pcr->finish_me);
  333. return err;
  334. }
  335. EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
  336. int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
  337. {
  338. int err;
  339. int i, j;
  340. u16 reg;
  341. u8 *ptr;
  342. if (buf_len > 512)
  343. buf_len = 512;
  344. ptr = buf;
  345. reg = PPBUF_BASE2;
  346. for (i = 0; i < buf_len / 256; i++) {
  347. rtsx_pci_init_cmd(pcr);
  348. for (j = 0; j < 256; j++)
  349. rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
  350. err = rtsx_pci_send_cmd(pcr, 250);
  351. if (err < 0)
  352. return err;
  353. memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
  354. ptr += 256;
  355. }
  356. if (buf_len % 256) {
  357. rtsx_pci_init_cmd(pcr);
  358. for (j = 0; j < buf_len % 256; j++)
  359. rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
  360. err = rtsx_pci_send_cmd(pcr, 250);
  361. if (err < 0)
  362. return err;
  363. }
  364. memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
  365. return 0;
  366. }
  367. EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
  368. int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
  369. {
  370. int err;
  371. int i, j;
  372. u16 reg;
  373. u8 *ptr;
  374. if (buf_len > 512)
  375. buf_len = 512;
  376. ptr = buf;
  377. reg = PPBUF_BASE2;
  378. for (i = 0; i < buf_len / 256; i++) {
  379. rtsx_pci_init_cmd(pcr);
  380. for (j = 0; j < 256; j++) {
  381. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  382. reg++, 0xFF, *ptr);
  383. ptr++;
  384. }
  385. err = rtsx_pci_send_cmd(pcr, 250);
  386. if (err < 0)
  387. return err;
  388. }
  389. if (buf_len % 256) {
  390. rtsx_pci_init_cmd(pcr);
  391. for (j = 0; j < buf_len % 256; j++) {
  392. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  393. reg++, 0xFF, *ptr);
  394. ptr++;
  395. }
  396. err = rtsx_pci_send_cmd(pcr, 250);
  397. if (err < 0)
  398. return err;
  399. }
  400. return 0;
  401. }
  402. EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
  403. static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
  404. {
  405. int err;
  406. rtsx_pci_init_cmd(pcr);
  407. while (*tbl & 0xFFFF0000) {
  408. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  409. (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
  410. tbl++;
  411. }
  412. err = rtsx_pci_send_cmd(pcr, 100);
  413. if (err < 0)
  414. return err;
  415. return 0;
  416. }
  417. int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
  418. {
  419. const u32 *tbl;
  420. if (card == RTSX_SD_CARD)
  421. tbl = pcr->sd_pull_ctl_enable_tbl;
  422. else if (card == RTSX_MS_CARD)
  423. tbl = pcr->ms_pull_ctl_enable_tbl;
  424. else
  425. return -EINVAL;
  426. return rtsx_pci_set_pull_ctl(pcr, tbl);
  427. }
  428. EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
  429. int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
  430. {
  431. const u32 *tbl;
  432. if (card == RTSX_SD_CARD)
  433. tbl = pcr->sd_pull_ctl_disable_tbl;
  434. else if (card == RTSX_MS_CARD)
  435. tbl = pcr->ms_pull_ctl_disable_tbl;
  436. else
  437. return -EINVAL;
  438. return rtsx_pci_set_pull_ctl(pcr, tbl);
  439. }
  440. EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
  441. static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
  442. {
  443. pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
  444. if (pcr->num_slots > 1)
  445. pcr->bier |= MS_INT_EN;
  446. /* Enable Bus Interrupt */
  447. rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
  448. dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
  449. }
  450. static inline u8 double_ssc_depth(u8 depth)
  451. {
  452. return ((depth > 1) ? (depth - 1) : depth);
  453. }
  454. static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
  455. {
  456. if (div > CLK_DIV_1) {
  457. if (ssc_depth > (div - 1))
  458. ssc_depth -= (div - 1);
  459. else
  460. ssc_depth = SSC_DEPTH_4M;
  461. }
  462. return ssc_depth;
  463. }
  464. int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
  465. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
  466. {
  467. int err, clk;
  468. u8 N, min_N, max_N, clk_divider;
  469. u8 mcu_cnt, div, max_div;
  470. u8 depth[] = {
  471. [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
  472. [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
  473. [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
  474. [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
  475. [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
  476. };
  477. if (initial_mode) {
  478. /* We use 250k(around) here, in initial stage */
  479. clk_divider = SD_CLK_DIVIDE_128;
  480. card_clock = 30000000;
  481. } else {
  482. clk_divider = SD_CLK_DIVIDE_0;
  483. }
  484. err = rtsx_pci_write_register(pcr, SD_CFG1,
  485. SD_CLK_DIVIDE_MASK, clk_divider);
  486. if (err < 0)
  487. return err;
  488. card_clock /= 1000000;
  489. dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
  490. min_N = 80;
  491. max_N = 208;
  492. max_div = CLK_DIV_8;
  493. clk = card_clock;
  494. if (!initial_mode && double_clk)
  495. clk = card_clock * 2;
  496. dev_dbg(&(pcr->pci->dev),
  497. "Internal SSC clock: %dMHz (cur_clock = %d)\n",
  498. clk, pcr->cur_clock);
  499. if (clk == pcr->cur_clock)
  500. return 0;
  501. N = (u8)(clk - 2);
  502. if ((clk <= 2) || (N > max_N))
  503. return -EINVAL;
  504. mcu_cnt = (u8)(125/clk + 3);
  505. if (mcu_cnt > 15)
  506. mcu_cnt = 15;
  507. /* Make sure that the SSC clock div_n is equal or greater than min_N */
  508. div = CLK_DIV_1;
  509. while ((N < min_N) && (div < max_div)) {
  510. N = (N + 2) * 2 - 2;
  511. div++;
  512. }
  513. dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div);
  514. ssc_depth = depth[ssc_depth];
  515. if (double_clk)
  516. ssc_depth = double_ssc_depth(ssc_depth);
  517. ssc_depth = revise_ssc_depth(ssc_depth, div);
  518. dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
  519. rtsx_pci_init_cmd(pcr);
  520. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
  521. CLK_LOW_FREQ, CLK_LOW_FREQ);
  522. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
  523. 0xFF, (div << 4) | mcu_cnt);
  524. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
  525. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
  526. SSC_DEPTH_MASK, ssc_depth);
  527. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
  528. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
  529. if (vpclk) {
  530. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  531. PHASE_NOT_RESET, 0);
  532. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  533. PHASE_NOT_RESET, PHASE_NOT_RESET);
  534. }
  535. err = rtsx_pci_send_cmd(pcr, 2000);
  536. if (err < 0)
  537. return err;
  538. /* Wait SSC clock stable */
  539. udelay(10);
  540. err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  541. if (err < 0)
  542. return err;
  543. pcr->cur_clock = clk;
  544. return 0;
  545. }
  546. EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
  547. int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
  548. {
  549. if (pcr->ops->card_power_on)
  550. return pcr->ops->card_power_on(pcr, card);
  551. return 0;
  552. }
  553. EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
  554. int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
  555. {
  556. if (pcr->ops->card_power_off)
  557. return pcr->ops->card_power_off(pcr, card);
  558. return 0;
  559. }
  560. EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
  561. unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
  562. {
  563. unsigned int val;
  564. val = rtsx_pci_readl(pcr, RTSX_BIPR);
  565. if (pcr->ops->cd_deglitch)
  566. val = pcr->ops->cd_deglitch(pcr);
  567. return val;
  568. }
  569. EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
  570. void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
  571. {
  572. struct completion finish;
  573. pcr->finish_me = &finish;
  574. init_completion(&finish);
  575. if (pcr->done)
  576. complete(pcr->done);
  577. if (!pcr->remove_pci)
  578. rtsx_pci_stop_cmd(pcr);
  579. wait_for_completion_interruptible_timeout(&finish,
  580. msecs_to_jiffies(2));
  581. pcr->finish_me = NULL;
  582. }
  583. EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
  584. static void rtsx_pci_card_detect(struct work_struct *work)
  585. {
  586. struct delayed_work *dwork;
  587. struct rtsx_pcr *pcr;
  588. unsigned long flags;
  589. unsigned int card_detect = 0;
  590. u32 irq_status;
  591. dwork = to_delayed_work(work);
  592. pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
  593. dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
  594. spin_lock_irqsave(&pcr->lock, flags);
  595. irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
  596. dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
  597. if (pcr->card_inserted || pcr->card_removed) {
  598. dev_dbg(&(pcr->pci->dev),
  599. "card_inserted: 0x%x, card_removed: 0x%x\n",
  600. pcr->card_inserted, pcr->card_removed);
  601. if (pcr->ops->cd_deglitch)
  602. pcr->card_inserted = pcr->ops->cd_deglitch(pcr);
  603. card_detect = pcr->card_inserted | pcr->card_removed;
  604. pcr->card_inserted = 0;
  605. pcr->card_removed = 0;
  606. }
  607. spin_unlock_irqrestore(&pcr->lock, flags);
  608. if (card_detect & SD_EXIST)
  609. pcr->slots[RTSX_SD_CARD].card_event(
  610. pcr->slots[RTSX_SD_CARD].p_dev);
  611. if (card_detect & MS_EXIST)
  612. pcr->slots[RTSX_MS_CARD].card_event(
  613. pcr->slots[RTSX_MS_CARD].p_dev);
  614. }
  615. static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
  616. {
  617. struct rtsx_pcr *pcr = dev_id;
  618. u32 int_reg;
  619. if (!pcr)
  620. return IRQ_NONE;
  621. spin_lock(&pcr->lock);
  622. int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
  623. /* Clear interrupt flag */
  624. rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
  625. if ((int_reg & pcr->bier) == 0) {
  626. spin_unlock(&pcr->lock);
  627. return IRQ_NONE;
  628. }
  629. if (int_reg == 0xFFFFFFFF) {
  630. spin_unlock(&pcr->lock);
  631. return IRQ_HANDLED;
  632. }
  633. int_reg &= (pcr->bier | 0x7FFFFF);
  634. if (int_reg & SD_INT) {
  635. if (int_reg & SD_EXIST) {
  636. pcr->card_inserted |= SD_EXIST;
  637. } else {
  638. pcr->card_removed |= SD_EXIST;
  639. pcr->card_inserted &= ~SD_EXIST;
  640. }
  641. }
  642. if (int_reg & MS_INT) {
  643. if (int_reg & MS_EXIST) {
  644. pcr->card_inserted |= MS_EXIST;
  645. } else {
  646. pcr->card_removed |= MS_EXIST;
  647. pcr->card_inserted &= ~MS_EXIST;
  648. }
  649. }
  650. if (pcr->card_inserted || pcr->card_removed)
  651. schedule_delayed_work(&pcr->carddet_work,
  652. msecs_to_jiffies(200));
  653. if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
  654. if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
  655. pcr->trans_result = TRANS_RESULT_FAIL;
  656. if (pcr->done)
  657. complete(pcr->done);
  658. } else if (int_reg & TRANS_OK_INT) {
  659. pcr->trans_result = TRANS_RESULT_OK;
  660. if (pcr->done)
  661. complete(pcr->done);
  662. }
  663. }
  664. spin_unlock(&pcr->lock);
  665. return IRQ_HANDLED;
  666. }
  667. static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
  668. {
  669. dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
  670. __func__, pcr->msi_en, pcr->pci->irq);
  671. if (request_irq(pcr->pci->irq, rtsx_pci_isr,
  672. pcr->msi_en ? 0 : IRQF_SHARED,
  673. DRV_NAME_RTSX_PCI, pcr)) {
  674. dev_err(&(pcr->pci->dev),
  675. "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
  676. pcr->pci->irq);
  677. return -1;
  678. }
  679. pcr->irq = pcr->pci->irq;
  680. pci_intx(pcr->pci, !pcr->msi_en);
  681. return 0;
  682. }
  683. static void rtsx_pci_idle_work(struct work_struct *work)
  684. {
  685. struct delayed_work *dwork = to_delayed_work(work);
  686. struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
  687. dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
  688. mutex_lock(&pcr->pcr_mutex);
  689. pcr->state = PDEV_STAT_IDLE;
  690. if (pcr->ops->disable_auto_blink)
  691. pcr->ops->disable_auto_blink(pcr);
  692. if (pcr->ops->turn_off_led)
  693. pcr->ops->turn_off_led(pcr);
  694. mutex_unlock(&pcr->pcr_mutex);
  695. }
  696. static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
  697. {
  698. int err;
  699. rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
  700. rtsx_pci_enable_bus_int(pcr);
  701. /* Power on SSC */
  702. err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
  703. if (err < 0)
  704. return err;
  705. /* Wait SSC power stable */
  706. udelay(200);
  707. if (pcr->ops->optimize_phy) {
  708. err = pcr->ops->optimize_phy(pcr);
  709. if (err < 0)
  710. return err;
  711. }
  712. rtsx_pci_init_cmd(pcr);
  713. /* Set mcu_cnt to 7 to ensure data can be sampled properly */
  714. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
  715. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
  716. /* Disable card clock */
  717. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
  718. /* Reset ASPM state to default value */
  719. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
  720. /* Reset delink mode */
  721. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
  722. /* Card driving select */
  723. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
  724. 0x07, DRIVER_TYPE_D);
  725. /* Enable SSC Clock */
  726. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
  727. 0xFF, SSC_8X_EN | SSC_SEL_4M);
  728. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
  729. /* Disable cd_pwr_save */
  730. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
  731. /* Clear Link Ready Interrupt */
  732. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
  733. LINK_RDY_INT, LINK_RDY_INT);
  734. /* Enlarge the estimation window of PERST# glitch
  735. * to reduce the chance of invalid card interrupt
  736. */
  737. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
  738. /* Update RC oscillator to 400k
  739. * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
  740. * 1: 2M 0: 400k
  741. */
  742. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
  743. /* Set interrupt write clear
  744. * bit 1: U_elbi_if_rd_clr_en
  745. * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
  746. * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
  747. */
  748. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
  749. /* Force CLKREQ# PIN to drive 0 to request clock */
  750. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
  751. err = rtsx_pci_send_cmd(pcr, 100);
  752. if (err < 0)
  753. return err;
  754. /* Enable clk_request_n to enable clock power management */
  755. rtsx_pci_write_config_byte(pcr, 0x81, 1);
  756. /* Enter L1 when host tx idle */
  757. rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
  758. if (pcr->ops->extra_init_hw) {
  759. err = pcr->ops->extra_init_hw(pcr);
  760. if (err < 0)
  761. return err;
  762. }
  763. return 0;
  764. }
  765. static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
  766. {
  767. int err;
  768. spin_lock_init(&pcr->lock);
  769. mutex_init(&pcr->pcr_mutex);
  770. switch (PCI_PID(pcr)) {
  771. default:
  772. case 0x5209:
  773. rts5209_init_params(pcr);
  774. break;
  775. case 0x5229:
  776. rts5229_init_params(pcr);
  777. break;
  778. case 0x5289:
  779. rtl8411_init_params(pcr);
  780. break;
  781. }
  782. dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
  783. PCI_PID(pcr), pcr->ic_version);
  784. pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
  785. GFP_KERNEL);
  786. if (!pcr->slots)
  787. return -ENOMEM;
  788. pcr->state = PDEV_STAT_IDLE;
  789. err = rtsx_pci_init_hw(pcr);
  790. if (err < 0) {
  791. kfree(pcr->slots);
  792. return err;
  793. }
  794. return 0;
  795. }
  796. static int __devinit rtsx_pci_probe(struct pci_dev *pcidev,
  797. const struct pci_device_id *id)
  798. {
  799. struct rtsx_pcr *pcr;
  800. struct pcr_handle *handle;
  801. u32 base, len;
  802. int ret, i;
  803. dev_dbg(&(pcidev->dev),
  804. ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
  805. pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
  806. (int)pcidev->revision);
  807. ret = pci_enable_device(pcidev);
  808. if (ret)
  809. return ret;
  810. ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
  811. if (ret)
  812. goto disable;
  813. pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
  814. if (!pcr) {
  815. ret = -ENOMEM;
  816. goto release_pci;
  817. }
  818. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  819. if (!handle) {
  820. ret = -ENOMEM;
  821. goto free_pcr;
  822. }
  823. handle->pcr = pcr;
  824. if (!idr_pre_get(&rtsx_pci_idr, GFP_KERNEL)) {
  825. ret = -ENOMEM;
  826. goto free_handle;
  827. }
  828. spin_lock(&rtsx_pci_lock);
  829. ret = idr_get_new(&rtsx_pci_idr, pcr, &pcr->id);
  830. spin_unlock(&rtsx_pci_lock);
  831. if (ret)
  832. goto free_handle;
  833. pcr->pci = pcidev;
  834. dev_set_drvdata(&pcidev->dev, handle);
  835. len = pci_resource_len(pcidev, 0);
  836. base = pci_resource_start(pcidev, 0);
  837. pcr->remap_addr = ioremap_nocache(base, len);
  838. if (!pcr->remap_addr) {
  839. ret = -ENOMEM;
  840. goto free_host;
  841. }
  842. pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
  843. RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
  844. GFP_KERNEL);
  845. if (pcr->rtsx_resv_buf == NULL) {
  846. ret = -ENXIO;
  847. goto unmap;
  848. }
  849. pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
  850. pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
  851. pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
  852. pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
  853. pcr->card_inserted = 0;
  854. pcr->card_removed = 0;
  855. INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
  856. INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
  857. pcr->msi_en = msi_en;
  858. if (pcr->msi_en) {
  859. ret = pci_enable_msi(pcidev);
  860. if (ret < 0)
  861. pcr->msi_en = false;
  862. }
  863. ret = rtsx_pci_acquire_irq(pcr);
  864. if (ret < 0)
  865. goto free_dma;
  866. pci_set_master(pcidev);
  867. synchronize_irq(pcr->irq);
  868. ret = rtsx_pci_init_chip(pcr);
  869. if (ret < 0)
  870. goto disable_irq;
  871. for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
  872. rtsx_pcr_cells[i].platform_data = handle;
  873. rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
  874. }
  875. ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
  876. ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
  877. if (ret < 0)
  878. goto disable_irq;
  879. schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
  880. return 0;
  881. disable_irq:
  882. free_irq(pcr->irq, (void *)pcr);
  883. free_dma:
  884. dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
  885. pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
  886. unmap:
  887. iounmap(pcr->remap_addr);
  888. free_host:
  889. dev_set_drvdata(&pcidev->dev, NULL);
  890. free_handle:
  891. kfree(handle);
  892. free_pcr:
  893. kfree(pcr);
  894. release_pci:
  895. pci_release_regions(pcidev);
  896. disable:
  897. pci_disable_device(pcidev);
  898. return ret;
  899. }
  900. static void __devexit rtsx_pci_remove(struct pci_dev *pcidev)
  901. {
  902. struct pcr_handle *handle = pci_get_drvdata(pcidev);
  903. struct rtsx_pcr *pcr = handle->pcr;
  904. pcr->remove_pci = true;
  905. cancel_delayed_work(&pcr->carddet_work);
  906. cancel_delayed_work(&pcr->idle_work);
  907. mfd_remove_devices(&pcidev->dev);
  908. dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
  909. pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
  910. free_irq(pcr->irq, (void *)pcr);
  911. if (pcr->msi_en)
  912. pci_disable_msi(pcr->pci);
  913. iounmap(pcr->remap_addr);
  914. dev_set_drvdata(&pcidev->dev, NULL);
  915. pci_release_regions(pcidev);
  916. pci_disable_device(pcidev);
  917. spin_lock(&rtsx_pci_lock);
  918. idr_remove(&rtsx_pci_idr, pcr->id);
  919. spin_unlock(&rtsx_pci_lock);
  920. kfree(pcr->slots);
  921. kfree(pcr);
  922. kfree(handle);
  923. dev_dbg(&(pcidev->dev),
  924. ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
  925. pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
  926. }
  927. #ifdef CONFIG_PM
  928. static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
  929. {
  930. struct pcr_handle *handle;
  931. struct rtsx_pcr *pcr;
  932. int ret = 0;
  933. dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
  934. handle = pci_get_drvdata(pcidev);
  935. pcr = handle->pcr;
  936. cancel_delayed_work(&pcr->carddet_work);
  937. cancel_delayed_work(&pcr->idle_work);
  938. mutex_lock(&pcr->pcr_mutex);
  939. if (pcr->ops->turn_off_led)
  940. pcr->ops->turn_off_led(pcr);
  941. rtsx_pci_writel(pcr, RTSX_BIER, 0);
  942. pcr->bier = 0;
  943. rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
  944. rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
  945. pci_save_state(pcidev);
  946. pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
  947. pci_disable_device(pcidev);
  948. pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
  949. mutex_unlock(&pcr->pcr_mutex);
  950. return ret;
  951. }
  952. static int rtsx_pci_resume(struct pci_dev *pcidev)
  953. {
  954. struct pcr_handle *handle;
  955. struct rtsx_pcr *pcr;
  956. int ret = 0;
  957. dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
  958. handle = pci_get_drvdata(pcidev);
  959. pcr = handle->pcr;
  960. mutex_lock(&pcr->pcr_mutex);
  961. pci_set_power_state(pcidev, PCI_D0);
  962. pci_restore_state(pcidev);
  963. ret = pci_enable_device(pcidev);
  964. if (ret)
  965. goto out;
  966. pci_set_master(pcidev);
  967. ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
  968. if (ret)
  969. goto out;
  970. ret = rtsx_pci_init_hw(pcr);
  971. if (ret)
  972. goto out;
  973. schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
  974. out:
  975. mutex_unlock(&pcr->pcr_mutex);
  976. return ret;
  977. }
  978. #else /* CONFIG_PM */
  979. #define rtsx_pci_suspend NULL
  980. #define rtsx_pci_resume NULL
  981. #endif /* CONFIG_PM */
  982. static struct pci_driver rtsx_pci_driver = {
  983. .name = DRV_NAME_RTSX_PCI,
  984. .id_table = rtsx_pci_ids,
  985. .probe = rtsx_pci_probe,
  986. .remove = __devexit_p(rtsx_pci_remove),
  987. .suspend = rtsx_pci_suspend,
  988. .resume = rtsx_pci_resume,
  989. };
  990. module_pci_driver(rtsx_pci_driver);
  991. MODULE_LICENSE("GPL");
  992. MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
  993. MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");