radeon_cs.c 17 KB

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  1. /*
  2. * Copyright 2008 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Jerome Glisse <glisse@freedesktop.org>
  26. */
  27. #include "drmP.h"
  28. #include "radeon_drm.h"
  29. #include "radeon_reg.h"
  30. #include "radeon.h"
  31. void r100_cs_dump_packet(struct radeon_cs_parser *p,
  32. struct radeon_cs_packet *pkt);
  33. int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
  34. {
  35. struct drm_device *ddev = p->rdev->ddev;
  36. struct radeon_cs_chunk *chunk;
  37. unsigned i, j;
  38. bool duplicate;
  39. if (p->chunk_relocs_idx == -1) {
  40. return 0;
  41. }
  42. chunk = &p->chunks[p->chunk_relocs_idx];
  43. /* FIXME: we assume that each relocs use 4 dwords */
  44. p->nrelocs = chunk->length_dw / 4;
  45. p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
  46. if (p->relocs_ptr == NULL) {
  47. return -ENOMEM;
  48. }
  49. p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
  50. if (p->relocs == NULL) {
  51. return -ENOMEM;
  52. }
  53. for (i = 0; i < p->nrelocs; i++) {
  54. struct drm_radeon_cs_reloc *r;
  55. duplicate = false;
  56. r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
  57. for (j = 0; j < i; j++) {
  58. if (r->handle == p->relocs[j].handle) {
  59. p->relocs_ptr[i] = &p->relocs[j];
  60. duplicate = true;
  61. break;
  62. }
  63. }
  64. if (!duplicate) {
  65. p->relocs[i].gobj = drm_gem_object_lookup(ddev,
  66. p->filp,
  67. r->handle);
  68. if (p->relocs[i].gobj == NULL) {
  69. DRM_ERROR("gem object lookup failed 0x%x\n",
  70. r->handle);
  71. return -ENOENT;
  72. }
  73. p->relocs_ptr[i] = &p->relocs[i];
  74. p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
  75. p->relocs[i].lobj.bo = p->relocs[i].robj;
  76. p->relocs[i].lobj.wdomain = r->write_domain;
  77. p->relocs[i].lobj.rdomain = r->read_domains;
  78. p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
  79. p->relocs[i].handle = r->handle;
  80. p->relocs[i].flags = r->flags;
  81. radeon_bo_list_add_object(&p->relocs[i].lobj,
  82. &p->validated);
  83. } else
  84. p->relocs[i].handle = 0;
  85. }
  86. return radeon_bo_list_validate(&p->validated);
  87. }
  88. static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
  89. {
  90. p->priority = priority;
  91. switch (ring) {
  92. default:
  93. DRM_ERROR("unknown ring id: %d\n", ring);
  94. return -EINVAL;
  95. case RADEON_CS_RING_GFX:
  96. p->ring = RADEON_RING_TYPE_GFX_INDEX;
  97. break;
  98. case RADEON_CS_RING_COMPUTE:
  99. if (p->rdev->family >= CHIP_TAHITI) {
  100. if (p->priority > 0)
  101. p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
  102. else
  103. p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
  104. } else
  105. p->ring = RADEON_RING_TYPE_GFX_INDEX;
  106. break;
  107. }
  108. return 0;
  109. }
  110. static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
  111. {
  112. bool sync_to_ring[RADEON_NUM_RINGS] = { };
  113. int i, r;
  114. for (i = 0; i < p->nrelocs; i++) {
  115. if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
  116. continue;
  117. if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
  118. struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
  119. if (!radeon_fence_signaled(fence)) {
  120. sync_to_ring[fence->ring] = true;
  121. }
  122. }
  123. }
  124. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  125. /* no need to sync to our own or unused rings */
  126. if (i == p->ring || !sync_to_ring[i] || !p->rdev->ring[i].ready)
  127. continue;
  128. if (!p->ib->fence->semaphore) {
  129. r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
  130. if (r)
  131. return r;
  132. }
  133. r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
  134. if (r)
  135. return r;
  136. radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
  137. radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);
  138. r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
  139. if (r)
  140. return r;
  141. radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
  142. radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
  143. }
  144. return 0;
  145. }
  146. int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
  147. {
  148. struct drm_radeon_cs *cs = data;
  149. uint64_t *chunk_array_ptr;
  150. unsigned size, i;
  151. u32 ring = RADEON_CS_RING_GFX;
  152. s32 priority = 0;
  153. if (!cs->num_chunks) {
  154. return 0;
  155. }
  156. /* get chunks */
  157. INIT_LIST_HEAD(&p->validated);
  158. p->idx = 0;
  159. p->chunk_ib_idx = -1;
  160. p->chunk_relocs_idx = -1;
  161. p->chunk_flags_idx = -1;
  162. p->chunk_const_ib_idx = -1;
  163. p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
  164. if (p->chunks_array == NULL) {
  165. return -ENOMEM;
  166. }
  167. chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
  168. if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
  169. sizeof(uint64_t)*cs->num_chunks)) {
  170. return -EFAULT;
  171. }
  172. p->cs_flags = 0;
  173. p->nchunks = cs->num_chunks;
  174. p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
  175. if (p->chunks == NULL) {
  176. return -ENOMEM;
  177. }
  178. for (i = 0; i < p->nchunks; i++) {
  179. struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
  180. struct drm_radeon_cs_chunk user_chunk;
  181. uint32_t __user *cdata;
  182. chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
  183. if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
  184. sizeof(struct drm_radeon_cs_chunk))) {
  185. return -EFAULT;
  186. }
  187. p->chunks[i].length_dw = user_chunk.length_dw;
  188. p->chunks[i].kdata = NULL;
  189. p->chunks[i].chunk_id = user_chunk.chunk_id;
  190. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
  191. p->chunk_relocs_idx = i;
  192. }
  193. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
  194. p->chunk_ib_idx = i;
  195. /* zero length IB isn't useful */
  196. if (p->chunks[i].length_dw == 0)
  197. return -EINVAL;
  198. }
  199. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
  200. p->chunk_const_ib_idx = i;
  201. /* zero length CONST IB isn't useful */
  202. if (p->chunks[i].length_dw == 0)
  203. return -EINVAL;
  204. }
  205. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
  206. p->chunk_flags_idx = i;
  207. /* zero length flags aren't useful */
  208. if (p->chunks[i].length_dw == 0)
  209. return -EINVAL;
  210. }
  211. p->chunks[i].length_dw = user_chunk.length_dw;
  212. p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
  213. cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
  214. if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
  215. (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
  216. size = p->chunks[i].length_dw * sizeof(uint32_t);
  217. p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
  218. if (p->chunks[i].kdata == NULL) {
  219. return -ENOMEM;
  220. }
  221. if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
  222. p->chunks[i].user_ptr, size)) {
  223. return -EFAULT;
  224. }
  225. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
  226. p->cs_flags = p->chunks[i].kdata[0];
  227. if (p->chunks[i].length_dw > 1)
  228. ring = p->chunks[i].kdata[1];
  229. if (p->chunks[i].length_dw > 2)
  230. priority = (s32)p->chunks[i].kdata[2];
  231. }
  232. }
  233. }
  234. if ((p->cs_flags & RADEON_CS_USE_VM) &&
  235. !p->rdev->vm_manager.enabled) {
  236. DRM_ERROR("VM not active on asic!\n");
  237. return -EINVAL;
  238. }
  239. /* we only support VM on SI+ */
  240. if ((p->rdev->family >= CHIP_TAHITI) &&
  241. ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
  242. DRM_ERROR("VM required on SI+!\n");
  243. return -EINVAL;
  244. }
  245. if (radeon_cs_get_ring(p, ring, priority))
  246. return -EINVAL;
  247. /* deal with non-vm */
  248. if ((p->chunk_ib_idx != -1) &&
  249. ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
  250. (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
  251. if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
  252. DRM_ERROR("cs IB too big: %d\n",
  253. p->chunks[p->chunk_ib_idx].length_dw);
  254. return -EINVAL;
  255. }
  256. if ((p->rdev->flags & RADEON_IS_AGP)) {
  257. p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
  258. p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
  259. if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
  260. p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
  261. kfree(p->chunks[i].kpage[0]);
  262. kfree(p->chunks[i].kpage[1]);
  263. return -ENOMEM;
  264. }
  265. }
  266. p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
  267. p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
  268. p->chunks[p->chunk_ib_idx].last_copied_page = -1;
  269. p->chunks[p->chunk_ib_idx].last_page_index =
  270. ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
  271. }
  272. return 0;
  273. }
  274. /**
  275. * cs_parser_fini() - clean parser states
  276. * @parser: parser structure holding parsing context.
  277. * @error: error number
  278. *
  279. * If error is set than unvalidate buffer, otherwise just free memory
  280. * used by parsing context.
  281. **/
  282. static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
  283. {
  284. unsigned i;
  285. if (!error && parser->ib)
  286. ttm_eu_fence_buffer_objects(&parser->validated,
  287. parser->ib->fence);
  288. else
  289. ttm_eu_backoff_reservation(&parser->validated);
  290. if (parser->relocs != NULL) {
  291. for (i = 0; i < parser->nrelocs; i++) {
  292. if (parser->relocs[i].gobj)
  293. drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
  294. }
  295. }
  296. kfree(parser->track);
  297. kfree(parser->relocs);
  298. kfree(parser->relocs_ptr);
  299. for (i = 0; i < parser->nchunks; i++) {
  300. kfree(parser->chunks[i].kdata);
  301. if ((parser->rdev->flags & RADEON_IS_AGP)) {
  302. kfree(parser->chunks[i].kpage[0]);
  303. kfree(parser->chunks[i].kpage[1]);
  304. }
  305. }
  306. kfree(parser->chunks);
  307. kfree(parser->chunks_array);
  308. radeon_ib_free(parser->rdev, &parser->ib);
  309. }
  310. static int radeon_cs_ib_chunk(struct radeon_device *rdev,
  311. struct radeon_cs_parser *parser)
  312. {
  313. struct radeon_cs_chunk *ib_chunk;
  314. int r;
  315. if (parser->chunk_ib_idx == -1)
  316. return 0;
  317. if (parser->cs_flags & RADEON_CS_USE_VM)
  318. return 0;
  319. ib_chunk = &parser->chunks[parser->chunk_ib_idx];
  320. /* Copy the packet into the IB, the parser will read from the
  321. * input memory (cached) and write to the IB (which can be
  322. * uncached).
  323. */
  324. r = radeon_ib_get(rdev, parser->ring, &parser->ib,
  325. ib_chunk->length_dw * 4);
  326. if (r) {
  327. DRM_ERROR("Failed to get ib !\n");
  328. return r;
  329. }
  330. parser->ib->length_dw = ib_chunk->length_dw;
  331. r = radeon_cs_parse(rdev, parser->ring, parser);
  332. if (r || parser->parser_error) {
  333. DRM_ERROR("Invalid command stream !\n");
  334. return r;
  335. }
  336. r = radeon_cs_finish_pages(parser);
  337. if (r) {
  338. DRM_ERROR("Invalid command stream !\n");
  339. return r;
  340. }
  341. r = radeon_cs_sync_rings(parser);
  342. if (r) {
  343. DRM_ERROR("Failed to synchronize rings !\n");
  344. }
  345. parser->ib->vm_id = 0;
  346. r = radeon_ib_schedule(rdev, parser->ib);
  347. if (r) {
  348. DRM_ERROR("Failed to schedule IB !\n");
  349. }
  350. return 0;
  351. }
  352. static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
  353. struct radeon_vm *vm)
  354. {
  355. struct radeon_bo_list *lobj;
  356. struct radeon_bo *bo;
  357. int r;
  358. list_for_each_entry(lobj, &parser->validated, tv.head) {
  359. bo = lobj->bo;
  360. r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
  361. if (r) {
  362. return r;
  363. }
  364. }
  365. return 0;
  366. }
  367. static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
  368. struct radeon_cs_parser *parser)
  369. {
  370. struct radeon_cs_chunk *ib_chunk;
  371. struct radeon_fpriv *fpriv = parser->filp->driver_priv;
  372. struct radeon_vm *vm = &fpriv->vm;
  373. int r;
  374. if (parser->chunk_ib_idx == -1)
  375. return 0;
  376. if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
  377. return 0;
  378. if ((rdev->family >= CHIP_TAHITI) &&
  379. (parser->chunk_const_ib_idx != -1)) {
  380. ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
  381. if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
  382. DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
  383. return -EINVAL;
  384. }
  385. r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
  386. ib_chunk->length_dw * 4);
  387. if (r) {
  388. DRM_ERROR("Failed to get const ib !\n");
  389. return r;
  390. }
  391. parser->const_ib->is_const_ib = true;
  392. parser->const_ib->length_dw = ib_chunk->length_dw;
  393. /* Copy the packet into the IB */
  394. if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr,
  395. ib_chunk->length_dw * 4)) {
  396. return -EFAULT;
  397. }
  398. r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
  399. if (r) {
  400. return r;
  401. }
  402. }
  403. ib_chunk = &parser->chunks[parser->chunk_ib_idx];
  404. if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
  405. DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
  406. return -EINVAL;
  407. }
  408. r = radeon_ib_get(rdev, parser->ring, &parser->ib,
  409. ib_chunk->length_dw * 4);
  410. if (r) {
  411. DRM_ERROR("Failed to get ib !\n");
  412. return r;
  413. }
  414. parser->ib->length_dw = ib_chunk->length_dw;
  415. /* Copy the packet into the IB */
  416. if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
  417. ib_chunk->length_dw * 4)) {
  418. return -EFAULT;
  419. }
  420. r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
  421. if (r) {
  422. return r;
  423. }
  424. mutex_lock(&vm->mutex);
  425. r = radeon_vm_bind(rdev, vm);
  426. if (r) {
  427. goto out;
  428. }
  429. r = radeon_bo_vm_update_pte(parser, vm);
  430. if (r) {
  431. goto out;
  432. }
  433. r = radeon_cs_sync_rings(parser);
  434. if (r) {
  435. DRM_ERROR("Failed to synchronize rings !\n");
  436. }
  437. if ((rdev->family >= CHIP_TAHITI) &&
  438. (parser->chunk_const_ib_idx != -1)) {
  439. parser->const_ib->vm_id = vm->id;
  440. /* ib pool is bind at 0 in virtual address space to gpu_addr is the
  441. * offset inside the pool bo
  442. */
  443. parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset;
  444. r = radeon_ib_schedule(rdev, parser->const_ib);
  445. if (r)
  446. goto out;
  447. }
  448. parser->ib->vm_id = vm->id;
  449. /* ib pool is bind at 0 in virtual address space to gpu_addr is the
  450. * offset inside the pool bo
  451. */
  452. parser->ib->gpu_addr = parser->ib->sa_bo.offset;
  453. parser->ib->is_const_ib = false;
  454. r = radeon_ib_schedule(rdev, parser->ib);
  455. out:
  456. if (!r) {
  457. if (vm->fence) {
  458. radeon_fence_unref(&vm->fence);
  459. }
  460. vm->fence = radeon_fence_ref(parser->ib->fence);
  461. }
  462. mutex_unlock(&fpriv->vm.mutex);
  463. return r;
  464. }
  465. int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  466. {
  467. struct radeon_device *rdev = dev->dev_private;
  468. struct radeon_cs_parser parser;
  469. int r;
  470. radeon_mutex_lock(&rdev->cs_mutex);
  471. if (!rdev->accel_working) {
  472. radeon_mutex_unlock(&rdev->cs_mutex);
  473. return -EBUSY;
  474. }
  475. /* initialize parser */
  476. memset(&parser, 0, sizeof(struct radeon_cs_parser));
  477. parser.filp = filp;
  478. parser.rdev = rdev;
  479. parser.dev = rdev->dev;
  480. parser.family = rdev->family;
  481. r = radeon_cs_parser_init(&parser, data);
  482. if (r) {
  483. DRM_ERROR("Failed to initialize parser !\n");
  484. radeon_cs_parser_fini(&parser, r);
  485. radeon_mutex_unlock(&rdev->cs_mutex);
  486. return r;
  487. }
  488. r = radeon_cs_parser_relocs(&parser);
  489. if (r) {
  490. if (r != -ERESTARTSYS)
  491. DRM_ERROR("Failed to parse relocation %d!\n", r);
  492. radeon_cs_parser_fini(&parser, r);
  493. radeon_mutex_unlock(&rdev->cs_mutex);
  494. return r;
  495. }
  496. r = radeon_cs_ib_chunk(rdev, &parser);
  497. if (r) {
  498. goto out;
  499. }
  500. r = radeon_cs_ib_vm_chunk(rdev, &parser);
  501. if (r) {
  502. goto out;
  503. }
  504. out:
  505. radeon_cs_parser_fini(&parser, r);
  506. radeon_mutex_unlock(&rdev->cs_mutex);
  507. return r;
  508. }
  509. int radeon_cs_finish_pages(struct radeon_cs_parser *p)
  510. {
  511. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  512. int i;
  513. int size = PAGE_SIZE;
  514. for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
  515. if (i == ibc->last_page_index) {
  516. size = (ibc->length_dw * 4) % PAGE_SIZE;
  517. if (size == 0)
  518. size = PAGE_SIZE;
  519. }
  520. if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
  521. ibc->user_ptr + (i * PAGE_SIZE),
  522. size))
  523. return -EFAULT;
  524. }
  525. return 0;
  526. }
  527. int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
  528. {
  529. int new_page;
  530. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  531. int i;
  532. int size = PAGE_SIZE;
  533. bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
  534. for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
  535. if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
  536. ibc->user_ptr + (i * PAGE_SIZE),
  537. PAGE_SIZE)) {
  538. p->parser_error = -EFAULT;
  539. return 0;
  540. }
  541. }
  542. if (pg_idx == ibc->last_page_index) {
  543. size = (ibc->length_dw * 4) % PAGE_SIZE;
  544. if (size == 0)
  545. size = PAGE_SIZE;
  546. }
  547. new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
  548. if (copy1)
  549. ibc->kpage[new_page] = p->ib->ptr + (pg_idx * (PAGE_SIZE / 4));
  550. if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
  551. ibc->user_ptr + (pg_idx * PAGE_SIZE),
  552. size)) {
  553. p->parser_error = -EFAULT;
  554. return 0;
  555. }
  556. /* copy to IB for non single case */
  557. if (!copy1)
  558. memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
  559. ibc->last_copied_page = pg_idx;
  560. ibc->kpage_idx[new_page] = pg_idx;
  561. return new_page;
  562. }