intel_sdvo.c 78 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "drm_crtc.h"
  35. #include "drm_edid.h"
  36. #include "intel_drv.h"
  37. #include "i915_drm.h"
  38. #include "i915_drv.h"
  39. #include "intel_sdvo_regs.h"
  40. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  41. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  42. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  43. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  44. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  45. SDVO_TV_MASK)
  46. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  47. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  48. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  49. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  50. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  51. static const char *tv_format_names[] = {
  52. "NTSC_M" , "NTSC_J" , "NTSC_443",
  53. "PAL_B" , "PAL_D" , "PAL_G" ,
  54. "PAL_H" , "PAL_I" , "PAL_M" ,
  55. "PAL_N" , "PAL_NC" , "PAL_60" ,
  56. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  57. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  58. "SECAM_60"
  59. };
  60. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  61. struct intel_sdvo {
  62. struct intel_encoder base;
  63. struct i2c_adapter *i2c;
  64. u8 slave_addr;
  65. struct i2c_adapter ddc;
  66. /* Register for the SDVO device: SDVOB or SDVOC */
  67. uint32_t sdvo_reg;
  68. /* Active outputs controlled by this SDVO output */
  69. uint16_t controlled_output;
  70. /*
  71. * Capabilities of the SDVO device returned by
  72. * i830_sdvo_get_capabilities()
  73. */
  74. struct intel_sdvo_caps caps;
  75. /* Pixel clock limitations reported by the SDVO device, in kHz */
  76. int pixel_clock_min, pixel_clock_max;
  77. /*
  78. * For multiple function SDVO device,
  79. * this is for current attached outputs.
  80. */
  81. uint16_t attached_output;
  82. /*
  83. * Hotplug activation bits for this device
  84. */
  85. uint8_t hotplug_active[2];
  86. /**
  87. * This is used to select the color range of RBG outputs in HDMI mode.
  88. * It is only valid when using TMDS encoding and 8 bit per color mode.
  89. */
  90. uint32_t color_range;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* On different gens SDVOB is at different places. */
  100. bool is_sdvob;
  101. /* This is for current tv format name */
  102. int tv_format_index;
  103. /**
  104. * This is set if we treat the device as HDMI, instead of DVI.
  105. */
  106. bool is_hdmi;
  107. bool has_hdmi_monitor;
  108. bool has_hdmi_audio;
  109. /**
  110. * This is set if we detect output of sdvo device as LVDS and
  111. * have a valid fixed mode to use with the panel.
  112. */
  113. bool is_lvds;
  114. /**
  115. * This is sdvo fixed pannel mode pointer
  116. */
  117. struct drm_display_mode *sdvo_lvds_fixed_mode;
  118. /* DDC bus used by this SDVO encoder */
  119. uint8_t ddc_bus;
  120. /* Input timings for adjusted_mode */
  121. struct intel_sdvo_dtd input_dtd;
  122. };
  123. struct intel_sdvo_connector {
  124. struct intel_connector base;
  125. /* Mark the type of connector */
  126. uint16_t output_flag;
  127. enum hdmi_force_audio force_audio;
  128. /* This contains all current supported TV format */
  129. u8 tv_format_supported[TV_FORMAT_NUM];
  130. int format_supported_num;
  131. struct drm_property *tv_format;
  132. /* add the property for the SDVO-TV */
  133. struct drm_property *left;
  134. struct drm_property *right;
  135. struct drm_property *top;
  136. struct drm_property *bottom;
  137. struct drm_property *hpos;
  138. struct drm_property *vpos;
  139. struct drm_property *contrast;
  140. struct drm_property *saturation;
  141. struct drm_property *hue;
  142. struct drm_property *sharpness;
  143. struct drm_property *flicker_filter;
  144. struct drm_property *flicker_filter_adaptive;
  145. struct drm_property *flicker_filter_2d;
  146. struct drm_property *tv_chroma_filter;
  147. struct drm_property *tv_luma_filter;
  148. struct drm_property *dot_crawl;
  149. /* add the property for the SDVO-TV/LVDS */
  150. struct drm_property *brightness;
  151. /* Add variable to record current setting for the above property */
  152. u32 left_margin, right_margin, top_margin, bottom_margin;
  153. /* this is to get the range of margin.*/
  154. u32 max_hscan, max_vscan;
  155. u32 max_hpos, cur_hpos;
  156. u32 max_vpos, cur_vpos;
  157. u32 cur_brightness, max_brightness;
  158. u32 cur_contrast, max_contrast;
  159. u32 cur_saturation, max_saturation;
  160. u32 cur_hue, max_hue;
  161. u32 cur_sharpness, max_sharpness;
  162. u32 cur_flicker_filter, max_flicker_filter;
  163. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  164. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  165. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  166. u32 cur_tv_luma_filter, max_tv_luma_filter;
  167. u32 cur_dot_crawl, max_dot_crawl;
  168. };
  169. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  170. {
  171. return container_of(encoder, struct intel_sdvo, base.base);
  172. }
  173. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  174. {
  175. return container_of(intel_attached_encoder(connector),
  176. struct intel_sdvo, base);
  177. }
  178. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  179. {
  180. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  181. }
  182. static bool
  183. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  184. static bool
  185. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  186. struct intel_sdvo_connector *intel_sdvo_connector,
  187. int type);
  188. static bool
  189. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  190. struct intel_sdvo_connector *intel_sdvo_connector);
  191. /**
  192. * Writes the SDVOB or SDVOC with the given value, but always writes both
  193. * SDVOB and SDVOC to work around apparent hardware issues (according to
  194. * comments in the BIOS).
  195. */
  196. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  197. {
  198. struct drm_device *dev = intel_sdvo->base.base.dev;
  199. struct drm_i915_private *dev_priv = dev->dev_private;
  200. u32 bval = val, cval = val;
  201. int i;
  202. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  203. I915_WRITE(intel_sdvo->sdvo_reg, val);
  204. I915_READ(intel_sdvo->sdvo_reg);
  205. return;
  206. }
  207. if (intel_sdvo->sdvo_reg == SDVOB) {
  208. cval = I915_READ(SDVOC);
  209. } else {
  210. bval = I915_READ(SDVOB);
  211. }
  212. /*
  213. * Write the registers twice for luck. Sometimes,
  214. * writing them only once doesn't appear to 'stick'.
  215. * The BIOS does this too. Yay, magic
  216. */
  217. for (i = 0; i < 2; i++)
  218. {
  219. I915_WRITE(SDVOB, bval);
  220. I915_READ(SDVOB);
  221. I915_WRITE(SDVOC, cval);
  222. I915_READ(SDVOC);
  223. }
  224. }
  225. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  226. {
  227. struct i2c_msg msgs[] = {
  228. {
  229. .addr = intel_sdvo->slave_addr,
  230. .flags = 0,
  231. .len = 1,
  232. .buf = &addr,
  233. },
  234. {
  235. .addr = intel_sdvo->slave_addr,
  236. .flags = I2C_M_RD,
  237. .len = 1,
  238. .buf = ch,
  239. }
  240. };
  241. int ret;
  242. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  243. return true;
  244. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  245. return false;
  246. }
  247. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  248. /** Mapping of command numbers to names, for debug output */
  249. static const struct _sdvo_cmd_name {
  250. u8 cmd;
  251. const char *name;
  252. } sdvo_cmd_names[] = {
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  296. /* Add the op code for SDVO enhancements */
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  341. /* HDMI op code */
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  360. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  361. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  362. };
  363. #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
  364. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  365. const void *args, int args_len)
  366. {
  367. int i;
  368. DRM_DEBUG_KMS("%s: W: %02X ",
  369. SDVO_NAME(intel_sdvo), cmd);
  370. for (i = 0; i < args_len; i++)
  371. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  372. for (; i < 8; i++)
  373. DRM_LOG_KMS(" ");
  374. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  375. if (cmd == sdvo_cmd_names[i].cmd) {
  376. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  377. break;
  378. }
  379. }
  380. if (i == ARRAY_SIZE(sdvo_cmd_names))
  381. DRM_LOG_KMS("(%02X)", cmd);
  382. DRM_LOG_KMS("\n");
  383. }
  384. static const char *cmd_status_names[] = {
  385. "Power on",
  386. "Success",
  387. "Not supported",
  388. "Invalid arg",
  389. "Pending",
  390. "Target not specified",
  391. "Scaling not supported"
  392. };
  393. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  394. const void *args, int args_len)
  395. {
  396. u8 *buf, status;
  397. struct i2c_msg *msgs;
  398. int i, ret = true;
  399. buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
  400. if (!buf)
  401. return false;
  402. msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
  403. if (!msgs)
  404. return false;
  405. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  406. for (i = 0; i < args_len; i++) {
  407. msgs[i].addr = intel_sdvo->slave_addr;
  408. msgs[i].flags = 0;
  409. msgs[i].len = 2;
  410. msgs[i].buf = buf + 2 *i;
  411. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  412. buf[2*i + 1] = ((u8*)args)[i];
  413. }
  414. msgs[i].addr = intel_sdvo->slave_addr;
  415. msgs[i].flags = 0;
  416. msgs[i].len = 2;
  417. msgs[i].buf = buf + 2*i;
  418. buf[2*i + 0] = SDVO_I2C_OPCODE;
  419. buf[2*i + 1] = cmd;
  420. /* the following two are to read the response */
  421. status = SDVO_I2C_CMD_STATUS;
  422. msgs[i+1].addr = intel_sdvo->slave_addr;
  423. msgs[i+1].flags = 0;
  424. msgs[i+1].len = 1;
  425. msgs[i+1].buf = &status;
  426. msgs[i+2].addr = intel_sdvo->slave_addr;
  427. msgs[i+2].flags = I2C_M_RD;
  428. msgs[i+2].len = 1;
  429. msgs[i+2].buf = &status;
  430. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  431. if (ret < 0) {
  432. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  433. ret = false;
  434. goto out;
  435. }
  436. if (ret != i+3) {
  437. /* failure in I2C transfer */
  438. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  439. ret = false;
  440. }
  441. out:
  442. kfree(msgs);
  443. kfree(buf);
  444. return ret;
  445. }
  446. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  447. void *response, int response_len)
  448. {
  449. u8 retry = 5;
  450. u8 status;
  451. int i;
  452. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  453. /*
  454. * The documentation states that all commands will be
  455. * processed within 15µs, and that we need only poll
  456. * the status byte a maximum of 3 times in order for the
  457. * command to be complete.
  458. *
  459. * Check 5 times in case the hardware failed to read the docs.
  460. */
  461. if (!intel_sdvo_read_byte(intel_sdvo,
  462. SDVO_I2C_CMD_STATUS,
  463. &status))
  464. goto log_fail;
  465. while (status == SDVO_CMD_STATUS_PENDING && retry--) {
  466. udelay(15);
  467. if (!intel_sdvo_read_byte(intel_sdvo,
  468. SDVO_I2C_CMD_STATUS,
  469. &status))
  470. goto log_fail;
  471. }
  472. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  473. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  474. else
  475. DRM_LOG_KMS("(??? %d)", status);
  476. if (status != SDVO_CMD_STATUS_SUCCESS)
  477. goto log_fail;
  478. /* Read the command response */
  479. for (i = 0; i < response_len; i++) {
  480. if (!intel_sdvo_read_byte(intel_sdvo,
  481. SDVO_I2C_RETURN_0 + i,
  482. &((u8 *)response)[i]))
  483. goto log_fail;
  484. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  485. }
  486. DRM_LOG_KMS("\n");
  487. return true;
  488. log_fail:
  489. DRM_LOG_KMS("... failed\n");
  490. return false;
  491. }
  492. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  493. {
  494. if (mode->clock >= 100000)
  495. return 1;
  496. else if (mode->clock >= 50000)
  497. return 2;
  498. else
  499. return 4;
  500. }
  501. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  502. u8 ddc_bus)
  503. {
  504. /* This must be the immediately preceding write before the i2c xfer */
  505. return intel_sdvo_write_cmd(intel_sdvo,
  506. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  507. &ddc_bus, 1);
  508. }
  509. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  510. {
  511. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  512. return false;
  513. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  514. }
  515. static bool
  516. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  517. {
  518. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  519. return false;
  520. return intel_sdvo_read_response(intel_sdvo, value, len);
  521. }
  522. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  523. {
  524. struct intel_sdvo_set_target_input_args targets = {0};
  525. return intel_sdvo_set_value(intel_sdvo,
  526. SDVO_CMD_SET_TARGET_INPUT,
  527. &targets, sizeof(targets));
  528. }
  529. /**
  530. * Return whether each input is trained.
  531. *
  532. * This function is making an assumption about the layout of the response,
  533. * which should be checked against the docs.
  534. */
  535. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  536. {
  537. struct intel_sdvo_get_trained_inputs_response response;
  538. BUILD_BUG_ON(sizeof(response) != 1);
  539. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  540. &response, sizeof(response)))
  541. return false;
  542. *input_1 = response.input0_trained;
  543. *input_2 = response.input1_trained;
  544. return true;
  545. }
  546. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  547. u16 outputs)
  548. {
  549. return intel_sdvo_set_value(intel_sdvo,
  550. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  551. &outputs, sizeof(outputs));
  552. }
  553. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  554. int mode)
  555. {
  556. u8 state = SDVO_ENCODER_STATE_ON;
  557. switch (mode) {
  558. case DRM_MODE_DPMS_ON:
  559. state = SDVO_ENCODER_STATE_ON;
  560. break;
  561. case DRM_MODE_DPMS_STANDBY:
  562. state = SDVO_ENCODER_STATE_STANDBY;
  563. break;
  564. case DRM_MODE_DPMS_SUSPEND:
  565. state = SDVO_ENCODER_STATE_SUSPEND;
  566. break;
  567. case DRM_MODE_DPMS_OFF:
  568. state = SDVO_ENCODER_STATE_OFF;
  569. break;
  570. }
  571. return intel_sdvo_set_value(intel_sdvo,
  572. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  573. }
  574. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  575. int *clock_min,
  576. int *clock_max)
  577. {
  578. struct intel_sdvo_pixel_clock_range clocks;
  579. BUILD_BUG_ON(sizeof(clocks) != 4);
  580. if (!intel_sdvo_get_value(intel_sdvo,
  581. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  582. &clocks, sizeof(clocks)))
  583. return false;
  584. /* Convert the values from units of 10 kHz to kHz. */
  585. *clock_min = clocks.min * 10;
  586. *clock_max = clocks.max * 10;
  587. return true;
  588. }
  589. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  590. u16 outputs)
  591. {
  592. return intel_sdvo_set_value(intel_sdvo,
  593. SDVO_CMD_SET_TARGET_OUTPUT,
  594. &outputs, sizeof(outputs));
  595. }
  596. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  597. struct intel_sdvo_dtd *dtd)
  598. {
  599. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  600. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  601. }
  602. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  603. struct intel_sdvo_dtd *dtd)
  604. {
  605. return intel_sdvo_set_timing(intel_sdvo,
  606. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  607. }
  608. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  609. struct intel_sdvo_dtd *dtd)
  610. {
  611. return intel_sdvo_set_timing(intel_sdvo,
  612. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  613. }
  614. static bool
  615. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  616. uint16_t clock,
  617. uint16_t width,
  618. uint16_t height)
  619. {
  620. struct intel_sdvo_preferred_input_timing_args args;
  621. memset(&args, 0, sizeof(args));
  622. args.clock = clock;
  623. args.width = width;
  624. args.height = height;
  625. args.interlace = 0;
  626. if (intel_sdvo->is_lvds &&
  627. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  628. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  629. args.scaled = 1;
  630. return intel_sdvo_set_value(intel_sdvo,
  631. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  632. &args, sizeof(args));
  633. }
  634. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  635. struct intel_sdvo_dtd *dtd)
  636. {
  637. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  638. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  639. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  640. &dtd->part1, sizeof(dtd->part1)) &&
  641. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  642. &dtd->part2, sizeof(dtd->part2));
  643. }
  644. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  645. {
  646. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  647. }
  648. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  649. const struct drm_display_mode *mode)
  650. {
  651. uint16_t width, height;
  652. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  653. uint16_t h_sync_offset, v_sync_offset;
  654. width = mode->crtc_hdisplay;
  655. height = mode->crtc_vdisplay;
  656. /* do some mode translations */
  657. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  658. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  659. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  660. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  661. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  662. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  663. dtd->part1.clock = mode->clock / 10;
  664. dtd->part1.h_active = width & 0xff;
  665. dtd->part1.h_blank = h_blank_len & 0xff;
  666. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  667. ((h_blank_len >> 8) & 0xf);
  668. dtd->part1.v_active = height & 0xff;
  669. dtd->part1.v_blank = v_blank_len & 0xff;
  670. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  671. ((v_blank_len >> 8) & 0xf);
  672. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  673. dtd->part2.h_sync_width = h_sync_len & 0xff;
  674. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  675. (v_sync_len & 0xf);
  676. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  677. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  678. ((v_sync_len & 0x30) >> 4);
  679. dtd->part2.dtd_flags = 0x18;
  680. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  681. dtd->part2.dtd_flags |= 0x2;
  682. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  683. dtd->part2.dtd_flags |= 0x4;
  684. dtd->part2.sdvo_flags = 0;
  685. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  686. dtd->part2.reserved = 0;
  687. }
  688. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  689. const struct intel_sdvo_dtd *dtd)
  690. {
  691. mode->hdisplay = dtd->part1.h_active;
  692. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  693. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  694. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  695. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  696. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  697. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  698. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  699. mode->vdisplay = dtd->part1.v_active;
  700. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  701. mode->vsync_start = mode->vdisplay;
  702. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  703. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  704. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  705. mode->vsync_end = mode->vsync_start +
  706. (dtd->part2.v_sync_off_width & 0xf);
  707. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  708. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  709. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  710. mode->clock = dtd->part1.clock * 10;
  711. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  712. if (dtd->part2.dtd_flags & 0x2)
  713. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  714. if (dtd->part2.dtd_flags & 0x4)
  715. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  716. }
  717. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  718. {
  719. struct intel_sdvo_encode encode;
  720. BUILD_BUG_ON(sizeof(encode) != 2);
  721. return intel_sdvo_get_value(intel_sdvo,
  722. SDVO_CMD_GET_SUPP_ENCODE,
  723. &encode, sizeof(encode));
  724. }
  725. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  726. uint8_t mode)
  727. {
  728. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  729. }
  730. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  731. uint8_t mode)
  732. {
  733. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  734. }
  735. #if 0
  736. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  737. {
  738. int i, j;
  739. uint8_t set_buf_index[2];
  740. uint8_t av_split;
  741. uint8_t buf_size;
  742. uint8_t buf[48];
  743. uint8_t *pos;
  744. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  745. for (i = 0; i <= av_split; i++) {
  746. set_buf_index[0] = i; set_buf_index[1] = 0;
  747. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  748. set_buf_index, 2);
  749. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  750. intel_sdvo_read_response(encoder, &buf_size, 1);
  751. pos = buf;
  752. for (j = 0; j <= buf_size; j += 8) {
  753. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  754. NULL, 0);
  755. intel_sdvo_read_response(encoder, pos, 8);
  756. pos += 8;
  757. }
  758. }
  759. }
  760. #endif
  761. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
  762. {
  763. struct dip_infoframe avi_if = {
  764. .type = DIP_TYPE_AVI,
  765. .ver = DIP_VERSION_AVI,
  766. .len = DIP_LEN_AVI,
  767. };
  768. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  769. uint8_t set_buf_index[2] = { 1, 0 };
  770. uint64_t *data = (uint64_t *)&avi_if;
  771. unsigned i;
  772. intel_dip_infoframe_csum(&avi_if);
  773. if (!intel_sdvo_set_value(intel_sdvo,
  774. SDVO_CMD_SET_HBUF_INDEX,
  775. set_buf_index, 2))
  776. return false;
  777. for (i = 0; i < sizeof(avi_if); i += 8) {
  778. if (!intel_sdvo_set_value(intel_sdvo,
  779. SDVO_CMD_SET_HBUF_DATA,
  780. data, 8))
  781. return false;
  782. data++;
  783. }
  784. return intel_sdvo_set_value(intel_sdvo,
  785. SDVO_CMD_SET_HBUF_TXRATE,
  786. &tx_rate, 1);
  787. }
  788. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  789. {
  790. struct intel_sdvo_tv_format format;
  791. uint32_t format_map;
  792. format_map = 1 << intel_sdvo->tv_format_index;
  793. memset(&format, 0, sizeof(format));
  794. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  795. BUILD_BUG_ON(sizeof(format) != 6);
  796. return intel_sdvo_set_value(intel_sdvo,
  797. SDVO_CMD_SET_TV_FORMAT,
  798. &format, sizeof(format));
  799. }
  800. static bool
  801. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  802. struct drm_display_mode *mode)
  803. {
  804. struct intel_sdvo_dtd output_dtd;
  805. if (!intel_sdvo_set_target_output(intel_sdvo,
  806. intel_sdvo->attached_output))
  807. return false;
  808. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  809. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  810. return false;
  811. return true;
  812. }
  813. static bool
  814. intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
  815. struct drm_display_mode *mode,
  816. struct drm_display_mode *adjusted_mode)
  817. {
  818. /* Reset the input timing to the screen. Assume always input 0. */
  819. if (!intel_sdvo_set_target_input(intel_sdvo))
  820. return false;
  821. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  822. mode->clock / 10,
  823. mode->hdisplay,
  824. mode->vdisplay))
  825. return false;
  826. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  827. &intel_sdvo->input_dtd))
  828. return false;
  829. intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
  830. return true;
  831. }
  832. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  833. struct drm_display_mode *mode,
  834. struct drm_display_mode *adjusted_mode)
  835. {
  836. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  837. int multiplier;
  838. /* We need to construct preferred input timings based on our
  839. * output timings. To do that, we have to set the output
  840. * timings, even though this isn't really the right place in
  841. * the sequence to do it. Oh well.
  842. */
  843. if (intel_sdvo->is_tv) {
  844. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  845. return false;
  846. (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
  847. mode,
  848. adjusted_mode);
  849. } else if (intel_sdvo->is_lvds) {
  850. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  851. intel_sdvo->sdvo_lvds_fixed_mode))
  852. return false;
  853. (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
  854. mode,
  855. adjusted_mode);
  856. }
  857. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  858. * SDVO device will factor out the multiplier during mode_set.
  859. */
  860. multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
  861. intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  862. return true;
  863. }
  864. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  865. struct drm_display_mode *mode,
  866. struct drm_display_mode *adjusted_mode)
  867. {
  868. struct drm_device *dev = encoder->dev;
  869. struct drm_i915_private *dev_priv = dev->dev_private;
  870. struct drm_crtc *crtc = encoder->crtc;
  871. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  872. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  873. u32 sdvox;
  874. struct intel_sdvo_in_out_map in_out;
  875. struct intel_sdvo_dtd input_dtd;
  876. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  877. int rate;
  878. if (!mode)
  879. return;
  880. /* First, set the input mapping for the first input to our controlled
  881. * output. This is only correct if we're a single-input device, in
  882. * which case the first input is the output from the appropriate SDVO
  883. * channel on the motherboard. In a two-input device, the first input
  884. * will be SDVOB and the second SDVOC.
  885. */
  886. in_out.in0 = intel_sdvo->attached_output;
  887. in_out.in1 = 0;
  888. intel_sdvo_set_value(intel_sdvo,
  889. SDVO_CMD_SET_IN_OUT_MAP,
  890. &in_out, sizeof(in_out));
  891. /* Set the output timings to the screen */
  892. if (!intel_sdvo_set_target_output(intel_sdvo,
  893. intel_sdvo->attached_output))
  894. return;
  895. /* We have tried to get input timing in mode_fixup, and filled into
  896. * adjusted_mode.
  897. */
  898. if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
  899. input_dtd = intel_sdvo->input_dtd;
  900. } else {
  901. /* Set the output timing to the screen */
  902. if (!intel_sdvo_set_target_output(intel_sdvo,
  903. intel_sdvo->attached_output))
  904. return;
  905. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  906. (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
  907. }
  908. /* Set the input timing to the screen. Assume always input 0. */
  909. if (!intel_sdvo_set_target_input(intel_sdvo))
  910. return;
  911. if (intel_sdvo->has_hdmi_monitor) {
  912. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  913. intel_sdvo_set_colorimetry(intel_sdvo,
  914. SDVO_COLORIMETRY_RGB256);
  915. intel_sdvo_set_avi_infoframe(intel_sdvo);
  916. } else
  917. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  918. if (intel_sdvo->is_tv &&
  919. !intel_sdvo_set_tv_format(intel_sdvo))
  920. return;
  921. (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
  922. switch (pixel_multiplier) {
  923. default:
  924. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  925. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  926. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  927. }
  928. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  929. return;
  930. /* Set the SDVO control regs. */
  931. if (INTEL_INFO(dev)->gen >= 4) {
  932. /* The real mode polarity is set by the SDVO commands, using
  933. * struct intel_sdvo_dtd. */
  934. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  935. if (intel_sdvo->is_hdmi)
  936. sdvox |= intel_sdvo->color_range;
  937. if (INTEL_INFO(dev)->gen < 5)
  938. sdvox |= SDVO_BORDER_ENABLE;
  939. } else {
  940. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  941. switch (intel_sdvo->sdvo_reg) {
  942. case SDVOB:
  943. sdvox &= SDVOB_PRESERVE_MASK;
  944. break;
  945. case SDVOC:
  946. sdvox &= SDVOC_PRESERVE_MASK;
  947. break;
  948. }
  949. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  950. }
  951. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  952. sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
  953. else
  954. sdvox |= TRANSCODER(intel_crtc->pipe);
  955. if (intel_sdvo->has_hdmi_audio)
  956. sdvox |= SDVO_AUDIO_ENABLE;
  957. if (INTEL_INFO(dev)->gen >= 4) {
  958. /* done in crtc_mode_set as the dpll_md reg must be written early */
  959. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  960. /* done in crtc_mode_set as it lives inside the dpll register */
  961. } else {
  962. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  963. }
  964. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  965. INTEL_INFO(dev)->gen < 5)
  966. sdvox |= SDVO_STALL_SELECT;
  967. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  968. }
  969. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  970. {
  971. struct drm_device *dev = encoder->dev;
  972. struct drm_i915_private *dev_priv = dev->dev_private;
  973. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  974. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  975. u32 temp;
  976. if (mode != DRM_MODE_DPMS_ON) {
  977. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  978. if (0)
  979. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  980. if (mode == DRM_MODE_DPMS_OFF) {
  981. temp = I915_READ(intel_sdvo->sdvo_reg);
  982. if ((temp & SDVO_ENABLE) != 0) {
  983. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  984. }
  985. }
  986. } else {
  987. bool input1, input2;
  988. int i;
  989. u8 status;
  990. temp = I915_READ(intel_sdvo->sdvo_reg);
  991. if ((temp & SDVO_ENABLE) == 0)
  992. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  993. for (i = 0; i < 2; i++)
  994. intel_wait_for_vblank(dev, intel_crtc->pipe);
  995. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  996. /* Warn if the device reported failure to sync.
  997. * A lot of SDVO devices fail to notify of sync, but it's
  998. * a given it the status is a success, we succeeded.
  999. */
  1000. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1001. DRM_DEBUG_KMS("First %s output reported failure to "
  1002. "sync\n", SDVO_NAME(intel_sdvo));
  1003. }
  1004. if (0)
  1005. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1006. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1007. }
  1008. return;
  1009. }
  1010. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1011. struct drm_display_mode *mode)
  1012. {
  1013. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1014. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1015. return MODE_NO_DBLESCAN;
  1016. if (intel_sdvo->pixel_clock_min > mode->clock)
  1017. return MODE_CLOCK_LOW;
  1018. if (intel_sdvo->pixel_clock_max < mode->clock)
  1019. return MODE_CLOCK_HIGH;
  1020. if (intel_sdvo->is_lvds) {
  1021. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1022. return MODE_PANEL;
  1023. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1024. return MODE_PANEL;
  1025. }
  1026. return MODE_OK;
  1027. }
  1028. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1029. {
  1030. BUILD_BUG_ON(sizeof(*caps) != 8);
  1031. if (!intel_sdvo_get_value(intel_sdvo,
  1032. SDVO_CMD_GET_DEVICE_CAPS,
  1033. caps, sizeof(*caps)))
  1034. return false;
  1035. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1036. " vendor_id: %d\n"
  1037. " device_id: %d\n"
  1038. " device_rev_id: %d\n"
  1039. " sdvo_version_major: %d\n"
  1040. " sdvo_version_minor: %d\n"
  1041. " sdvo_inputs_mask: %d\n"
  1042. " smooth_scaling: %d\n"
  1043. " sharp_scaling: %d\n"
  1044. " up_scaling: %d\n"
  1045. " down_scaling: %d\n"
  1046. " stall_support: %d\n"
  1047. " output_flags: %d\n",
  1048. caps->vendor_id,
  1049. caps->device_id,
  1050. caps->device_rev_id,
  1051. caps->sdvo_version_major,
  1052. caps->sdvo_version_minor,
  1053. caps->sdvo_inputs_mask,
  1054. caps->smooth_scaling,
  1055. caps->sharp_scaling,
  1056. caps->up_scaling,
  1057. caps->down_scaling,
  1058. caps->stall_support,
  1059. caps->output_flags);
  1060. return true;
  1061. }
  1062. static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
  1063. {
  1064. u8 response[2];
  1065. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1066. &response, 2) && response[0];
  1067. }
  1068. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1069. {
  1070. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1071. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
  1072. }
  1073. static bool
  1074. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1075. {
  1076. /* Is there more than one type of output? */
  1077. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1078. }
  1079. static struct edid *
  1080. intel_sdvo_get_edid(struct drm_connector *connector)
  1081. {
  1082. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1083. return drm_get_edid(connector, &sdvo->ddc);
  1084. }
  1085. /* Mac mini hack -- use the same DDC as the analog connector */
  1086. static struct edid *
  1087. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1088. {
  1089. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1090. return drm_get_edid(connector,
  1091. intel_gmbus_get_adapter(dev_priv,
  1092. dev_priv->crt_ddc_pin));
  1093. }
  1094. static enum drm_connector_status
  1095. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1096. {
  1097. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1098. enum drm_connector_status status;
  1099. struct edid *edid;
  1100. edid = intel_sdvo_get_edid(connector);
  1101. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1102. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1103. /*
  1104. * Don't use the 1 as the argument of DDC bus switch to get
  1105. * the EDID. It is used for SDVO SPD ROM.
  1106. */
  1107. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1108. intel_sdvo->ddc_bus = ddc;
  1109. edid = intel_sdvo_get_edid(connector);
  1110. if (edid)
  1111. break;
  1112. }
  1113. /*
  1114. * If we found the EDID on the other bus,
  1115. * assume that is the correct DDC bus.
  1116. */
  1117. if (edid == NULL)
  1118. intel_sdvo->ddc_bus = saved_ddc;
  1119. }
  1120. /*
  1121. * When there is no edid and no monitor is connected with VGA
  1122. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1123. */
  1124. if (edid == NULL)
  1125. edid = intel_sdvo_get_analog_edid(connector);
  1126. status = connector_status_unknown;
  1127. if (edid != NULL) {
  1128. /* DDC bus is shared, match EDID to connector type */
  1129. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1130. status = connector_status_connected;
  1131. if (intel_sdvo->is_hdmi) {
  1132. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1133. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1134. }
  1135. } else
  1136. status = connector_status_disconnected;
  1137. connector->display_info.raw_edid = NULL;
  1138. kfree(edid);
  1139. }
  1140. if (status == connector_status_connected) {
  1141. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1142. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1143. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1144. }
  1145. return status;
  1146. }
  1147. static bool
  1148. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1149. struct edid *edid)
  1150. {
  1151. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1152. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1153. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1154. connector_is_digital, monitor_is_digital);
  1155. return connector_is_digital == monitor_is_digital;
  1156. }
  1157. static enum drm_connector_status
  1158. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1159. {
  1160. uint16_t response;
  1161. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1162. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1163. enum drm_connector_status ret;
  1164. if (!intel_sdvo_write_cmd(intel_sdvo,
  1165. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1166. return connector_status_unknown;
  1167. /* add 30ms delay when the output type might be TV */
  1168. if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
  1169. mdelay(30);
  1170. if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
  1171. return connector_status_unknown;
  1172. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1173. response & 0xff, response >> 8,
  1174. intel_sdvo_connector->output_flag);
  1175. if (response == 0)
  1176. return connector_status_disconnected;
  1177. intel_sdvo->attached_output = response;
  1178. intel_sdvo->has_hdmi_monitor = false;
  1179. intel_sdvo->has_hdmi_audio = false;
  1180. if ((intel_sdvo_connector->output_flag & response) == 0)
  1181. ret = connector_status_disconnected;
  1182. else if (IS_TMDS(intel_sdvo_connector))
  1183. ret = intel_sdvo_tmds_sink_detect(connector);
  1184. else {
  1185. struct edid *edid;
  1186. /* if we have an edid check it matches the connection */
  1187. edid = intel_sdvo_get_edid(connector);
  1188. if (edid == NULL)
  1189. edid = intel_sdvo_get_analog_edid(connector);
  1190. if (edid != NULL) {
  1191. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1192. edid))
  1193. ret = connector_status_connected;
  1194. else
  1195. ret = connector_status_disconnected;
  1196. connector->display_info.raw_edid = NULL;
  1197. kfree(edid);
  1198. } else
  1199. ret = connector_status_connected;
  1200. }
  1201. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1202. if (ret == connector_status_connected) {
  1203. intel_sdvo->is_tv = false;
  1204. intel_sdvo->is_lvds = false;
  1205. intel_sdvo->base.needs_tv_clock = false;
  1206. if (response & SDVO_TV_MASK) {
  1207. intel_sdvo->is_tv = true;
  1208. intel_sdvo->base.needs_tv_clock = true;
  1209. }
  1210. if (response & SDVO_LVDS_MASK)
  1211. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1212. }
  1213. return ret;
  1214. }
  1215. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1216. {
  1217. struct edid *edid;
  1218. /* set the bus switch and get the modes */
  1219. edid = intel_sdvo_get_edid(connector);
  1220. /*
  1221. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1222. * link between analog and digital outputs. So, if the regular SDVO
  1223. * DDC fails, check to see if the analog output is disconnected, in
  1224. * which case we'll look there for the digital DDC data.
  1225. */
  1226. if (edid == NULL)
  1227. edid = intel_sdvo_get_analog_edid(connector);
  1228. if (edid != NULL) {
  1229. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1230. edid)) {
  1231. drm_mode_connector_update_edid_property(connector, edid);
  1232. drm_add_edid_modes(connector, edid);
  1233. }
  1234. connector->display_info.raw_edid = NULL;
  1235. kfree(edid);
  1236. }
  1237. }
  1238. /*
  1239. * Set of SDVO TV modes.
  1240. * Note! This is in reply order (see loop in get_tv_modes).
  1241. * XXX: all 60Hz refresh?
  1242. */
  1243. static const struct drm_display_mode sdvo_tv_modes[] = {
  1244. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1245. 416, 0, 200, 201, 232, 233, 0,
  1246. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1247. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1248. 416, 0, 240, 241, 272, 273, 0,
  1249. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1250. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1251. 496, 0, 300, 301, 332, 333, 0,
  1252. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1253. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1254. 736, 0, 350, 351, 382, 383, 0,
  1255. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1256. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1257. 736, 0, 400, 401, 432, 433, 0,
  1258. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1259. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1260. 736, 0, 480, 481, 512, 513, 0,
  1261. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1262. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1263. 800, 0, 480, 481, 512, 513, 0,
  1264. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1265. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1266. 800, 0, 576, 577, 608, 609, 0,
  1267. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1268. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1269. 816, 0, 350, 351, 382, 383, 0,
  1270. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1271. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1272. 816, 0, 400, 401, 432, 433, 0,
  1273. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1274. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1275. 816, 0, 480, 481, 512, 513, 0,
  1276. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1277. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1278. 816, 0, 540, 541, 572, 573, 0,
  1279. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1280. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1281. 816, 0, 576, 577, 608, 609, 0,
  1282. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1283. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1284. 864, 0, 576, 577, 608, 609, 0,
  1285. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1286. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1287. 896, 0, 600, 601, 632, 633, 0,
  1288. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1289. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1290. 928, 0, 624, 625, 656, 657, 0,
  1291. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1292. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1293. 1016, 0, 766, 767, 798, 799, 0,
  1294. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1295. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1296. 1120, 0, 768, 769, 800, 801, 0,
  1297. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1298. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1299. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1300. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1301. };
  1302. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1303. {
  1304. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1305. struct intel_sdvo_sdtv_resolution_request tv_res;
  1306. uint32_t reply = 0, format_map = 0;
  1307. int i;
  1308. /* Read the list of supported input resolutions for the selected TV
  1309. * format.
  1310. */
  1311. format_map = 1 << intel_sdvo->tv_format_index;
  1312. memcpy(&tv_res, &format_map,
  1313. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1314. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1315. return;
  1316. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1317. if (!intel_sdvo_write_cmd(intel_sdvo,
  1318. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1319. &tv_res, sizeof(tv_res)))
  1320. return;
  1321. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1322. return;
  1323. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1324. if (reply & (1 << i)) {
  1325. struct drm_display_mode *nmode;
  1326. nmode = drm_mode_duplicate(connector->dev,
  1327. &sdvo_tv_modes[i]);
  1328. if (nmode)
  1329. drm_mode_probed_add(connector, nmode);
  1330. }
  1331. }
  1332. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1333. {
  1334. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1335. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1336. struct drm_display_mode *newmode;
  1337. /*
  1338. * Attempt to get the mode list from DDC.
  1339. * Assume that the preferred modes are
  1340. * arranged in priority order.
  1341. */
  1342. intel_ddc_get_modes(connector, intel_sdvo->i2c);
  1343. if (list_empty(&connector->probed_modes) == false)
  1344. goto end;
  1345. /* Fetch modes from VBT */
  1346. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1347. newmode = drm_mode_duplicate(connector->dev,
  1348. dev_priv->sdvo_lvds_vbt_mode);
  1349. if (newmode != NULL) {
  1350. /* Guarantee the mode is preferred */
  1351. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1352. DRM_MODE_TYPE_DRIVER);
  1353. drm_mode_probed_add(connector, newmode);
  1354. }
  1355. }
  1356. end:
  1357. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1358. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1359. intel_sdvo->sdvo_lvds_fixed_mode =
  1360. drm_mode_duplicate(connector->dev, newmode);
  1361. drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
  1362. 0);
  1363. intel_sdvo->is_lvds = true;
  1364. break;
  1365. }
  1366. }
  1367. }
  1368. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1369. {
  1370. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1371. if (IS_TV(intel_sdvo_connector))
  1372. intel_sdvo_get_tv_modes(connector);
  1373. else if (IS_LVDS(intel_sdvo_connector))
  1374. intel_sdvo_get_lvds_modes(connector);
  1375. else
  1376. intel_sdvo_get_ddc_modes(connector);
  1377. return !list_empty(&connector->probed_modes);
  1378. }
  1379. static void
  1380. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1381. {
  1382. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1383. struct drm_device *dev = connector->dev;
  1384. if (intel_sdvo_connector->left)
  1385. drm_property_destroy(dev, intel_sdvo_connector->left);
  1386. if (intel_sdvo_connector->right)
  1387. drm_property_destroy(dev, intel_sdvo_connector->right);
  1388. if (intel_sdvo_connector->top)
  1389. drm_property_destroy(dev, intel_sdvo_connector->top);
  1390. if (intel_sdvo_connector->bottom)
  1391. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1392. if (intel_sdvo_connector->hpos)
  1393. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1394. if (intel_sdvo_connector->vpos)
  1395. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1396. if (intel_sdvo_connector->saturation)
  1397. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1398. if (intel_sdvo_connector->contrast)
  1399. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1400. if (intel_sdvo_connector->hue)
  1401. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1402. if (intel_sdvo_connector->sharpness)
  1403. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1404. if (intel_sdvo_connector->flicker_filter)
  1405. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1406. if (intel_sdvo_connector->flicker_filter_2d)
  1407. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1408. if (intel_sdvo_connector->flicker_filter_adaptive)
  1409. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1410. if (intel_sdvo_connector->tv_luma_filter)
  1411. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1412. if (intel_sdvo_connector->tv_chroma_filter)
  1413. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1414. if (intel_sdvo_connector->dot_crawl)
  1415. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1416. if (intel_sdvo_connector->brightness)
  1417. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1418. }
  1419. static void intel_sdvo_destroy(struct drm_connector *connector)
  1420. {
  1421. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1422. if (intel_sdvo_connector->tv_format)
  1423. drm_property_destroy(connector->dev,
  1424. intel_sdvo_connector->tv_format);
  1425. intel_sdvo_destroy_enhance_property(connector);
  1426. drm_sysfs_connector_remove(connector);
  1427. drm_connector_cleanup(connector);
  1428. kfree(connector);
  1429. }
  1430. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1431. {
  1432. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1433. struct edid *edid;
  1434. bool has_audio = false;
  1435. if (!intel_sdvo->is_hdmi)
  1436. return false;
  1437. edid = intel_sdvo_get_edid(connector);
  1438. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1439. has_audio = drm_detect_monitor_audio(edid);
  1440. return has_audio;
  1441. }
  1442. static int
  1443. intel_sdvo_set_property(struct drm_connector *connector,
  1444. struct drm_property *property,
  1445. uint64_t val)
  1446. {
  1447. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1448. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1449. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1450. uint16_t temp_value;
  1451. uint8_t cmd;
  1452. int ret;
  1453. ret = drm_connector_property_set_value(connector, property, val);
  1454. if (ret)
  1455. return ret;
  1456. if (property == dev_priv->force_audio_property) {
  1457. int i = val;
  1458. bool has_audio;
  1459. if (i == intel_sdvo_connector->force_audio)
  1460. return 0;
  1461. intel_sdvo_connector->force_audio = i;
  1462. if (i == HDMI_AUDIO_AUTO)
  1463. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1464. else
  1465. has_audio = (i == HDMI_AUDIO_ON);
  1466. if (has_audio == intel_sdvo->has_hdmi_audio)
  1467. return 0;
  1468. intel_sdvo->has_hdmi_audio = has_audio;
  1469. goto done;
  1470. }
  1471. if (property == dev_priv->broadcast_rgb_property) {
  1472. if (val == !!intel_sdvo->color_range)
  1473. return 0;
  1474. intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1475. goto done;
  1476. }
  1477. #define CHECK_PROPERTY(name, NAME) \
  1478. if (intel_sdvo_connector->name == property) { \
  1479. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1480. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1481. cmd = SDVO_CMD_SET_##NAME; \
  1482. intel_sdvo_connector->cur_##name = temp_value; \
  1483. goto set_value; \
  1484. }
  1485. if (property == intel_sdvo_connector->tv_format) {
  1486. if (val >= TV_FORMAT_NUM)
  1487. return -EINVAL;
  1488. if (intel_sdvo->tv_format_index ==
  1489. intel_sdvo_connector->tv_format_supported[val])
  1490. return 0;
  1491. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1492. goto done;
  1493. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1494. temp_value = val;
  1495. if (intel_sdvo_connector->left == property) {
  1496. drm_connector_property_set_value(connector,
  1497. intel_sdvo_connector->right, val);
  1498. if (intel_sdvo_connector->left_margin == temp_value)
  1499. return 0;
  1500. intel_sdvo_connector->left_margin = temp_value;
  1501. intel_sdvo_connector->right_margin = temp_value;
  1502. temp_value = intel_sdvo_connector->max_hscan -
  1503. intel_sdvo_connector->left_margin;
  1504. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1505. goto set_value;
  1506. } else if (intel_sdvo_connector->right == property) {
  1507. drm_connector_property_set_value(connector,
  1508. intel_sdvo_connector->left, val);
  1509. if (intel_sdvo_connector->right_margin == temp_value)
  1510. return 0;
  1511. intel_sdvo_connector->left_margin = temp_value;
  1512. intel_sdvo_connector->right_margin = temp_value;
  1513. temp_value = intel_sdvo_connector->max_hscan -
  1514. intel_sdvo_connector->left_margin;
  1515. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1516. goto set_value;
  1517. } else if (intel_sdvo_connector->top == property) {
  1518. drm_connector_property_set_value(connector,
  1519. intel_sdvo_connector->bottom, val);
  1520. if (intel_sdvo_connector->top_margin == temp_value)
  1521. return 0;
  1522. intel_sdvo_connector->top_margin = temp_value;
  1523. intel_sdvo_connector->bottom_margin = temp_value;
  1524. temp_value = intel_sdvo_connector->max_vscan -
  1525. intel_sdvo_connector->top_margin;
  1526. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1527. goto set_value;
  1528. } else if (intel_sdvo_connector->bottom == property) {
  1529. drm_connector_property_set_value(connector,
  1530. intel_sdvo_connector->top, val);
  1531. if (intel_sdvo_connector->bottom_margin == temp_value)
  1532. return 0;
  1533. intel_sdvo_connector->top_margin = temp_value;
  1534. intel_sdvo_connector->bottom_margin = temp_value;
  1535. temp_value = intel_sdvo_connector->max_vscan -
  1536. intel_sdvo_connector->top_margin;
  1537. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1538. goto set_value;
  1539. }
  1540. CHECK_PROPERTY(hpos, HPOS)
  1541. CHECK_PROPERTY(vpos, VPOS)
  1542. CHECK_PROPERTY(saturation, SATURATION)
  1543. CHECK_PROPERTY(contrast, CONTRAST)
  1544. CHECK_PROPERTY(hue, HUE)
  1545. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1546. CHECK_PROPERTY(sharpness, SHARPNESS)
  1547. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1548. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1549. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1550. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1551. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1552. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1553. }
  1554. return -EINVAL; /* unknown property */
  1555. set_value:
  1556. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1557. return -EIO;
  1558. done:
  1559. if (intel_sdvo->base.base.crtc) {
  1560. struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
  1561. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1562. crtc->y, crtc->fb);
  1563. }
  1564. return 0;
  1565. #undef CHECK_PROPERTY
  1566. }
  1567. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1568. .dpms = intel_sdvo_dpms,
  1569. .mode_fixup = intel_sdvo_mode_fixup,
  1570. .prepare = intel_encoder_prepare,
  1571. .mode_set = intel_sdvo_mode_set,
  1572. .commit = intel_encoder_commit,
  1573. };
  1574. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1575. .dpms = drm_helper_connector_dpms,
  1576. .detect = intel_sdvo_detect,
  1577. .fill_modes = drm_helper_probe_single_connector_modes,
  1578. .set_property = intel_sdvo_set_property,
  1579. .destroy = intel_sdvo_destroy,
  1580. };
  1581. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1582. .get_modes = intel_sdvo_get_modes,
  1583. .mode_valid = intel_sdvo_mode_valid,
  1584. .best_encoder = intel_best_encoder,
  1585. };
  1586. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1587. {
  1588. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1589. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1590. drm_mode_destroy(encoder->dev,
  1591. intel_sdvo->sdvo_lvds_fixed_mode);
  1592. i2c_del_adapter(&intel_sdvo->ddc);
  1593. intel_encoder_destroy(encoder);
  1594. }
  1595. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1596. .destroy = intel_sdvo_enc_destroy,
  1597. };
  1598. static void
  1599. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1600. {
  1601. uint16_t mask = 0;
  1602. unsigned int num_bits;
  1603. /* Make a mask of outputs less than or equal to our own priority in the
  1604. * list.
  1605. */
  1606. switch (sdvo->controlled_output) {
  1607. case SDVO_OUTPUT_LVDS1:
  1608. mask |= SDVO_OUTPUT_LVDS1;
  1609. case SDVO_OUTPUT_LVDS0:
  1610. mask |= SDVO_OUTPUT_LVDS0;
  1611. case SDVO_OUTPUT_TMDS1:
  1612. mask |= SDVO_OUTPUT_TMDS1;
  1613. case SDVO_OUTPUT_TMDS0:
  1614. mask |= SDVO_OUTPUT_TMDS0;
  1615. case SDVO_OUTPUT_RGB1:
  1616. mask |= SDVO_OUTPUT_RGB1;
  1617. case SDVO_OUTPUT_RGB0:
  1618. mask |= SDVO_OUTPUT_RGB0;
  1619. break;
  1620. }
  1621. /* Count bits to find what number we are in the priority list. */
  1622. mask &= sdvo->caps.output_flags;
  1623. num_bits = hweight16(mask);
  1624. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1625. if (num_bits > 3)
  1626. num_bits = 3;
  1627. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1628. sdvo->ddc_bus = 1 << num_bits;
  1629. }
  1630. /**
  1631. * Choose the appropriate DDC bus for control bus switch command for this
  1632. * SDVO output based on the controlled output.
  1633. *
  1634. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1635. * outputs, then LVDS outputs.
  1636. */
  1637. static void
  1638. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1639. struct intel_sdvo *sdvo, u32 reg)
  1640. {
  1641. struct sdvo_device_mapping *mapping;
  1642. if (sdvo->is_sdvob)
  1643. mapping = &(dev_priv->sdvo_mappings[0]);
  1644. else
  1645. mapping = &(dev_priv->sdvo_mappings[1]);
  1646. if (mapping->initialized)
  1647. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1648. else
  1649. intel_sdvo_guess_ddc_bus(sdvo);
  1650. }
  1651. static void
  1652. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1653. struct intel_sdvo *sdvo, u32 reg)
  1654. {
  1655. struct sdvo_device_mapping *mapping;
  1656. u8 pin;
  1657. if (sdvo->is_sdvob)
  1658. mapping = &dev_priv->sdvo_mappings[0];
  1659. else
  1660. mapping = &dev_priv->sdvo_mappings[1];
  1661. pin = GMBUS_PORT_DPB;
  1662. if (mapping->initialized)
  1663. pin = mapping->i2c_pin;
  1664. if (intel_gmbus_is_port_valid(pin)) {
  1665. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
  1666. intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
  1667. intel_gmbus_force_bit(sdvo->i2c, true);
  1668. } else {
  1669. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  1670. }
  1671. }
  1672. static bool
  1673. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1674. {
  1675. return intel_sdvo_check_supp_encode(intel_sdvo);
  1676. }
  1677. static u8
  1678. intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
  1679. {
  1680. struct drm_i915_private *dev_priv = dev->dev_private;
  1681. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1682. if (sdvo->is_sdvob) {
  1683. my_mapping = &dev_priv->sdvo_mappings[0];
  1684. other_mapping = &dev_priv->sdvo_mappings[1];
  1685. } else {
  1686. my_mapping = &dev_priv->sdvo_mappings[1];
  1687. other_mapping = &dev_priv->sdvo_mappings[0];
  1688. }
  1689. /* If the BIOS described our SDVO device, take advantage of it. */
  1690. if (my_mapping->slave_addr)
  1691. return my_mapping->slave_addr;
  1692. /* If the BIOS only described a different SDVO device, use the
  1693. * address that it isn't using.
  1694. */
  1695. if (other_mapping->slave_addr) {
  1696. if (other_mapping->slave_addr == 0x70)
  1697. return 0x72;
  1698. else
  1699. return 0x70;
  1700. }
  1701. /* No SDVO device info is found for another DVO port,
  1702. * so use mapping assumption we had before BIOS parsing.
  1703. */
  1704. if (sdvo->is_sdvob)
  1705. return 0x70;
  1706. else
  1707. return 0x72;
  1708. }
  1709. static void
  1710. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1711. struct intel_sdvo *encoder)
  1712. {
  1713. drm_connector_init(encoder->base.base.dev,
  1714. &connector->base.base,
  1715. &intel_sdvo_connector_funcs,
  1716. connector->base.base.connector_type);
  1717. drm_connector_helper_add(&connector->base.base,
  1718. &intel_sdvo_connector_helper_funcs);
  1719. connector->base.base.interlace_allowed = 1;
  1720. connector->base.base.doublescan_allowed = 0;
  1721. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1722. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1723. drm_sysfs_connector_add(&connector->base.base);
  1724. }
  1725. static void
  1726. intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
  1727. {
  1728. struct drm_device *dev = connector->base.base.dev;
  1729. intel_attach_force_audio_property(&connector->base.base);
  1730. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
  1731. intel_attach_broadcast_rgb_property(&connector->base.base);
  1732. }
  1733. static bool
  1734. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1735. {
  1736. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1737. struct drm_connector *connector;
  1738. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  1739. struct intel_connector *intel_connector;
  1740. struct intel_sdvo_connector *intel_sdvo_connector;
  1741. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1742. if (!intel_sdvo_connector)
  1743. return false;
  1744. if (device == 0) {
  1745. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1746. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1747. } else if (device == 1) {
  1748. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1749. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1750. }
  1751. intel_connector = &intel_sdvo_connector->base;
  1752. connector = &intel_connector->base;
  1753. if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
  1754. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1755. intel_sdvo->hotplug_active[0] |= 1 << device;
  1756. /* Some SDVO devices have one-shot hotplug interrupts.
  1757. * Ensure that they get re-enabled when an interrupt happens.
  1758. */
  1759. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  1760. intel_sdvo_enable_hotplug(intel_encoder);
  1761. }
  1762. else
  1763. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1764. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1765. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1766. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1767. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1768. intel_sdvo->is_hdmi = true;
  1769. }
  1770. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1771. (1 << INTEL_ANALOG_CLONE_BIT));
  1772. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1773. if (intel_sdvo->is_hdmi)
  1774. intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
  1775. return true;
  1776. }
  1777. static bool
  1778. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1779. {
  1780. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1781. struct drm_connector *connector;
  1782. struct intel_connector *intel_connector;
  1783. struct intel_sdvo_connector *intel_sdvo_connector;
  1784. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1785. if (!intel_sdvo_connector)
  1786. return false;
  1787. intel_connector = &intel_sdvo_connector->base;
  1788. connector = &intel_connector->base;
  1789. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1790. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1791. intel_sdvo->controlled_output |= type;
  1792. intel_sdvo_connector->output_flag = type;
  1793. intel_sdvo->is_tv = true;
  1794. intel_sdvo->base.needs_tv_clock = true;
  1795. intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1796. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1797. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1798. goto err;
  1799. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1800. goto err;
  1801. return true;
  1802. err:
  1803. intel_sdvo_destroy(connector);
  1804. return false;
  1805. }
  1806. static bool
  1807. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1808. {
  1809. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1810. struct drm_connector *connector;
  1811. struct intel_connector *intel_connector;
  1812. struct intel_sdvo_connector *intel_sdvo_connector;
  1813. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1814. if (!intel_sdvo_connector)
  1815. return false;
  1816. intel_connector = &intel_sdvo_connector->base;
  1817. connector = &intel_connector->base;
  1818. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1819. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1820. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1821. if (device == 0) {
  1822. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1823. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1824. } else if (device == 1) {
  1825. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1826. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1827. }
  1828. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1829. (1 << INTEL_ANALOG_CLONE_BIT));
  1830. intel_sdvo_connector_init(intel_sdvo_connector,
  1831. intel_sdvo);
  1832. return true;
  1833. }
  1834. static bool
  1835. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  1836. {
  1837. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1838. struct drm_connector *connector;
  1839. struct intel_connector *intel_connector;
  1840. struct intel_sdvo_connector *intel_sdvo_connector;
  1841. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1842. if (!intel_sdvo_connector)
  1843. return false;
  1844. intel_connector = &intel_sdvo_connector->base;
  1845. connector = &intel_connector->base;
  1846. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1847. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1848. if (device == 0) {
  1849. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1850. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1851. } else if (device == 1) {
  1852. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1853. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1854. }
  1855. intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1856. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1857. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1858. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1859. goto err;
  1860. return true;
  1861. err:
  1862. intel_sdvo_destroy(connector);
  1863. return false;
  1864. }
  1865. static bool
  1866. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  1867. {
  1868. intel_sdvo->is_tv = false;
  1869. intel_sdvo->base.needs_tv_clock = false;
  1870. intel_sdvo->is_lvds = false;
  1871. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1872. if (flags & SDVO_OUTPUT_TMDS0)
  1873. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  1874. return false;
  1875. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1876. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  1877. return false;
  1878. /* TV has no XXX1 function block */
  1879. if (flags & SDVO_OUTPUT_SVID0)
  1880. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  1881. return false;
  1882. if (flags & SDVO_OUTPUT_CVBS0)
  1883. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  1884. return false;
  1885. if (flags & SDVO_OUTPUT_YPRPB0)
  1886. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
  1887. return false;
  1888. if (flags & SDVO_OUTPUT_RGB0)
  1889. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  1890. return false;
  1891. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1892. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  1893. return false;
  1894. if (flags & SDVO_OUTPUT_LVDS0)
  1895. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  1896. return false;
  1897. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1898. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  1899. return false;
  1900. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1901. unsigned char bytes[2];
  1902. intel_sdvo->controlled_output = 0;
  1903. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  1904. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1905. SDVO_NAME(intel_sdvo),
  1906. bytes[0], bytes[1]);
  1907. return false;
  1908. }
  1909. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  1910. return true;
  1911. }
  1912. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  1913. struct intel_sdvo_connector *intel_sdvo_connector,
  1914. int type)
  1915. {
  1916. struct drm_device *dev = intel_sdvo->base.base.dev;
  1917. struct intel_sdvo_tv_format format;
  1918. uint32_t format_map, i;
  1919. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  1920. return false;
  1921. BUILD_BUG_ON(sizeof(format) != 6);
  1922. if (!intel_sdvo_get_value(intel_sdvo,
  1923. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1924. &format, sizeof(format)))
  1925. return false;
  1926. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1927. if (format_map == 0)
  1928. return false;
  1929. intel_sdvo_connector->format_supported_num = 0;
  1930. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1931. if (format_map & (1 << i))
  1932. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  1933. intel_sdvo_connector->tv_format =
  1934. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1935. "mode", intel_sdvo_connector->format_supported_num);
  1936. if (!intel_sdvo_connector->tv_format)
  1937. return false;
  1938. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  1939. drm_property_add_enum(
  1940. intel_sdvo_connector->tv_format, i,
  1941. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  1942. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  1943. drm_connector_attach_property(&intel_sdvo_connector->base.base,
  1944. intel_sdvo_connector->tv_format, 0);
  1945. return true;
  1946. }
  1947. #define ENHANCEMENT(name, NAME) do { \
  1948. if (enhancements.name) { \
  1949. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1950. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1951. return false; \
  1952. intel_sdvo_connector->max_##name = data_value[0]; \
  1953. intel_sdvo_connector->cur_##name = response; \
  1954. intel_sdvo_connector->name = \
  1955. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  1956. if (!intel_sdvo_connector->name) return false; \
  1957. drm_connector_attach_property(connector, \
  1958. intel_sdvo_connector->name, \
  1959. intel_sdvo_connector->cur_##name); \
  1960. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1961. data_value[0], data_value[1], response); \
  1962. } \
  1963. } while (0)
  1964. static bool
  1965. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  1966. struct intel_sdvo_connector *intel_sdvo_connector,
  1967. struct intel_sdvo_enhancements_reply enhancements)
  1968. {
  1969. struct drm_device *dev = intel_sdvo->base.base.dev;
  1970. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  1971. uint16_t response, data_value[2];
  1972. /* when horizontal overscan is supported, Add the left/right property */
  1973. if (enhancements.overscan_h) {
  1974. if (!intel_sdvo_get_value(intel_sdvo,
  1975. SDVO_CMD_GET_MAX_OVERSCAN_H,
  1976. &data_value, 4))
  1977. return false;
  1978. if (!intel_sdvo_get_value(intel_sdvo,
  1979. SDVO_CMD_GET_OVERSCAN_H,
  1980. &response, 2))
  1981. return false;
  1982. intel_sdvo_connector->max_hscan = data_value[0];
  1983. intel_sdvo_connector->left_margin = data_value[0] - response;
  1984. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  1985. intel_sdvo_connector->left =
  1986. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  1987. if (!intel_sdvo_connector->left)
  1988. return false;
  1989. drm_connector_attach_property(connector,
  1990. intel_sdvo_connector->left,
  1991. intel_sdvo_connector->left_margin);
  1992. intel_sdvo_connector->right =
  1993. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  1994. if (!intel_sdvo_connector->right)
  1995. return false;
  1996. drm_connector_attach_property(connector,
  1997. intel_sdvo_connector->right,
  1998. intel_sdvo_connector->right_margin);
  1999. DRM_DEBUG_KMS("h_overscan: max %d, "
  2000. "default %d, current %d\n",
  2001. data_value[0], data_value[1], response);
  2002. }
  2003. if (enhancements.overscan_v) {
  2004. if (!intel_sdvo_get_value(intel_sdvo,
  2005. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2006. &data_value, 4))
  2007. return false;
  2008. if (!intel_sdvo_get_value(intel_sdvo,
  2009. SDVO_CMD_GET_OVERSCAN_V,
  2010. &response, 2))
  2011. return false;
  2012. intel_sdvo_connector->max_vscan = data_value[0];
  2013. intel_sdvo_connector->top_margin = data_value[0] - response;
  2014. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2015. intel_sdvo_connector->top =
  2016. drm_property_create_range(dev, 0,
  2017. "top_margin", 0, data_value[0]);
  2018. if (!intel_sdvo_connector->top)
  2019. return false;
  2020. drm_connector_attach_property(connector,
  2021. intel_sdvo_connector->top,
  2022. intel_sdvo_connector->top_margin);
  2023. intel_sdvo_connector->bottom =
  2024. drm_property_create_range(dev, 0,
  2025. "bottom_margin", 0, data_value[0]);
  2026. if (!intel_sdvo_connector->bottom)
  2027. return false;
  2028. drm_connector_attach_property(connector,
  2029. intel_sdvo_connector->bottom,
  2030. intel_sdvo_connector->bottom_margin);
  2031. DRM_DEBUG_KMS("v_overscan: max %d, "
  2032. "default %d, current %d\n",
  2033. data_value[0], data_value[1], response);
  2034. }
  2035. ENHANCEMENT(hpos, HPOS);
  2036. ENHANCEMENT(vpos, VPOS);
  2037. ENHANCEMENT(saturation, SATURATION);
  2038. ENHANCEMENT(contrast, CONTRAST);
  2039. ENHANCEMENT(hue, HUE);
  2040. ENHANCEMENT(sharpness, SHARPNESS);
  2041. ENHANCEMENT(brightness, BRIGHTNESS);
  2042. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2043. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2044. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2045. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2046. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2047. if (enhancements.dot_crawl) {
  2048. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2049. return false;
  2050. intel_sdvo_connector->max_dot_crawl = 1;
  2051. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2052. intel_sdvo_connector->dot_crawl =
  2053. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2054. if (!intel_sdvo_connector->dot_crawl)
  2055. return false;
  2056. drm_connector_attach_property(connector,
  2057. intel_sdvo_connector->dot_crawl,
  2058. intel_sdvo_connector->cur_dot_crawl);
  2059. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2060. }
  2061. return true;
  2062. }
  2063. static bool
  2064. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2065. struct intel_sdvo_connector *intel_sdvo_connector,
  2066. struct intel_sdvo_enhancements_reply enhancements)
  2067. {
  2068. struct drm_device *dev = intel_sdvo->base.base.dev;
  2069. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2070. uint16_t response, data_value[2];
  2071. ENHANCEMENT(brightness, BRIGHTNESS);
  2072. return true;
  2073. }
  2074. #undef ENHANCEMENT
  2075. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2076. struct intel_sdvo_connector *intel_sdvo_connector)
  2077. {
  2078. union {
  2079. struct intel_sdvo_enhancements_reply reply;
  2080. uint16_t response;
  2081. } enhancements;
  2082. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2083. enhancements.response = 0;
  2084. intel_sdvo_get_value(intel_sdvo,
  2085. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2086. &enhancements, sizeof(enhancements));
  2087. if (enhancements.response == 0) {
  2088. DRM_DEBUG_KMS("No enhancement is supported\n");
  2089. return true;
  2090. }
  2091. if (IS_TV(intel_sdvo_connector))
  2092. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2093. else if (IS_LVDS(intel_sdvo_connector))
  2094. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2095. else
  2096. return true;
  2097. }
  2098. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2099. struct i2c_msg *msgs,
  2100. int num)
  2101. {
  2102. struct intel_sdvo *sdvo = adapter->algo_data;
  2103. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2104. return -EIO;
  2105. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2106. }
  2107. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2108. {
  2109. struct intel_sdvo *sdvo = adapter->algo_data;
  2110. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2111. }
  2112. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2113. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2114. .functionality = intel_sdvo_ddc_proxy_func
  2115. };
  2116. static bool
  2117. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2118. struct drm_device *dev)
  2119. {
  2120. sdvo->ddc.owner = THIS_MODULE;
  2121. sdvo->ddc.class = I2C_CLASS_DDC;
  2122. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2123. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2124. sdvo->ddc.algo_data = sdvo;
  2125. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2126. return i2c_add_adapter(&sdvo->ddc) == 0;
  2127. }
  2128. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
  2129. {
  2130. struct drm_i915_private *dev_priv = dev->dev_private;
  2131. struct intel_encoder *intel_encoder;
  2132. struct intel_sdvo *intel_sdvo;
  2133. int i;
  2134. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2135. if (!intel_sdvo)
  2136. return false;
  2137. intel_sdvo->sdvo_reg = sdvo_reg;
  2138. intel_sdvo->is_sdvob = is_sdvob;
  2139. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
  2140. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2141. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
  2142. kfree(intel_sdvo);
  2143. return false;
  2144. }
  2145. /* encoder type will be decided later */
  2146. intel_encoder = &intel_sdvo->base;
  2147. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2148. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2149. /* Read the regs to test if we can talk to the device */
  2150. for (i = 0; i < 0x40; i++) {
  2151. u8 byte;
  2152. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2153. DRM_DEBUG_KMS("No SDVO device found on %s\n",
  2154. SDVO_NAME(intel_sdvo));
  2155. goto err;
  2156. }
  2157. }
  2158. if (intel_sdvo->is_sdvob)
  2159. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2160. else
  2161. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2162. drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
  2163. /* In default case sdvo lvds is false */
  2164. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2165. goto err;
  2166. /* Set up hotplug command - note paranoia about contents of reply.
  2167. * We assume that the hardware is in a sane state, and only touch
  2168. * the bits we think we understand.
  2169. */
  2170. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
  2171. &intel_sdvo->hotplug_active, 2);
  2172. intel_sdvo->hotplug_active[0] &= ~0x3;
  2173. if (intel_sdvo_output_setup(intel_sdvo,
  2174. intel_sdvo->caps.output_flags) != true) {
  2175. DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
  2176. SDVO_NAME(intel_sdvo));
  2177. goto err;
  2178. }
  2179. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2180. /* Set the input timing to the screen. Assume always input 0. */
  2181. if (!intel_sdvo_set_target_input(intel_sdvo))
  2182. goto err;
  2183. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2184. &intel_sdvo->pixel_clock_min,
  2185. &intel_sdvo->pixel_clock_max))
  2186. goto err;
  2187. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2188. "clock range %dMHz - %dMHz, "
  2189. "input 1: %c, input 2: %c, "
  2190. "output 1: %c, output 2: %c\n",
  2191. SDVO_NAME(intel_sdvo),
  2192. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2193. intel_sdvo->caps.device_rev_id,
  2194. intel_sdvo->pixel_clock_min / 1000,
  2195. intel_sdvo->pixel_clock_max / 1000,
  2196. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2197. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2198. /* check currently supported outputs */
  2199. intel_sdvo->caps.output_flags &
  2200. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2201. intel_sdvo->caps.output_flags &
  2202. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2203. return true;
  2204. err:
  2205. drm_encoder_cleanup(&intel_encoder->base);
  2206. i2c_del_adapter(&intel_sdvo->ddc);
  2207. kfree(intel_sdvo);
  2208. return false;
  2209. }