i915_drv.h 47 KB

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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #ifndef _I915_DRV_H_
  30. #define _I915_DRV_H_
  31. #include "i915_reg.h"
  32. #include "intel_bios.h"
  33. #include "intel_ringbuffer.h"
  34. #include <linux/io-mapping.h>
  35. #include <linux/i2c.h>
  36. #include <linux/i2c-algo-bit.h>
  37. #include <drm/intel-gtt.h>
  38. #include <linux/backlight.h>
  39. #include <linux/intel-iommu.h>
  40. /* General customization:
  41. */
  42. #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
  43. #define DRIVER_NAME "i915"
  44. #define DRIVER_DESC "Intel Graphics"
  45. #define DRIVER_DATE "20080730"
  46. enum pipe {
  47. PIPE_A = 0,
  48. PIPE_B,
  49. PIPE_C,
  50. I915_MAX_PIPES
  51. };
  52. #define pipe_name(p) ((p) + 'A')
  53. enum plane {
  54. PLANE_A = 0,
  55. PLANE_B,
  56. PLANE_C,
  57. };
  58. #define plane_name(p) ((p) + 'A')
  59. enum port {
  60. PORT_A = 0,
  61. PORT_B,
  62. PORT_C,
  63. PORT_D,
  64. PORT_E,
  65. I915_MAX_PORTS
  66. };
  67. #define port_name(p) ((p) + 'A')
  68. #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  69. #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  70. /* Interface history:
  71. *
  72. * 1.1: Original.
  73. * 1.2: Add Power Management
  74. * 1.3: Add vblank support
  75. * 1.4: Fix cmdbuffer path, add heap destroy
  76. * 1.5: Add vblank pipe configuration
  77. * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  78. * - Support vertical blank on secondary display pipe
  79. */
  80. #define DRIVER_MAJOR 1
  81. #define DRIVER_MINOR 6
  82. #define DRIVER_PATCHLEVEL 0
  83. #define WATCH_COHERENCY 0
  84. #define WATCH_LISTS 0
  85. #define I915_GEM_PHYS_CURSOR_0 1
  86. #define I915_GEM_PHYS_CURSOR_1 2
  87. #define I915_GEM_PHYS_OVERLAY_REGS 3
  88. #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  89. struct drm_i915_gem_phys_object {
  90. int id;
  91. struct page **page_list;
  92. drm_dma_handle_t *handle;
  93. struct drm_i915_gem_object *cur_obj;
  94. };
  95. struct mem_block {
  96. struct mem_block *next;
  97. struct mem_block *prev;
  98. int start;
  99. int size;
  100. struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
  101. };
  102. struct opregion_header;
  103. struct opregion_acpi;
  104. struct opregion_swsci;
  105. struct opregion_asle;
  106. struct drm_i915_private;
  107. struct intel_opregion {
  108. struct opregion_header *header;
  109. struct opregion_acpi *acpi;
  110. struct opregion_swsci *swsci;
  111. struct opregion_asle *asle;
  112. void *vbt;
  113. u32 __iomem *lid_state;
  114. };
  115. #define OPREGION_SIZE (8*1024)
  116. struct intel_overlay;
  117. struct intel_overlay_error_state;
  118. struct drm_i915_master_private {
  119. drm_local_map_t *sarea;
  120. struct _drm_i915_sarea *sarea_priv;
  121. };
  122. #define I915_FENCE_REG_NONE -1
  123. #define I915_MAX_NUM_FENCES 16
  124. /* 16 fences + sign bit for FENCE_REG_NONE */
  125. #define I915_MAX_NUM_FENCE_BITS 5
  126. struct drm_i915_fence_reg {
  127. struct list_head lru_list;
  128. struct drm_i915_gem_object *obj;
  129. int pin_count;
  130. };
  131. struct sdvo_device_mapping {
  132. u8 initialized;
  133. u8 dvo_port;
  134. u8 slave_addr;
  135. u8 dvo_wiring;
  136. u8 i2c_pin;
  137. u8 ddc_pin;
  138. };
  139. struct intel_display_error_state;
  140. struct drm_i915_error_state {
  141. u32 eir;
  142. u32 pgtbl_er;
  143. u32 pipestat[I915_MAX_PIPES];
  144. u32 tail[I915_NUM_RINGS];
  145. u32 head[I915_NUM_RINGS];
  146. u32 ipeir[I915_NUM_RINGS];
  147. u32 ipehr[I915_NUM_RINGS];
  148. u32 instdone[I915_NUM_RINGS];
  149. u32 acthd[I915_NUM_RINGS];
  150. u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
  151. /* our own tracking of ring head and tail */
  152. u32 cpu_ring_head[I915_NUM_RINGS];
  153. u32 cpu_ring_tail[I915_NUM_RINGS];
  154. u32 error; /* gen6+ */
  155. u32 instpm[I915_NUM_RINGS];
  156. u32 instps[I915_NUM_RINGS];
  157. u32 instdone1;
  158. u32 seqno[I915_NUM_RINGS];
  159. u64 bbaddr;
  160. u32 fault_reg[I915_NUM_RINGS];
  161. u32 done_reg;
  162. u32 faddr[I915_NUM_RINGS];
  163. u64 fence[I915_MAX_NUM_FENCES];
  164. struct timeval time;
  165. struct drm_i915_error_ring {
  166. struct drm_i915_error_object {
  167. int page_count;
  168. u32 gtt_offset;
  169. u32 *pages[0];
  170. } *ringbuffer, *batchbuffer;
  171. struct drm_i915_error_request {
  172. long jiffies;
  173. u32 seqno;
  174. u32 tail;
  175. } *requests;
  176. int num_requests;
  177. } ring[I915_NUM_RINGS];
  178. struct drm_i915_error_buffer {
  179. u32 size;
  180. u32 name;
  181. u32 seqno;
  182. u32 gtt_offset;
  183. u32 read_domains;
  184. u32 write_domain;
  185. s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
  186. s32 pinned:2;
  187. u32 tiling:2;
  188. u32 dirty:1;
  189. u32 purgeable:1;
  190. s32 ring:4;
  191. u32 cache_level:2;
  192. } *active_bo, *pinned_bo;
  193. u32 active_bo_count, pinned_bo_count;
  194. struct intel_overlay_error_state *overlay;
  195. struct intel_display_error_state *display;
  196. };
  197. struct drm_i915_display_funcs {
  198. void (*dpms)(struct drm_crtc *crtc, int mode);
  199. bool (*fbc_enabled)(struct drm_device *dev);
  200. void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
  201. void (*disable_fbc)(struct drm_device *dev);
  202. int (*get_display_clock_speed)(struct drm_device *dev);
  203. int (*get_fifo_size)(struct drm_device *dev, int plane);
  204. void (*update_wm)(struct drm_device *dev);
  205. void (*update_sprite_wm)(struct drm_device *dev, int pipe,
  206. uint32_t sprite_width, int pixel_size);
  207. int (*crtc_mode_set)(struct drm_crtc *crtc,
  208. struct drm_display_mode *mode,
  209. struct drm_display_mode *adjusted_mode,
  210. int x, int y,
  211. struct drm_framebuffer *old_fb);
  212. void (*write_eld)(struct drm_connector *connector,
  213. struct drm_crtc *crtc);
  214. void (*fdi_link_train)(struct drm_crtc *crtc);
  215. void (*init_clock_gating)(struct drm_device *dev);
  216. void (*init_pch_clock_gating)(struct drm_device *dev);
  217. int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
  218. struct drm_framebuffer *fb,
  219. struct drm_i915_gem_object *obj);
  220. int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  221. int x, int y);
  222. void (*force_wake_get)(struct drm_i915_private *dev_priv);
  223. void (*force_wake_put)(struct drm_i915_private *dev_priv);
  224. /* clock updates for mode set */
  225. /* cursor updates */
  226. /* render clock increase/decrease */
  227. /* display clock increase/decrease */
  228. /* pll clock increase/decrease */
  229. };
  230. struct intel_device_info {
  231. u8 gen;
  232. u8 is_mobile:1;
  233. u8 is_i85x:1;
  234. u8 is_i915g:1;
  235. u8 is_i945gm:1;
  236. u8 is_g33:1;
  237. u8 need_gfx_hws:1;
  238. u8 is_g4x:1;
  239. u8 is_pineview:1;
  240. u8 is_broadwater:1;
  241. u8 is_crestline:1;
  242. u8 is_ivybridge:1;
  243. u8 is_valleyview:1;
  244. u8 has_pch_split:1;
  245. u8 is_haswell:1;
  246. u8 has_fbc:1;
  247. u8 has_pipe_cxsr:1;
  248. u8 has_hotplug:1;
  249. u8 cursor_needs_physical:1;
  250. u8 has_overlay:1;
  251. u8 overlay_needs_physical:1;
  252. u8 supports_tv:1;
  253. u8 has_bsd_ring:1;
  254. u8 has_blt_ring:1;
  255. u8 has_llc:1;
  256. };
  257. #define I915_PPGTT_PD_ENTRIES 512
  258. #define I915_PPGTT_PT_ENTRIES 1024
  259. struct i915_hw_ppgtt {
  260. unsigned num_pd_entries;
  261. struct page **pt_pages;
  262. uint32_t pd_offset;
  263. dma_addr_t *pt_dma_addr;
  264. dma_addr_t scratch_page_dma_addr;
  265. };
  266. enum no_fbc_reason {
  267. FBC_NO_OUTPUT, /* no outputs enabled to compress */
  268. FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
  269. FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  270. FBC_MODE_TOO_LARGE, /* mode too large for compression */
  271. FBC_BAD_PLANE, /* fbc not supported on plane */
  272. FBC_NOT_TILED, /* buffer not tiled */
  273. FBC_MULTIPLE_PIPES, /* more than one pipe active */
  274. FBC_MODULE_PARAM,
  275. };
  276. enum intel_pch {
  277. PCH_IBX, /* Ibexpeak PCH */
  278. PCH_CPT, /* Cougarpoint PCH */
  279. PCH_LPT, /* Lynxpoint PCH */
  280. };
  281. #define QUIRK_PIPEA_FORCE (1<<0)
  282. #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  283. #define QUIRK_INVERT_BRIGHTNESS (1<<2)
  284. struct intel_fbdev;
  285. struct intel_fbc_work;
  286. struct intel_gmbus {
  287. struct i2c_adapter adapter;
  288. bool force_bit;
  289. u32 reg0;
  290. u32 gpio_reg;
  291. struct i2c_algo_bit_data bit_algo;
  292. struct drm_i915_private *dev_priv;
  293. };
  294. typedef struct drm_i915_private {
  295. struct drm_device *dev;
  296. const struct intel_device_info *info;
  297. int has_gem;
  298. int relative_constants_mode;
  299. void __iomem *regs;
  300. /** gt_fifo_count and the subsequent register write are synchronized
  301. * with dev->struct_mutex. */
  302. unsigned gt_fifo_count;
  303. /** forcewake_count is protected by gt_lock */
  304. unsigned forcewake_count;
  305. /** gt_lock is also taken in irq contexts. */
  306. struct spinlock gt_lock;
  307. struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
  308. /** gmbus_mutex protects against concurrent usage of the single hw gmbus
  309. * controller on different i2c buses. */
  310. struct mutex gmbus_mutex;
  311. /**
  312. * Base address of the gmbus and gpio block.
  313. */
  314. uint32_t gpio_mmio_base;
  315. struct pci_dev *bridge_dev;
  316. struct intel_ring_buffer ring[I915_NUM_RINGS];
  317. uint32_t next_seqno;
  318. drm_dma_handle_t *status_page_dmah;
  319. uint32_t counter;
  320. drm_local_map_t hws_map;
  321. struct drm_i915_gem_object *pwrctx;
  322. struct drm_i915_gem_object *renderctx;
  323. struct resource mch_res;
  324. unsigned int cpp;
  325. int back_offset;
  326. int front_offset;
  327. int current_page;
  328. int page_flipping;
  329. atomic_t irq_received;
  330. /* protects the irq masks */
  331. spinlock_t irq_lock;
  332. /* DPIO indirect register protection */
  333. spinlock_t dpio_lock;
  334. /** Cached value of IMR to avoid reads in updating the bitfield */
  335. u32 pipestat[2];
  336. u32 irq_mask;
  337. u32 gt_irq_mask;
  338. u32 pch_irq_mask;
  339. u32 hotplug_supported_mask;
  340. struct work_struct hotplug_work;
  341. int tex_lru_log_granularity;
  342. int allow_batchbuffer;
  343. unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
  344. int vblank_pipe;
  345. int num_pipe;
  346. /* For hangcheck timer */
  347. #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  348. struct timer_list hangcheck_timer;
  349. int hangcheck_count;
  350. uint32_t last_acthd;
  351. uint32_t last_acthd_bsd;
  352. uint32_t last_acthd_blt;
  353. uint32_t last_instdone;
  354. uint32_t last_instdone1;
  355. unsigned long cfb_size;
  356. unsigned int cfb_fb;
  357. enum plane cfb_plane;
  358. int cfb_y;
  359. struct intel_fbc_work *fbc_work;
  360. struct intel_opregion opregion;
  361. /* overlay */
  362. struct intel_overlay *overlay;
  363. bool sprite_scaling_enabled;
  364. /* LVDS info */
  365. int backlight_level; /* restore backlight to this value */
  366. bool backlight_enabled;
  367. struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  368. struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  369. /* Feature bits from the VBIOS */
  370. unsigned int int_tv_support:1;
  371. unsigned int lvds_dither:1;
  372. unsigned int lvds_vbt:1;
  373. unsigned int int_crt_support:1;
  374. unsigned int lvds_use_ssc:1;
  375. unsigned int display_clock_mode:1;
  376. int lvds_ssc_freq;
  377. unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
  378. unsigned int lvds_val; /* used for checking LVDS channel mode */
  379. struct {
  380. int rate;
  381. int lanes;
  382. int preemphasis;
  383. int vswing;
  384. bool initialized;
  385. bool support;
  386. int bpp;
  387. struct edp_power_seq pps;
  388. } edp;
  389. bool no_aux_handshake;
  390. struct notifier_block lid_notifier;
  391. int crt_ddc_pin;
  392. struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
  393. int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  394. int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  395. unsigned int fsb_freq, mem_freq, is_ddr3;
  396. spinlock_t error_lock;
  397. struct drm_i915_error_state *first_error;
  398. struct work_struct error_work;
  399. struct completion error_completion;
  400. struct workqueue_struct *wq;
  401. /* Display functions */
  402. struct drm_i915_display_funcs display;
  403. /* PCH chipset type */
  404. enum intel_pch pch_type;
  405. unsigned long quirks;
  406. /* Register state */
  407. bool modeset_on_lid;
  408. u8 saveLBB;
  409. u32 saveDSPACNTR;
  410. u32 saveDSPBCNTR;
  411. u32 saveDSPARB;
  412. u32 saveHWS;
  413. u32 savePIPEACONF;
  414. u32 savePIPEBCONF;
  415. u32 savePIPEASRC;
  416. u32 savePIPEBSRC;
  417. u32 saveFPA0;
  418. u32 saveFPA1;
  419. u32 saveDPLL_A;
  420. u32 saveDPLL_A_MD;
  421. u32 saveHTOTAL_A;
  422. u32 saveHBLANK_A;
  423. u32 saveHSYNC_A;
  424. u32 saveVTOTAL_A;
  425. u32 saveVBLANK_A;
  426. u32 saveVSYNC_A;
  427. u32 saveBCLRPAT_A;
  428. u32 saveTRANSACONF;
  429. u32 saveTRANS_HTOTAL_A;
  430. u32 saveTRANS_HBLANK_A;
  431. u32 saveTRANS_HSYNC_A;
  432. u32 saveTRANS_VTOTAL_A;
  433. u32 saveTRANS_VBLANK_A;
  434. u32 saveTRANS_VSYNC_A;
  435. u32 savePIPEASTAT;
  436. u32 saveDSPASTRIDE;
  437. u32 saveDSPASIZE;
  438. u32 saveDSPAPOS;
  439. u32 saveDSPAADDR;
  440. u32 saveDSPASURF;
  441. u32 saveDSPATILEOFF;
  442. u32 savePFIT_PGM_RATIOS;
  443. u32 saveBLC_HIST_CTL;
  444. u32 saveBLC_PWM_CTL;
  445. u32 saveBLC_PWM_CTL2;
  446. u32 saveBLC_CPU_PWM_CTL;
  447. u32 saveBLC_CPU_PWM_CTL2;
  448. u32 saveFPB0;
  449. u32 saveFPB1;
  450. u32 saveDPLL_B;
  451. u32 saveDPLL_B_MD;
  452. u32 saveHTOTAL_B;
  453. u32 saveHBLANK_B;
  454. u32 saveHSYNC_B;
  455. u32 saveVTOTAL_B;
  456. u32 saveVBLANK_B;
  457. u32 saveVSYNC_B;
  458. u32 saveBCLRPAT_B;
  459. u32 saveTRANSBCONF;
  460. u32 saveTRANS_HTOTAL_B;
  461. u32 saveTRANS_HBLANK_B;
  462. u32 saveTRANS_HSYNC_B;
  463. u32 saveTRANS_VTOTAL_B;
  464. u32 saveTRANS_VBLANK_B;
  465. u32 saveTRANS_VSYNC_B;
  466. u32 savePIPEBSTAT;
  467. u32 saveDSPBSTRIDE;
  468. u32 saveDSPBSIZE;
  469. u32 saveDSPBPOS;
  470. u32 saveDSPBADDR;
  471. u32 saveDSPBSURF;
  472. u32 saveDSPBTILEOFF;
  473. u32 saveVGA0;
  474. u32 saveVGA1;
  475. u32 saveVGA_PD;
  476. u32 saveVGACNTRL;
  477. u32 saveADPA;
  478. u32 saveLVDS;
  479. u32 savePP_ON_DELAYS;
  480. u32 savePP_OFF_DELAYS;
  481. u32 saveDVOA;
  482. u32 saveDVOB;
  483. u32 saveDVOC;
  484. u32 savePP_ON;
  485. u32 savePP_OFF;
  486. u32 savePP_CONTROL;
  487. u32 savePP_DIVISOR;
  488. u32 savePFIT_CONTROL;
  489. u32 save_palette_a[256];
  490. u32 save_palette_b[256];
  491. u32 saveDPFC_CB_BASE;
  492. u32 saveFBC_CFB_BASE;
  493. u32 saveFBC_LL_BASE;
  494. u32 saveFBC_CONTROL;
  495. u32 saveFBC_CONTROL2;
  496. u32 saveIER;
  497. u32 saveIIR;
  498. u32 saveIMR;
  499. u32 saveDEIER;
  500. u32 saveDEIMR;
  501. u32 saveGTIER;
  502. u32 saveGTIMR;
  503. u32 saveFDI_RXA_IMR;
  504. u32 saveFDI_RXB_IMR;
  505. u32 saveCACHE_MODE_0;
  506. u32 saveMI_ARB_STATE;
  507. u32 saveSWF0[16];
  508. u32 saveSWF1[16];
  509. u32 saveSWF2[3];
  510. u8 saveMSR;
  511. u8 saveSR[8];
  512. u8 saveGR[25];
  513. u8 saveAR_INDEX;
  514. u8 saveAR[21];
  515. u8 saveDACMASK;
  516. u8 saveCR[37];
  517. uint64_t saveFENCE[I915_MAX_NUM_FENCES];
  518. u32 saveCURACNTR;
  519. u32 saveCURAPOS;
  520. u32 saveCURABASE;
  521. u32 saveCURBCNTR;
  522. u32 saveCURBPOS;
  523. u32 saveCURBBASE;
  524. u32 saveCURSIZE;
  525. u32 saveDP_B;
  526. u32 saveDP_C;
  527. u32 saveDP_D;
  528. u32 savePIPEA_GMCH_DATA_M;
  529. u32 savePIPEB_GMCH_DATA_M;
  530. u32 savePIPEA_GMCH_DATA_N;
  531. u32 savePIPEB_GMCH_DATA_N;
  532. u32 savePIPEA_DP_LINK_M;
  533. u32 savePIPEB_DP_LINK_M;
  534. u32 savePIPEA_DP_LINK_N;
  535. u32 savePIPEB_DP_LINK_N;
  536. u32 saveFDI_RXA_CTL;
  537. u32 saveFDI_TXA_CTL;
  538. u32 saveFDI_RXB_CTL;
  539. u32 saveFDI_TXB_CTL;
  540. u32 savePFA_CTL_1;
  541. u32 savePFB_CTL_1;
  542. u32 savePFA_WIN_SZ;
  543. u32 savePFB_WIN_SZ;
  544. u32 savePFA_WIN_POS;
  545. u32 savePFB_WIN_POS;
  546. u32 savePCH_DREF_CONTROL;
  547. u32 saveDISP_ARB_CTL;
  548. u32 savePIPEA_DATA_M1;
  549. u32 savePIPEA_DATA_N1;
  550. u32 savePIPEA_LINK_M1;
  551. u32 savePIPEA_LINK_N1;
  552. u32 savePIPEB_DATA_M1;
  553. u32 savePIPEB_DATA_N1;
  554. u32 savePIPEB_LINK_M1;
  555. u32 savePIPEB_LINK_N1;
  556. u32 saveMCHBAR_RENDER_STANDBY;
  557. u32 savePCH_PORT_HOTPLUG;
  558. struct {
  559. /** Bridge to intel-gtt-ko */
  560. const struct intel_gtt *gtt;
  561. /** Memory allocator for GTT stolen memory */
  562. struct drm_mm stolen;
  563. /** Memory allocator for GTT */
  564. struct drm_mm gtt_space;
  565. /** List of all objects in gtt_space. Used to restore gtt
  566. * mappings on resume */
  567. struct list_head gtt_list;
  568. /** Usable portion of the GTT for GEM */
  569. unsigned long gtt_start;
  570. unsigned long gtt_mappable_end;
  571. unsigned long gtt_end;
  572. struct io_mapping *gtt_mapping;
  573. int gtt_mtrr;
  574. /** PPGTT used for aliasing the PPGTT with the GTT */
  575. struct i915_hw_ppgtt *aliasing_ppgtt;
  576. struct shrinker inactive_shrinker;
  577. /**
  578. * List of objects currently involved in rendering.
  579. *
  580. * Includes buffers having the contents of their GPU caches
  581. * flushed, not necessarily primitives. last_rendering_seqno
  582. * represents when the rendering involved will be completed.
  583. *
  584. * A reference is held on the buffer while on this list.
  585. */
  586. struct list_head active_list;
  587. /**
  588. * List of objects which are not in the ringbuffer but which
  589. * still have a write_domain which needs to be flushed before
  590. * unbinding.
  591. *
  592. * last_rendering_seqno is 0 while an object is in this list.
  593. *
  594. * A reference is held on the buffer while on this list.
  595. */
  596. struct list_head flushing_list;
  597. /**
  598. * LRU list of objects which are not in the ringbuffer and
  599. * are ready to unbind, but are still in the GTT.
  600. *
  601. * last_rendering_seqno is 0 while an object is in this list.
  602. *
  603. * A reference is not held on the buffer while on this list,
  604. * as merely being GTT-bound shouldn't prevent its being
  605. * freed, and we'll pull it off the list in the free path.
  606. */
  607. struct list_head inactive_list;
  608. /**
  609. * LRU list of objects which are not in the ringbuffer but
  610. * are still pinned in the GTT.
  611. */
  612. struct list_head pinned_list;
  613. /** LRU list of objects with fence regs on them. */
  614. struct list_head fence_list;
  615. /**
  616. * List of objects currently pending being freed.
  617. *
  618. * These objects are no longer in use, but due to a signal
  619. * we were prevented from freeing them at the appointed time.
  620. */
  621. struct list_head deferred_free_list;
  622. /**
  623. * We leave the user IRQ off as much as possible,
  624. * but this means that requests will finish and never
  625. * be retired once the system goes idle. Set a timer to
  626. * fire periodically while the ring is running. When it
  627. * fires, go retire requests.
  628. */
  629. struct delayed_work retire_work;
  630. /**
  631. * Are we in a non-interruptible section of code like
  632. * modesetting?
  633. */
  634. bool interruptible;
  635. /**
  636. * Flag if the X Server, and thus DRM, is not currently in
  637. * control of the device.
  638. *
  639. * This is set between LeaveVT and EnterVT. It needs to be
  640. * replaced with a semaphore. It also needs to be
  641. * transitioned away from for kernel modesetting.
  642. */
  643. int suspended;
  644. /**
  645. * Flag if the hardware appears to be wedged.
  646. *
  647. * This is set when attempts to idle the device timeout.
  648. * It prevents command submission from occurring and makes
  649. * every pending request fail
  650. */
  651. atomic_t wedged;
  652. /** Bit 6 swizzling required for X tiling */
  653. uint32_t bit_6_swizzle_x;
  654. /** Bit 6 swizzling required for Y tiling */
  655. uint32_t bit_6_swizzle_y;
  656. /* storage for physical objects */
  657. struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
  658. /* accounting, useful for userland debugging */
  659. size_t gtt_total;
  660. size_t mappable_gtt_total;
  661. size_t object_memory;
  662. u32 object_count;
  663. } mm;
  664. struct sdvo_device_mapping sdvo_mappings[2];
  665. /* indicate whether the LVDS_BORDER should be enabled or not */
  666. unsigned int lvds_border_bits;
  667. /* Panel fitter placement and size for Ironlake+ */
  668. u32 pch_pf_pos, pch_pf_size;
  669. struct drm_crtc *plane_to_crtc_mapping[3];
  670. struct drm_crtc *pipe_to_crtc_mapping[3];
  671. wait_queue_head_t pending_flip_queue;
  672. bool flip_pending_is_done;
  673. /* Reclocking support */
  674. bool render_reclock_avail;
  675. bool lvds_downclock_avail;
  676. /* indicates the reduced downclock for LVDS*/
  677. int lvds_downclock;
  678. struct work_struct idle_work;
  679. struct timer_list idle_timer;
  680. bool busy;
  681. u16 orig_clock;
  682. int child_dev_num;
  683. struct child_device_config *child_dev;
  684. struct drm_connector *int_lvds_connector;
  685. struct drm_connector *int_edp_connector;
  686. bool mchbar_need_disable;
  687. struct work_struct rps_work;
  688. spinlock_t rps_lock;
  689. u32 pm_iir;
  690. u8 cur_delay;
  691. u8 min_delay;
  692. u8 max_delay;
  693. u8 fmax;
  694. u8 fstart;
  695. u64 last_count1;
  696. unsigned long last_time1;
  697. unsigned long chipset_power;
  698. u64 last_count2;
  699. struct timespec last_time2;
  700. unsigned long gfx_power;
  701. int c_m;
  702. int r_t;
  703. u8 corr;
  704. spinlock_t *mchdev_lock;
  705. enum no_fbc_reason no_fbc_reason;
  706. struct drm_mm_node *compressed_fb;
  707. struct drm_mm_node *compressed_llb;
  708. unsigned long last_gpu_reset;
  709. /* list of fbdev register on this device */
  710. struct intel_fbdev *fbdev;
  711. struct backlight_device *backlight;
  712. struct drm_property *broadcast_rgb_property;
  713. struct drm_property *force_audio_property;
  714. } drm_i915_private_t;
  715. enum hdmi_force_audio {
  716. HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
  717. HDMI_AUDIO_OFF, /* force turn off HDMI audio */
  718. HDMI_AUDIO_AUTO, /* trust EDID */
  719. HDMI_AUDIO_ON, /* force turn on HDMI audio */
  720. };
  721. enum i915_cache_level {
  722. I915_CACHE_NONE,
  723. I915_CACHE_LLC,
  724. I915_CACHE_LLC_MLC, /* gen6+ */
  725. };
  726. struct drm_i915_gem_object {
  727. struct drm_gem_object base;
  728. /** Current space allocated to this object in the GTT, if any. */
  729. struct drm_mm_node *gtt_space;
  730. struct list_head gtt_list;
  731. /** This object's place on the active/flushing/inactive lists */
  732. struct list_head ring_list;
  733. struct list_head mm_list;
  734. /** This object's place on GPU write list */
  735. struct list_head gpu_write_list;
  736. /** This object's place in the batchbuffer or on the eviction list */
  737. struct list_head exec_list;
  738. /**
  739. * This is set if the object is on the active or flushing lists
  740. * (has pending rendering), and is not set if it's on inactive (ready
  741. * to be unbound).
  742. */
  743. unsigned int active:1;
  744. /**
  745. * This is set if the object has been written to since last bound
  746. * to the GTT
  747. */
  748. unsigned int dirty:1;
  749. /**
  750. * This is set if the object has been written to since the last
  751. * GPU flush.
  752. */
  753. unsigned int pending_gpu_write:1;
  754. /**
  755. * Fence register bits (if any) for this object. Will be set
  756. * as needed when mapped into the GTT.
  757. * Protected by dev->struct_mutex.
  758. */
  759. signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
  760. /**
  761. * Advice: are the backing pages purgeable?
  762. */
  763. unsigned int madv:2;
  764. /**
  765. * Current tiling mode for the object.
  766. */
  767. unsigned int tiling_mode:2;
  768. unsigned int tiling_changed:1;
  769. /** How many users have pinned this object in GTT space. The following
  770. * users can each hold at most one reference: pwrite/pread, pin_ioctl
  771. * (via user_pin_count), execbuffer (objects are not allowed multiple
  772. * times for the same batchbuffer), and the framebuffer code. When
  773. * switching/pageflipping, the framebuffer code has at most two buffers
  774. * pinned per crtc.
  775. *
  776. * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  777. * bits with absolutely no headroom. So use 4 bits. */
  778. unsigned int pin_count:4;
  779. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  780. /**
  781. * Is the object at the current location in the gtt mappable and
  782. * fenceable? Used to avoid costly recalculations.
  783. */
  784. unsigned int map_and_fenceable:1;
  785. /**
  786. * Whether the current gtt mapping needs to be mappable (and isn't just
  787. * mappable by accident). Track pin and fault separate for a more
  788. * accurate mappable working set.
  789. */
  790. unsigned int fault_mappable:1;
  791. unsigned int pin_mappable:1;
  792. /*
  793. * Is the GPU currently using a fence to access this buffer,
  794. */
  795. unsigned int pending_fenced_gpu_access:1;
  796. unsigned int fenced_gpu_access:1;
  797. unsigned int cache_level:2;
  798. unsigned int has_aliasing_ppgtt_mapping:1;
  799. unsigned int has_global_gtt_mapping:1;
  800. struct page **pages;
  801. /**
  802. * DMAR support
  803. */
  804. struct scatterlist *sg_list;
  805. int num_sg;
  806. /**
  807. * Used for performing relocations during execbuffer insertion.
  808. */
  809. struct hlist_node exec_node;
  810. unsigned long exec_handle;
  811. struct drm_i915_gem_exec_object2 *exec_entry;
  812. /**
  813. * Current offset of the object in GTT space.
  814. *
  815. * This is the same as gtt_space->start
  816. */
  817. uint32_t gtt_offset;
  818. struct intel_ring_buffer *ring;
  819. /** Breadcrumb of last rendering to the buffer. */
  820. uint32_t last_rendering_seqno;
  821. /** Breadcrumb of last fenced GPU access to the buffer. */
  822. uint32_t last_fenced_seqno;
  823. /** Current tiling stride for the object, if it's tiled. */
  824. uint32_t stride;
  825. /** Record of address bit 17 of each page at last unbind. */
  826. unsigned long *bit_17;
  827. /** User space pin count and filp owning the pin */
  828. uint32_t user_pin_count;
  829. struct drm_file *pin_filp;
  830. /** for phy allocated objects */
  831. struct drm_i915_gem_phys_object *phys_obj;
  832. /**
  833. * Number of crtcs where this object is currently the fb, but
  834. * will be page flipped away on the next vblank. When it
  835. * reaches 0, dev_priv->pending_flip_queue will be woken up.
  836. */
  837. atomic_t pending_flip;
  838. };
  839. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  840. /**
  841. * Request queue structure.
  842. *
  843. * The request queue allows us to note sequence numbers that have been emitted
  844. * and may be associated with active buffers to be retired.
  845. *
  846. * By keeping this list, we can avoid having to do questionable
  847. * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  848. * an emission time with seqnos for tracking how far ahead of the GPU we are.
  849. */
  850. struct drm_i915_gem_request {
  851. /** On Which ring this request was generated */
  852. struct intel_ring_buffer *ring;
  853. /** GEM sequence number associated with this request. */
  854. uint32_t seqno;
  855. /** Postion in the ringbuffer of the end of the request */
  856. u32 tail;
  857. /** Time at which this request was emitted, in jiffies. */
  858. unsigned long emitted_jiffies;
  859. /** global list entry for this request */
  860. struct list_head list;
  861. struct drm_i915_file_private *file_priv;
  862. /** file_priv list entry for this request */
  863. struct list_head client_list;
  864. };
  865. struct drm_i915_file_private {
  866. struct {
  867. struct spinlock lock;
  868. struct list_head request_list;
  869. } mm;
  870. };
  871. #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
  872. #define IS_I830(dev) ((dev)->pci_device == 0x3577)
  873. #define IS_845G(dev) ((dev)->pci_device == 0x2562)
  874. #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
  875. #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
  876. #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
  877. #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
  878. #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
  879. #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
  880. #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
  881. #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
  882. #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
  883. #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
  884. #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
  885. #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
  886. #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
  887. #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
  888. #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
  889. #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
  890. #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
  891. #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
  892. #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
  893. #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
  894. /*
  895. * The genX designation typically refers to the render engine, so render
  896. * capability related checks should use IS_GEN, while display and other checks
  897. * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  898. * chips, etc.).
  899. */
  900. #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
  901. #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
  902. #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
  903. #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
  904. #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
  905. #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
  906. #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
  907. #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
  908. #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
  909. #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
  910. #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
  911. #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
  912. #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
  913. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  914. * rows, which changed the alignment requirements and fence programming.
  915. */
  916. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  917. IS_I915GM(dev)))
  918. #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  919. #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
  920. #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
  921. #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
  922. #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
  923. #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
  924. /* dsparb controlled by hw only */
  925. #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
  926. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  927. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  928. #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  929. #define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split)
  930. #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
  931. #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
  932. #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
  933. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  934. #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
  935. #include "i915_trace.h"
  936. /**
  937. * RC6 is a special power stage which allows the GPU to enter an very
  938. * low-voltage mode when idle, using down to 0V while at this stage. This
  939. * stage is entered automatically when the GPU is idle when RC6 support is
  940. * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  941. *
  942. * There are different RC6 modes available in Intel GPU, which differentiate
  943. * among each other with the latency required to enter and leave RC6 and
  944. * voltage consumed by the GPU in different states.
  945. *
  946. * The combination of the following flags define which states GPU is allowed
  947. * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  948. * RC6pp is deepest RC6. Their support by hardware varies according to the
  949. * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  950. * which brings the most power savings; deeper states save more power, but
  951. * require higher latency to switch to and wake up.
  952. */
  953. #define INTEL_RC6_ENABLE (1<<0)
  954. #define INTEL_RC6p_ENABLE (1<<1)
  955. #define INTEL_RC6pp_ENABLE (1<<2)
  956. extern struct drm_ioctl_desc i915_ioctls[];
  957. extern int i915_max_ioctl;
  958. extern unsigned int i915_fbpercrtc __always_unused;
  959. extern int i915_panel_ignore_lid __read_mostly;
  960. extern unsigned int i915_powersave __read_mostly;
  961. extern int i915_semaphores __read_mostly;
  962. extern unsigned int i915_lvds_downclock __read_mostly;
  963. extern int i915_lvds_channel_mode __read_mostly;
  964. extern int i915_panel_use_ssc __read_mostly;
  965. extern int i915_vbt_sdvo_panel_type __read_mostly;
  966. extern int i915_enable_rc6 __read_mostly;
  967. extern int i915_enable_fbc __read_mostly;
  968. extern bool i915_enable_hangcheck __read_mostly;
  969. extern int i915_enable_ppgtt __read_mostly;
  970. extern int i915_suspend(struct drm_device *dev, pm_message_t state);
  971. extern int i915_resume(struct drm_device *dev);
  972. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  973. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  974. /* i915_dma.c */
  975. extern void i915_kernel_lost_context(struct drm_device * dev);
  976. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  977. extern int i915_driver_unload(struct drm_device *);
  978. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
  979. extern void i915_driver_lastclose(struct drm_device * dev);
  980. extern void i915_driver_preclose(struct drm_device *dev,
  981. struct drm_file *file_priv);
  982. extern void i915_driver_postclose(struct drm_device *dev,
  983. struct drm_file *file_priv);
  984. extern int i915_driver_device_is_agp(struct drm_device * dev);
  985. #ifdef CONFIG_COMPAT
  986. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  987. unsigned long arg);
  988. #endif
  989. extern int i915_emit_box(struct drm_device *dev,
  990. struct drm_clip_rect *box,
  991. int DR1, int DR4);
  992. extern int i915_reset(struct drm_device *dev, u8 flags);
  993. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  994. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  995. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  996. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  997. /* i915_irq.c */
  998. void i915_hangcheck_elapsed(unsigned long data);
  999. void i915_handle_error(struct drm_device *dev, bool wedged);
  1000. extern int i915_irq_emit(struct drm_device *dev, void *data,
  1001. struct drm_file *file_priv);
  1002. extern int i915_irq_wait(struct drm_device *dev, void *data,
  1003. struct drm_file *file_priv);
  1004. extern void intel_irq_init(struct drm_device *dev);
  1005. extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
  1006. struct drm_file *file_priv);
  1007. extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
  1008. struct drm_file *file_priv);
  1009. extern int i915_vblank_swap(struct drm_device *dev, void *data,
  1010. struct drm_file *file_priv);
  1011. void
  1012. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1013. void
  1014. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1015. void intel_enable_asle(struct drm_device *dev);
  1016. #ifdef CONFIG_DEBUG_FS
  1017. extern void i915_destroy_error_state(struct drm_device *dev);
  1018. #else
  1019. #define i915_destroy_error_state(x)
  1020. #endif
  1021. /* i915_gem.c */
  1022. int i915_gem_init_ioctl(struct drm_device *dev, void *data,
  1023. struct drm_file *file_priv);
  1024. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  1025. struct drm_file *file_priv);
  1026. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  1027. struct drm_file *file_priv);
  1028. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  1029. struct drm_file *file_priv);
  1030. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1031. struct drm_file *file_priv);
  1032. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  1033. struct drm_file *file_priv);
  1034. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  1035. struct drm_file *file_priv);
  1036. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  1037. struct drm_file *file_priv);
  1038. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  1039. struct drm_file *file_priv);
  1040. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1041. struct drm_file *file_priv);
  1042. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  1043. struct drm_file *file_priv);
  1044. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  1045. struct drm_file *file_priv);
  1046. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  1047. struct drm_file *file_priv);
  1048. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  1049. struct drm_file *file_priv);
  1050. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  1051. struct drm_file *file_priv);
  1052. int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  1053. struct drm_file *file_priv);
  1054. int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  1055. struct drm_file *file_priv);
  1056. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  1057. struct drm_file *file_priv);
  1058. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  1059. struct drm_file *file_priv);
  1060. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  1061. struct drm_file *file_priv);
  1062. void i915_gem_load(struct drm_device *dev);
  1063. int i915_gem_init_object(struct drm_gem_object *obj);
  1064. int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
  1065. uint32_t invalidate_domains,
  1066. uint32_t flush_domains);
  1067. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  1068. size_t size);
  1069. void i915_gem_free_object(struct drm_gem_object *obj);
  1070. int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
  1071. uint32_t alignment,
  1072. bool map_and_fenceable);
  1073. void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
  1074. int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
  1075. void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
  1076. void i915_gem_lastclose(struct drm_device *dev);
  1077. int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
  1078. int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
  1079. int i915_gem_object_sync(struct drm_i915_gem_object *obj,
  1080. struct intel_ring_buffer *to);
  1081. void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
  1082. struct intel_ring_buffer *ring,
  1083. u32 seqno);
  1084. int i915_gem_dumb_create(struct drm_file *file_priv,
  1085. struct drm_device *dev,
  1086. struct drm_mode_create_dumb *args);
  1087. int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
  1088. uint32_t handle, uint64_t *offset);
  1089. int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
  1090. uint32_t handle);
  1091. /**
  1092. * Returns true if seq1 is later than seq2.
  1093. */
  1094. static inline bool
  1095. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  1096. {
  1097. return (int32_t)(seq1 - seq2) >= 0;
  1098. }
  1099. u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
  1100. int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
  1101. int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
  1102. static inline bool
  1103. i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
  1104. {
  1105. if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1106. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1107. dev_priv->fence_regs[obj->fence_reg].pin_count++;
  1108. return true;
  1109. } else
  1110. return false;
  1111. }
  1112. static inline void
  1113. i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
  1114. {
  1115. if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1116. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1117. dev_priv->fence_regs[obj->fence_reg].pin_count--;
  1118. }
  1119. }
  1120. void i915_gem_retire_requests(struct drm_device *dev);
  1121. void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
  1122. void i915_gem_reset(struct drm_device *dev);
  1123. void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
  1124. int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
  1125. uint32_t read_domains,
  1126. uint32_t write_domain);
  1127. int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
  1128. int __must_check i915_gem_init_hw(struct drm_device *dev);
  1129. void i915_gem_init_swizzling(struct drm_device *dev);
  1130. void i915_gem_init_ppgtt(struct drm_device *dev);
  1131. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  1132. int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire);
  1133. int __must_check i915_gem_idle(struct drm_device *dev);
  1134. int __must_check i915_add_request(struct intel_ring_buffer *ring,
  1135. struct drm_file *file,
  1136. struct drm_i915_gem_request *request);
  1137. int __must_check i915_wait_request(struct intel_ring_buffer *ring,
  1138. uint32_t seqno,
  1139. bool do_retire);
  1140. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  1141. int __must_check
  1142. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
  1143. bool write);
  1144. int __must_check
  1145. i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
  1146. int __must_check
  1147. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  1148. u32 alignment,
  1149. struct intel_ring_buffer *pipelined);
  1150. int i915_gem_attach_phys_object(struct drm_device *dev,
  1151. struct drm_i915_gem_object *obj,
  1152. int id,
  1153. int align);
  1154. void i915_gem_detach_phys_object(struct drm_device *dev,
  1155. struct drm_i915_gem_object *obj);
  1156. void i915_gem_free_all_phys_object(struct drm_device *dev);
  1157. void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  1158. uint32_t
  1159. i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
  1160. uint32_t size,
  1161. int tiling_mode);
  1162. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  1163. enum i915_cache_level cache_level);
  1164. /* i915_gem_gtt.c */
  1165. int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
  1166. void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
  1167. void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
  1168. struct drm_i915_gem_object *obj,
  1169. enum i915_cache_level cache_level);
  1170. void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
  1171. struct drm_i915_gem_object *obj);
  1172. void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  1173. int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
  1174. void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
  1175. enum i915_cache_level cache_level);
  1176. void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
  1177. void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
  1178. void i915_gem_init_global_gtt(struct drm_device *dev,
  1179. unsigned long start,
  1180. unsigned long mappable_end,
  1181. unsigned long end);
  1182. /* i915_gem_evict.c */
  1183. int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
  1184. unsigned alignment, bool mappable);
  1185. int __must_check i915_gem_evict_everything(struct drm_device *dev,
  1186. bool purgeable_only);
  1187. int __must_check i915_gem_evict_inactive(struct drm_device *dev,
  1188. bool purgeable_only);
  1189. /* i915_gem_tiling.c */
  1190. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  1191. void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1192. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1193. /* i915_gem_debug.c */
  1194. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1195. const char *where, uint32_t mark);
  1196. #if WATCH_LISTS
  1197. int i915_verify_lists(struct drm_device *dev);
  1198. #else
  1199. #define i915_verify_lists(dev) 0
  1200. #endif
  1201. void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
  1202. int handle);
  1203. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1204. const char *where, uint32_t mark);
  1205. /* i915_debugfs.c */
  1206. int i915_debugfs_init(struct drm_minor *minor);
  1207. void i915_debugfs_cleanup(struct drm_minor *minor);
  1208. /* i915_suspend.c */
  1209. extern int i915_save_state(struct drm_device *dev);
  1210. extern int i915_restore_state(struct drm_device *dev);
  1211. /* i915_suspend.c */
  1212. extern int i915_save_state(struct drm_device *dev);
  1213. extern int i915_restore_state(struct drm_device *dev);
  1214. /* i915_sysfs.c */
  1215. void i915_setup_sysfs(struct drm_device *dev_priv);
  1216. void i915_teardown_sysfs(struct drm_device *dev_priv);
  1217. /* intel_i2c.c */
  1218. extern int intel_setup_gmbus(struct drm_device *dev);
  1219. extern void intel_teardown_gmbus(struct drm_device *dev);
  1220. extern inline bool intel_gmbus_is_port_valid(unsigned port)
  1221. {
  1222. return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
  1223. }
  1224. extern struct i2c_adapter *intel_gmbus_get_adapter(
  1225. struct drm_i915_private *dev_priv, unsigned port);
  1226. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  1227. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  1228. extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  1229. {
  1230. return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  1231. }
  1232. extern void intel_i2c_reset(struct drm_device *dev);
  1233. /* intel_opregion.c */
  1234. extern int intel_opregion_setup(struct drm_device *dev);
  1235. #ifdef CONFIG_ACPI
  1236. extern void intel_opregion_init(struct drm_device *dev);
  1237. extern void intel_opregion_fini(struct drm_device *dev);
  1238. extern void intel_opregion_asle_intr(struct drm_device *dev);
  1239. extern void intel_opregion_gse_intr(struct drm_device *dev);
  1240. extern void intel_opregion_enable_asle(struct drm_device *dev);
  1241. #else
  1242. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  1243. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  1244. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  1245. static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
  1246. static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
  1247. #endif
  1248. /* intel_acpi.c */
  1249. #ifdef CONFIG_ACPI
  1250. extern void intel_register_dsm_handler(void);
  1251. extern void intel_unregister_dsm_handler(void);
  1252. #else
  1253. static inline void intel_register_dsm_handler(void) { return; }
  1254. static inline void intel_unregister_dsm_handler(void) { return; }
  1255. #endif /* CONFIG_ACPI */
  1256. /* modesetting */
  1257. extern void intel_modeset_init_hw(struct drm_device *dev);
  1258. extern void intel_modeset_init(struct drm_device *dev);
  1259. extern void intel_modeset_gem_init(struct drm_device *dev);
  1260. extern void intel_modeset_cleanup(struct drm_device *dev);
  1261. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  1262. extern bool intel_fbc_enabled(struct drm_device *dev);
  1263. extern void intel_disable_fbc(struct drm_device *dev);
  1264. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  1265. extern void ironlake_init_pch_refclk(struct drm_device *dev);
  1266. extern void ironlake_enable_rc6(struct drm_device *dev);
  1267. extern void gen6_set_rps(struct drm_device *dev, u8 val);
  1268. extern void intel_detect_pch(struct drm_device *dev);
  1269. extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
  1270. extern int intel_enable_rc6(const struct drm_device *dev);
  1271. extern bool i915_semaphore_is_enabled(struct drm_device *dev);
  1272. extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  1273. extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
  1274. extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  1275. extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
  1276. extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
  1277. extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
  1278. /* overlay */
  1279. #ifdef CONFIG_DEBUG_FS
  1280. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  1281. extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
  1282. extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
  1283. extern void intel_display_print_error_state(struct seq_file *m,
  1284. struct drm_device *dev,
  1285. struct intel_display_error_state *error);
  1286. #endif
  1287. #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  1288. #define BEGIN_LP_RING(n) \
  1289. intel_ring_begin(LP_RING(dev_priv), (n))
  1290. #define OUT_RING(x) \
  1291. intel_ring_emit(LP_RING(dev_priv), x)
  1292. #define ADVANCE_LP_RING() \
  1293. intel_ring_advance(LP_RING(dev_priv))
  1294. /**
  1295. * Lock test for when it's just for synchronization of ring access.
  1296. *
  1297. * In that case, we don't need to do it when GEM is initialized as nobody else
  1298. * has access to the ring.
  1299. */
  1300. #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
  1301. if (LP_RING(dev->dev_private)->obj == NULL) \
  1302. LOCK_TEST_WITH_RETURN(dev, file); \
  1303. } while (0)
  1304. /* On SNB platform, before reading ring registers forcewake bit
  1305. * must be set to prevent GT core from power down and stale values being
  1306. * returned.
  1307. */
  1308. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  1309. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  1310. int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
  1311. #define __i915_read(x, y) \
  1312. u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
  1313. __i915_read(8, b)
  1314. __i915_read(16, w)
  1315. __i915_read(32, l)
  1316. __i915_read(64, q)
  1317. #undef __i915_read
  1318. #define __i915_write(x, y) \
  1319. void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
  1320. __i915_write(8, b)
  1321. __i915_write(16, w)
  1322. __i915_write(32, l)
  1323. __i915_write(64, q)
  1324. #undef __i915_write
  1325. #define I915_READ8(reg) i915_read8(dev_priv, (reg))
  1326. #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
  1327. #define I915_READ16(reg) i915_read16(dev_priv, (reg))
  1328. #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
  1329. #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
  1330. #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
  1331. #define I915_READ(reg) i915_read32(dev_priv, (reg))
  1332. #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
  1333. #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
  1334. #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
  1335. #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
  1336. #define I915_READ64(reg) i915_read64(dev_priv, (reg))
  1337. #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
  1338. #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
  1339. #endif