mach-vr1000.c 9.2 KB

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  1. /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
  2. *
  3. * Copyright (c) 2003-2005 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * Machine support for Thorcom VR1000 board. Designed for Thorcom by
  7. * Simtec Electronics, http://www.simtec.co.uk/
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * Modifications:
  14. * 14-Sep-2004 BJD USB Power control
  15. * 04-Sep-2004 BJD Added new uart init, and io init
  16. * 21-Aug-2004 BJD Added struct s3c2410_board
  17. * 06-Aug-2004 BJD Fixed call to time initialisation
  18. * 05-Apr-2004 BJD Copied to make mach-vr1000.c
  19. * 18-Oct-2004 BJD Updated board struct
  20. * 04-Nov-2004 BJD Clock and serial configuration update
  21. *
  22. * 04-Jan-2005 BJD Updated uart init call
  23. * 10-Jan-2005 BJD Removed include of s3c2410.h
  24. * 14-Jan-2005 BJD Added clock init
  25. * 15-Jan-2005 BJD Add serial port device definition
  26. * 20-Jan-2005 BJD Use UPF_IOREMAP for ports
  27. * 10-Feb-2005 BJD Added power-off capability
  28. * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
  29. * 14-Mar-2006 BJD void __iomem fixes
  30. */
  31. #include <linux/kernel.h>
  32. #include <linux/types.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/list.h>
  35. #include <linux/timer.h>
  36. #include <linux/init.h>
  37. #include <linux/serial.h>
  38. #include <linux/tty.h>
  39. #include <linux/serial_8250.h>
  40. #include <linux/serial_reg.h>
  41. #include <asm/mach/arch.h>
  42. #include <asm/mach/map.h>
  43. #include <asm/mach/irq.h>
  44. #include <asm/arch/bast-map.h>
  45. #include <asm/arch/vr1000-map.h>
  46. #include <asm/arch/vr1000-irq.h>
  47. #include <asm/arch/vr1000-cpld.h>
  48. #include <asm/hardware.h>
  49. #include <asm/io.h>
  50. #include <asm/irq.h>
  51. #include <asm/mach-types.h>
  52. #include <asm/arch/regs-serial.h>
  53. #include <asm/arch/regs-gpio.h>
  54. #include "clock.h"
  55. #include "devs.h"
  56. #include "cpu.h"
  57. #include "usb-simtec.h"
  58. /* macros for virtual address mods for the io space entries */
  59. #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  60. #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  61. #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  62. #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  63. /* macros to modify the physical addresses for io space */
  64. #define PA_CS2(item) ((item) + S3C2410_CS2)
  65. #define PA_CS3(item) ((item) + S3C2410_CS3)
  66. #define PA_CS4(item) ((item) + S3C2410_CS4)
  67. #define PA_CS5(item) ((item) + S3C2410_CS5)
  68. static struct map_desc vr1000_iodesc[] __initdata = {
  69. /* ISA IO areas */
  70. { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
  71. { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
  72. /* we could possibly compress the next set down into a set of smaller tables
  73. * pagetables, but that would mean using an L2 section, and it still means
  74. * we cannot actually feed the same register to an LDR due to 16K spacing
  75. */
  76. /* bast CPLD control registers, and external interrupt controls */
  77. { (u32)VR1000_VA_CTRL1, VR1000_PA_CTRL1, SZ_1M, MT_DEVICE },
  78. { (u32)VR1000_VA_CTRL2, VR1000_PA_CTRL2, SZ_1M, MT_DEVICE },
  79. { (u32)VR1000_VA_CTRL3, VR1000_PA_CTRL3, SZ_1M, MT_DEVICE },
  80. { (u32)VR1000_VA_CTRL4, VR1000_PA_CTRL4, SZ_1M, MT_DEVICE },
  81. /* peripheral space... one for each of fast/slow/byte/16bit */
  82. /* note, ide is only decoded in word space, even though some registers
  83. * are only 8bit */
  84. /* slow, byte */
  85. { VA_C2(VR1000_VA_DM9000), PA_CS2(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
  86. { VA_C2(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
  87. { VA_C2(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
  88. { VA_C2(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  89. { VA_C2(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
  90. /* slow, word */
  91. { VA_C3(VR1000_VA_DM9000), PA_CS3(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
  92. { VA_C3(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
  93. { VA_C3(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
  94. { VA_C3(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  95. { VA_C3(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
  96. /* fast, byte */
  97. { VA_C4(VR1000_VA_DM9000), PA_CS4(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
  98. { VA_C4(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
  99. { VA_C4(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
  100. { VA_C4(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  101. { VA_C4(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
  102. /* fast, word */
  103. { VA_C5(VR1000_VA_DM9000), PA_CS5(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
  104. { VA_C5(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
  105. { VA_C5(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
  106. { VA_C5(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  107. { VA_C5(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
  108. };
  109. #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  110. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  111. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  112. /* uart clock source(s) */
  113. static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
  114. [0] = {
  115. .name = "uclk",
  116. .divisor = 1,
  117. .min_baud = 0,
  118. .max_baud = 0,
  119. },
  120. [1] = {
  121. .name = "pclk",
  122. .divisor = 1,
  123. .min_baud = 0,
  124. .max_baud = 0.
  125. }
  126. };
  127. static struct s3c2410_uartcfg vr1000_uartcfgs[] = {
  128. [0] = {
  129. .hwport = 0,
  130. .flags = 0,
  131. .ucon = UCON,
  132. .ulcon = ULCON,
  133. .ufcon = UFCON,
  134. .clocks = vr1000_serial_clocks,
  135. .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
  136. },
  137. [1] = {
  138. .hwport = 1,
  139. .flags = 0,
  140. .ucon = UCON,
  141. .ulcon = ULCON,
  142. .ufcon = UFCON,
  143. .clocks = vr1000_serial_clocks,
  144. .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
  145. },
  146. /* port 2 is not actually used */
  147. [2] = {
  148. .hwport = 2,
  149. .flags = 0,
  150. .ucon = UCON,
  151. .ulcon = ULCON,
  152. .ufcon = UFCON,
  153. .clocks = vr1000_serial_clocks,
  154. .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
  155. }
  156. };
  157. /* definitions for the vr1000 extra 16550 serial ports */
  158. #define VR1000_BAUDBASE (3692307)
  159. #define VR1000_SERIAL_MAPBASE(x) (VR1000_PA_SERIAL + 0x80 + ((x) << 5))
  160. static struct plat_serial8250_port serial_platform_data[] = {
  161. [0] = {
  162. .mapbase = VR1000_SERIAL_MAPBASE(0),
  163. .irq = IRQ_VR1000_SERIAL + 0,
  164. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  165. .iotype = UPIO_MEM,
  166. .regshift = 0,
  167. .uartclk = VR1000_BAUDBASE,
  168. },
  169. [1] = {
  170. .mapbase = VR1000_SERIAL_MAPBASE(1),
  171. .irq = IRQ_VR1000_SERIAL + 1,
  172. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  173. .iotype = UPIO_MEM,
  174. .regshift = 0,
  175. .uartclk = VR1000_BAUDBASE,
  176. },
  177. [2] = {
  178. .mapbase = VR1000_SERIAL_MAPBASE(2),
  179. .irq = IRQ_VR1000_SERIAL + 2,
  180. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  181. .iotype = UPIO_MEM,
  182. .regshift = 0,
  183. .uartclk = VR1000_BAUDBASE,
  184. },
  185. [3] = {
  186. .mapbase = VR1000_SERIAL_MAPBASE(3),
  187. .irq = IRQ_VR1000_SERIAL + 3,
  188. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  189. .iotype = UPIO_MEM,
  190. .regshift = 0,
  191. .uartclk = VR1000_BAUDBASE,
  192. },
  193. { },
  194. };
  195. static struct platform_device serial_device = {
  196. .name = "serial8250",
  197. .id = 0,
  198. .dev = {
  199. .platform_data = serial_platform_data,
  200. },
  201. };
  202. /* MTD NOR Flash */
  203. static struct resource vr1000_nor_resource[] = {
  204. [0] = {
  205. .start = S3C2410_CS1 + 0x4000000,
  206. .end = S3C2410_CS1 + 0x4000000 + SZ_16M - 1,
  207. .flags = IORESOURCE_MEM,
  208. }
  209. };
  210. static struct platform_device vr1000_nor = {
  211. .name = "bast-nor",
  212. .id = -1,
  213. .num_resources = ARRAY_SIZE(vr1000_nor_resource),
  214. .resource = vr1000_nor_resource,
  215. };
  216. static struct platform_device *vr1000_devices[] __initdata = {
  217. &s3c_device_usb,
  218. &s3c_device_lcd,
  219. &s3c_device_wdt,
  220. &s3c_device_i2c,
  221. &s3c_device_iis,
  222. &serial_device,
  223. &vr1000_nor,
  224. };
  225. static struct clk *vr1000_clocks[] = {
  226. &s3c24xx_dclk0,
  227. &s3c24xx_dclk1,
  228. &s3c24xx_clkout0,
  229. &s3c24xx_clkout1,
  230. &s3c24xx_uclk,
  231. };
  232. static struct s3c24xx_board vr1000_board __initdata = {
  233. .devices = vr1000_devices,
  234. .devices_count = ARRAY_SIZE(vr1000_devices),
  235. .clocks = vr1000_clocks,
  236. .clocks_count = ARRAY_SIZE(vr1000_clocks),
  237. };
  238. static void vr1000_power_off(void)
  239. {
  240. s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP);
  241. s3c2410_gpio_setpin(S3C2410_GPB9, 1);
  242. }
  243. void __init vr1000_map_io(void)
  244. {
  245. /* initialise clock sources */
  246. s3c24xx_dclk0.parent = NULL;
  247. s3c24xx_dclk0.rate = 12*1000*1000;
  248. s3c24xx_dclk1.parent = NULL;
  249. s3c24xx_dclk1.rate = 3692307;
  250. s3c24xx_clkout0.parent = &s3c24xx_dclk0;
  251. s3c24xx_clkout1.parent = &s3c24xx_dclk1;
  252. s3c24xx_uclk.parent = &s3c24xx_clkout1;
  253. pm_power_off = vr1000_power_off;
  254. s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
  255. s3c24xx_init_clocks(0);
  256. s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
  257. s3c24xx_set_board(&vr1000_board);
  258. usb_simtec_init();
  259. }
  260. void __init vr1000_init_irq(void)
  261. {
  262. s3c24xx_init_irq();
  263. }
  264. MACHINE_START(VR1000, "Thorcom-VR1000")
  265. MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
  266. BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, (u32)S3C24XX_VA_UART)
  267. BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
  268. MAPIO(vr1000_map_io)
  269. INITIRQ(vr1000_init_irq)
  270. .timer = &s3c24xx_timer,
  271. MACHINE_END