mv_sas.c 60 KB

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  1. /*
  2. * Marvell 88SE64xx/88SE94xx main function
  3. *
  4. * Copyright 2007 Red Hat, Inc.
  5. * Copyright 2008 Marvell. <kewei@marvell.com>
  6. * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
  7. *
  8. * This file is licensed under GPLv2.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; version 2 of the
  13. * License.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23. * USA
  24. */
  25. #include "mv_sas.h"
  26. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  27. {
  28. if (task->lldd_task) {
  29. struct mvs_slot_info *slot;
  30. slot = task->lldd_task;
  31. *tag = slot->slot_tag;
  32. return 1;
  33. }
  34. return 0;
  35. }
  36. void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  37. {
  38. void *bitmap = &mvi->tags;
  39. clear_bit(tag, bitmap);
  40. }
  41. void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  42. {
  43. mvs_tag_clear(mvi, tag);
  44. }
  45. void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  46. {
  47. void *bitmap = &mvi->tags;
  48. set_bit(tag, bitmap);
  49. }
  50. inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  51. {
  52. unsigned int index, tag;
  53. void *bitmap = &mvi->tags;
  54. index = find_first_zero_bit(bitmap, mvi->tags_num);
  55. tag = index;
  56. if (tag >= mvi->tags_num)
  57. return -SAS_QUEUE_FULL;
  58. mvs_tag_set(mvi, tag);
  59. *tag_out = tag;
  60. return 0;
  61. }
  62. void mvs_tag_init(struct mvs_info *mvi)
  63. {
  64. int i;
  65. for (i = 0; i < mvi->tags_num; ++i)
  66. mvs_tag_clear(mvi, i);
  67. }
  68. void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
  69. {
  70. u32 i;
  71. u32 run;
  72. u32 offset;
  73. offset = 0;
  74. while (size) {
  75. printk(KERN_DEBUG"%08X : ", baseaddr + offset);
  76. if (size >= 16)
  77. run = 16;
  78. else
  79. run = size;
  80. size -= run;
  81. for (i = 0; i < 16; i++) {
  82. if (i < run)
  83. printk(KERN_DEBUG"%02X ", (u32)data[i]);
  84. else
  85. printk(KERN_DEBUG" ");
  86. }
  87. printk(KERN_DEBUG": ");
  88. for (i = 0; i < run; i++)
  89. printk(KERN_DEBUG"%c",
  90. isalnum(data[i]) ? data[i] : '.');
  91. printk(KERN_DEBUG"\n");
  92. data = &data[16];
  93. offset += run;
  94. }
  95. printk(KERN_DEBUG"\n");
  96. }
  97. #if (_MV_DUMP > 1)
  98. static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
  99. enum sas_protocol proto)
  100. {
  101. u32 offset;
  102. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  103. offset = slot->cmd_size + MVS_OAF_SZ +
  104. MVS_CHIP_DISP->prd_size() * slot->n_elem;
  105. dev_printk(KERN_DEBUG, mvi->dev, "+---->Status buffer[%d] :\n",
  106. tag);
  107. mvs_hexdump(32, (u8 *) slot->response,
  108. (u32) slot->buf_dma + offset);
  109. }
  110. #endif
  111. static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
  112. enum sas_protocol proto)
  113. {
  114. #if (_MV_DUMP > 1)
  115. u32 sz, w_ptr;
  116. u64 addr;
  117. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  118. /*Delivery Queue */
  119. sz = MVS_CHIP_SLOT_SZ;
  120. w_ptr = slot->tx;
  121. addr = mvi->tx_dma;
  122. dev_printk(KERN_DEBUG, mvi->dev,
  123. "Delivery Queue Size=%04d , WRT_PTR=%04X\n", sz, w_ptr);
  124. dev_printk(KERN_DEBUG, mvi->dev,
  125. "Delivery Queue Base Address=0x%llX (PA)"
  126. "(tx_dma=0x%llX), Entry=%04d\n",
  127. addr, (unsigned long long)mvi->tx_dma, w_ptr);
  128. mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
  129. (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
  130. /*Command List */
  131. addr = mvi->slot_dma;
  132. dev_printk(KERN_DEBUG, mvi->dev,
  133. "Command List Base Address=0x%llX (PA)"
  134. "(slot_dma=0x%llX), Header=%03d\n",
  135. addr, (unsigned long long)slot->buf_dma, tag);
  136. dev_printk(KERN_DEBUG, mvi->dev, "Command Header[%03d]:\n", tag);
  137. /*mvs_cmd_hdr */
  138. mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
  139. (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
  140. /*1.command table area */
  141. dev_printk(KERN_DEBUG, mvi->dev, "+---->Command Table :\n");
  142. mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
  143. /*2.open address frame area */
  144. dev_printk(KERN_DEBUG, mvi->dev, "+---->Open Address Frame :\n");
  145. mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
  146. (u32) slot->buf_dma + slot->cmd_size);
  147. /*3.status buffer */
  148. mvs_hba_sb_dump(mvi, tag, proto);
  149. /*4.PRD table */
  150. dev_printk(KERN_DEBUG, mvi->dev, "+---->PRD table :\n");
  151. mvs_hexdump(MVS_CHIP_DISP->prd_size() * slot->n_elem,
  152. (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
  153. (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
  154. #endif
  155. }
  156. static void mvs_hba_cq_dump(struct mvs_info *mvi)
  157. {
  158. #if (_MV_DUMP > 2)
  159. u64 addr;
  160. void __iomem *regs = mvi->regs;
  161. u32 entry = mvi->rx_cons + 1;
  162. u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
  163. /*Completion Queue */
  164. addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
  165. dev_printk(KERN_DEBUG, mvi->dev, "Completion Task = 0x%p\n",
  166. mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
  167. dev_printk(KERN_DEBUG, mvi->dev,
  168. "Completion List Base Address=0x%llX (PA), "
  169. "CQ_Entry=%04d, CQ_WP=0x%08X\n",
  170. addr, entry - 1, mvi->rx[0]);
  171. mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
  172. mvi->rx_dma + sizeof(u32) * entry);
  173. #endif
  174. }
  175. void mvs_get_sas_addr(void *buf, u32 buflen)
  176. {
  177. /*memcpy(buf, "\x50\x05\x04\x30\x11\xab\x64\x40", 8);*/
  178. }
  179. struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  180. {
  181. unsigned long i = 0, j = 0, hi = 0;
  182. struct sas_ha_struct *sha = dev->port->ha;
  183. struct mvs_info *mvi = NULL;
  184. struct asd_sas_phy *phy;
  185. while (sha->sas_port[i]) {
  186. if (sha->sas_port[i] == dev->port) {
  187. phy = container_of(sha->sas_port[i]->phy_list.next,
  188. struct asd_sas_phy, port_phy_el);
  189. j = 0;
  190. while (sha->sas_phy[j]) {
  191. if (sha->sas_phy[j] == phy)
  192. break;
  193. j++;
  194. }
  195. break;
  196. }
  197. i++;
  198. }
  199. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  200. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  201. return mvi;
  202. }
  203. /* FIXME */
  204. int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  205. {
  206. unsigned long i = 0, j = 0, n = 0, num = 0;
  207. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  208. struct mvs_info *mvi = mvi_dev->mvi_info;
  209. struct sas_ha_struct *sha = dev->port->ha;
  210. while (sha->sas_port[i]) {
  211. if (sha->sas_port[i] == dev->port) {
  212. struct asd_sas_phy *phy;
  213. list_for_each_entry(phy,
  214. &sha->sas_port[i]->phy_list, port_phy_el) {
  215. j = 0;
  216. while (sha->sas_phy[j]) {
  217. if (sha->sas_phy[j] == phy)
  218. break;
  219. j++;
  220. }
  221. phyno[n] = (j >= mvi->chip->n_phy) ?
  222. (j - mvi->chip->n_phy) : j;
  223. num++;
  224. n++;
  225. }
  226. break;
  227. }
  228. i++;
  229. }
  230. return num;
  231. }
  232. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  233. struct mvs_device *dev)
  234. {
  235. if (!dev) {
  236. mv_printk("device has been free.\n");
  237. return;
  238. }
  239. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  240. return;
  241. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  242. }
  243. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  244. struct mvs_device *dev)
  245. {
  246. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  247. return 0;
  248. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  249. }
  250. void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
  251. {
  252. u32 no;
  253. for_each_phy(phy_mask, phy_mask, no) {
  254. if (!(phy_mask & 1))
  255. continue;
  256. MVS_CHIP_DISP->phy_reset(mvi, no, hard);
  257. }
  258. }
  259. /* FIXME: locking? */
  260. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  261. void *funcdata)
  262. {
  263. int rc = 0, phy_id = sas_phy->id;
  264. u32 tmp, i = 0, hi;
  265. struct sas_ha_struct *sha = sas_phy->ha;
  266. struct mvs_info *mvi = NULL;
  267. while (sha->sas_phy[i]) {
  268. if (sha->sas_phy[i] == sas_phy)
  269. break;
  270. i++;
  271. }
  272. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  273. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  274. switch (func) {
  275. case PHY_FUNC_SET_LINK_RATE:
  276. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  277. break;
  278. case PHY_FUNC_HARD_RESET:
  279. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  280. if (tmp & PHY_RST_HARD)
  281. break;
  282. MVS_CHIP_DISP->phy_reset(mvi, phy_id, 1);
  283. break;
  284. case PHY_FUNC_LINK_RESET:
  285. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  286. MVS_CHIP_DISP->phy_reset(mvi, phy_id, 0);
  287. break;
  288. case PHY_FUNC_DISABLE:
  289. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  290. break;
  291. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  292. default:
  293. rc = -EOPNOTSUPP;
  294. }
  295. msleep(200);
  296. return rc;
  297. }
  298. void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
  299. u32 off_lo, u32 off_hi, u64 sas_addr)
  300. {
  301. u32 lo = (u32)sas_addr;
  302. u32 hi = (u32)(sas_addr>>32);
  303. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  304. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  305. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  306. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  307. }
  308. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
  309. {
  310. struct mvs_phy *phy = &mvi->phy[i];
  311. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  312. struct sas_ha_struct *sas_ha;
  313. if (!phy->phy_attached)
  314. return;
  315. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  316. && phy->phy_type & PORT_TYPE_SAS) {
  317. return;
  318. }
  319. sas_ha = mvi->sas;
  320. sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
  321. if (sas_phy->phy) {
  322. struct sas_phy *sphy = sas_phy->phy;
  323. sphy->negotiated_linkrate = sas_phy->linkrate;
  324. sphy->minimum_linkrate = phy->minimum_linkrate;
  325. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  326. sphy->maximum_linkrate = phy->maximum_linkrate;
  327. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  328. }
  329. if (phy->phy_type & PORT_TYPE_SAS) {
  330. struct sas_identify_frame *id;
  331. id = (struct sas_identify_frame *)phy->frame_rcvd;
  332. id->dev_type = phy->identify.device_type;
  333. id->initiator_bits = SAS_PROTOCOL_ALL;
  334. id->target_bits = phy->identify.target_port_protocols;
  335. } else if (phy->phy_type & PORT_TYPE_SATA) {
  336. /*Nothing*/
  337. }
  338. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  339. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  340. mvi->sas->notify_port_event(sas_phy,
  341. PORTE_BYTES_DMAED);
  342. }
  343. int mvs_slave_alloc(struct scsi_device *scsi_dev)
  344. {
  345. struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
  346. if (dev_is_sata(dev)) {
  347. /* We don't need to rescan targets
  348. * if REPORT_LUNS request is failed
  349. */
  350. if (scsi_dev->lun > 0)
  351. return -ENXIO;
  352. scsi_dev->tagged_supported = 1;
  353. }
  354. return sas_slave_alloc(scsi_dev);
  355. }
  356. int mvs_slave_configure(struct scsi_device *sdev)
  357. {
  358. struct domain_device *dev = sdev_to_domain_dev(sdev);
  359. int ret = sas_slave_configure(sdev);
  360. if (ret)
  361. return ret;
  362. if (dev_is_sata(dev)) {
  363. /* may set PIO mode */
  364. #if MV_DISABLE_NCQ
  365. struct ata_port *ap = dev->sata_dev.ap;
  366. struct ata_device *adev = ap->link.device;
  367. adev->flags |= ATA_DFLAG_NCQ_OFF;
  368. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
  369. #endif
  370. }
  371. return 0;
  372. }
  373. void mvs_scan_start(struct Scsi_Host *shost)
  374. {
  375. int i, j;
  376. unsigned short core_nr;
  377. struct mvs_info *mvi;
  378. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  379. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  380. for (j = 0; j < core_nr; j++) {
  381. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  382. for (i = 0; i < mvi->chip->n_phy; ++i)
  383. mvs_bytes_dmaed(mvi, i);
  384. }
  385. }
  386. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  387. {
  388. /* give the phy enabling interrupt event time to come in (1s
  389. * is empirically about all it takes) */
  390. if (time < HZ)
  391. return 0;
  392. /* Wait for discovery to finish */
  393. scsi_flush_work(shost);
  394. return 1;
  395. }
  396. static int mvs_task_prep_smp(struct mvs_info *mvi,
  397. struct mvs_task_exec_info *tei)
  398. {
  399. int elem, rc, i;
  400. struct sas_task *task = tei->task;
  401. struct mvs_cmd_hdr *hdr = tei->hdr;
  402. struct domain_device *dev = task->dev;
  403. struct asd_sas_port *sas_port = dev->port;
  404. struct scatterlist *sg_req, *sg_resp;
  405. u32 req_len, resp_len, tag = tei->tag;
  406. void *buf_tmp;
  407. u8 *buf_oaf;
  408. dma_addr_t buf_tmp_dma;
  409. void *buf_prd;
  410. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  411. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  412. #if _MV_DUMP
  413. u8 *buf_cmd;
  414. void *from;
  415. #endif
  416. /*
  417. * DMA-map SMP request, response buffers
  418. */
  419. sg_req = &task->smp_task.smp_req;
  420. elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
  421. if (!elem)
  422. return -ENOMEM;
  423. req_len = sg_dma_len(sg_req);
  424. sg_resp = &task->smp_task.smp_resp;
  425. elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  426. if (!elem) {
  427. rc = -ENOMEM;
  428. goto err_out;
  429. }
  430. resp_len = SB_RFB_MAX;
  431. /* must be in dwords */
  432. if ((req_len & 0x3) || (resp_len & 0x3)) {
  433. rc = -EINVAL;
  434. goto err_out_2;
  435. }
  436. /*
  437. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  438. */
  439. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  440. buf_tmp = slot->buf;
  441. buf_tmp_dma = slot->buf_dma;
  442. #if _MV_DUMP
  443. buf_cmd = buf_tmp;
  444. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  445. buf_tmp += req_len;
  446. buf_tmp_dma += req_len;
  447. slot->cmd_size = req_len;
  448. #else
  449. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  450. #endif
  451. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  452. buf_oaf = buf_tmp;
  453. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  454. buf_tmp += MVS_OAF_SZ;
  455. buf_tmp_dma += MVS_OAF_SZ;
  456. /* region 3: PRD table *********************************** */
  457. buf_prd = buf_tmp;
  458. if (tei->n_elem)
  459. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  460. else
  461. hdr->prd_tbl = 0;
  462. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  463. buf_tmp += i;
  464. buf_tmp_dma += i;
  465. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  466. slot->response = buf_tmp;
  467. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  468. if (mvi->flags & MVF_FLAG_SOC)
  469. hdr->reserved[0] = 0;
  470. /*
  471. * Fill in TX ring and command slot header
  472. */
  473. slot->tx = mvi->tx_prod;
  474. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  475. TXQ_MODE_I | tag |
  476. (sas_port->phy_mask << TXQ_PHY_SHIFT));
  477. hdr->flags |= flags;
  478. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  479. hdr->tags = cpu_to_le32(tag);
  480. hdr->data_len = 0;
  481. /* generate open address frame hdr (first 12 bytes) */
  482. /* initiator, SMP, ftype 1h */
  483. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  484. buf_oaf[1] = dev->linkrate & 0xf;
  485. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  486. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  487. /* fill in PRD (scatter/gather) table, if any */
  488. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  489. #if _MV_DUMP
  490. /* copy cmd table */
  491. from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
  492. memcpy(buf_cmd, from + sg_req->offset, req_len);
  493. kunmap_atomic(from, KM_IRQ0);
  494. #endif
  495. return 0;
  496. err_out_2:
  497. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  498. PCI_DMA_FROMDEVICE);
  499. err_out:
  500. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  501. PCI_DMA_TODEVICE);
  502. return rc;
  503. }
  504. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  505. {
  506. struct ata_queued_cmd *qc = task->uldd_task;
  507. if (qc) {
  508. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  509. qc->tf.command == ATA_CMD_FPDMA_READ) {
  510. *tag = qc->tag;
  511. return 1;
  512. }
  513. }
  514. return 0;
  515. }
  516. static int mvs_task_prep_ata(struct mvs_info *mvi,
  517. struct mvs_task_exec_info *tei)
  518. {
  519. struct sas_task *task = tei->task;
  520. struct domain_device *dev = task->dev;
  521. struct mvs_device *mvi_dev = dev->lldd_dev;
  522. struct mvs_cmd_hdr *hdr = tei->hdr;
  523. struct asd_sas_port *sas_port = dev->port;
  524. struct mvs_slot_info *slot;
  525. void *buf_prd;
  526. u32 tag = tei->tag, hdr_tag;
  527. u32 flags, del_q;
  528. void *buf_tmp;
  529. u8 *buf_cmd, *buf_oaf;
  530. dma_addr_t buf_tmp_dma;
  531. u32 i, req_len, resp_len;
  532. const u32 max_resp_len = SB_RFB_MAX;
  533. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  534. mv_dprintk("Have not enough regiset for dev %d.\n",
  535. mvi_dev->device_id);
  536. return -EBUSY;
  537. }
  538. slot = &mvi->slot_info[tag];
  539. slot->tx = mvi->tx_prod;
  540. del_q = TXQ_MODE_I | tag |
  541. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  542. (sas_port->phy_mask << TXQ_PHY_SHIFT) |
  543. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  544. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  545. #ifndef DISABLE_HOTPLUG_DMA_FIX
  546. if (task->data_dir == DMA_FROM_DEVICE)
  547. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  548. else
  549. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  550. #else
  551. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  552. #endif
  553. if (task->ata_task.use_ncq)
  554. flags |= MCH_FPDMA;
  555. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
  556. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  557. flags |= MCH_ATAPI;
  558. }
  559. /* FIXME: fill in port multiplier number */
  560. hdr->flags = cpu_to_le32(flags);
  561. /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
  562. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  563. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  564. else
  565. hdr_tag = tag;
  566. hdr->tags = cpu_to_le32(hdr_tag);
  567. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  568. /*
  569. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  570. */
  571. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  572. buf_cmd = buf_tmp = slot->buf;
  573. buf_tmp_dma = slot->buf_dma;
  574. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  575. buf_tmp += MVS_ATA_CMD_SZ;
  576. buf_tmp_dma += MVS_ATA_CMD_SZ;
  577. #if _MV_DUMP
  578. slot->cmd_size = MVS_ATA_CMD_SZ;
  579. #endif
  580. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  581. /* used for STP. unused for SATA? */
  582. buf_oaf = buf_tmp;
  583. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  584. buf_tmp += MVS_OAF_SZ;
  585. buf_tmp_dma += MVS_OAF_SZ;
  586. /* region 3: PRD table ********************************************* */
  587. buf_prd = buf_tmp;
  588. if (tei->n_elem)
  589. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  590. else
  591. hdr->prd_tbl = 0;
  592. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  593. buf_tmp += i;
  594. buf_tmp_dma += i;
  595. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  596. /* FIXME: probably unused, for SATA. kept here just in case
  597. * we get a STP/SATA error information record
  598. */
  599. slot->response = buf_tmp;
  600. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  601. if (mvi->flags & MVF_FLAG_SOC)
  602. hdr->reserved[0] = 0;
  603. req_len = sizeof(struct host_to_dev_fis);
  604. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  605. sizeof(struct mvs_err_info) - i;
  606. /* request, response lengths */
  607. resp_len = min(resp_len, max_resp_len);
  608. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  609. if (likely(!task->ata_task.device_control_reg_update))
  610. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  611. /* fill in command FIS and ATAPI CDB */
  612. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  613. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
  614. memcpy(buf_cmd + STP_ATAPI_CMD,
  615. task->ata_task.atapi_packet, 16);
  616. /* generate open address frame hdr (first 12 bytes) */
  617. /* initiator, STP, ftype 1h */
  618. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  619. buf_oaf[1] = dev->linkrate & 0xf;
  620. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  621. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  622. /* fill in PRD (scatter/gather) table, if any */
  623. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  624. #ifndef DISABLE_HOTPLUG_DMA_FIX
  625. if (task->data_dir == DMA_FROM_DEVICE)
  626. MVS_CHIP_DISP->dma_fix(mvi->bulk_buffer_dma,
  627. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  628. #endif
  629. return 0;
  630. }
  631. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  632. struct mvs_task_exec_info *tei, int is_tmf,
  633. struct mvs_tmf_task *tmf)
  634. {
  635. struct sas_task *task = tei->task;
  636. struct mvs_cmd_hdr *hdr = tei->hdr;
  637. struct mvs_port *port = tei->port;
  638. struct domain_device *dev = task->dev;
  639. struct mvs_device *mvi_dev = dev->lldd_dev;
  640. struct asd_sas_port *sas_port = dev->port;
  641. struct mvs_slot_info *slot;
  642. void *buf_prd;
  643. struct ssp_frame_hdr *ssp_hdr;
  644. void *buf_tmp;
  645. u8 *buf_cmd, *buf_oaf, fburst = 0;
  646. dma_addr_t buf_tmp_dma;
  647. u32 flags;
  648. u32 resp_len, req_len, i, tag = tei->tag;
  649. const u32 max_resp_len = SB_RFB_MAX;
  650. u32 phy_mask;
  651. slot = &mvi->slot_info[tag];
  652. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  653. sas_port->phy_mask) & TXQ_PHY_MASK;
  654. slot->tx = mvi->tx_prod;
  655. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  656. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  657. (phy_mask << TXQ_PHY_SHIFT));
  658. flags = MCH_RETRY;
  659. if (task->ssp_task.enable_first_burst) {
  660. flags |= MCH_FBURST;
  661. fburst = (1 << 7);
  662. }
  663. if (is_tmf)
  664. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  665. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  666. hdr->tags = cpu_to_le32(tag);
  667. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  668. /*
  669. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  670. */
  671. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  672. buf_cmd = buf_tmp = slot->buf;
  673. buf_tmp_dma = slot->buf_dma;
  674. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  675. buf_tmp += MVS_SSP_CMD_SZ;
  676. buf_tmp_dma += MVS_SSP_CMD_SZ;
  677. #if _MV_DUMP
  678. slot->cmd_size = MVS_SSP_CMD_SZ;
  679. #endif
  680. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  681. buf_oaf = buf_tmp;
  682. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  683. buf_tmp += MVS_OAF_SZ;
  684. buf_tmp_dma += MVS_OAF_SZ;
  685. /* region 3: PRD table ********************************************* */
  686. buf_prd = buf_tmp;
  687. if (tei->n_elem)
  688. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  689. else
  690. hdr->prd_tbl = 0;
  691. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  692. buf_tmp += i;
  693. buf_tmp_dma += i;
  694. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  695. slot->response = buf_tmp;
  696. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  697. if (mvi->flags & MVF_FLAG_SOC)
  698. hdr->reserved[0] = 0;
  699. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  700. sizeof(struct mvs_err_info) - i;
  701. resp_len = min(resp_len, max_resp_len);
  702. req_len = sizeof(struct ssp_frame_hdr) + 28;
  703. /* request, response lengths */
  704. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  705. /* generate open address frame hdr (first 12 bytes) */
  706. /* initiator, SSP, ftype 1h */
  707. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  708. buf_oaf[1] = dev->linkrate & 0xf;
  709. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  710. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  711. /* fill in SSP frame header (Command Table.SSP frame header) */
  712. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  713. if (is_tmf)
  714. ssp_hdr->frame_type = SSP_TASK;
  715. else
  716. ssp_hdr->frame_type = SSP_COMMAND;
  717. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  718. HASHED_SAS_ADDR_SIZE);
  719. memcpy(ssp_hdr->hashed_src_addr,
  720. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  721. ssp_hdr->tag = cpu_to_be16(tag);
  722. /* fill in IU for TASK and Command Frame */
  723. buf_cmd += sizeof(*ssp_hdr);
  724. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  725. if (ssp_hdr->frame_type != SSP_TASK) {
  726. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  727. (task->ssp_task.task_prio << 3);
  728. memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
  729. } else{
  730. buf_cmd[10] = tmf->tmf;
  731. switch (tmf->tmf) {
  732. case TMF_ABORT_TASK:
  733. case TMF_QUERY_TASK:
  734. buf_cmd[12] =
  735. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  736. buf_cmd[13] =
  737. tmf->tag_of_task_to_be_managed & 0xff;
  738. break;
  739. default:
  740. break;
  741. }
  742. }
  743. /* fill in PRD (scatter/gather) table, if any */
  744. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  745. return 0;
  746. }
  747. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
  748. static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
  749. struct mvs_tmf_task *tmf, int *pass)
  750. {
  751. struct domain_device *dev = task->dev;
  752. struct mvs_device *mvi_dev = dev->lldd_dev;
  753. struct mvs_task_exec_info tei;
  754. struct mvs_slot_info *slot;
  755. u32 tag = 0xdeadbeef, n_elem = 0;
  756. int rc = 0;
  757. if (!dev->port) {
  758. struct task_status_struct *tsm = &task->task_status;
  759. tsm->resp = SAS_TASK_UNDELIVERED;
  760. tsm->stat = SAS_PHY_DOWN;
  761. /*
  762. * libsas will use dev->port, should
  763. * not call task_done for sata
  764. */
  765. if (dev->dev_type != SATA_DEV)
  766. task->task_done(task);
  767. return rc;
  768. }
  769. if (DEV_IS_GONE(mvi_dev)) {
  770. if (mvi_dev)
  771. mv_dprintk("device %d not ready.\n",
  772. mvi_dev->device_id);
  773. else
  774. mv_dprintk("device %016llx not ready.\n",
  775. SAS_ADDR(dev->sas_addr));
  776. rc = SAS_PHY_DOWN;
  777. return rc;
  778. }
  779. tei.port = dev->port->lldd_port;
  780. if (tei.port && !tei.port->port_attached && !tmf) {
  781. if (sas_protocol_ata(task->task_proto)) {
  782. struct task_status_struct *ts = &task->task_status;
  783. mv_dprintk("SATA/STP port %d does not attach"
  784. "device.\n", dev->port->id);
  785. ts->resp = SAS_TASK_COMPLETE;
  786. ts->stat = SAS_PHY_DOWN;
  787. task->task_done(task);
  788. } else {
  789. struct task_status_struct *ts = &task->task_status;
  790. mv_dprintk("SAS port %d does not attach"
  791. "device.\n", dev->port->id);
  792. ts->resp = SAS_TASK_UNDELIVERED;
  793. ts->stat = SAS_PHY_DOWN;
  794. task->task_done(task);
  795. }
  796. return rc;
  797. }
  798. if (!sas_protocol_ata(task->task_proto)) {
  799. if (task->num_scatter) {
  800. n_elem = dma_map_sg(mvi->dev,
  801. task->scatter,
  802. task->num_scatter,
  803. task->data_dir);
  804. if (!n_elem) {
  805. rc = -ENOMEM;
  806. goto prep_out;
  807. }
  808. }
  809. } else {
  810. n_elem = task->num_scatter;
  811. }
  812. rc = mvs_tag_alloc(mvi, &tag);
  813. if (rc)
  814. goto err_out;
  815. slot = &mvi->slot_info[tag];
  816. task->lldd_task = NULL;
  817. slot->n_elem = n_elem;
  818. slot->slot_tag = tag;
  819. slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
  820. if (!slot->buf)
  821. goto err_out_tag;
  822. memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
  823. tei.task = task;
  824. tei.hdr = &mvi->slot[tag];
  825. tei.tag = tag;
  826. tei.n_elem = n_elem;
  827. switch (task->task_proto) {
  828. case SAS_PROTOCOL_SMP:
  829. rc = mvs_task_prep_smp(mvi, &tei);
  830. break;
  831. case SAS_PROTOCOL_SSP:
  832. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  833. break;
  834. case SAS_PROTOCOL_SATA:
  835. case SAS_PROTOCOL_STP:
  836. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  837. rc = mvs_task_prep_ata(mvi, &tei);
  838. break;
  839. default:
  840. dev_printk(KERN_ERR, mvi->dev,
  841. "unknown sas_task proto: 0x%x\n",
  842. task->task_proto);
  843. rc = -EINVAL;
  844. break;
  845. }
  846. if (rc) {
  847. mv_dprintk("rc is %x\n", rc);
  848. goto err_out_slot_buf;
  849. }
  850. slot->task = task;
  851. slot->port = tei.port;
  852. task->lldd_task = slot;
  853. list_add_tail(&slot->entry, &tei.port->list);
  854. spin_lock(&task->task_state_lock);
  855. task->task_state_flags |= SAS_TASK_AT_INITIATOR;
  856. spin_unlock(&task->task_state_lock);
  857. mvs_hba_memory_dump(mvi, tag, task->task_proto);
  858. mvi_dev->running_req++;
  859. ++(*pass);
  860. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  861. return rc;
  862. err_out_slot_buf:
  863. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  864. err_out_tag:
  865. mvs_tag_free(mvi, tag);
  866. err_out:
  867. dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
  868. if (!sas_protocol_ata(task->task_proto))
  869. if (n_elem)
  870. dma_unmap_sg(mvi->dev, task->scatter, n_elem,
  871. task->data_dir);
  872. prep_out:
  873. return rc;
  874. }
  875. static struct mvs_task_list *mvs_task_alloc_list(int *num, gfp_t gfp_flags)
  876. {
  877. struct mvs_task_list *first = NULL;
  878. for (; *num > 0; --*num) {
  879. struct mvs_task_list *mvs_list = kmem_cache_zalloc(mvs_task_list_cache, gfp_flags);
  880. if (!mvs_list)
  881. break;
  882. INIT_LIST_HEAD(&mvs_list->list);
  883. if (!first)
  884. first = mvs_list;
  885. else
  886. list_add_tail(&mvs_list->list, &first->list);
  887. }
  888. return first;
  889. }
  890. static inline void mvs_task_free_list(struct mvs_task_list *mvs_list)
  891. {
  892. LIST_HEAD(list);
  893. struct list_head *pos, *a;
  894. struct mvs_task_list *mlist = NULL;
  895. __list_add(&list, mvs_list->list.prev, &mvs_list->list);
  896. list_for_each_safe(pos, a, &list) {
  897. list_del_init(pos);
  898. mlist = list_entry(pos, struct mvs_task_list, list);
  899. kmem_cache_free(mvs_task_list_cache, mlist);
  900. }
  901. }
  902. static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  903. struct completion *completion, int is_tmf,
  904. struct mvs_tmf_task *tmf)
  905. {
  906. struct domain_device *dev = task->dev;
  907. struct mvs_info *mvi = NULL;
  908. u32 rc = 0;
  909. u32 pass = 0;
  910. unsigned long flags = 0;
  911. mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
  912. if ((dev->dev_type == SATA_DEV) && (dev->sata_dev.ap != NULL))
  913. spin_unlock_irq(dev->sata_dev.ap->lock);
  914. spin_lock_irqsave(&mvi->lock, flags);
  915. rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
  916. if (rc)
  917. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  918. if (likely(pass))
  919. MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
  920. (MVS_CHIP_SLOT_SZ - 1));
  921. spin_unlock_irqrestore(&mvi->lock, flags);
  922. if ((dev->dev_type == SATA_DEV) && (dev->sata_dev.ap != NULL))
  923. spin_lock_irq(dev->sata_dev.ap->lock);
  924. return rc;
  925. }
  926. static int mvs_collector_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  927. struct completion *completion, int is_tmf,
  928. struct mvs_tmf_task *tmf)
  929. {
  930. struct domain_device *dev = task->dev;
  931. struct mvs_prv_info *mpi = dev->port->ha->lldd_ha;
  932. struct mvs_info *mvi = NULL;
  933. struct sas_task *t = task;
  934. struct mvs_task_list *mvs_list = NULL, *a;
  935. LIST_HEAD(q);
  936. int pass[2] = {0};
  937. u32 rc = 0;
  938. u32 n = num;
  939. unsigned long flags = 0;
  940. mvs_list = mvs_task_alloc_list(&n, gfp_flags);
  941. if (n) {
  942. printk(KERN_ERR "%s: mvs alloc list failed.\n", __func__);
  943. rc = -ENOMEM;
  944. goto free_list;
  945. }
  946. __list_add(&q, mvs_list->list.prev, &mvs_list->list);
  947. list_for_each_entry(a, &q, list) {
  948. a->task = t;
  949. t = list_entry(t->list.next, struct sas_task, list);
  950. }
  951. list_for_each_entry(a, &q , list) {
  952. t = a->task;
  953. mvi = ((struct mvs_device *)t->dev->lldd_dev)->mvi_info;
  954. spin_lock_irqsave(&mvi->lock, flags);
  955. rc = mvs_task_prep(t, mvi, is_tmf, tmf, &pass[mvi->id]);
  956. if (rc)
  957. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  958. spin_unlock_irqrestore(&mvi->lock, flags);
  959. }
  960. if (likely(pass[0]))
  961. MVS_CHIP_DISP->start_delivery(mpi->mvi[0],
  962. (mpi->mvi[0]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
  963. if (likely(pass[1]))
  964. MVS_CHIP_DISP->start_delivery(mpi->mvi[1],
  965. (mpi->mvi[1]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
  966. list_del_init(&q);
  967. free_list:
  968. if (mvs_list)
  969. mvs_task_free_list(mvs_list);
  970. return rc;
  971. }
  972. int mvs_queue_command(struct sas_task *task, const int num,
  973. gfp_t gfp_flags)
  974. {
  975. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  976. struct sas_ha_struct *sas = mvi_dev->mvi_info->sas;
  977. if (sas->lldd_max_execute_num < 2)
  978. return mvs_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  979. else
  980. return mvs_collector_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  981. }
  982. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  983. {
  984. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  985. mvs_tag_clear(mvi, slot_idx);
  986. }
  987. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  988. struct mvs_slot_info *slot, u32 slot_idx)
  989. {
  990. if (!slot->task)
  991. return;
  992. if (!sas_protocol_ata(task->task_proto))
  993. if (slot->n_elem)
  994. dma_unmap_sg(mvi->dev, task->scatter,
  995. slot->n_elem, task->data_dir);
  996. switch (task->task_proto) {
  997. case SAS_PROTOCOL_SMP:
  998. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  999. PCI_DMA_FROMDEVICE);
  1000. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  1001. PCI_DMA_TODEVICE);
  1002. break;
  1003. case SAS_PROTOCOL_SATA:
  1004. case SAS_PROTOCOL_STP:
  1005. case SAS_PROTOCOL_SSP:
  1006. default:
  1007. /* do nothing */
  1008. break;
  1009. }
  1010. if (slot->buf) {
  1011. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  1012. slot->buf = NULL;
  1013. }
  1014. list_del_init(&slot->entry);
  1015. task->lldd_task = NULL;
  1016. slot->task = NULL;
  1017. slot->port = NULL;
  1018. slot->slot_tag = 0xFFFFFFFF;
  1019. mvs_slot_free(mvi, slot_idx);
  1020. }
  1021. static void mvs_update_wideport(struct mvs_info *mvi, int i)
  1022. {
  1023. struct mvs_phy *phy = &mvi->phy[i];
  1024. struct mvs_port *port = phy->port;
  1025. int j, no;
  1026. for_each_phy(port->wide_port_phymap, j, no) {
  1027. if (j & 1) {
  1028. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  1029. PHYR_WIDE_PORT);
  1030. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  1031. port->wide_port_phymap);
  1032. } else {
  1033. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  1034. PHYR_WIDE_PORT);
  1035. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  1036. 0);
  1037. }
  1038. }
  1039. }
  1040. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  1041. {
  1042. u32 tmp;
  1043. struct mvs_phy *phy = &mvi->phy[i];
  1044. struct mvs_port *port = phy->port;
  1045. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  1046. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  1047. if (!port)
  1048. phy->phy_attached = 1;
  1049. return tmp;
  1050. }
  1051. if (port) {
  1052. if (phy->phy_type & PORT_TYPE_SAS) {
  1053. port->wide_port_phymap &= ~(1U << i);
  1054. if (!port->wide_port_phymap)
  1055. port->port_attached = 0;
  1056. mvs_update_wideport(mvi, i);
  1057. } else if (phy->phy_type & PORT_TYPE_SATA)
  1058. port->port_attached = 0;
  1059. phy->port = NULL;
  1060. phy->phy_attached = 0;
  1061. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  1062. }
  1063. return 0;
  1064. }
  1065. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  1066. {
  1067. u32 *s = (u32 *) buf;
  1068. if (!s)
  1069. return NULL;
  1070. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  1071. s[3] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  1072. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  1073. s[2] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  1074. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  1075. s[1] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  1076. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  1077. s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  1078. /* Workaround: take some ATAPI devices for ATA */
  1079. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  1080. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  1081. return s;
  1082. }
  1083. static u32 mvs_is_sig_fis_received(u32 irq_status)
  1084. {
  1085. return irq_status & PHYEV_SIG_FIS;
  1086. }
  1087. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  1088. {
  1089. struct mvs_phy *phy = &mvi->phy[i];
  1090. struct sas_identify_frame *id;
  1091. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1092. if (get_st) {
  1093. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  1094. phy->phy_status = mvs_is_phy_ready(mvi, i);
  1095. }
  1096. if (phy->phy_status) {
  1097. int oob_done = 0;
  1098. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  1099. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  1100. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  1101. if (phy->phy_type & PORT_TYPE_SATA) {
  1102. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  1103. if (mvs_is_sig_fis_received(phy->irq_status)) {
  1104. phy->phy_attached = 1;
  1105. phy->att_dev_sas_addr =
  1106. i + mvi->id * mvi->chip->n_phy;
  1107. if (oob_done)
  1108. sas_phy->oob_mode = SATA_OOB_MODE;
  1109. phy->frame_rcvd_size =
  1110. sizeof(struct dev_to_host_fis);
  1111. mvs_get_d2h_reg(mvi, i, id);
  1112. } else {
  1113. u32 tmp;
  1114. dev_printk(KERN_DEBUG, mvi->dev,
  1115. "Phy%d : No sig fis\n", i);
  1116. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  1117. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  1118. tmp | PHYEV_SIG_FIS);
  1119. phy->phy_attached = 0;
  1120. phy->phy_type &= ~PORT_TYPE_SATA;
  1121. MVS_CHIP_DISP->phy_reset(mvi, i, 0);
  1122. goto out_done;
  1123. }
  1124. } else if (phy->phy_type & PORT_TYPE_SAS
  1125. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  1126. phy->phy_attached = 1;
  1127. phy->identify.device_type =
  1128. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  1129. if (phy->identify.device_type == SAS_END_DEV)
  1130. phy->identify.target_port_protocols =
  1131. SAS_PROTOCOL_SSP;
  1132. else if (phy->identify.device_type != NO_DEVICE)
  1133. phy->identify.target_port_protocols =
  1134. SAS_PROTOCOL_SMP;
  1135. if (oob_done)
  1136. sas_phy->oob_mode = SAS_OOB_MODE;
  1137. phy->frame_rcvd_size =
  1138. sizeof(struct sas_identify_frame);
  1139. }
  1140. memcpy(sas_phy->attached_sas_addr,
  1141. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  1142. if (MVS_CHIP_DISP->phy_work_around)
  1143. MVS_CHIP_DISP->phy_work_around(mvi, i);
  1144. }
  1145. mv_dprintk("port %d attach dev info is %x\n",
  1146. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  1147. mv_dprintk("port %d attach sas addr is %llx\n",
  1148. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  1149. out_done:
  1150. if (get_st)
  1151. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  1152. }
  1153. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  1154. {
  1155. struct sas_ha_struct *sas_ha = sas_phy->ha;
  1156. struct mvs_info *mvi = NULL; int i = 0, hi;
  1157. struct mvs_phy *phy = sas_phy->lldd_phy;
  1158. struct asd_sas_port *sas_port = sas_phy->port;
  1159. struct mvs_port *port;
  1160. unsigned long flags = 0;
  1161. if (!sas_port)
  1162. return;
  1163. while (sas_ha->sas_phy[i]) {
  1164. if (sas_ha->sas_phy[i] == sas_phy)
  1165. break;
  1166. i++;
  1167. }
  1168. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  1169. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  1170. if (sas_port->id >= mvi->chip->n_phy)
  1171. port = &mvi->port[sas_port->id - mvi->chip->n_phy];
  1172. else
  1173. port = &mvi->port[sas_port->id];
  1174. if (lock)
  1175. spin_lock_irqsave(&mvi->lock, flags);
  1176. port->port_attached = 1;
  1177. phy->port = port;
  1178. sas_port->lldd_port = port;
  1179. if (phy->phy_type & PORT_TYPE_SAS) {
  1180. port->wide_port_phymap = sas_port->phy_mask;
  1181. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  1182. mvs_update_wideport(mvi, sas_phy->id);
  1183. }
  1184. if (lock)
  1185. spin_unlock_irqrestore(&mvi->lock, flags);
  1186. }
  1187. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  1188. {
  1189. struct domain_device *dev;
  1190. struct mvs_phy *phy = sas_phy->lldd_phy;
  1191. struct mvs_info *mvi = phy->mvi;
  1192. struct asd_sas_port *port = sas_phy->port;
  1193. int phy_no = 0;
  1194. while (phy != &mvi->phy[phy_no]) {
  1195. phy_no++;
  1196. if (phy_no >= MVS_MAX_PHYS)
  1197. return;
  1198. }
  1199. list_for_each_entry(dev, &port->dev_list, dev_list_node)
  1200. mvs_do_release_task(phy->mvi, phy_no, NULL);
  1201. }
  1202. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  1203. {
  1204. mvs_port_notify_formed(sas_phy, 1);
  1205. }
  1206. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  1207. {
  1208. mvs_port_notify_deformed(sas_phy, 1);
  1209. }
  1210. struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  1211. {
  1212. u32 dev;
  1213. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  1214. if (mvi->devices[dev].dev_type == NO_DEVICE) {
  1215. mvi->devices[dev].device_id = dev;
  1216. return &mvi->devices[dev];
  1217. }
  1218. }
  1219. if (dev == MVS_MAX_DEVICES)
  1220. mv_printk("max support %d devices, ignore ..\n",
  1221. MVS_MAX_DEVICES);
  1222. return NULL;
  1223. }
  1224. void mvs_free_dev(struct mvs_device *mvi_dev)
  1225. {
  1226. u32 id = mvi_dev->device_id;
  1227. memset(mvi_dev, 0, sizeof(*mvi_dev));
  1228. mvi_dev->device_id = id;
  1229. mvi_dev->dev_type = NO_DEVICE;
  1230. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1231. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  1232. }
  1233. int mvs_dev_found_notify(struct domain_device *dev, int lock)
  1234. {
  1235. unsigned long flags = 0;
  1236. int res = 0;
  1237. struct mvs_info *mvi = NULL;
  1238. struct domain_device *parent_dev = dev->parent;
  1239. struct mvs_device *mvi_device;
  1240. mvi = mvs_find_dev_mvi(dev);
  1241. if (lock)
  1242. spin_lock_irqsave(&mvi->lock, flags);
  1243. mvi_device = mvs_alloc_dev(mvi);
  1244. if (!mvi_device) {
  1245. res = -1;
  1246. goto found_out;
  1247. }
  1248. dev->lldd_dev = mvi_device;
  1249. mvi_device->dev_status = MVS_DEV_NORMAL;
  1250. mvi_device->dev_type = dev->dev_type;
  1251. mvi_device->mvi_info = mvi;
  1252. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
  1253. int phy_id;
  1254. u8 phy_num = parent_dev->ex_dev.num_phys;
  1255. struct ex_phy *phy;
  1256. for (phy_id = 0; phy_id < phy_num; phy_id++) {
  1257. phy = &parent_dev->ex_dev.ex_phy[phy_id];
  1258. if (SAS_ADDR(phy->attached_sas_addr) ==
  1259. SAS_ADDR(dev->sas_addr)) {
  1260. mvi_device->attached_phy = phy_id;
  1261. break;
  1262. }
  1263. }
  1264. if (phy_id == phy_num) {
  1265. mv_printk("Error: no attached dev:%016llx"
  1266. "at ex:%016llx.\n",
  1267. SAS_ADDR(dev->sas_addr),
  1268. SAS_ADDR(parent_dev->sas_addr));
  1269. res = -1;
  1270. }
  1271. }
  1272. found_out:
  1273. if (lock)
  1274. spin_unlock_irqrestore(&mvi->lock, flags);
  1275. return res;
  1276. }
  1277. int mvs_dev_found(struct domain_device *dev)
  1278. {
  1279. return mvs_dev_found_notify(dev, 1);
  1280. }
  1281. void mvs_dev_gone_notify(struct domain_device *dev)
  1282. {
  1283. unsigned long flags = 0;
  1284. struct mvs_device *mvi_dev = dev->lldd_dev;
  1285. struct mvs_info *mvi = mvi_dev->mvi_info;
  1286. spin_lock_irqsave(&mvi->lock, flags);
  1287. if (mvi_dev) {
  1288. mv_dprintk("found dev[%d:%x] is gone.\n",
  1289. mvi_dev->device_id, mvi_dev->dev_type);
  1290. mvs_release_task(mvi, dev);
  1291. mvs_free_reg_set(mvi, mvi_dev);
  1292. mvs_free_dev(mvi_dev);
  1293. } else {
  1294. mv_dprintk("found dev has gone.\n");
  1295. }
  1296. dev->lldd_dev = NULL;
  1297. spin_unlock_irqrestore(&mvi->lock, flags);
  1298. }
  1299. void mvs_dev_gone(struct domain_device *dev)
  1300. {
  1301. mvs_dev_gone_notify(dev);
  1302. }
  1303. static struct sas_task *mvs_alloc_task(void)
  1304. {
  1305. struct sas_task *task = kzalloc(sizeof(struct sas_task), GFP_KERNEL);
  1306. if (task) {
  1307. INIT_LIST_HEAD(&task->list);
  1308. spin_lock_init(&task->task_state_lock);
  1309. task->task_state_flags = SAS_TASK_STATE_PENDING;
  1310. init_timer(&task->timer);
  1311. init_completion(&task->completion);
  1312. }
  1313. return task;
  1314. }
  1315. static void mvs_free_task(struct sas_task *task)
  1316. {
  1317. if (task) {
  1318. BUG_ON(!list_empty(&task->list));
  1319. kfree(task);
  1320. }
  1321. }
  1322. static void mvs_task_done(struct sas_task *task)
  1323. {
  1324. if (!del_timer(&task->timer))
  1325. return;
  1326. complete(&task->completion);
  1327. }
  1328. static void mvs_tmf_timedout(unsigned long data)
  1329. {
  1330. struct sas_task *task = (struct sas_task *)data;
  1331. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1332. complete(&task->completion);
  1333. }
  1334. /* XXX */
  1335. #define MVS_TASK_TIMEOUT 20
  1336. static int mvs_exec_internal_tmf_task(struct domain_device *dev,
  1337. void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
  1338. {
  1339. int res, retry;
  1340. struct sas_task *task = NULL;
  1341. for (retry = 0; retry < 3; retry++) {
  1342. task = mvs_alloc_task();
  1343. if (!task)
  1344. return -ENOMEM;
  1345. task->dev = dev;
  1346. task->task_proto = dev->tproto;
  1347. memcpy(&task->ssp_task, parameter, para_len);
  1348. task->task_done = mvs_task_done;
  1349. task->timer.data = (unsigned long) task;
  1350. task->timer.function = mvs_tmf_timedout;
  1351. task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
  1352. add_timer(&task->timer);
  1353. res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 1, tmf);
  1354. if (res) {
  1355. del_timer(&task->timer);
  1356. mv_printk("executing internel task failed:%d\n", res);
  1357. goto ex_err;
  1358. }
  1359. wait_for_completion(&task->completion);
  1360. res = -TMF_RESP_FUNC_FAILED;
  1361. /* Even TMF timed out, return direct. */
  1362. if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
  1363. if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
  1364. mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
  1365. goto ex_err;
  1366. }
  1367. }
  1368. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1369. task->task_status.stat == SAM_STAT_GOOD) {
  1370. res = TMF_RESP_FUNC_COMPLETE;
  1371. break;
  1372. }
  1373. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1374. task->task_status.stat == SAS_DATA_UNDERRUN) {
  1375. /* no error, but return the number of bytes of
  1376. * underrun */
  1377. res = task->task_status.residual;
  1378. break;
  1379. }
  1380. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1381. task->task_status.stat == SAS_DATA_OVERRUN) {
  1382. mv_dprintk("blocked task error.\n");
  1383. res = -EMSGSIZE;
  1384. break;
  1385. } else {
  1386. mv_dprintk(" task to dev %016llx response: 0x%x "
  1387. "status 0x%x\n",
  1388. SAS_ADDR(dev->sas_addr),
  1389. task->task_status.resp,
  1390. task->task_status.stat);
  1391. mvs_free_task(task);
  1392. task = NULL;
  1393. }
  1394. }
  1395. ex_err:
  1396. BUG_ON(retry == 3 && task != NULL);
  1397. if (task != NULL)
  1398. mvs_free_task(task);
  1399. return res;
  1400. }
  1401. static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
  1402. u8 *lun, struct mvs_tmf_task *tmf)
  1403. {
  1404. struct sas_ssp_task ssp_task;
  1405. DECLARE_COMPLETION_ONSTACK(completion);
  1406. if (!(dev->tproto & SAS_PROTOCOL_SSP))
  1407. return TMF_RESP_FUNC_ESUPP;
  1408. strncpy((u8 *)&ssp_task.LUN, lun, 8);
  1409. return mvs_exec_internal_tmf_task(dev, &ssp_task,
  1410. sizeof(ssp_task), tmf);
  1411. }
  1412. /* Standard mandates link reset for ATA (type 0)
  1413. and hard reset for SSP (type 1) , only for RECOVERY */
  1414. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1415. {
  1416. int rc;
  1417. struct sas_phy *phy = sas_find_local_phy(dev);
  1418. int reset_type = (dev->dev_type == SATA_DEV ||
  1419. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1420. rc = sas_phy_reset(phy, reset_type);
  1421. msleep(2000);
  1422. return rc;
  1423. }
  1424. /* mandatory SAM-3 */
  1425. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1426. {
  1427. unsigned long flags;
  1428. int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
  1429. struct mvs_tmf_task tmf_task;
  1430. struct mvs_device * mvi_dev = dev->lldd_dev;
  1431. struct mvs_info *mvi = mvi_dev->mvi_info;
  1432. tmf_task.tmf = TMF_LU_RESET;
  1433. mvi_dev->dev_status = MVS_DEV_EH;
  1434. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1435. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1436. num = mvs_find_dev_phyno(dev, phyno);
  1437. spin_lock_irqsave(&mvi->lock, flags);
  1438. for (i = 0; i < num; i++)
  1439. mvs_release_task(mvi, dev);
  1440. spin_unlock_irqrestore(&mvi->lock, flags);
  1441. }
  1442. /* If failed, fall-through I_T_Nexus reset */
  1443. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1444. mvi_dev->device_id, rc);
  1445. return rc;
  1446. }
  1447. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1448. {
  1449. unsigned long flags;
  1450. int rc = TMF_RESP_FUNC_FAILED;
  1451. struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1452. struct mvs_info *mvi = mvi_dev->mvi_info;
  1453. if (mvi_dev->dev_status != MVS_DEV_EH)
  1454. return TMF_RESP_FUNC_COMPLETE;
  1455. rc = mvs_debug_I_T_nexus_reset(dev);
  1456. mv_printk("%s for device[%x]:rc= %d\n",
  1457. __func__, mvi_dev->device_id, rc);
  1458. /* housekeeper */
  1459. spin_lock_irqsave(&mvi->lock, flags);
  1460. mvs_release_task(mvi, dev);
  1461. spin_unlock_irqrestore(&mvi->lock, flags);
  1462. return rc;
  1463. }
  1464. /* optional SAM-3 */
  1465. int mvs_query_task(struct sas_task *task)
  1466. {
  1467. u32 tag;
  1468. struct scsi_lun lun;
  1469. struct mvs_tmf_task tmf_task;
  1470. int rc = TMF_RESP_FUNC_FAILED;
  1471. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1472. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1473. struct domain_device *dev = task->dev;
  1474. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1475. struct mvs_info *mvi = mvi_dev->mvi_info;
  1476. int_to_scsilun(cmnd->device->lun, &lun);
  1477. rc = mvs_find_tag(mvi, task, &tag);
  1478. if (rc == 0) {
  1479. rc = TMF_RESP_FUNC_FAILED;
  1480. return rc;
  1481. }
  1482. tmf_task.tmf = TMF_QUERY_TASK;
  1483. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1484. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1485. switch (rc) {
  1486. /* The task is still in Lun, release it then */
  1487. case TMF_RESP_FUNC_SUCC:
  1488. /* The task is not in Lun or failed, reset the phy */
  1489. case TMF_RESP_FUNC_FAILED:
  1490. case TMF_RESP_FUNC_COMPLETE:
  1491. break;
  1492. default:
  1493. rc = TMF_RESP_FUNC_COMPLETE;
  1494. break;
  1495. }
  1496. }
  1497. mv_printk("%s:rc= %d\n", __func__, rc);
  1498. return rc;
  1499. }
  1500. /* mandatory SAM-3, still need free task/slot info */
  1501. int mvs_abort_task(struct sas_task *task)
  1502. {
  1503. struct scsi_lun lun;
  1504. struct mvs_tmf_task tmf_task;
  1505. struct domain_device *dev = task->dev;
  1506. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1507. struct mvs_info *mvi;
  1508. int rc = TMF_RESP_FUNC_FAILED;
  1509. unsigned long flags;
  1510. u32 tag;
  1511. if (!mvi_dev) {
  1512. mv_printk("%s:%d TMF_RESP_FUNC_FAILED\n", __func__, __LINE__);
  1513. rc = TMF_RESP_FUNC_FAILED;
  1514. }
  1515. mvi = mvi_dev->mvi_info;
  1516. spin_lock_irqsave(&task->task_state_lock, flags);
  1517. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1518. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1519. rc = TMF_RESP_FUNC_COMPLETE;
  1520. goto out;
  1521. }
  1522. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1523. mvi_dev->dev_status = MVS_DEV_EH;
  1524. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1525. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1526. int_to_scsilun(cmnd->device->lun, &lun);
  1527. rc = mvs_find_tag(mvi, task, &tag);
  1528. if (rc == 0) {
  1529. mv_printk("No such tag in %s\n", __func__);
  1530. rc = TMF_RESP_FUNC_FAILED;
  1531. return rc;
  1532. }
  1533. tmf_task.tmf = TMF_ABORT_TASK;
  1534. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1535. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1536. /* if successful, clear the task and callback forwards.*/
  1537. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1538. u32 slot_no;
  1539. struct mvs_slot_info *slot;
  1540. if (task->lldd_task) {
  1541. slot = task->lldd_task;
  1542. slot_no = (u32) (slot - mvi->slot_info);
  1543. spin_lock_irqsave(&mvi->lock, flags);
  1544. mvs_slot_complete(mvi, slot_no, 1);
  1545. spin_unlock_irqrestore(&mvi->lock, flags);
  1546. }
  1547. }
  1548. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1549. task->task_proto & SAS_PROTOCOL_STP) {
  1550. /* to do free register_set */
  1551. if (SATA_DEV == dev->dev_type) {
  1552. struct mvs_slot_info *slot = task->lldd_task;
  1553. struct task_status_struct *tstat;
  1554. u32 slot_idx = (u32)(slot - mvi->slot_info);
  1555. tstat = &task->task_status;
  1556. mv_dprintk(KERN_DEBUG "mv_abort_task() mvi=%p task=%p "
  1557. "slot=%p slot_idx=x%x\n",
  1558. mvi, task, slot, slot_idx);
  1559. tstat->stat = SAS_ABORTED_TASK;
  1560. if (mvi_dev && mvi_dev->running_req)
  1561. mvi_dev->running_req--;
  1562. if (sas_protocol_ata(task->task_proto))
  1563. mvs_free_reg_set(mvi, mvi_dev);
  1564. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1565. return -1;
  1566. }
  1567. } else {
  1568. /* SMP */
  1569. }
  1570. out:
  1571. if (rc != TMF_RESP_FUNC_COMPLETE)
  1572. mv_printk("%s:rc= %d\n", __func__, rc);
  1573. return rc;
  1574. }
  1575. int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
  1576. {
  1577. int rc = TMF_RESP_FUNC_FAILED;
  1578. struct mvs_tmf_task tmf_task;
  1579. tmf_task.tmf = TMF_ABORT_TASK_SET;
  1580. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1581. return rc;
  1582. }
  1583. int mvs_clear_aca(struct domain_device *dev, u8 *lun)
  1584. {
  1585. int rc = TMF_RESP_FUNC_FAILED;
  1586. struct mvs_tmf_task tmf_task;
  1587. tmf_task.tmf = TMF_CLEAR_ACA;
  1588. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1589. return rc;
  1590. }
  1591. int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
  1592. {
  1593. int rc = TMF_RESP_FUNC_FAILED;
  1594. struct mvs_tmf_task tmf_task;
  1595. tmf_task.tmf = TMF_CLEAR_TASK_SET;
  1596. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1597. return rc;
  1598. }
  1599. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1600. u32 slot_idx, int err)
  1601. {
  1602. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  1603. struct task_status_struct *tstat = &task->task_status;
  1604. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1605. int stat = SAM_STAT_GOOD;
  1606. resp->frame_len = sizeof(struct dev_to_host_fis);
  1607. memcpy(&resp->ending_fis[0],
  1608. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1609. sizeof(struct dev_to_host_fis));
  1610. tstat->buf_valid_size = sizeof(*resp);
  1611. if (unlikely(err)) {
  1612. if (unlikely(err & CMD_ISS_STPD))
  1613. stat = SAS_OPEN_REJECT;
  1614. else
  1615. stat = SAS_PROTO_RESPONSE;
  1616. }
  1617. return stat;
  1618. }
  1619. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1620. u32 slot_idx)
  1621. {
  1622. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1623. int stat;
  1624. u32 err_dw0 = le32_to_cpu(*(u32 *) (slot->response));
  1625. u32 tfs = 0;
  1626. enum mvs_port_type type = PORT_TYPE_SAS;
  1627. if (err_dw0 & CMD_ISS_STPD)
  1628. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1629. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1630. stat = SAM_STAT_CHECK_CONDITION;
  1631. switch (task->task_proto) {
  1632. case SAS_PROTOCOL_SSP:
  1633. stat = SAS_ABORTED_TASK;
  1634. break;
  1635. case SAS_PROTOCOL_SMP:
  1636. stat = SAM_STAT_CHECK_CONDITION;
  1637. break;
  1638. case SAS_PROTOCOL_SATA:
  1639. case SAS_PROTOCOL_STP:
  1640. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1641. {
  1642. if (err_dw0 == 0x80400002)
  1643. mv_printk("find reserved error, why?\n");
  1644. task->ata_task.use_ncq = 0;
  1645. mvs_sata_done(mvi, task, slot_idx, err_dw0);
  1646. }
  1647. break;
  1648. default:
  1649. break;
  1650. }
  1651. return stat;
  1652. }
  1653. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1654. {
  1655. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1656. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1657. struct sas_task *task = slot->task;
  1658. struct mvs_device *mvi_dev = NULL;
  1659. struct task_status_struct *tstat;
  1660. struct domain_device *dev;
  1661. u32 aborted;
  1662. void *to;
  1663. enum exec_status sts;
  1664. if (mvi->exp_req)
  1665. mvi->exp_req--;
  1666. if (unlikely(!task || !task->lldd_task || !task->dev))
  1667. return -1;
  1668. tstat = &task->task_status;
  1669. dev = task->dev;
  1670. mvi_dev = dev->lldd_dev;
  1671. mvs_hba_cq_dump(mvi);
  1672. spin_lock(&task->task_state_lock);
  1673. task->task_state_flags &=
  1674. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1675. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1676. /* race condition*/
  1677. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1678. spin_unlock(&task->task_state_lock);
  1679. memset(tstat, 0, sizeof(*tstat));
  1680. tstat->resp = SAS_TASK_COMPLETE;
  1681. if (unlikely(aborted)) {
  1682. tstat->stat = SAS_ABORTED_TASK;
  1683. if (mvi_dev && mvi_dev->running_req)
  1684. mvi_dev->running_req--;
  1685. if (sas_protocol_ata(task->task_proto))
  1686. mvs_free_reg_set(mvi, mvi_dev);
  1687. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1688. return -1;
  1689. }
  1690. if (unlikely(!mvi_dev || flags)) {
  1691. if (!mvi_dev)
  1692. mv_dprintk("port has not device.\n");
  1693. tstat->stat = SAS_PHY_DOWN;
  1694. goto out;
  1695. }
  1696. /* error info record present */
  1697. if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
  1698. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1699. tstat->resp = SAS_TASK_COMPLETE;
  1700. goto out;
  1701. }
  1702. switch (task->task_proto) {
  1703. case SAS_PROTOCOL_SSP:
  1704. /* hw says status == 0, datapres == 0 */
  1705. if (rx_desc & RXQ_GOOD) {
  1706. tstat->stat = SAM_STAT_GOOD;
  1707. tstat->resp = SAS_TASK_COMPLETE;
  1708. }
  1709. /* response frame present */
  1710. else if (rx_desc & RXQ_RSP) {
  1711. struct ssp_response_iu *iu = slot->response +
  1712. sizeof(struct mvs_err_info);
  1713. sas_ssp_task_response(mvi->dev, task, iu);
  1714. } else
  1715. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1716. break;
  1717. case SAS_PROTOCOL_SMP: {
  1718. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1719. tstat->stat = SAM_STAT_GOOD;
  1720. to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
  1721. memcpy(to + sg_resp->offset,
  1722. slot->response + sizeof(struct mvs_err_info),
  1723. sg_dma_len(sg_resp));
  1724. kunmap_atomic(to, KM_IRQ0);
  1725. break;
  1726. }
  1727. case SAS_PROTOCOL_SATA:
  1728. case SAS_PROTOCOL_STP:
  1729. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1730. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1731. break;
  1732. }
  1733. default:
  1734. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1735. break;
  1736. }
  1737. if (!slot->port->port_attached) {
  1738. mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
  1739. tstat->stat = SAS_PHY_DOWN;
  1740. }
  1741. out:
  1742. if (mvi_dev && mvi_dev->running_req) {
  1743. mvi_dev->running_req--;
  1744. if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
  1745. mvs_free_reg_set(mvi, mvi_dev);
  1746. }
  1747. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1748. sts = tstat->stat;
  1749. spin_unlock(&mvi->lock);
  1750. if (task->task_done)
  1751. task->task_done(task);
  1752. else
  1753. mv_dprintk("why has not task_done.\n");
  1754. spin_lock(&mvi->lock);
  1755. return sts;
  1756. }
  1757. void mvs_do_release_task(struct mvs_info *mvi,
  1758. int phy_no, struct domain_device *dev)
  1759. {
  1760. u32 slot_idx;
  1761. struct mvs_phy *phy;
  1762. struct mvs_port *port;
  1763. struct mvs_slot_info *slot, *slot2;
  1764. phy = &mvi->phy[phy_no];
  1765. port = phy->port;
  1766. if (!port)
  1767. return;
  1768. /* clean cmpl queue in case request is already finished */
  1769. mvs_int_rx(mvi, false);
  1770. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1771. struct sas_task *task;
  1772. slot_idx = (u32) (slot - mvi->slot_info);
  1773. task = slot->task;
  1774. if (dev && task->dev != dev)
  1775. continue;
  1776. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1777. slot_idx, slot->slot_tag, task);
  1778. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1779. mvs_slot_complete(mvi, slot_idx, 1);
  1780. }
  1781. }
  1782. void mvs_release_task(struct mvs_info *mvi,
  1783. struct domain_device *dev)
  1784. {
  1785. int i, phyno[WIDE_PORT_MAX_PHY], num;
  1786. /* housekeeper */
  1787. num = mvs_find_dev_phyno(dev, phyno);
  1788. for (i = 0; i < num; i++)
  1789. mvs_do_release_task(mvi, phyno[i], dev);
  1790. }
  1791. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1792. {
  1793. phy->phy_attached = 0;
  1794. phy->att_dev_info = 0;
  1795. phy->att_dev_sas_addr = 0;
  1796. }
  1797. static void mvs_work_queue(struct work_struct *work)
  1798. {
  1799. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1800. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1801. struct mvs_info *mvi = mwq->mvi;
  1802. unsigned long flags;
  1803. spin_lock_irqsave(&mvi->lock, flags);
  1804. if (mwq->handler & PHY_PLUG_EVENT) {
  1805. u32 phy_no = (unsigned long) mwq->data;
  1806. struct sas_ha_struct *sas_ha = mvi->sas;
  1807. struct mvs_phy *phy = &mvi->phy[phy_no];
  1808. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1809. if (phy->phy_event & PHY_PLUG_OUT) {
  1810. u32 tmp;
  1811. struct sas_identify_frame *id;
  1812. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1813. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1814. phy->phy_event &= ~PHY_PLUG_OUT;
  1815. if (!(tmp & PHY_READY_MASK)) {
  1816. sas_phy_disconnected(sas_phy);
  1817. mvs_phy_disconnected(phy);
  1818. sas_ha->notify_phy_event(sas_phy,
  1819. PHYE_LOSS_OF_SIGNAL);
  1820. mv_dprintk("phy%d Removed Device\n", phy_no);
  1821. } else {
  1822. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1823. mvs_update_phyinfo(mvi, phy_no, 1);
  1824. mvs_bytes_dmaed(mvi, phy_no);
  1825. mvs_port_notify_formed(sas_phy, 0);
  1826. mv_dprintk("phy%d Attached Device\n", phy_no);
  1827. }
  1828. }
  1829. }
  1830. list_del(&mwq->entry);
  1831. spin_unlock_irqrestore(&mvi->lock, flags);
  1832. kfree(mwq);
  1833. }
  1834. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1835. {
  1836. struct mvs_wq *mwq;
  1837. int ret = 0;
  1838. mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
  1839. if (mwq) {
  1840. mwq->mvi = mvi;
  1841. mwq->data = data;
  1842. mwq->handler = handler;
  1843. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1844. list_add_tail(&mwq->entry, &mvi->wq_list);
  1845. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1846. } else
  1847. ret = -ENOMEM;
  1848. return ret;
  1849. }
  1850. static void mvs_sig_time_out(unsigned long tphy)
  1851. {
  1852. struct mvs_phy *phy = (struct mvs_phy *)tphy;
  1853. struct mvs_info *mvi = phy->mvi;
  1854. u8 phy_no;
  1855. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1856. if (&mvi->phy[phy_no] == phy) {
  1857. mv_dprintk("Get signature time out, reset phy %d\n",
  1858. phy_no+mvi->id*mvi->chip->n_phy);
  1859. MVS_CHIP_DISP->phy_reset(mvi, phy_no, 1);
  1860. }
  1861. }
  1862. }
  1863. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  1864. {
  1865. if (phy->timer.function)
  1866. del_timer(&phy->timer);
  1867. phy->timer.function = NULL;
  1868. }
  1869. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1870. {
  1871. u32 tmp;
  1872. struct sas_ha_struct *sas_ha = mvi->sas;
  1873. struct mvs_phy *phy = &mvi->phy[phy_no];
  1874. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1875. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1876. mv_dprintk("port %d ctrl sts=0x%X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1877. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1878. mv_dprintk("Port %d irq sts = 0x%X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1879. phy->irq_status);
  1880. /*
  1881. * events is port event now ,
  1882. * we need check the interrupt status which belongs to per port.
  1883. */
  1884. if (phy->irq_status & PHYEV_DCDR_ERR) {
  1885. mv_dprintk("port %d STP decoding error.\n",
  1886. phy_no + mvi->id*mvi->chip->n_phy);
  1887. }
  1888. if (phy->irq_status & PHYEV_POOF) {
  1889. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1890. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1891. int ready;
  1892. mvs_do_release_task(mvi, phy_no, NULL);
  1893. phy->phy_event |= PHY_PLUG_OUT;
  1894. MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
  1895. mvs_handle_event(mvi,
  1896. (void *)(unsigned long)phy_no,
  1897. PHY_PLUG_EVENT);
  1898. ready = mvs_is_phy_ready(mvi, phy_no);
  1899. if (!ready)
  1900. mv_dprintk("phy%d Unplug Notice\n",
  1901. phy_no +
  1902. mvi->id * mvi->chip->n_phy);
  1903. if (ready || dev_sata) {
  1904. if (MVS_CHIP_DISP->stp_reset)
  1905. MVS_CHIP_DISP->stp_reset(mvi,
  1906. phy_no);
  1907. else
  1908. MVS_CHIP_DISP->phy_reset(mvi,
  1909. phy_no, 0);
  1910. return;
  1911. }
  1912. }
  1913. }
  1914. if (phy->irq_status & PHYEV_COMWAKE) {
  1915. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1916. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1917. tmp | PHYEV_SIG_FIS);
  1918. if (phy->timer.function == NULL) {
  1919. phy->timer.data = (unsigned long)phy;
  1920. phy->timer.function = mvs_sig_time_out;
  1921. phy->timer.expires = jiffies + 10*HZ;
  1922. add_timer(&phy->timer);
  1923. }
  1924. }
  1925. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1926. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1927. mvs_sig_remove_timer(phy);
  1928. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1929. if (phy->phy_status) {
  1930. mdelay(10);
  1931. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1932. if (phy->phy_type & PORT_TYPE_SATA) {
  1933. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1934. mvi, phy_no);
  1935. tmp &= ~PHYEV_SIG_FIS;
  1936. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1937. phy_no, tmp);
  1938. }
  1939. mvs_update_phyinfo(mvi, phy_no, 0);
  1940. if (phy->phy_type & PORT_TYPE_SAS) {
  1941. MVS_CHIP_DISP->phy_reset(mvi, phy_no, 2);
  1942. mdelay(10);
  1943. }
  1944. mvs_bytes_dmaed(mvi, phy_no);
  1945. /* whether driver is going to handle hot plug */
  1946. if (phy->phy_event & PHY_PLUG_OUT) {
  1947. mvs_port_notify_formed(sas_phy, 0);
  1948. phy->phy_event &= ~PHY_PLUG_OUT;
  1949. }
  1950. } else {
  1951. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1952. phy_no + mvi->id*mvi->chip->n_phy);
  1953. }
  1954. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1955. mv_dprintk("port %d broadcast change.\n",
  1956. phy_no + mvi->id*mvi->chip->n_phy);
  1957. /* exception for Samsung disk drive*/
  1958. mdelay(1000);
  1959. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  1960. }
  1961. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1962. }
  1963. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1964. {
  1965. u32 rx_prod_idx, rx_desc;
  1966. bool attn = false;
  1967. /* the first dword in the RX ring is special: it contains
  1968. * a mirror of the hardware's RX producer index, so that
  1969. * we don't have to stall the CPU reading that register.
  1970. * The actual RX ring is offset by one dword, due to this.
  1971. */
  1972. rx_prod_idx = mvi->rx_cons;
  1973. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1974. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1975. return 0;
  1976. /* The CMPL_Q may come late, read from register and try again
  1977. * note: if coalescing is enabled,
  1978. * it will need to read from register every time for sure
  1979. */
  1980. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1981. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1982. if (mvi->rx_cons == rx_prod_idx)
  1983. return 0;
  1984. while (mvi->rx_cons != rx_prod_idx) {
  1985. /* increment our internal RX consumer pointer */
  1986. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1987. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1988. if (likely(rx_desc & RXQ_DONE))
  1989. mvs_slot_complete(mvi, rx_desc, 0);
  1990. if (rx_desc & RXQ_ATTN) {
  1991. attn = true;
  1992. } else if (rx_desc & RXQ_ERR) {
  1993. if (!(rx_desc & RXQ_DONE))
  1994. mvs_slot_complete(mvi, rx_desc, 0);
  1995. } else if (rx_desc & RXQ_SLOT_RESET) {
  1996. mvs_slot_free(mvi, rx_desc);
  1997. }
  1998. }
  1999. if (attn && self_clear)
  2000. MVS_CHIP_DISP->int_full(mvi);
  2001. return 0;
  2002. }