at91sam9x5.dtsi 13 KB

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  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9x5 family SoC";
  14. compatible = "atmel,at91sam9x5";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. tcb0 = &tcb0;
  26. tcb1 = &tcb1;
  27. i2c0 = &i2c0;
  28. i2c1 = &i2c1;
  29. i2c2 = &i2c2;
  30. ssc0 = &ssc0;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x20000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe800 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe800 0x200>;
  60. };
  61. pmc: pmc@fffffc00 {
  62. compatible = "atmel,at91rm9200-pmc";
  63. reg = <0xfffffc00 0x100>;
  64. };
  65. rstc@fffffe00 {
  66. compatible = "atmel,at91sam9g45-rstc";
  67. reg = <0xfffffe00 0x10>;
  68. };
  69. shdwc@fffffe10 {
  70. compatible = "atmel,at91sam9x5-shdwc";
  71. reg = <0xfffffe10 0x10>;
  72. };
  73. pit: timer@fffffe30 {
  74. compatible = "atmel,at91sam9260-pit";
  75. reg = <0xfffffe30 0xf>;
  76. interrupts = <1 4 7>;
  77. };
  78. tcb0: timer@f8008000 {
  79. compatible = "atmel,at91sam9x5-tcb";
  80. reg = <0xf8008000 0x100>;
  81. interrupts = <17 4 0>;
  82. };
  83. tcb1: timer@f800c000 {
  84. compatible = "atmel,at91sam9x5-tcb";
  85. reg = <0xf800c000 0x100>;
  86. interrupts = <17 4 0>;
  87. };
  88. dma0: dma-controller@ffffec00 {
  89. compatible = "atmel,at91sam9g45-dma";
  90. reg = <0xffffec00 0x200>;
  91. interrupts = <20 4 0>;
  92. };
  93. dma1: dma-controller@ffffee00 {
  94. compatible = "atmel,at91sam9g45-dma";
  95. reg = <0xffffee00 0x200>;
  96. interrupts = <21 4 0>;
  97. };
  98. pinctrl@fffff400 {
  99. #address-cells = <1>;
  100. #size-cells = <1>;
  101. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  102. ranges = <0xfffff400 0xfffff400 0x800>;
  103. /* shared pinctrl settings */
  104. dbgu {
  105. pinctrl_dbgu: dbgu-0 {
  106. atmel,pins =
  107. <0 9 0x1 0x0 /* PA9 periph A */
  108. 0 10 0x1 0x1>; /* PA10 periph A with pullup */
  109. };
  110. };
  111. usart0 {
  112. pinctrl_usart0: usart0-0 {
  113. atmel,pins =
  114. <0 0 0x1 0x1 /* PA0 periph A with pullup */
  115. 0 1 0x1 0x0>; /* PA1 periph A */
  116. };
  117. pinctrl_usart0_rts: usart0_rts-0 {
  118. atmel,pins =
  119. <0 2 0x1 0x0>; /* PA2 periph A */
  120. };
  121. pinctrl_usart0_cts: usart0_cts-0 {
  122. atmel,pins =
  123. <0 3 0x1 0x0>; /* PA3 periph A */
  124. };
  125. };
  126. usart1 {
  127. pinctrl_usart1: usart1-0 {
  128. atmel,pins =
  129. <0 5 0x1 0x1 /* PA5 periph A with pullup */
  130. 0 6 0x1 0x0>; /* PA6 periph A */
  131. };
  132. pinctrl_usart1_rts: usart1_rts-0 {
  133. atmel,pins =
  134. <3 27 0x3 0x0>; /* PC27 periph C */
  135. };
  136. pinctrl_usart1_cts: usart1_cts-0 {
  137. atmel,pins =
  138. <3 28 0x3 0x0>; /* PC28 periph C */
  139. };
  140. };
  141. usart2 {
  142. pinctrl_usart2: usart2-0 {
  143. atmel,pins =
  144. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  145. 0 8 0x1 0x0>; /* PA8 periph A */
  146. };
  147. pinctrl_uart2_rts: uart2_rts-0 {
  148. atmel,pins =
  149. <0 0 0x2 0x0>; /* PB0 periph B */
  150. };
  151. pinctrl_uart2_cts: uart2_cts-0 {
  152. atmel,pins =
  153. <0 1 0x2 0x0>; /* PB1 periph B */
  154. };
  155. };
  156. usart3 {
  157. pinctrl_uart3: usart3-0 {
  158. atmel,pins =
  159. <3 23 0x2 0x1 /* PC22 periph B with pullup */
  160. 3 23 0x2 0x0>; /* PC23 periph B */
  161. };
  162. pinctrl_usart3_rts: usart3_rts-0 {
  163. atmel,pins =
  164. <3 24 0x2 0x0>; /* PC24 periph B */
  165. };
  166. pinctrl_usart3_cts: usart3_cts-0 {
  167. atmel,pins =
  168. <3 25 0x2 0x0>; /* PC25 periph B */
  169. };
  170. };
  171. uart0 {
  172. pinctrl_uart0: uart0-0 {
  173. atmel,pins =
  174. <3 8 0x3 0x0 /* PC8 periph C */
  175. 3 9 0x3 0x1>; /* PC9 periph C with pullup */
  176. };
  177. };
  178. uart1 {
  179. pinctrl_uart1: uart1-0 {
  180. atmel,pins =
  181. <3 16 0x3 0x0 /* PC16 periph C */
  182. 3 17 0x3 0x1>; /* PC17 periph C with pullup */
  183. };
  184. };
  185. nand {
  186. pinctrl_nand: nand-0 {
  187. atmel,pins =
  188. <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
  189. 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  190. };
  191. };
  192. macb0 {
  193. pinctrl_macb0_rmii: macb0_rmii-0 {
  194. atmel,pins =
  195. <1 0 0x1 0x0 /* PB0 periph A */
  196. 1 1 0x1 0x0 /* PB1 periph A */
  197. 1 2 0x1 0x0 /* PB2 periph A */
  198. 1 3 0x1 0x0 /* PB3 periph A */
  199. 1 4 0x1 0x0 /* PB4 periph A */
  200. 1 5 0x1 0x0 /* PB5 periph A */
  201. 1 6 0x1 0x0 /* PB6 periph A */
  202. 1 7 0x1 0x0 /* PB7 periph A */
  203. 1 9 0x1 0x0 /* PB9 periph A */
  204. 1 10 0x1 0x0>; /* PB10 periph A */
  205. };
  206. pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
  207. atmel,pins =
  208. <1 8 0x1 0x0 /* PA8 periph A */
  209. 1 11 0x1 0x0 /* PA11 periph A */
  210. 1 12 0x1 0x0 /* PA12 periph A */
  211. 1 13 0x1 0x0 /* PA13 periph A */
  212. 1 14 0x1 0x0 /* PA14 periph A */
  213. 1 15 0x1 0x0 /* PA15 periph A */
  214. 1 16 0x1 0x0 /* PA16 periph A */
  215. 1 17 0x1 0x0>; /* PA17 periph A */
  216. };
  217. };
  218. mmc0 {
  219. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  220. atmel,pins =
  221. <0 17 0x1 0x0 /* PA17 periph A */
  222. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  223. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  224. };
  225. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  226. atmel,pins =
  227. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  228. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  229. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  230. };
  231. };
  232. mmc1 {
  233. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  234. atmel,pins =
  235. <0 13 0x2 0x0 /* PA13 periph B */
  236. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  237. 0 11 0x2 0x1>; /* PA11 periph B with pullup */
  238. };
  239. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  240. atmel,pins =
  241. <0 2 0x2 0x1 /* PA2 periph B with pullup */
  242. 0 3 0x2 0x1 /* PA3 periph B with pullup */
  243. 0 4 0x2 0x1>; /* PA4 periph B with pullup */
  244. };
  245. };
  246. ssc0 {
  247. pinctrl_ssc0_tx: ssc0_tx-0 {
  248. atmel,pins =
  249. <0 24 0x2 0x0 /* PA24 periph B */
  250. 0 25 0x2 0x0 /* PA25 periph B */
  251. 0 26 0x2 0x0>; /* PA26 periph B */
  252. };
  253. pinctrl_ssc0_rx: ssc0_rx-0 {
  254. atmel,pins =
  255. <0 27 0x2 0x0 /* PA27 periph B */
  256. 0 28 0x2 0x0 /* PA28 periph B */
  257. 0 29 0x2 0x0>; /* PA29 periph B */
  258. };
  259. };
  260. pioA: gpio@fffff400 {
  261. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  262. reg = <0xfffff400 0x200>;
  263. interrupts = <2 4 1>;
  264. #gpio-cells = <2>;
  265. gpio-controller;
  266. interrupt-controller;
  267. #interrupt-cells = <2>;
  268. };
  269. pioB: gpio@fffff600 {
  270. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  271. reg = <0xfffff600 0x200>;
  272. interrupts = <2 4 1>;
  273. #gpio-cells = <2>;
  274. gpio-controller;
  275. #gpio-lines = <19>;
  276. interrupt-controller;
  277. #interrupt-cells = <2>;
  278. };
  279. pioC: gpio@fffff800 {
  280. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  281. reg = <0xfffff800 0x200>;
  282. interrupts = <3 4 1>;
  283. #gpio-cells = <2>;
  284. gpio-controller;
  285. interrupt-controller;
  286. #interrupt-cells = <2>;
  287. };
  288. pioD: gpio@fffffa00 {
  289. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  290. reg = <0xfffffa00 0x200>;
  291. interrupts = <3 4 1>;
  292. #gpio-cells = <2>;
  293. gpio-controller;
  294. #gpio-lines = <22>;
  295. interrupt-controller;
  296. #interrupt-cells = <2>;
  297. };
  298. };
  299. ssc0: ssc@f0010000 {
  300. compatible = "atmel,at91sam9g45-ssc";
  301. reg = <0xf0010000 0x4000>;
  302. interrupts = <28 4 5>;
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  305. status = "disabled";
  306. };
  307. mmc0: mmc@f0008000 {
  308. compatible = "atmel,hsmci";
  309. reg = <0xf0008000 0x600>;
  310. interrupts = <12 4 0>;
  311. #address-cells = <1>;
  312. #size-cells = <0>;
  313. status = "disabled";
  314. };
  315. mmc1: mmc@f000c000 {
  316. compatible = "atmel,hsmci";
  317. reg = <0xf000c000 0x600>;
  318. interrupts = <26 4 0>;
  319. #address-cells = <1>;
  320. #size-cells = <0>;
  321. status = "disabled";
  322. };
  323. dbgu: serial@fffff200 {
  324. compatible = "atmel,at91sam9260-usart";
  325. reg = <0xfffff200 0x200>;
  326. interrupts = <1 4 7>;
  327. pinctrl-names = "default";
  328. pinctrl-0 = <&pinctrl_dbgu>;
  329. status = "disabled";
  330. };
  331. usart0: serial@f801c000 {
  332. compatible = "atmel,at91sam9260-usart";
  333. reg = <0xf801c000 0x200>;
  334. interrupts = <5 4 5>;
  335. atmel,use-dma-rx;
  336. atmel,use-dma-tx;
  337. pinctrl-names = "default";
  338. pinctrl-0 = <&pinctrl_usart0>;
  339. status = "disabled";
  340. };
  341. usart1: serial@f8020000 {
  342. compatible = "atmel,at91sam9260-usart";
  343. reg = <0xf8020000 0x200>;
  344. interrupts = <6 4 5>;
  345. atmel,use-dma-rx;
  346. atmel,use-dma-tx;
  347. pinctrl-names = "default";
  348. pinctrl-0 = <&pinctrl_usart1>;
  349. status = "disabled";
  350. };
  351. usart2: serial@f8024000 {
  352. compatible = "atmel,at91sam9260-usart";
  353. reg = <0xf8024000 0x200>;
  354. interrupts = <7 4 5>;
  355. atmel,use-dma-rx;
  356. atmel,use-dma-tx;
  357. pinctrl-names = "default";
  358. pinctrl-0 = <&pinctrl_usart2>;
  359. status = "disabled";
  360. };
  361. macb0: ethernet@f802c000 {
  362. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  363. reg = <0xf802c000 0x100>;
  364. interrupts = <24 4 3>;
  365. pinctrl-names = "default";
  366. pinctrl-0 = <&pinctrl_macb0_rmii>;
  367. status = "disabled";
  368. };
  369. macb1: ethernet@f8030000 {
  370. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  371. reg = <0xf8030000 0x100>;
  372. interrupts = <27 4 3>;
  373. status = "disabled";
  374. };
  375. i2c0: i2c@f8010000 {
  376. compatible = "atmel,at91sam9x5-i2c";
  377. reg = <0xf8010000 0x100>;
  378. interrupts = <9 4 6>;
  379. #address-cells = <1>;
  380. #size-cells = <0>;
  381. status = "disabled";
  382. };
  383. i2c1: i2c@f8014000 {
  384. compatible = "atmel,at91sam9x5-i2c";
  385. reg = <0xf8014000 0x100>;
  386. interrupts = <10 4 6>;
  387. #address-cells = <1>;
  388. #size-cells = <0>;
  389. status = "disabled";
  390. };
  391. i2c2: i2c@f8018000 {
  392. compatible = "atmel,at91sam9x5-i2c";
  393. reg = <0xf8018000 0x100>;
  394. interrupts = <11 4 6>;
  395. #address-cells = <1>;
  396. #size-cells = <0>;
  397. status = "disabled";
  398. };
  399. adc0: adc@f804c000 {
  400. compatible = "atmel,at91sam9260-adc";
  401. reg = <0xf804c000 0x100>;
  402. interrupts = <19 4 0>;
  403. atmel,adc-use-external;
  404. atmel,adc-channels-used = <0xffff>;
  405. atmel,adc-vref = <3300>;
  406. atmel,adc-num-channels = <12>;
  407. atmel,adc-startup-time = <40>;
  408. atmel,adc-channel-base = <0x50>;
  409. atmel,adc-drdy-mask = <0x1000000>;
  410. atmel,adc-status-register = <0x30>;
  411. atmel,adc-trigger-register = <0xc0>;
  412. trigger@0 {
  413. trigger-name = "external-rising";
  414. trigger-value = <0x1>;
  415. trigger-external;
  416. };
  417. trigger@1 {
  418. trigger-name = "external-falling";
  419. trigger-value = <0x2>;
  420. trigger-external;
  421. };
  422. trigger@2 {
  423. trigger-name = "external-any";
  424. trigger-value = <0x3>;
  425. trigger-external;
  426. };
  427. trigger@3 {
  428. trigger-name = "continuous";
  429. trigger-value = <0x6>;
  430. };
  431. };
  432. };
  433. nand0: nand@40000000 {
  434. compatible = "atmel,at91rm9200-nand";
  435. #address-cells = <1>;
  436. #size-cells = <1>;
  437. reg = <0x40000000 0x10000000
  438. >;
  439. atmel,nand-addr-offset = <21>;
  440. atmel,nand-cmd-offset = <22>;
  441. pinctrl-names = "default";
  442. pinctrl-0 = <&pinctrl_nand>;
  443. gpios = <&pioD 5 0
  444. &pioD 4 0
  445. 0
  446. >;
  447. status = "disabled";
  448. };
  449. usb0: ohci@00600000 {
  450. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  451. reg = <0x00600000 0x100000>;
  452. interrupts = <22 4 2>;
  453. status = "disabled";
  454. };
  455. usb1: ehci@00700000 {
  456. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  457. reg = <0x00700000 0x100000>;
  458. interrupts = <22 4 2>;
  459. status = "disabled";
  460. };
  461. };
  462. i2c@0 {
  463. compatible = "i2c-gpio";
  464. gpios = <&pioA 30 0 /* sda */
  465. &pioA 31 0 /* scl */
  466. >;
  467. i2c-gpio,sda-open-drain;
  468. i2c-gpio,scl-open-drain;
  469. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  470. #address-cells = <1>;
  471. #size-cells = <0>;
  472. status = "disabled";
  473. };
  474. i2c@1 {
  475. compatible = "i2c-gpio";
  476. gpios = <&pioC 0 0 /* sda */
  477. &pioC 1 0 /* scl */
  478. >;
  479. i2c-gpio,sda-open-drain;
  480. i2c-gpio,scl-open-drain;
  481. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  482. #address-cells = <1>;
  483. #size-cells = <0>;
  484. status = "disabled";
  485. };
  486. i2c@2 {
  487. compatible = "i2c-gpio";
  488. gpios = <&pioB 4 0 /* sda */
  489. &pioB 5 0 /* scl */
  490. >;
  491. i2c-gpio,sda-open-drain;
  492. i2c-gpio,scl-open-drain;
  493. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  494. #address-cells = <1>;
  495. #size-cells = <0>;
  496. status = "disabled";
  497. };
  498. };