main.c 58 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static u8 parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. spin_unlock(&common->cc_lock);
  92. }
  93. unlock:
  94. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  95. }
  96. void ath9k_ps_restore(struct ath_softc *sc)
  97. {
  98. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  99. enum ath9k_power_mode mode;
  100. unsigned long flags;
  101. bool reset;
  102. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  103. if (--sc->ps_usecount != 0)
  104. goto unlock;
  105. if (sc->ps_idle) {
  106. ath9k_hw_setrxabort(sc->sc_ah, 1);
  107. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  108. mode = ATH9K_PM_FULL_SLEEP;
  109. } else if (sc->ps_enabled &&
  110. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  111. PS_WAIT_FOR_CAB |
  112. PS_WAIT_FOR_PSPOLL_DATA |
  113. PS_WAIT_FOR_TX_ACK))) {
  114. mode = ATH9K_PM_NETWORK_SLEEP;
  115. } else {
  116. goto unlock;
  117. }
  118. spin_lock(&common->cc_lock);
  119. ath_hw_cycle_counters_update(common);
  120. spin_unlock(&common->cc_lock);
  121. ath9k_hw_setpower(sc->sc_ah, mode);
  122. unlock:
  123. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  124. }
  125. void ath_start_ani(struct ath_common *common)
  126. {
  127. struct ath_hw *ah = common->ah;
  128. unsigned long timestamp = jiffies_to_msecs(jiffies);
  129. struct ath_softc *sc = (struct ath_softc *) common->priv;
  130. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  131. return;
  132. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  133. return;
  134. common->ani.longcal_timer = timestamp;
  135. common->ani.shortcal_timer = timestamp;
  136. common->ani.checkani_timer = timestamp;
  137. mod_timer(&common->ani.timer,
  138. jiffies +
  139. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  140. }
  141. static void ath_update_survey_nf(struct ath_softc *sc, int channel)
  142. {
  143. struct ath_hw *ah = sc->sc_ah;
  144. struct ath9k_channel *chan = &ah->channels[channel];
  145. struct survey_info *survey = &sc->survey[channel];
  146. if (chan->noisefloor) {
  147. survey->filled |= SURVEY_INFO_NOISE_DBM;
  148. survey->noise = ath9k_hw_getchan_noise(ah, chan);
  149. }
  150. }
  151. /*
  152. * Updates the survey statistics and returns the busy time since last
  153. * update in %, if the measurement duration was long enough for the
  154. * result to be useful, -1 otherwise.
  155. */
  156. static int ath_update_survey_stats(struct ath_softc *sc)
  157. {
  158. struct ath_hw *ah = sc->sc_ah;
  159. struct ath_common *common = ath9k_hw_common(ah);
  160. int pos = ah->curchan - &ah->channels[0];
  161. struct survey_info *survey = &sc->survey[pos];
  162. struct ath_cycle_counters *cc = &common->cc_survey;
  163. unsigned int div = common->clockrate * 1000;
  164. int ret = 0;
  165. if (!ah->curchan)
  166. return -1;
  167. if (ah->power_mode == ATH9K_PM_AWAKE)
  168. ath_hw_cycle_counters_update(common);
  169. if (cc->cycles > 0) {
  170. survey->filled |= SURVEY_INFO_CHANNEL_TIME |
  171. SURVEY_INFO_CHANNEL_TIME_BUSY |
  172. SURVEY_INFO_CHANNEL_TIME_RX |
  173. SURVEY_INFO_CHANNEL_TIME_TX;
  174. survey->channel_time += cc->cycles / div;
  175. survey->channel_time_busy += cc->rx_busy / div;
  176. survey->channel_time_rx += cc->rx_frame / div;
  177. survey->channel_time_tx += cc->tx_frame / div;
  178. }
  179. if (cc->cycles < div)
  180. return -1;
  181. if (cc->cycles > 0)
  182. ret = cc->rx_busy * 100 / cc->cycles;
  183. memset(cc, 0, sizeof(*cc));
  184. ath_update_survey_nf(sc, pos);
  185. return ret;
  186. }
  187. static void __ath_cancel_work(struct ath_softc *sc)
  188. {
  189. cancel_work_sync(&sc->paprd_work);
  190. cancel_work_sync(&sc->hw_check_work);
  191. cancel_delayed_work_sync(&sc->tx_complete_work);
  192. cancel_delayed_work_sync(&sc->hw_pll_work);
  193. }
  194. static void ath_cancel_work(struct ath_softc *sc)
  195. {
  196. __ath_cancel_work(sc);
  197. cancel_work_sync(&sc->hw_reset_work);
  198. }
  199. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  200. {
  201. struct ath_hw *ah = sc->sc_ah;
  202. struct ath_common *common = ath9k_hw_common(ah);
  203. bool ret;
  204. ieee80211_stop_queues(sc->hw);
  205. sc->hw_busy_count = 0;
  206. del_timer_sync(&common->ani.timer);
  207. del_timer_sync(&sc->rx_poll_timer);
  208. ath9k_debug_samp_bb_mac(sc);
  209. ath9k_hw_disable_interrupts(ah);
  210. ret = ath_drain_all_txq(sc, retry_tx);
  211. if (!ath_stoprecv(sc))
  212. ret = false;
  213. if (!flush) {
  214. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  215. ath_rx_tasklet(sc, 1, true);
  216. ath_rx_tasklet(sc, 1, false);
  217. } else {
  218. ath_flushrecv(sc);
  219. }
  220. return ret;
  221. }
  222. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  223. {
  224. struct ath_hw *ah = sc->sc_ah;
  225. struct ath_common *common = ath9k_hw_common(ah);
  226. if (ath_startrecv(sc) != 0) {
  227. ath_err(common, "Unable to restart recv logic\n");
  228. return false;
  229. }
  230. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  231. sc->config.txpowlimit, &sc->curtxpow);
  232. ath9k_hw_set_interrupts(ah);
  233. ath9k_hw_enable_interrupts(ah);
  234. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
  235. if (sc->sc_flags & SC_OP_BEACONS)
  236. ath_set_beacon(sc);
  237. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  238. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
  239. ath_start_rx_poll(sc, 3);
  240. if (!common->disable_ani)
  241. ath_start_ani(common);
  242. }
  243. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {
  244. struct ath_hw_antcomb_conf div_ant_conf;
  245. u8 lna_conf;
  246. ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
  247. if (sc->ant_rx == 1)
  248. lna_conf = ATH_ANT_DIV_COMB_LNA1;
  249. else
  250. lna_conf = ATH_ANT_DIV_COMB_LNA2;
  251. div_ant_conf.main_lna_conf = lna_conf;
  252. div_ant_conf.alt_lna_conf = lna_conf;
  253. ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
  254. }
  255. ieee80211_wake_queues(sc->hw);
  256. return true;
  257. }
  258. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  259. bool retry_tx)
  260. {
  261. struct ath_hw *ah = sc->sc_ah;
  262. struct ath_common *common = ath9k_hw_common(ah);
  263. struct ath9k_hw_cal_data *caldata = NULL;
  264. bool fastcc = true;
  265. bool flush = false;
  266. int r;
  267. __ath_cancel_work(sc);
  268. spin_lock_bh(&sc->sc_pcu_lock);
  269. if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
  270. fastcc = false;
  271. caldata = &sc->caldata;
  272. }
  273. if (!hchan) {
  274. fastcc = false;
  275. flush = true;
  276. hchan = ah->curchan;
  277. }
  278. if (!ath_prepare_reset(sc, retry_tx, flush))
  279. fastcc = false;
  280. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  281. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  282. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  283. if (r) {
  284. ath_err(common,
  285. "Unable to reset channel, reset status %d\n", r);
  286. goto out;
  287. }
  288. if (!ath_complete_reset(sc, true))
  289. r = -EIO;
  290. out:
  291. spin_unlock_bh(&sc->sc_pcu_lock);
  292. return r;
  293. }
  294. /*
  295. * Set/change channels. If the channel is really being changed, it's done
  296. * by reseting the chip. To accomplish this we must first cleanup any pending
  297. * DMA, then restart stuff.
  298. */
  299. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  300. struct ath9k_channel *hchan)
  301. {
  302. int r;
  303. if (sc->sc_flags & SC_OP_INVALID)
  304. return -EIO;
  305. r = ath_reset_internal(sc, hchan, false);
  306. return r;
  307. }
  308. static void ath_paprd_activate(struct ath_softc *sc)
  309. {
  310. struct ath_hw *ah = sc->sc_ah;
  311. struct ath9k_hw_cal_data *caldata = ah->caldata;
  312. int chain;
  313. if (!caldata || !caldata->paprd_done)
  314. return;
  315. ath9k_ps_wakeup(sc);
  316. ar9003_paprd_enable(ah, false);
  317. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  318. if (!(ah->txchainmask & BIT(chain)))
  319. continue;
  320. ar9003_paprd_populate_single_table(ah, caldata, chain);
  321. }
  322. ar9003_paprd_enable(ah, true);
  323. ath9k_ps_restore(sc);
  324. }
  325. static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
  326. {
  327. struct ieee80211_hw *hw = sc->hw;
  328. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  329. struct ath_hw *ah = sc->sc_ah;
  330. struct ath_common *common = ath9k_hw_common(ah);
  331. struct ath_tx_control txctl;
  332. int time_left;
  333. memset(&txctl, 0, sizeof(txctl));
  334. txctl.txq = sc->tx.txq_map[WME_AC_BE];
  335. memset(tx_info, 0, sizeof(*tx_info));
  336. tx_info->band = hw->conf.channel->band;
  337. tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
  338. tx_info->control.rates[0].idx = 0;
  339. tx_info->control.rates[0].count = 1;
  340. tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
  341. tx_info->control.rates[1].idx = -1;
  342. init_completion(&sc->paprd_complete);
  343. txctl.paprd = BIT(chain);
  344. if (ath_tx_start(hw, skb, &txctl) != 0) {
  345. ath_dbg(common, CALIBRATE, "PAPRD TX failed\n");
  346. dev_kfree_skb_any(skb);
  347. return false;
  348. }
  349. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  350. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  351. if (!time_left)
  352. ath_dbg(common, CALIBRATE,
  353. "Timeout waiting for paprd training on TX chain %d\n",
  354. chain);
  355. return !!time_left;
  356. }
  357. void ath_paprd_calibrate(struct work_struct *work)
  358. {
  359. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  360. struct ieee80211_hw *hw = sc->hw;
  361. struct ath_hw *ah = sc->sc_ah;
  362. struct ieee80211_hdr *hdr;
  363. struct sk_buff *skb = NULL;
  364. struct ath9k_hw_cal_data *caldata = ah->caldata;
  365. struct ath_common *common = ath9k_hw_common(ah);
  366. int ftype;
  367. int chain_ok = 0;
  368. int chain;
  369. int len = 1800;
  370. if (!caldata)
  371. return;
  372. ath9k_ps_wakeup(sc);
  373. if (ar9003_paprd_init_table(ah) < 0)
  374. goto fail_paprd;
  375. skb = alloc_skb(len, GFP_KERNEL);
  376. if (!skb)
  377. goto fail_paprd;
  378. skb_put(skb, len);
  379. memset(skb->data, 0, len);
  380. hdr = (struct ieee80211_hdr *)skb->data;
  381. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  382. hdr->frame_control = cpu_to_le16(ftype);
  383. hdr->duration_id = cpu_to_le16(10);
  384. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  385. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  386. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  387. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  388. if (!(ah->txchainmask & BIT(chain)))
  389. continue;
  390. chain_ok = 0;
  391. ath_dbg(common, CALIBRATE,
  392. "Sending PAPRD frame for thermal measurement on chain %d\n",
  393. chain);
  394. if (!ath_paprd_send_frame(sc, skb, chain))
  395. goto fail_paprd;
  396. ar9003_paprd_setup_gain_table(ah, chain);
  397. ath_dbg(common, CALIBRATE,
  398. "Sending PAPRD training frame on chain %d\n", chain);
  399. if (!ath_paprd_send_frame(sc, skb, chain))
  400. goto fail_paprd;
  401. if (!ar9003_paprd_is_done(ah)) {
  402. ath_dbg(common, CALIBRATE,
  403. "PAPRD not yet done on chain %d\n", chain);
  404. break;
  405. }
  406. if (ar9003_paprd_create_curve(ah, caldata, chain)) {
  407. ath_dbg(common, CALIBRATE,
  408. "PAPRD create curve failed on chain %d\n",
  409. chain);
  410. break;
  411. }
  412. chain_ok = 1;
  413. }
  414. kfree_skb(skb);
  415. if (chain_ok) {
  416. caldata->paprd_done = true;
  417. ath_paprd_activate(sc);
  418. }
  419. fail_paprd:
  420. ath9k_ps_restore(sc);
  421. }
  422. /*
  423. * This routine performs the periodic noise floor calibration function
  424. * that is used to adjust and optimize the chip performance. This
  425. * takes environmental changes (location, temperature) into account.
  426. * When the task is complete, it reschedules itself depending on the
  427. * appropriate interval that was calculated.
  428. */
  429. void ath_ani_calibrate(unsigned long data)
  430. {
  431. struct ath_softc *sc = (struct ath_softc *)data;
  432. struct ath_hw *ah = sc->sc_ah;
  433. struct ath_common *common = ath9k_hw_common(ah);
  434. bool longcal = false;
  435. bool shortcal = false;
  436. bool aniflag = false;
  437. unsigned int timestamp = jiffies_to_msecs(jiffies);
  438. u32 cal_interval, short_cal_interval, long_cal_interval;
  439. unsigned long flags;
  440. if (ah->caldata && ah->caldata->nfcal_interference)
  441. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  442. else
  443. long_cal_interval = ATH_LONG_CALINTERVAL;
  444. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  445. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  446. /* Only calibrate if awake */
  447. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  448. goto set_timer;
  449. ath9k_ps_wakeup(sc);
  450. /* Long calibration runs independently of short calibration. */
  451. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  452. longcal = true;
  453. common->ani.longcal_timer = timestamp;
  454. }
  455. /* Short calibration applies only while caldone is false */
  456. if (!common->ani.caldone) {
  457. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  458. shortcal = true;
  459. common->ani.shortcal_timer = timestamp;
  460. common->ani.resetcal_timer = timestamp;
  461. }
  462. } else {
  463. if ((timestamp - common->ani.resetcal_timer) >=
  464. ATH_RESTART_CALINTERVAL) {
  465. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  466. if (common->ani.caldone)
  467. common->ani.resetcal_timer = timestamp;
  468. }
  469. }
  470. /* Verify whether we must check ANI */
  471. if (sc->sc_ah->config.enable_ani
  472. && (timestamp - common->ani.checkani_timer) >=
  473. ah->config.ani_poll_interval) {
  474. aniflag = true;
  475. common->ani.checkani_timer = timestamp;
  476. }
  477. /* Call ANI routine if necessary */
  478. if (aniflag) {
  479. spin_lock_irqsave(&common->cc_lock, flags);
  480. ath9k_hw_ani_monitor(ah, ah->curchan);
  481. ath_update_survey_stats(sc);
  482. spin_unlock_irqrestore(&common->cc_lock, flags);
  483. }
  484. /* Perform calibration if necessary */
  485. if (longcal || shortcal) {
  486. common->ani.caldone =
  487. ath9k_hw_calibrate(ah, ah->curchan,
  488. ah->rxchainmask, longcal);
  489. }
  490. ath_dbg(common, ANI,
  491. "Calibration @%lu finished: %s %s %s, caldone: %s\n",
  492. jiffies,
  493. longcal ? "long" : "", shortcal ? "short" : "",
  494. aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
  495. ath9k_ps_restore(sc);
  496. set_timer:
  497. /*
  498. * Set timer interval based on previous results.
  499. * The interval must be the shortest necessary to satisfy ANI,
  500. * short calibration and long calibration.
  501. */
  502. ath9k_debug_samp_bb_mac(sc);
  503. cal_interval = ATH_LONG_CALINTERVAL;
  504. if (sc->sc_ah->config.enable_ani)
  505. cal_interval = min(cal_interval,
  506. (u32)ah->config.ani_poll_interval);
  507. if (!common->ani.caldone)
  508. cal_interval = min(cal_interval, (u32)short_cal_interval);
  509. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  510. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  511. if (!ah->caldata->paprd_done)
  512. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  513. else if (!ah->paprd_table_write_done)
  514. ath_paprd_activate(sc);
  515. }
  516. }
  517. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  518. struct ieee80211_vif *vif)
  519. {
  520. struct ath_node *an;
  521. an = (struct ath_node *)sta->drv_priv;
  522. #ifdef CONFIG_ATH9K_DEBUGFS
  523. spin_lock(&sc->nodes_lock);
  524. list_add(&an->list, &sc->nodes);
  525. spin_unlock(&sc->nodes_lock);
  526. #endif
  527. an->sta = sta;
  528. an->vif = vif;
  529. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  530. ath_tx_node_init(sc, an);
  531. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  532. sta->ht_cap.ampdu_factor);
  533. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  534. }
  535. }
  536. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  537. {
  538. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  539. #ifdef CONFIG_ATH9K_DEBUGFS
  540. spin_lock(&sc->nodes_lock);
  541. list_del(&an->list);
  542. spin_unlock(&sc->nodes_lock);
  543. an->sta = NULL;
  544. #endif
  545. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  546. ath_tx_node_cleanup(sc, an);
  547. }
  548. void ath9k_tasklet(unsigned long data)
  549. {
  550. struct ath_softc *sc = (struct ath_softc *)data;
  551. struct ath_hw *ah = sc->sc_ah;
  552. struct ath_common *common = ath9k_hw_common(ah);
  553. u32 status = sc->intrstatus;
  554. u32 rxmask;
  555. ath9k_ps_wakeup(sc);
  556. spin_lock(&sc->sc_pcu_lock);
  557. if ((status & ATH9K_INT_FATAL) ||
  558. (status & ATH9K_INT_BB_WATCHDOG)) {
  559. #ifdef CONFIG_ATH9K_DEBUGFS
  560. enum ath_reset_type type;
  561. if (status & ATH9K_INT_FATAL)
  562. type = RESET_TYPE_FATAL_INT;
  563. else
  564. type = RESET_TYPE_BB_WATCHDOG;
  565. RESET_STAT_INC(sc, type);
  566. #endif
  567. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  568. goto out;
  569. }
  570. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  571. /*
  572. * TSF sync does not look correct; remain awake to sync with
  573. * the next Beacon.
  574. */
  575. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  576. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  577. }
  578. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  579. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  580. ATH9K_INT_RXORN);
  581. else
  582. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  583. if (status & rxmask) {
  584. /* Check for high priority Rx first */
  585. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  586. (status & ATH9K_INT_RXHP))
  587. ath_rx_tasklet(sc, 0, true);
  588. ath_rx_tasklet(sc, 0, false);
  589. }
  590. if (status & ATH9K_INT_TX) {
  591. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  592. ath_tx_edma_tasklet(sc);
  593. else
  594. ath_tx_tasklet(sc);
  595. }
  596. ath9k_btcoex_handle_interrupt(sc, status);
  597. out:
  598. /* re-enable hardware interrupt */
  599. ath9k_hw_enable_interrupts(ah);
  600. spin_unlock(&sc->sc_pcu_lock);
  601. ath9k_ps_restore(sc);
  602. }
  603. irqreturn_t ath_isr(int irq, void *dev)
  604. {
  605. #define SCHED_INTR ( \
  606. ATH9K_INT_FATAL | \
  607. ATH9K_INT_BB_WATCHDOG | \
  608. ATH9K_INT_RXORN | \
  609. ATH9K_INT_RXEOL | \
  610. ATH9K_INT_RX | \
  611. ATH9K_INT_RXLP | \
  612. ATH9K_INT_RXHP | \
  613. ATH9K_INT_TX | \
  614. ATH9K_INT_BMISS | \
  615. ATH9K_INT_CST | \
  616. ATH9K_INT_TSFOOR | \
  617. ATH9K_INT_GENTIMER | \
  618. ATH9K_INT_MCI)
  619. struct ath_softc *sc = dev;
  620. struct ath_hw *ah = sc->sc_ah;
  621. struct ath_common *common = ath9k_hw_common(ah);
  622. enum ath9k_int status;
  623. bool sched = false;
  624. /*
  625. * The hardware is not ready/present, don't
  626. * touch anything. Note this can happen early
  627. * on if the IRQ is shared.
  628. */
  629. if (sc->sc_flags & SC_OP_INVALID)
  630. return IRQ_NONE;
  631. /* shared irq, not for us */
  632. if (!ath9k_hw_intrpend(ah))
  633. return IRQ_NONE;
  634. /*
  635. * Figure out the reason(s) for the interrupt. Note
  636. * that the hal returns a pseudo-ISR that may include
  637. * bits we haven't explicitly enabled so we mask the
  638. * value to insure we only process bits we requested.
  639. */
  640. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  641. status &= ah->imask; /* discard unasked-for bits */
  642. /*
  643. * If there are no status bits set, then this interrupt was not
  644. * for me (should have been caught above).
  645. */
  646. if (!status)
  647. return IRQ_NONE;
  648. /* Cache the status */
  649. sc->intrstatus = status;
  650. if (status & SCHED_INTR)
  651. sched = true;
  652. /*
  653. * If a FATAL or RXORN interrupt is received, we have to reset the
  654. * chip immediately.
  655. */
  656. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  657. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  658. goto chip_reset;
  659. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  660. (status & ATH9K_INT_BB_WATCHDOG)) {
  661. spin_lock(&common->cc_lock);
  662. ath_hw_cycle_counters_update(common);
  663. ar9003_hw_bb_watchdog_dbg_info(ah);
  664. spin_unlock(&common->cc_lock);
  665. goto chip_reset;
  666. }
  667. if (status & ATH9K_INT_SWBA)
  668. tasklet_schedule(&sc->bcon_tasklet);
  669. if (status & ATH9K_INT_TXURN)
  670. ath9k_hw_updatetxtriglevel(ah, true);
  671. if (status & ATH9K_INT_RXEOL) {
  672. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  673. ath9k_hw_set_interrupts(ah);
  674. }
  675. if (status & ATH9K_INT_MIB) {
  676. /*
  677. * Disable interrupts until we service the MIB
  678. * interrupt; otherwise it will continue to
  679. * fire.
  680. */
  681. ath9k_hw_disable_interrupts(ah);
  682. /*
  683. * Let the hal handle the event. We assume
  684. * it will clear whatever condition caused
  685. * the interrupt.
  686. */
  687. spin_lock(&common->cc_lock);
  688. ath9k_hw_proc_mib_event(ah);
  689. spin_unlock(&common->cc_lock);
  690. ath9k_hw_enable_interrupts(ah);
  691. }
  692. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  693. if (status & ATH9K_INT_TIM_TIMER) {
  694. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  695. goto chip_reset;
  696. /* Clear RxAbort bit so that we can
  697. * receive frames */
  698. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  699. ath9k_hw_setrxabort(sc->sc_ah, 0);
  700. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  701. }
  702. chip_reset:
  703. ath_debug_stat_interrupt(sc, status);
  704. if (sched) {
  705. /* turn off every interrupt */
  706. ath9k_hw_disable_interrupts(ah);
  707. tasklet_schedule(&sc->intr_tq);
  708. }
  709. return IRQ_HANDLED;
  710. #undef SCHED_INTR
  711. }
  712. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  713. {
  714. int r;
  715. ath9k_ps_wakeup(sc);
  716. r = ath_reset_internal(sc, NULL, retry_tx);
  717. if (retry_tx) {
  718. int i;
  719. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  720. if (ATH_TXQ_SETUP(sc, i)) {
  721. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  722. ath_txq_schedule(sc, &sc->tx.txq[i]);
  723. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  724. }
  725. }
  726. }
  727. ath9k_ps_restore(sc);
  728. return r;
  729. }
  730. void ath_reset_work(struct work_struct *work)
  731. {
  732. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  733. ath_reset(sc, true);
  734. }
  735. void ath_hw_check(struct work_struct *work)
  736. {
  737. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  738. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  739. unsigned long flags;
  740. int busy;
  741. u8 is_alive, nbeacon = 1;
  742. ath9k_ps_wakeup(sc);
  743. is_alive = ath9k_hw_check_alive(sc->sc_ah);
  744. if (is_alive && !AR_SREV_9300(sc->sc_ah))
  745. goto out;
  746. else if (!is_alive && AR_SREV_9300(sc->sc_ah)) {
  747. ath_dbg(common, RESET,
  748. "DCU stuck is detected. Schedule chip reset\n");
  749. RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG);
  750. goto sched_reset;
  751. }
  752. spin_lock_irqsave(&common->cc_lock, flags);
  753. busy = ath_update_survey_stats(sc);
  754. spin_unlock_irqrestore(&common->cc_lock, flags);
  755. ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
  756. busy, sc->hw_busy_count + 1);
  757. if (busy >= 99) {
  758. if (++sc->hw_busy_count >= 3) {
  759. RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
  760. goto sched_reset;
  761. }
  762. } else if (busy >= 0) {
  763. sc->hw_busy_count = 0;
  764. nbeacon = 3;
  765. }
  766. ath_start_rx_poll(sc, nbeacon);
  767. goto out;
  768. sched_reset:
  769. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  770. out:
  771. ath9k_ps_restore(sc);
  772. }
  773. static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
  774. {
  775. static int count;
  776. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  777. if (pll_sqsum >= 0x40000) {
  778. count++;
  779. if (count == 3) {
  780. /* Rx is hung for more than 500ms. Reset it */
  781. ath_dbg(common, RESET, "Possible RX hang, resetting\n");
  782. RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
  783. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  784. count = 0;
  785. }
  786. } else
  787. count = 0;
  788. }
  789. void ath_hw_pll_work(struct work_struct *work)
  790. {
  791. struct ath_softc *sc = container_of(work, struct ath_softc,
  792. hw_pll_work.work);
  793. u32 pll_sqsum;
  794. if (AR_SREV_9485(sc->sc_ah)) {
  795. ath9k_ps_wakeup(sc);
  796. pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
  797. ath9k_ps_restore(sc);
  798. ath_hw_pll_rx_hang_check(sc, pll_sqsum);
  799. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
  800. }
  801. }
  802. /**********************/
  803. /* mac80211 callbacks */
  804. /**********************/
  805. static int ath9k_start(struct ieee80211_hw *hw)
  806. {
  807. struct ath_softc *sc = hw->priv;
  808. struct ath_hw *ah = sc->sc_ah;
  809. struct ath_common *common = ath9k_hw_common(ah);
  810. struct ieee80211_channel *curchan = hw->conf.channel;
  811. struct ath9k_channel *init_channel;
  812. int r;
  813. ath_dbg(common, CONFIG,
  814. "Starting driver with initial channel: %d MHz\n",
  815. curchan->center_freq);
  816. ath9k_ps_wakeup(sc);
  817. mutex_lock(&sc->mutex);
  818. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  819. /* Reset SERDES registers */
  820. ath9k_hw_configpcipowersave(ah, false);
  821. /*
  822. * The basic interface to setting the hardware in a good
  823. * state is ``reset''. On return the hardware is known to
  824. * be powered up and with interrupts disabled. This must
  825. * be followed by initialization of the appropriate bits
  826. * and then setup of the interrupt mask.
  827. */
  828. spin_lock_bh(&sc->sc_pcu_lock);
  829. atomic_set(&ah->intr_ref_cnt, -1);
  830. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  831. if (r) {
  832. ath_err(common,
  833. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  834. r, curchan->center_freq);
  835. spin_unlock_bh(&sc->sc_pcu_lock);
  836. goto mutex_unlock;
  837. }
  838. /* Setup our intr mask. */
  839. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  840. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  841. ATH9K_INT_GLOBAL;
  842. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  843. ah->imask |= ATH9K_INT_RXHP |
  844. ATH9K_INT_RXLP |
  845. ATH9K_INT_BB_WATCHDOG;
  846. else
  847. ah->imask |= ATH9K_INT_RX;
  848. ah->imask |= ATH9K_INT_GTT;
  849. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  850. ah->imask |= ATH9K_INT_CST;
  851. if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
  852. ah->imask |= ATH9K_INT_MCI;
  853. sc->sc_flags &= ~SC_OP_INVALID;
  854. sc->sc_ah->is_monitoring = false;
  855. if (!ath_complete_reset(sc, false)) {
  856. r = -EIO;
  857. spin_unlock_bh(&sc->sc_pcu_lock);
  858. goto mutex_unlock;
  859. }
  860. if (ah->led_pin >= 0) {
  861. ath9k_hw_cfg_output(ah, ah->led_pin,
  862. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  863. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  864. }
  865. /*
  866. * Reset key cache to sane defaults (all entries cleared) instead of
  867. * semi-random values after suspend/resume.
  868. */
  869. ath9k_cmn_init_crypto(sc->sc_ah);
  870. spin_unlock_bh(&sc->sc_pcu_lock);
  871. ath9k_start_btcoex(sc);
  872. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  873. common->bus_ops->extn_synch_en(common);
  874. mutex_unlock:
  875. mutex_unlock(&sc->mutex);
  876. ath9k_ps_restore(sc);
  877. return r;
  878. }
  879. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  880. {
  881. struct ath_softc *sc = hw->priv;
  882. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  883. struct ath_tx_control txctl;
  884. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  885. if (sc->ps_enabled) {
  886. /*
  887. * mac80211 does not set PM field for normal data frames, so we
  888. * need to update that based on the current PS mode.
  889. */
  890. if (ieee80211_is_data(hdr->frame_control) &&
  891. !ieee80211_is_nullfunc(hdr->frame_control) &&
  892. !ieee80211_has_pm(hdr->frame_control)) {
  893. ath_dbg(common, PS,
  894. "Add PM=1 for a TX frame while in PS mode\n");
  895. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  896. }
  897. }
  898. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  899. /*
  900. * We are using PS-Poll and mac80211 can request TX while in
  901. * power save mode. Need to wake up hardware for the TX to be
  902. * completed and if needed, also for RX of buffered frames.
  903. */
  904. ath9k_ps_wakeup(sc);
  905. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  906. ath9k_hw_setrxabort(sc->sc_ah, 0);
  907. if (ieee80211_is_pspoll(hdr->frame_control)) {
  908. ath_dbg(common, PS,
  909. "Sending PS-Poll to pick a buffered frame\n");
  910. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  911. } else {
  912. ath_dbg(common, PS, "Wake up to complete TX\n");
  913. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  914. }
  915. /*
  916. * The actual restore operation will happen only after
  917. * the ps_flags bit is cleared. We are just dropping
  918. * the ps_usecount here.
  919. */
  920. ath9k_ps_restore(sc);
  921. }
  922. /*
  923. * Cannot tx while the hardware is in full sleep, it first needs a full
  924. * chip reset to recover from that
  925. */
  926. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  927. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  928. goto exit;
  929. }
  930. memset(&txctl, 0, sizeof(struct ath_tx_control));
  931. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  932. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  933. if (ath_tx_start(hw, skb, &txctl) != 0) {
  934. ath_dbg(common, XMIT, "TX failed\n");
  935. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  936. goto exit;
  937. }
  938. return;
  939. exit:
  940. dev_kfree_skb_any(skb);
  941. }
  942. static void ath9k_stop(struct ieee80211_hw *hw)
  943. {
  944. struct ath_softc *sc = hw->priv;
  945. struct ath_hw *ah = sc->sc_ah;
  946. struct ath_common *common = ath9k_hw_common(ah);
  947. bool prev_idle;
  948. mutex_lock(&sc->mutex);
  949. ath_cancel_work(sc);
  950. del_timer_sync(&sc->rx_poll_timer);
  951. if (sc->sc_flags & SC_OP_INVALID) {
  952. ath_dbg(common, ANY, "Device not present\n");
  953. mutex_unlock(&sc->mutex);
  954. return;
  955. }
  956. /* Ensure HW is awake when we try to shut it down. */
  957. ath9k_ps_wakeup(sc);
  958. ath9k_stop_btcoex(sc);
  959. spin_lock_bh(&sc->sc_pcu_lock);
  960. /* prevent tasklets to enable interrupts once we disable them */
  961. ah->imask &= ~ATH9K_INT_GLOBAL;
  962. /* make sure h/w will not generate any interrupt
  963. * before setting the invalid flag. */
  964. ath9k_hw_disable_interrupts(ah);
  965. spin_unlock_bh(&sc->sc_pcu_lock);
  966. /* we can now sync irq and kill any running tasklets, since we already
  967. * disabled interrupts and not holding a spin lock */
  968. synchronize_irq(sc->irq);
  969. tasklet_kill(&sc->intr_tq);
  970. tasklet_kill(&sc->bcon_tasklet);
  971. prev_idle = sc->ps_idle;
  972. sc->ps_idle = true;
  973. spin_lock_bh(&sc->sc_pcu_lock);
  974. if (ah->led_pin >= 0) {
  975. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  976. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  977. }
  978. ath_prepare_reset(sc, false, true);
  979. if (sc->rx.frag) {
  980. dev_kfree_skb_any(sc->rx.frag);
  981. sc->rx.frag = NULL;
  982. }
  983. if (!ah->curchan)
  984. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  985. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  986. ath9k_hw_phy_disable(ah);
  987. ath9k_hw_configpcipowersave(ah, true);
  988. spin_unlock_bh(&sc->sc_pcu_lock);
  989. ath9k_ps_restore(sc);
  990. sc->sc_flags |= SC_OP_INVALID;
  991. sc->ps_idle = prev_idle;
  992. mutex_unlock(&sc->mutex);
  993. ath_dbg(common, CONFIG, "Driver halt\n");
  994. }
  995. bool ath9k_uses_beacons(int type)
  996. {
  997. switch (type) {
  998. case NL80211_IFTYPE_AP:
  999. case NL80211_IFTYPE_ADHOC:
  1000. case NL80211_IFTYPE_MESH_POINT:
  1001. return true;
  1002. default:
  1003. return false;
  1004. }
  1005. }
  1006. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  1007. struct ieee80211_vif *vif)
  1008. {
  1009. struct ath_vif *avp = (void *)vif->drv_priv;
  1010. ath9k_set_beaconing_status(sc, false);
  1011. ath_beacon_return(sc, avp);
  1012. ath9k_set_beaconing_status(sc, true);
  1013. }
  1014. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1015. {
  1016. struct ath9k_vif_iter_data *iter_data = data;
  1017. int i;
  1018. if (iter_data->hw_macaddr)
  1019. for (i = 0; i < ETH_ALEN; i++)
  1020. iter_data->mask[i] &=
  1021. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  1022. switch (vif->type) {
  1023. case NL80211_IFTYPE_AP:
  1024. iter_data->naps++;
  1025. break;
  1026. case NL80211_IFTYPE_STATION:
  1027. iter_data->nstations++;
  1028. break;
  1029. case NL80211_IFTYPE_ADHOC:
  1030. iter_data->nadhocs++;
  1031. break;
  1032. case NL80211_IFTYPE_MESH_POINT:
  1033. iter_data->nmeshes++;
  1034. break;
  1035. case NL80211_IFTYPE_WDS:
  1036. iter_data->nwds++;
  1037. break;
  1038. default:
  1039. break;
  1040. }
  1041. }
  1042. /* Called with sc->mutex held. */
  1043. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  1044. struct ieee80211_vif *vif,
  1045. struct ath9k_vif_iter_data *iter_data)
  1046. {
  1047. struct ath_softc *sc = hw->priv;
  1048. struct ath_hw *ah = sc->sc_ah;
  1049. struct ath_common *common = ath9k_hw_common(ah);
  1050. /*
  1051. * Use the hardware MAC address as reference, the hardware uses it
  1052. * together with the BSSID mask when matching addresses.
  1053. */
  1054. memset(iter_data, 0, sizeof(*iter_data));
  1055. iter_data->hw_macaddr = common->macaddr;
  1056. memset(&iter_data->mask, 0xff, ETH_ALEN);
  1057. if (vif)
  1058. ath9k_vif_iter(iter_data, vif->addr, vif);
  1059. /* Get list of all active MAC addresses */
  1060. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  1061. iter_data);
  1062. }
  1063. /* Called with sc->mutex held. */
  1064. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  1065. struct ieee80211_vif *vif)
  1066. {
  1067. struct ath_softc *sc = hw->priv;
  1068. struct ath_hw *ah = sc->sc_ah;
  1069. struct ath_common *common = ath9k_hw_common(ah);
  1070. struct ath9k_vif_iter_data iter_data;
  1071. ath9k_calculate_iter_data(hw, vif, &iter_data);
  1072. /* Set BSSID mask. */
  1073. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  1074. ath_hw_setbssidmask(common);
  1075. /* Set op-mode & TSF */
  1076. if (iter_data.naps > 0) {
  1077. ath9k_hw_set_tsfadjust(ah, 1);
  1078. sc->sc_flags |= SC_OP_TSF_RESET;
  1079. ah->opmode = NL80211_IFTYPE_AP;
  1080. } else {
  1081. ath9k_hw_set_tsfadjust(ah, 0);
  1082. sc->sc_flags &= ~SC_OP_TSF_RESET;
  1083. if (iter_data.nmeshes)
  1084. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  1085. else if (iter_data.nwds)
  1086. ah->opmode = NL80211_IFTYPE_AP;
  1087. else if (iter_data.nadhocs)
  1088. ah->opmode = NL80211_IFTYPE_ADHOC;
  1089. else
  1090. ah->opmode = NL80211_IFTYPE_STATION;
  1091. }
  1092. /*
  1093. * Enable MIB interrupts when there are hardware phy counters.
  1094. */
  1095. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  1096. if (ah->config.enable_ani)
  1097. ah->imask |= ATH9K_INT_MIB;
  1098. ah->imask |= ATH9K_INT_TSFOOR;
  1099. } else {
  1100. ah->imask &= ~ATH9K_INT_MIB;
  1101. ah->imask &= ~ATH9K_INT_TSFOOR;
  1102. }
  1103. ath9k_hw_set_interrupts(ah);
  1104. /* Set up ANI */
  1105. if (iter_data.naps > 0) {
  1106. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1107. if (!common->disable_ani) {
  1108. sc->sc_flags |= SC_OP_ANI_RUN;
  1109. ath_start_ani(common);
  1110. }
  1111. } else {
  1112. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1113. del_timer_sync(&common->ani.timer);
  1114. }
  1115. }
  1116. /* Called with sc->mutex held, vif counts set up properly. */
  1117. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  1118. struct ieee80211_vif *vif)
  1119. {
  1120. struct ath_softc *sc = hw->priv;
  1121. ath9k_calculate_summary_state(hw, vif);
  1122. if (ath9k_uses_beacons(vif->type)) {
  1123. /* Reserve a beacon slot for the vif */
  1124. ath9k_set_beaconing_status(sc, false);
  1125. ath_beacon_alloc(sc, vif);
  1126. ath9k_set_beaconing_status(sc, true);
  1127. }
  1128. }
  1129. void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon)
  1130. {
  1131. if (!AR_SREV_9300(sc->sc_ah))
  1132. return;
  1133. if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF))
  1134. return;
  1135. mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies
  1136. (nbeacon * sc->cur_beacon_conf.beacon_interval));
  1137. }
  1138. void ath_rx_poll(unsigned long data)
  1139. {
  1140. struct ath_softc *sc = (struct ath_softc *)data;
  1141. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  1142. }
  1143. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1144. struct ieee80211_vif *vif)
  1145. {
  1146. struct ath_softc *sc = hw->priv;
  1147. struct ath_hw *ah = sc->sc_ah;
  1148. struct ath_common *common = ath9k_hw_common(ah);
  1149. int ret = 0;
  1150. ath9k_ps_wakeup(sc);
  1151. mutex_lock(&sc->mutex);
  1152. switch (vif->type) {
  1153. case NL80211_IFTYPE_STATION:
  1154. case NL80211_IFTYPE_WDS:
  1155. case NL80211_IFTYPE_ADHOC:
  1156. case NL80211_IFTYPE_AP:
  1157. case NL80211_IFTYPE_MESH_POINT:
  1158. break;
  1159. default:
  1160. ath_err(common, "Interface type %d not yet supported\n",
  1161. vif->type);
  1162. ret = -EOPNOTSUPP;
  1163. goto out;
  1164. }
  1165. if (ath9k_uses_beacons(vif->type)) {
  1166. if (sc->nbcnvifs >= ATH_BCBUF) {
  1167. ath_err(common, "Not enough beacon buffers when adding"
  1168. " new interface of type: %i\n",
  1169. vif->type);
  1170. ret = -ENOBUFS;
  1171. goto out;
  1172. }
  1173. }
  1174. if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1175. ((vif->type == NL80211_IFTYPE_ADHOC) &&
  1176. sc->nvifs > 0)) {
  1177. ath_err(common, "Cannot create ADHOC interface when other"
  1178. " interfaces already exist.\n");
  1179. ret = -EINVAL;
  1180. goto out;
  1181. }
  1182. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  1183. sc->nvifs++;
  1184. ath9k_do_vif_add_setup(hw, vif);
  1185. out:
  1186. mutex_unlock(&sc->mutex);
  1187. ath9k_ps_restore(sc);
  1188. return ret;
  1189. }
  1190. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1191. struct ieee80211_vif *vif,
  1192. enum nl80211_iftype new_type,
  1193. bool p2p)
  1194. {
  1195. struct ath_softc *sc = hw->priv;
  1196. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1197. int ret = 0;
  1198. ath_dbg(common, CONFIG, "Change Interface\n");
  1199. mutex_lock(&sc->mutex);
  1200. ath9k_ps_wakeup(sc);
  1201. /* See if new interface type is valid. */
  1202. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  1203. (sc->nvifs > 1)) {
  1204. ath_err(common, "When using ADHOC, it must be the only"
  1205. " interface.\n");
  1206. ret = -EINVAL;
  1207. goto out;
  1208. }
  1209. if (ath9k_uses_beacons(new_type) &&
  1210. !ath9k_uses_beacons(vif->type)) {
  1211. if (sc->nbcnvifs >= ATH_BCBUF) {
  1212. ath_err(common, "No beacon slot available\n");
  1213. ret = -ENOBUFS;
  1214. goto out;
  1215. }
  1216. }
  1217. /* Clean up old vif stuff */
  1218. if (ath9k_uses_beacons(vif->type))
  1219. ath9k_reclaim_beacon(sc, vif);
  1220. /* Add new settings */
  1221. vif->type = new_type;
  1222. vif->p2p = p2p;
  1223. ath9k_do_vif_add_setup(hw, vif);
  1224. out:
  1225. ath9k_ps_restore(sc);
  1226. mutex_unlock(&sc->mutex);
  1227. return ret;
  1228. }
  1229. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1230. struct ieee80211_vif *vif)
  1231. {
  1232. struct ath_softc *sc = hw->priv;
  1233. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1234. ath_dbg(common, CONFIG, "Detach Interface\n");
  1235. ath9k_ps_wakeup(sc);
  1236. mutex_lock(&sc->mutex);
  1237. sc->nvifs--;
  1238. /* Reclaim beacon resources */
  1239. if (ath9k_uses_beacons(vif->type))
  1240. ath9k_reclaim_beacon(sc, vif);
  1241. ath9k_calculate_summary_state(hw, NULL);
  1242. mutex_unlock(&sc->mutex);
  1243. ath9k_ps_restore(sc);
  1244. }
  1245. static void ath9k_enable_ps(struct ath_softc *sc)
  1246. {
  1247. struct ath_hw *ah = sc->sc_ah;
  1248. struct ath_common *common = ath9k_hw_common(ah);
  1249. sc->ps_enabled = true;
  1250. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1251. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1252. ah->imask |= ATH9K_INT_TIM_TIMER;
  1253. ath9k_hw_set_interrupts(ah);
  1254. }
  1255. ath9k_hw_setrxabort(ah, 1);
  1256. }
  1257. ath_dbg(common, PS, "PowerSave enabled\n");
  1258. }
  1259. static void ath9k_disable_ps(struct ath_softc *sc)
  1260. {
  1261. struct ath_hw *ah = sc->sc_ah;
  1262. struct ath_common *common = ath9k_hw_common(ah);
  1263. sc->ps_enabled = false;
  1264. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1265. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1266. ath9k_hw_setrxabort(ah, 0);
  1267. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1268. PS_WAIT_FOR_CAB |
  1269. PS_WAIT_FOR_PSPOLL_DATA |
  1270. PS_WAIT_FOR_TX_ACK);
  1271. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1272. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1273. ath9k_hw_set_interrupts(ah);
  1274. }
  1275. }
  1276. ath_dbg(common, PS, "PowerSave disabled\n");
  1277. }
  1278. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1279. {
  1280. struct ath_softc *sc = hw->priv;
  1281. struct ath_hw *ah = sc->sc_ah;
  1282. struct ath_common *common = ath9k_hw_common(ah);
  1283. struct ieee80211_conf *conf = &hw->conf;
  1284. ath9k_ps_wakeup(sc);
  1285. mutex_lock(&sc->mutex);
  1286. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1287. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1288. if (sc->ps_idle)
  1289. ath_cancel_work(sc);
  1290. }
  1291. /*
  1292. * We just prepare to enable PS. We have to wait until our AP has
  1293. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1294. * those ACKs and end up retransmitting the same null data frames.
  1295. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1296. */
  1297. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1298. unsigned long flags;
  1299. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1300. if (conf->flags & IEEE80211_CONF_PS)
  1301. ath9k_enable_ps(sc);
  1302. else
  1303. ath9k_disable_ps(sc);
  1304. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1305. }
  1306. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1307. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1308. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  1309. sc->sc_ah->is_monitoring = true;
  1310. } else {
  1311. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  1312. sc->sc_ah->is_monitoring = false;
  1313. }
  1314. }
  1315. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1316. struct ieee80211_channel *curchan = hw->conf.channel;
  1317. int pos = curchan->hw_value;
  1318. int old_pos = -1;
  1319. unsigned long flags;
  1320. if (ah->curchan)
  1321. old_pos = ah->curchan - &ah->channels[0];
  1322. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1323. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1324. else
  1325. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1326. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  1327. curchan->center_freq, conf->channel_type);
  1328. /* update survey stats for the old channel before switching */
  1329. spin_lock_irqsave(&common->cc_lock, flags);
  1330. ath_update_survey_stats(sc);
  1331. spin_unlock_irqrestore(&common->cc_lock, flags);
  1332. /*
  1333. * Preserve the current channel values, before updating
  1334. * the same channel
  1335. */
  1336. if (ah->curchan && (old_pos == pos))
  1337. ath9k_hw_getnf(ah, ah->curchan);
  1338. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  1339. curchan, conf->channel_type);
  1340. /*
  1341. * If the operating channel changes, change the survey in-use flags
  1342. * along with it.
  1343. * Reset the survey data for the new channel, unless we're switching
  1344. * back to the operating channel from an off-channel operation.
  1345. */
  1346. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1347. sc->cur_survey != &sc->survey[pos]) {
  1348. if (sc->cur_survey)
  1349. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1350. sc->cur_survey = &sc->survey[pos];
  1351. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1352. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1353. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1354. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1355. }
  1356. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1357. ath_err(common, "Unable to set channel\n");
  1358. mutex_unlock(&sc->mutex);
  1359. return -EINVAL;
  1360. }
  1361. /*
  1362. * The most recent snapshot of channel->noisefloor for the old
  1363. * channel is only available after the hardware reset. Copy it to
  1364. * the survey stats now.
  1365. */
  1366. if (old_pos >= 0)
  1367. ath_update_survey_nf(sc, old_pos);
  1368. }
  1369. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1370. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1371. sc->config.txpowlimit = 2 * conf->power_level;
  1372. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1373. sc->config.txpowlimit, &sc->curtxpow);
  1374. }
  1375. mutex_unlock(&sc->mutex);
  1376. ath9k_ps_restore(sc);
  1377. return 0;
  1378. }
  1379. #define SUPPORTED_FILTERS \
  1380. (FIF_PROMISC_IN_BSS | \
  1381. FIF_ALLMULTI | \
  1382. FIF_CONTROL | \
  1383. FIF_PSPOLL | \
  1384. FIF_OTHER_BSS | \
  1385. FIF_BCN_PRBRESP_PROMISC | \
  1386. FIF_PROBE_REQ | \
  1387. FIF_FCSFAIL)
  1388. /* FIXME: sc->sc_full_reset ? */
  1389. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1390. unsigned int changed_flags,
  1391. unsigned int *total_flags,
  1392. u64 multicast)
  1393. {
  1394. struct ath_softc *sc = hw->priv;
  1395. u32 rfilt;
  1396. changed_flags &= SUPPORTED_FILTERS;
  1397. *total_flags &= SUPPORTED_FILTERS;
  1398. sc->rx.rxfilter = *total_flags;
  1399. ath9k_ps_wakeup(sc);
  1400. rfilt = ath_calcrxfilter(sc);
  1401. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1402. ath9k_ps_restore(sc);
  1403. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1404. rfilt);
  1405. }
  1406. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1407. struct ieee80211_vif *vif,
  1408. struct ieee80211_sta *sta)
  1409. {
  1410. struct ath_softc *sc = hw->priv;
  1411. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1412. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1413. struct ieee80211_key_conf ps_key = { };
  1414. ath_node_attach(sc, sta, vif);
  1415. if (vif->type != NL80211_IFTYPE_AP &&
  1416. vif->type != NL80211_IFTYPE_AP_VLAN)
  1417. return 0;
  1418. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1419. return 0;
  1420. }
  1421. static void ath9k_del_ps_key(struct ath_softc *sc,
  1422. struct ieee80211_vif *vif,
  1423. struct ieee80211_sta *sta)
  1424. {
  1425. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1426. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1427. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1428. if (!an->ps_key)
  1429. return;
  1430. ath_key_delete(common, &ps_key);
  1431. }
  1432. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1433. struct ieee80211_vif *vif,
  1434. struct ieee80211_sta *sta)
  1435. {
  1436. struct ath_softc *sc = hw->priv;
  1437. ath9k_del_ps_key(sc, vif, sta);
  1438. ath_node_detach(sc, sta);
  1439. return 0;
  1440. }
  1441. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1442. struct ieee80211_vif *vif,
  1443. enum sta_notify_cmd cmd,
  1444. struct ieee80211_sta *sta)
  1445. {
  1446. struct ath_softc *sc = hw->priv;
  1447. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1448. if (!sta->ht_cap.ht_supported)
  1449. return;
  1450. switch (cmd) {
  1451. case STA_NOTIFY_SLEEP:
  1452. an->sleeping = true;
  1453. ath_tx_aggr_sleep(sta, sc, an);
  1454. break;
  1455. case STA_NOTIFY_AWAKE:
  1456. an->sleeping = false;
  1457. ath_tx_aggr_wakeup(sc, an);
  1458. break;
  1459. }
  1460. }
  1461. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1462. struct ieee80211_vif *vif, u16 queue,
  1463. const struct ieee80211_tx_queue_params *params)
  1464. {
  1465. struct ath_softc *sc = hw->priv;
  1466. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1467. struct ath_txq *txq;
  1468. struct ath9k_tx_queue_info qi;
  1469. int ret = 0;
  1470. if (queue >= WME_NUM_AC)
  1471. return 0;
  1472. txq = sc->tx.txq_map[queue];
  1473. ath9k_ps_wakeup(sc);
  1474. mutex_lock(&sc->mutex);
  1475. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1476. qi.tqi_aifs = params->aifs;
  1477. qi.tqi_cwmin = params->cw_min;
  1478. qi.tqi_cwmax = params->cw_max;
  1479. qi.tqi_burstTime = params->txop;
  1480. ath_dbg(common, CONFIG,
  1481. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1482. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1483. params->cw_max, params->txop);
  1484. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1485. if (ret)
  1486. ath_err(common, "TXQ Update failed\n");
  1487. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1488. if (queue == WME_AC_BE && !ret)
  1489. ath_beaconq_config(sc);
  1490. mutex_unlock(&sc->mutex);
  1491. ath9k_ps_restore(sc);
  1492. return ret;
  1493. }
  1494. static int ath9k_set_key(struct ieee80211_hw *hw,
  1495. enum set_key_cmd cmd,
  1496. struct ieee80211_vif *vif,
  1497. struct ieee80211_sta *sta,
  1498. struct ieee80211_key_conf *key)
  1499. {
  1500. struct ath_softc *sc = hw->priv;
  1501. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1502. int ret = 0;
  1503. if (ath9k_modparam_nohwcrypt)
  1504. return -ENOSPC;
  1505. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1506. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1507. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1508. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1509. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1510. /*
  1511. * For now, disable hw crypto for the RSN IBSS group keys. This
  1512. * could be optimized in the future to use a modified key cache
  1513. * design to support per-STA RX GTK, but until that gets
  1514. * implemented, use of software crypto for group addressed
  1515. * frames is a acceptable to allow RSN IBSS to be used.
  1516. */
  1517. return -EOPNOTSUPP;
  1518. }
  1519. mutex_lock(&sc->mutex);
  1520. ath9k_ps_wakeup(sc);
  1521. ath_dbg(common, CONFIG, "Set HW Key\n");
  1522. switch (cmd) {
  1523. case SET_KEY:
  1524. if (sta)
  1525. ath9k_del_ps_key(sc, vif, sta);
  1526. ret = ath_key_config(common, vif, sta, key);
  1527. if (ret >= 0) {
  1528. key->hw_key_idx = ret;
  1529. /* push IV and Michael MIC generation to stack */
  1530. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1531. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1532. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1533. if (sc->sc_ah->sw_mgmt_crypto &&
  1534. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1535. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1536. ret = 0;
  1537. }
  1538. break;
  1539. case DISABLE_KEY:
  1540. ath_key_delete(common, key);
  1541. break;
  1542. default:
  1543. ret = -EINVAL;
  1544. }
  1545. ath9k_ps_restore(sc);
  1546. mutex_unlock(&sc->mutex);
  1547. return ret;
  1548. }
  1549. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1550. {
  1551. struct ath_softc *sc = data;
  1552. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1553. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1554. struct ath_vif *avp = (void *)vif->drv_priv;
  1555. /*
  1556. * Skip iteration if primary station vif's bss info
  1557. * was not changed
  1558. */
  1559. if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
  1560. return;
  1561. if (bss_conf->assoc) {
  1562. sc->sc_flags |= SC_OP_PRIM_STA_VIF;
  1563. avp->primary_sta_vif = true;
  1564. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1565. common->curaid = bss_conf->aid;
  1566. ath9k_hw_write_associd(sc->sc_ah);
  1567. ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
  1568. bss_conf->aid, common->curbssid);
  1569. ath_beacon_config(sc, vif);
  1570. /*
  1571. * Request a re-configuration of Beacon related timers
  1572. * on the receipt of the first Beacon frame (i.e.,
  1573. * after time sync with the AP).
  1574. */
  1575. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1576. /* Reset rssi stats */
  1577. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1578. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1579. ath_start_rx_poll(sc, 3);
  1580. if (!common->disable_ani) {
  1581. sc->sc_flags |= SC_OP_ANI_RUN;
  1582. ath_start_ani(common);
  1583. }
  1584. }
  1585. }
  1586. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1587. {
  1588. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1589. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1590. struct ath_vif *avp = (void *)vif->drv_priv;
  1591. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1592. return;
  1593. /* Reconfigure bss info */
  1594. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1595. ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
  1596. common->curaid, common->curbssid);
  1597. sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
  1598. avp->primary_sta_vif = false;
  1599. memset(common->curbssid, 0, ETH_ALEN);
  1600. common->curaid = 0;
  1601. }
  1602. ieee80211_iterate_active_interfaces_atomic(
  1603. sc->hw, ath9k_bss_iter, sc);
  1604. /*
  1605. * None of station vifs are associated.
  1606. * Clear bssid & aid
  1607. */
  1608. if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
  1609. ath9k_hw_write_associd(sc->sc_ah);
  1610. /* Stop ANI */
  1611. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1612. del_timer_sync(&common->ani.timer);
  1613. del_timer_sync(&sc->rx_poll_timer);
  1614. memset(&sc->caldata, 0, sizeof(sc->caldata));
  1615. }
  1616. }
  1617. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1618. struct ieee80211_vif *vif,
  1619. struct ieee80211_bss_conf *bss_conf,
  1620. u32 changed)
  1621. {
  1622. struct ath_softc *sc = hw->priv;
  1623. struct ath_hw *ah = sc->sc_ah;
  1624. struct ath_common *common = ath9k_hw_common(ah);
  1625. struct ath_vif *avp = (void *)vif->drv_priv;
  1626. int slottime;
  1627. ath9k_ps_wakeup(sc);
  1628. mutex_lock(&sc->mutex);
  1629. if (changed & BSS_CHANGED_ASSOC) {
  1630. ath9k_config_bss(sc, vif);
  1631. ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
  1632. common->curbssid, common->curaid);
  1633. }
  1634. if (changed & BSS_CHANGED_IBSS) {
  1635. /* There can be only one vif available */
  1636. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1637. common->curaid = bss_conf->aid;
  1638. ath9k_hw_write_associd(sc->sc_ah);
  1639. if (bss_conf->ibss_joined) {
  1640. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1641. if (!common->disable_ani) {
  1642. sc->sc_flags |= SC_OP_ANI_RUN;
  1643. ath_start_ani(common);
  1644. }
  1645. } else {
  1646. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1647. del_timer_sync(&common->ani.timer);
  1648. del_timer_sync(&sc->rx_poll_timer);
  1649. }
  1650. }
  1651. /*
  1652. * In case of AP mode, the HW TSF has to be reset
  1653. * when the beacon interval changes.
  1654. */
  1655. if ((changed & BSS_CHANGED_BEACON_INT) &&
  1656. (vif->type == NL80211_IFTYPE_AP))
  1657. sc->sc_flags |= SC_OP_TSF_RESET;
  1658. /* Configure beaconing (AP, IBSS, MESH) */
  1659. if (ath9k_uses_beacons(vif->type) &&
  1660. ((changed & BSS_CHANGED_BEACON) ||
  1661. (changed & BSS_CHANGED_BEACON_ENABLED) ||
  1662. (changed & BSS_CHANGED_BEACON_INT))) {
  1663. ath9k_set_beaconing_status(sc, false);
  1664. if (bss_conf->enable_beacon)
  1665. ath_beacon_alloc(sc, vif);
  1666. else
  1667. avp->is_bslot_active = false;
  1668. ath_beacon_config(sc, vif);
  1669. ath9k_set_beaconing_status(sc, true);
  1670. }
  1671. if (changed & BSS_CHANGED_ERP_SLOT) {
  1672. if (bss_conf->use_short_slot)
  1673. slottime = 9;
  1674. else
  1675. slottime = 20;
  1676. if (vif->type == NL80211_IFTYPE_AP) {
  1677. /*
  1678. * Defer update, so that connected stations can adjust
  1679. * their settings at the same time.
  1680. * See beacon.c for more details
  1681. */
  1682. sc->beacon.slottime = slottime;
  1683. sc->beacon.updateslot = UPDATE;
  1684. } else {
  1685. ah->slottime = slottime;
  1686. ath9k_hw_init_global_settings(ah);
  1687. }
  1688. }
  1689. mutex_unlock(&sc->mutex);
  1690. ath9k_ps_restore(sc);
  1691. }
  1692. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1693. {
  1694. struct ath_softc *sc = hw->priv;
  1695. u64 tsf;
  1696. mutex_lock(&sc->mutex);
  1697. ath9k_ps_wakeup(sc);
  1698. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1699. ath9k_ps_restore(sc);
  1700. mutex_unlock(&sc->mutex);
  1701. return tsf;
  1702. }
  1703. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1704. struct ieee80211_vif *vif,
  1705. u64 tsf)
  1706. {
  1707. struct ath_softc *sc = hw->priv;
  1708. mutex_lock(&sc->mutex);
  1709. ath9k_ps_wakeup(sc);
  1710. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1711. ath9k_ps_restore(sc);
  1712. mutex_unlock(&sc->mutex);
  1713. }
  1714. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1715. {
  1716. struct ath_softc *sc = hw->priv;
  1717. mutex_lock(&sc->mutex);
  1718. ath9k_ps_wakeup(sc);
  1719. ath9k_hw_reset_tsf(sc->sc_ah);
  1720. ath9k_ps_restore(sc);
  1721. mutex_unlock(&sc->mutex);
  1722. }
  1723. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1724. struct ieee80211_vif *vif,
  1725. enum ieee80211_ampdu_mlme_action action,
  1726. struct ieee80211_sta *sta,
  1727. u16 tid, u16 *ssn, u8 buf_size)
  1728. {
  1729. struct ath_softc *sc = hw->priv;
  1730. int ret = 0;
  1731. local_bh_disable();
  1732. switch (action) {
  1733. case IEEE80211_AMPDU_RX_START:
  1734. break;
  1735. case IEEE80211_AMPDU_RX_STOP:
  1736. break;
  1737. case IEEE80211_AMPDU_TX_START:
  1738. ath9k_ps_wakeup(sc);
  1739. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1740. if (!ret)
  1741. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1742. ath9k_ps_restore(sc);
  1743. break;
  1744. case IEEE80211_AMPDU_TX_STOP:
  1745. ath9k_ps_wakeup(sc);
  1746. ath_tx_aggr_stop(sc, sta, tid);
  1747. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1748. ath9k_ps_restore(sc);
  1749. break;
  1750. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1751. ath9k_ps_wakeup(sc);
  1752. ath_tx_aggr_resume(sc, sta, tid);
  1753. ath9k_ps_restore(sc);
  1754. break;
  1755. default:
  1756. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1757. }
  1758. local_bh_enable();
  1759. return ret;
  1760. }
  1761. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1762. struct survey_info *survey)
  1763. {
  1764. struct ath_softc *sc = hw->priv;
  1765. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1766. struct ieee80211_supported_band *sband;
  1767. struct ieee80211_channel *chan;
  1768. unsigned long flags;
  1769. int pos;
  1770. spin_lock_irqsave(&common->cc_lock, flags);
  1771. if (idx == 0)
  1772. ath_update_survey_stats(sc);
  1773. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1774. if (sband && idx >= sband->n_channels) {
  1775. idx -= sband->n_channels;
  1776. sband = NULL;
  1777. }
  1778. if (!sband)
  1779. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1780. if (!sband || idx >= sband->n_channels) {
  1781. spin_unlock_irqrestore(&common->cc_lock, flags);
  1782. return -ENOENT;
  1783. }
  1784. chan = &sband->channels[idx];
  1785. pos = chan->hw_value;
  1786. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1787. survey->channel = chan;
  1788. spin_unlock_irqrestore(&common->cc_lock, flags);
  1789. return 0;
  1790. }
  1791. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1792. {
  1793. struct ath_softc *sc = hw->priv;
  1794. struct ath_hw *ah = sc->sc_ah;
  1795. mutex_lock(&sc->mutex);
  1796. ah->coverage_class = coverage_class;
  1797. ath9k_ps_wakeup(sc);
  1798. ath9k_hw_init_global_settings(ah);
  1799. ath9k_ps_restore(sc);
  1800. mutex_unlock(&sc->mutex);
  1801. }
  1802. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1803. {
  1804. struct ath_softc *sc = hw->priv;
  1805. struct ath_hw *ah = sc->sc_ah;
  1806. struct ath_common *common = ath9k_hw_common(ah);
  1807. int timeout = 200; /* ms */
  1808. int i, j;
  1809. bool drain_txq;
  1810. mutex_lock(&sc->mutex);
  1811. cancel_delayed_work_sync(&sc->tx_complete_work);
  1812. if (ah->ah_flags & AH_UNPLUGGED) {
  1813. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1814. mutex_unlock(&sc->mutex);
  1815. return;
  1816. }
  1817. if (sc->sc_flags & SC_OP_INVALID) {
  1818. ath_dbg(common, ANY, "Device not present\n");
  1819. mutex_unlock(&sc->mutex);
  1820. return;
  1821. }
  1822. for (j = 0; j < timeout; j++) {
  1823. bool npend = false;
  1824. if (j)
  1825. usleep_range(1000, 2000);
  1826. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1827. if (!ATH_TXQ_SETUP(sc, i))
  1828. continue;
  1829. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1830. if (npend)
  1831. break;
  1832. }
  1833. if (!npend)
  1834. break;
  1835. }
  1836. if (drop) {
  1837. ath9k_ps_wakeup(sc);
  1838. spin_lock_bh(&sc->sc_pcu_lock);
  1839. drain_txq = ath_drain_all_txq(sc, false);
  1840. spin_unlock_bh(&sc->sc_pcu_lock);
  1841. if (!drain_txq)
  1842. ath_reset(sc, false);
  1843. ath9k_ps_restore(sc);
  1844. ieee80211_wake_queues(hw);
  1845. }
  1846. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1847. mutex_unlock(&sc->mutex);
  1848. }
  1849. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1850. {
  1851. struct ath_softc *sc = hw->priv;
  1852. int i;
  1853. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1854. if (!ATH_TXQ_SETUP(sc, i))
  1855. continue;
  1856. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1857. return true;
  1858. }
  1859. return false;
  1860. }
  1861. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1862. {
  1863. struct ath_softc *sc = hw->priv;
  1864. struct ath_hw *ah = sc->sc_ah;
  1865. struct ieee80211_vif *vif;
  1866. struct ath_vif *avp;
  1867. struct ath_buf *bf;
  1868. struct ath_tx_status ts;
  1869. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1870. int status;
  1871. vif = sc->beacon.bslot[0];
  1872. if (!vif)
  1873. return 0;
  1874. avp = (void *)vif->drv_priv;
  1875. if (!avp->is_bslot_active)
  1876. return 0;
  1877. if (!sc->beacon.tx_processed && !edma) {
  1878. tasklet_disable(&sc->bcon_tasklet);
  1879. bf = avp->av_bcbuf;
  1880. if (!bf || !bf->bf_mpdu)
  1881. goto skip;
  1882. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1883. if (status == -EINPROGRESS)
  1884. goto skip;
  1885. sc->beacon.tx_processed = true;
  1886. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1887. skip:
  1888. tasklet_enable(&sc->bcon_tasklet);
  1889. }
  1890. return sc->beacon.tx_last;
  1891. }
  1892. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1893. struct ieee80211_low_level_stats *stats)
  1894. {
  1895. struct ath_softc *sc = hw->priv;
  1896. struct ath_hw *ah = sc->sc_ah;
  1897. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1898. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1899. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1900. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1901. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1902. return 0;
  1903. }
  1904. static u32 fill_chainmask(u32 cap, u32 new)
  1905. {
  1906. u32 filled = 0;
  1907. int i;
  1908. for (i = 0; cap && new; i++, cap >>= 1) {
  1909. if (!(cap & BIT(0)))
  1910. continue;
  1911. if (new & BIT(0))
  1912. filled |= BIT(i);
  1913. new >>= 1;
  1914. }
  1915. return filled;
  1916. }
  1917. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1918. {
  1919. struct ath_softc *sc = hw->priv;
  1920. struct ath_hw *ah = sc->sc_ah;
  1921. if (!rx_ant || !tx_ant)
  1922. return -EINVAL;
  1923. sc->ant_rx = rx_ant;
  1924. sc->ant_tx = tx_ant;
  1925. if (ah->caps.rx_chainmask == 1)
  1926. return 0;
  1927. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1928. if (AR_SREV_9100(ah))
  1929. ah->rxchainmask = 0x7;
  1930. else
  1931. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1932. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1933. ath9k_reload_chainmask_settings(sc);
  1934. return 0;
  1935. }
  1936. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1937. {
  1938. struct ath_softc *sc = hw->priv;
  1939. *tx_ant = sc->ant_tx;
  1940. *rx_ant = sc->ant_rx;
  1941. return 0;
  1942. }
  1943. struct ieee80211_ops ath9k_ops = {
  1944. .tx = ath9k_tx,
  1945. .start = ath9k_start,
  1946. .stop = ath9k_stop,
  1947. .add_interface = ath9k_add_interface,
  1948. .change_interface = ath9k_change_interface,
  1949. .remove_interface = ath9k_remove_interface,
  1950. .config = ath9k_config,
  1951. .configure_filter = ath9k_configure_filter,
  1952. .sta_add = ath9k_sta_add,
  1953. .sta_remove = ath9k_sta_remove,
  1954. .sta_notify = ath9k_sta_notify,
  1955. .conf_tx = ath9k_conf_tx,
  1956. .bss_info_changed = ath9k_bss_info_changed,
  1957. .set_key = ath9k_set_key,
  1958. .get_tsf = ath9k_get_tsf,
  1959. .set_tsf = ath9k_set_tsf,
  1960. .reset_tsf = ath9k_reset_tsf,
  1961. .ampdu_action = ath9k_ampdu_action,
  1962. .get_survey = ath9k_get_survey,
  1963. .rfkill_poll = ath9k_rfkill_poll_state,
  1964. .set_coverage_class = ath9k_set_coverage_class,
  1965. .flush = ath9k_flush,
  1966. .tx_frames_pending = ath9k_tx_frames_pending,
  1967. .tx_last_beacon = ath9k_tx_last_beacon,
  1968. .get_stats = ath9k_get_stats,
  1969. .set_antenna = ath9k_set_antenna,
  1970. .get_antenna = ath9k_get_antenna,
  1971. };