wm8903.c 50 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813
  1. /*
  2. * wm8903.c -- WM8903 ALSA SoC Audio driver
  3. *
  4. * Copyright 2008 Wolfson Microelectronics
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * TODO:
  13. * - TDM mode configuration.
  14. * - Mic detect.
  15. * - Digital microphone support.
  16. * - Interrupt support (mic detect and sequencer).
  17. */
  18. #include <linux/module.h>
  19. #include <linux/moduleparam.h>
  20. #include <linux/init.h>
  21. #include <linux/delay.h>
  22. #include <linux/pm.h>
  23. #include <linux/i2c.h>
  24. #include <linux/platform_device.h>
  25. #include <sound/core.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/tlv.h>
  29. #include <sound/soc.h>
  30. #include <sound/soc-dapm.h>
  31. #include <sound/initval.h>
  32. #include "wm8903.h"
  33. struct wm8903_priv {
  34. int sysclk;
  35. /* Reference counts */
  36. int charge_pump_users;
  37. int class_w_users;
  38. int playback_active;
  39. int capture_active;
  40. struct snd_pcm_substream *master_substream;
  41. struct snd_pcm_substream *slave_substream;
  42. };
  43. /* Register defaults at reset */
  44. static u16 wm8903_reg_defaults[] = {
  45. 0x8903, /* R0 - SW Reset and ID */
  46. 0x0000, /* R1 - Revision Number */
  47. 0x0000, /* R2 */
  48. 0x0000, /* R3 */
  49. 0x0018, /* R4 - Bias Control 0 */
  50. 0x0000, /* R5 - VMID Control 0 */
  51. 0x0000, /* R6 - Mic Bias Control 0 */
  52. 0x0000, /* R7 */
  53. 0x0001, /* R8 - Analogue DAC 0 */
  54. 0x0000, /* R9 */
  55. 0x0001, /* R10 - Analogue ADC 0 */
  56. 0x0000, /* R11 */
  57. 0x0000, /* R12 - Power Management 0 */
  58. 0x0000, /* R13 - Power Management 1 */
  59. 0x0000, /* R14 - Power Management 2 */
  60. 0x0000, /* R15 - Power Management 3 */
  61. 0x0000, /* R16 - Power Management 4 */
  62. 0x0000, /* R17 - Power Management 5 */
  63. 0x0000, /* R18 - Power Management 6 */
  64. 0x0000, /* R19 */
  65. 0x0400, /* R20 - Clock Rates 0 */
  66. 0x0D07, /* R21 - Clock Rates 1 */
  67. 0x0000, /* R22 - Clock Rates 2 */
  68. 0x0000, /* R23 */
  69. 0x0050, /* R24 - Audio Interface 0 */
  70. 0x0242, /* R25 - Audio Interface 1 */
  71. 0x0008, /* R26 - Audio Interface 2 */
  72. 0x0022, /* R27 - Audio Interface 3 */
  73. 0x0000, /* R28 */
  74. 0x0000, /* R29 */
  75. 0x00C0, /* R30 - DAC Digital Volume Left */
  76. 0x00C0, /* R31 - DAC Digital Volume Right */
  77. 0x0000, /* R32 - DAC Digital 0 */
  78. 0x0000, /* R33 - DAC Digital 1 */
  79. 0x0000, /* R34 */
  80. 0x0000, /* R35 */
  81. 0x00C0, /* R36 - ADC Digital Volume Left */
  82. 0x00C0, /* R37 - ADC Digital Volume Right */
  83. 0x0000, /* R38 - ADC Digital 0 */
  84. 0x0073, /* R39 - Digital Microphone 0 */
  85. 0x09BF, /* R40 - DRC 0 */
  86. 0x3241, /* R41 - DRC 1 */
  87. 0x0020, /* R42 - DRC 2 */
  88. 0x0000, /* R43 - DRC 3 */
  89. 0x0085, /* R44 - Analogue Left Input 0 */
  90. 0x0085, /* R45 - Analogue Right Input 0 */
  91. 0x0044, /* R46 - Analogue Left Input 1 */
  92. 0x0044, /* R47 - Analogue Right Input 1 */
  93. 0x0000, /* R48 */
  94. 0x0000, /* R49 */
  95. 0x0008, /* R50 - Analogue Left Mix 0 */
  96. 0x0004, /* R51 - Analogue Right Mix 0 */
  97. 0x0000, /* R52 - Analogue Spk Mix Left 0 */
  98. 0x0000, /* R53 - Analogue Spk Mix Left 1 */
  99. 0x0000, /* R54 - Analogue Spk Mix Right 0 */
  100. 0x0000, /* R55 - Analogue Spk Mix Right 1 */
  101. 0x0000, /* R56 */
  102. 0x002D, /* R57 - Analogue OUT1 Left */
  103. 0x002D, /* R58 - Analogue OUT1 Right */
  104. 0x0039, /* R59 - Analogue OUT2 Left */
  105. 0x0039, /* R60 - Analogue OUT2 Right */
  106. 0x0100, /* R61 */
  107. 0x0139, /* R62 - Analogue OUT3 Left */
  108. 0x0139, /* R63 - Analogue OUT3 Right */
  109. 0x0000, /* R64 */
  110. 0x0000, /* R65 - Analogue SPK Output Control 0 */
  111. 0x0000, /* R66 */
  112. 0x0010, /* R67 - DC Servo 0 */
  113. 0x0100, /* R68 */
  114. 0x00A4, /* R69 - DC Servo 2 */
  115. 0x0807, /* R70 */
  116. 0x0000, /* R71 */
  117. 0x0000, /* R72 */
  118. 0x0000, /* R73 */
  119. 0x0000, /* R74 */
  120. 0x0000, /* R75 */
  121. 0x0000, /* R76 */
  122. 0x0000, /* R77 */
  123. 0x0000, /* R78 */
  124. 0x000E, /* R79 */
  125. 0x0000, /* R80 */
  126. 0x0000, /* R81 */
  127. 0x0000, /* R82 */
  128. 0x0000, /* R83 */
  129. 0x0000, /* R84 */
  130. 0x0000, /* R85 */
  131. 0x0000, /* R86 */
  132. 0x0006, /* R87 */
  133. 0x0000, /* R88 */
  134. 0x0000, /* R89 */
  135. 0x0000, /* R90 - Analogue HP 0 */
  136. 0x0060, /* R91 */
  137. 0x0000, /* R92 */
  138. 0x0000, /* R93 */
  139. 0x0000, /* R94 - Analogue Lineout 0 */
  140. 0x0060, /* R95 */
  141. 0x0000, /* R96 */
  142. 0x0000, /* R97 */
  143. 0x0000, /* R98 - Charge Pump 0 */
  144. 0x1F25, /* R99 */
  145. 0x2B19, /* R100 */
  146. 0x01C0, /* R101 */
  147. 0x01EF, /* R102 */
  148. 0x2B00, /* R103 */
  149. 0x0000, /* R104 - Class W 0 */
  150. 0x01C0, /* R105 */
  151. 0x1C10, /* R106 */
  152. 0x0000, /* R107 */
  153. 0x0000, /* R108 - Write Sequencer 0 */
  154. 0x0000, /* R109 - Write Sequencer 1 */
  155. 0x0000, /* R110 - Write Sequencer 2 */
  156. 0x0000, /* R111 - Write Sequencer 3 */
  157. 0x0000, /* R112 - Write Sequencer 4 */
  158. 0x0000, /* R113 */
  159. 0x0000, /* R114 - Control Interface */
  160. 0x0000, /* R115 */
  161. 0x00A8, /* R116 - GPIO Control 1 */
  162. 0x00A8, /* R117 - GPIO Control 2 */
  163. 0x00A8, /* R118 - GPIO Control 3 */
  164. 0x0220, /* R119 - GPIO Control 4 */
  165. 0x01A0, /* R120 - GPIO Control 5 */
  166. 0x0000, /* R121 - Interrupt Status 1 */
  167. 0xFFFF, /* R122 - Interrupt Status 1 Mask */
  168. 0x0000, /* R123 - Interrupt Polarity 1 */
  169. 0x0000, /* R124 */
  170. 0x0003, /* R125 */
  171. 0x0000, /* R126 - Interrupt Control */
  172. 0x0000, /* R127 */
  173. 0x0005, /* R128 */
  174. 0x0000, /* R129 - Control Interface Test 1 */
  175. 0x0000, /* R130 */
  176. 0x0000, /* R131 */
  177. 0x0000, /* R132 */
  178. 0x0000, /* R133 */
  179. 0x0000, /* R134 */
  180. 0x03FF, /* R135 */
  181. 0x0007, /* R136 */
  182. 0x0040, /* R137 */
  183. 0x0000, /* R138 */
  184. 0x0000, /* R139 */
  185. 0x0000, /* R140 */
  186. 0x0000, /* R141 */
  187. 0x0000, /* R142 */
  188. 0x0000, /* R143 */
  189. 0x0000, /* R144 */
  190. 0x0000, /* R145 */
  191. 0x0000, /* R146 */
  192. 0x0000, /* R147 */
  193. 0x4000, /* R148 */
  194. 0x6810, /* R149 - Charge Pump Test 1 */
  195. 0x0004, /* R150 */
  196. 0x0000, /* R151 */
  197. 0x0000, /* R152 */
  198. 0x0000, /* R153 */
  199. 0x0000, /* R154 */
  200. 0x0000, /* R155 */
  201. 0x0000, /* R156 */
  202. 0x0000, /* R157 */
  203. 0x0000, /* R158 */
  204. 0x0000, /* R159 */
  205. 0x0000, /* R160 */
  206. 0x0000, /* R161 */
  207. 0x0000, /* R162 */
  208. 0x0000, /* R163 */
  209. 0x0028, /* R164 - Clock Rate Test 4 */
  210. 0x0004, /* R165 */
  211. 0x0000, /* R166 */
  212. 0x0060, /* R167 */
  213. 0x0000, /* R168 */
  214. 0x0000, /* R169 */
  215. 0x0000, /* R170 */
  216. 0x0000, /* R171 */
  217. 0x0000, /* R172 - Analogue Output Bias 0 */
  218. };
  219. static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec,
  220. unsigned int reg)
  221. {
  222. u16 *cache = codec->reg_cache;
  223. BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
  224. return cache[reg];
  225. }
  226. static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg)
  227. {
  228. struct i2c_msg xfer[2];
  229. u16 data;
  230. int ret;
  231. struct i2c_client *client = codec->control_data;
  232. /* Write register */
  233. xfer[0].addr = client->addr;
  234. xfer[0].flags = 0;
  235. xfer[0].len = 1;
  236. xfer[0].buf = &reg;
  237. /* Read data */
  238. xfer[1].addr = client->addr;
  239. xfer[1].flags = I2C_M_RD;
  240. xfer[1].len = 2;
  241. xfer[1].buf = (u8 *)&data;
  242. ret = i2c_transfer(client->adapter, xfer, 2);
  243. if (ret != 2) {
  244. pr_err("i2c_transfer returned %d\n", ret);
  245. return 0;
  246. }
  247. return (data >> 8) | ((data & 0xff) << 8);
  248. }
  249. static unsigned int wm8903_read(struct snd_soc_codec *codec,
  250. unsigned int reg)
  251. {
  252. switch (reg) {
  253. case WM8903_SW_RESET_AND_ID:
  254. case WM8903_REVISION_NUMBER:
  255. case WM8903_INTERRUPT_STATUS_1:
  256. case WM8903_WRITE_SEQUENCER_4:
  257. return wm8903_hw_read(codec, reg);
  258. default:
  259. return wm8903_read_reg_cache(codec, reg);
  260. }
  261. }
  262. static void wm8903_write_reg_cache(struct snd_soc_codec *codec,
  263. u16 reg, unsigned int value)
  264. {
  265. u16 *cache = codec->reg_cache;
  266. BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
  267. switch (reg) {
  268. case WM8903_SW_RESET_AND_ID:
  269. case WM8903_REVISION_NUMBER:
  270. break;
  271. default:
  272. cache[reg] = value;
  273. break;
  274. }
  275. }
  276. static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg,
  277. unsigned int value)
  278. {
  279. u8 data[3];
  280. wm8903_write_reg_cache(codec, reg, value);
  281. /* Data format is 1 byte of address followed by 2 bytes of data */
  282. data[0] = reg;
  283. data[1] = (value >> 8) & 0xff;
  284. data[2] = value & 0xff;
  285. if (codec->hw_write(codec->control_data, data, 3) == 2)
  286. return 0;
  287. else
  288. return -EIO;
  289. }
  290. static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
  291. {
  292. u16 reg[5];
  293. struct i2c_client *i2c = codec->control_data;
  294. BUG_ON(start > 48);
  295. /* Enable the sequencer */
  296. reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0);
  297. reg[0] |= WM8903_WSEQ_ENA;
  298. wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
  299. dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
  300. wm8903_write(codec, WM8903_WRITE_SEQUENCER_3,
  301. start | WM8903_WSEQ_START);
  302. /* Wait for it to complete. If we have the interrupt wired up then
  303. * we could block waiting for an interrupt, though polling may still
  304. * be desirable for diagnostic purposes.
  305. */
  306. do {
  307. msleep(10);
  308. reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4);
  309. } while (reg[4] & WM8903_WSEQ_BUSY);
  310. dev_dbg(&i2c->dev, "Sequence complete\n");
  311. /* Disable the sequencer again */
  312. wm8903_write(codec, WM8903_WRITE_SEQUENCER_0,
  313. reg[0] & ~WM8903_WSEQ_ENA);
  314. return 0;
  315. }
  316. static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
  317. {
  318. int i;
  319. /* There really ought to be something better we can do here :/ */
  320. for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
  321. cache[i] = wm8903_hw_read(codec, i);
  322. }
  323. static void wm8903_reset(struct snd_soc_codec *codec)
  324. {
  325. wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0);
  326. }
  327. #define WM8903_OUTPUT_SHORT 0x8
  328. #define WM8903_OUTPUT_OUT 0x4
  329. #define WM8903_OUTPUT_INT 0x2
  330. #define WM8903_OUTPUT_IN 0x1
  331. /*
  332. * Event for headphone and line out amplifier power changes. Special
  333. * power up/down sequences are required in order to maximise pop/click
  334. * performance.
  335. */
  336. static int wm8903_output_event(struct snd_soc_dapm_widget *w,
  337. struct snd_kcontrol *kcontrol, int event)
  338. {
  339. struct snd_soc_codec *codec = w->codec;
  340. struct wm8903_priv *wm8903 = codec->private_data;
  341. struct i2c_client *i2c = codec->control_data;
  342. u16 val;
  343. u16 reg;
  344. int shift;
  345. u16 cp_reg = wm8903_read(codec, WM8903_CHARGE_PUMP_0);
  346. switch (w->reg) {
  347. case WM8903_POWER_MANAGEMENT_2:
  348. reg = WM8903_ANALOGUE_HP_0;
  349. break;
  350. case WM8903_POWER_MANAGEMENT_3:
  351. reg = WM8903_ANALOGUE_LINEOUT_0;
  352. break;
  353. default:
  354. BUG();
  355. }
  356. switch (w->shift) {
  357. case 0:
  358. shift = 0;
  359. break;
  360. case 1:
  361. shift = 4;
  362. break;
  363. default:
  364. BUG();
  365. }
  366. if (event & SND_SOC_DAPM_PRE_PMU) {
  367. val = wm8903_read(codec, reg);
  368. /* Short the output */
  369. val &= ~(WM8903_OUTPUT_SHORT << shift);
  370. wm8903_write(codec, reg, val);
  371. wm8903->charge_pump_users++;
  372. dev_dbg(&i2c->dev, "Charge pump use count now %d\n",
  373. wm8903->charge_pump_users);
  374. if (wm8903->charge_pump_users == 1) {
  375. dev_dbg(&i2c->dev, "Enabling charge pump\n");
  376. wm8903_write(codec, WM8903_CHARGE_PUMP_0,
  377. cp_reg | WM8903_CP_ENA);
  378. mdelay(4);
  379. }
  380. }
  381. if (event & SND_SOC_DAPM_POST_PMU) {
  382. val = wm8903_read(codec, reg);
  383. val |= (WM8903_OUTPUT_IN << shift);
  384. wm8903_write(codec, reg, val);
  385. val |= (WM8903_OUTPUT_INT << shift);
  386. wm8903_write(codec, reg, val);
  387. /* Turn on the output ENA_OUTP */
  388. val |= (WM8903_OUTPUT_OUT << shift);
  389. wm8903_write(codec, reg, val);
  390. /* Remove the short */
  391. val |= (WM8903_OUTPUT_SHORT << shift);
  392. wm8903_write(codec, reg, val);
  393. }
  394. if (event & SND_SOC_DAPM_PRE_PMD) {
  395. val = wm8903_read(codec, reg);
  396. /* Short the output */
  397. val &= ~(WM8903_OUTPUT_SHORT << shift);
  398. wm8903_write(codec, reg, val);
  399. /* Then disable the intermediate and output stages */
  400. val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
  401. WM8903_OUTPUT_IN) << shift);
  402. wm8903_write(codec, reg, val);
  403. }
  404. if (event & SND_SOC_DAPM_POST_PMD) {
  405. wm8903->charge_pump_users--;
  406. dev_dbg(&i2c->dev, "Charge pump use count now %d\n",
  407. wm8903->charge_pump_users);
  408. if (wm8903->charge_pump_users == 0) {
  409. dev_dbg(&i2c->dev, "Disabling charge pump\n");
  410. wm8903_write(codec, WM8903_CHARGE_PUMP_0,
  411. cp_reg & ~WM8903_CP_ENA);
  412. }
  413. }
  414. return 0;
  415. }
  416. /*
  417. * When used with DAC outputs only the WM8903 charge pump supports
  418. * operation in class W mode, providing very low power consumption
  419. * when used with digital sources. Enable and disable this mode
  420. * automatically depending on the mixer configuration.
  421. *
  422. * All the relevant controls are simple switches.
  423. */
  424. static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
  425. struct snd_ctl_elem_value *ucontrol)
  426. {
  427. struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
  428. struct snd_soc_codec *codec = widget->codec;
  429. struct wm8903_priv *wm8903 = codec->private_data;
  430. struct i2c_client *i2c = codec->control_data;
  431. u16 reg;
  432. int ret;
  433. reg = wm8903_read(codec, WM8903_CLASS_W_0);
  434. /* Turn it off if we're about to enable bypass */
  435. if (ucontrol->value.integer.value[0]) {
  436. if (wm8903->class_w_users == 0) {
  437. dev_dbg(&i2c->dev, "Disabling Class W\n");
  438. wm8903_write(codec, WM8903_CLASS_W_0, reg &
  439. ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
  440. }
  441. wm8903->class_w_users++;
  442. }
  443. /* Implement the change */
  444. ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
  445. /* If we've just disabled the last bypass path turn Class W on */
  446. if (!ucontrol->value.integer.value[0]) {
  447. if (wm8903->class_w_users == 1) {
  448. dev_dbg(&i2c->dev, "Enabling Class W\n");
  449. wm8903_write(codec, WM8903_CLASS_W_0, reg |
  450. WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
  451. }
  452. wm8903->class_w_users--;
  453. }
  454. dev_dbg(&i2c->dev, "Bypass use count now %d\n",
  455. wm8903->class_w_users);
  456. return ret;
  457. }
  458. #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
  459. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  460. .info = snd_soc_info_volsw, \
  461. .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
  462. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
  463. /* ALSA can only do steps of .01dB */
  464. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  465. static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
  466. static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
  467. static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
  468. static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
  469. static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
  470. static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
  471. static const char *drc_slope_text[] = {
  472. "1", "1/2", "1/4", "1/8", "1/16", "0"
  473. };
  474. static const struct soc_enum drc_slope_r0 =
  475. SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
  476. static const struct soc_enum drc_slope_r1 =
  477. SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
  478. static const char *drc_attack_text[] = {
  479. "instantaneous",
  480. "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
  481. "46.4ms", "92.8ms", "185.6ms"
  482. };
  483. static const struct soc_enum drc_attack =
  484. SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
  485. static const char *drc_decay_text[] = {
  486. "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
  487. "23.87s", "47.56s"
  488. };
  489. static const struct soc_enum drc_decay =
  490. SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
  491. static const char *drc_ff_delay_text[] = {
  492. "5 samples", "9 samples"
  493. };
  494. static const struct soc_enum drc_ff_delay =
  495. SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
  496. static const char *drc_qr_decay_text[] = {
  497. "0.725ms", "1.45ms", "5.8ms"
  498. };
  499. static const struct soc_enum drc_qr_decay =
  500. SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
  501. static const char *drc_smoothing_text[] = {
  502. "Low", "Medium", "High"
  503. };
  504. static const struct soc_enum drc_smoothing =
  505. SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
  506. static const char *soft_mute_text[] = {
  507. "Fast (fs/2)", "Slow (fs/32)"
  508. };
  509. static const struct soc_enum soft_mute =
  510. SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
  511. static const char *mute_mode_text[] = {
  512. "Hard", "Soft"
  513. };
  514. static const struct soc_enum mute_mode =
  515. SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
  516. static const char *dac_deemphasis_text[] = {
  517. "Disabled", "32kHz", "44.1kHz", "48kHz"
  518. };
  519. static const struct soc_enum dac_deemphasis =
  520. SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
  521. static const char *companding_text[] = {
  522. "ulaw", "alaw"
  523. };
  524. static const struct soc_enum dac_companding =
  525. SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
  526. static const struct soc_enum adc_companding =
  527. SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
  528. static const char *input_mode_text[] = {
  529. "Single-Ended", "Differential Line", "Differential Mic"
  530. };
  531. static const struct soc_enum linput_mode_enum =
  532. SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
  533. static const struct soc_enum rinput_mode_enum =
  534. SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
  535. static const char *linput_mux_text[] = {
  536. "IN1L", "IN2L", "IN3L"
  537. };
  538. static const struct soc_enum linput_enum =
  539. SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
  540. static const struct soc_enum linput_inv_enum =
  541. SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
  542. static const char *rinput_mux_text[] = {
  543. "IN1R", "IN2R", "IN3R"
  544. };
  545. static const struct soc_enum rinput_enum =
  546. SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
  547. static const struct soc_enum rinput_inv_enum =
  548. SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
  549. static const struct snd_kcontrol_new wm8903_snd_controls[] = {
  550. /* Input PGAs - No TLV since the scale depends on PGA mode */
  551. SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
  552. 7, 1, 1),
  553. SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
  554. 0, 31, 0),
  555. SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
  556. 6, 1, 0),
  557. SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
  558. 7, 1, 1),
  559. SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
  560. 0, 31, 0),
  561. SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
  562. 6, 1, 0),
  563. /* ADCs */
  564. SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
  565. SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
  566. SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
  567. SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8903_DRC_3, 5, 124, 1,
  568. drc_tlv_thresh),
  569. SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
  570. SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
  571. SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
  572. SOC_ENUM("DRC Attack Rate", drc_attack),
  573. SOC_ENUM("DRC Decay Rate", drc_decay),
  574. SOC_ENUM("DRC FF Delay", drc_ff_delay),
  575. SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
  576. SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
  577. SOC_SINGLE_TLV("DRC QR Threashold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
  578. SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
  579. SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
  580. SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
  581. SOC_ENUM("DRC Smoothing Threashold", drc_smoothing),
  582. SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
  583. SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
  584. WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
  585. SOC_ENUM("ADC Companding Mode", adc_companding),
  586. SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
  587. /* DAC */
  588. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
  589. WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
  590. SOC_ENUM("DAC Soft Mute Rate", soft_mute),
  591. SOC_ENUM("DAC Mute Mode", mute_mode),
  592. SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
  593. SOC_ENUM("DAC De-emphasis", dac_deemphasis),
  594. SOC_SINGLE("DAC Sloping Stopband Filter Switch",
  595. WM8903_DAC_DIGITAL_1, 11, 1, 0),
  596. SOC_ENUM("DAC Companding Mode", dac_companding),
  597. SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
  598. /* Headphones */
  599. SOC_DOUBLE_R("Headphone Switch",
  600. WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
  601. 8, 1, 1),
  602. SOC_DOUBLE_R("Headphone ZC Switch",
  603. WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
  604. 6, 1, 0),
  605. SOC_DOUBLE_R_TLV("Headphone Volume",
  606. WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
  607. 0, 63, 0, out_tlv),
  608. /* Line out */
  609. SOC_DOUBLE_R("Line Out Switch",
  610. WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
  611. 8, 1, 1),
  612. SOC_DOUBLE_R("Line Out ZC Switch",
  613. WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
  614. 6, 1, 0),
  615. SOC_DOUBLE_R_TLV("Line Out Volume",
  616. WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
  617. 0, 63, 0, out_tlv),
  618. /* Speaker */
  619. SOC_DOUBLE_R("Speaker Switch",
  620. WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
  621. SOC_DOUBLE_R("Speaker ZC Switch",
  622. WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
  623. SOC_DOUBLE_R_TLV("Speaker Volume",
  624. WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
  625. 0, 63, 0, out_tlv),
  626. };
  627. static int wm8903_add_controls(struct snd_soc_codec *codec)
  628. {
  629. int err, i;
  630. for (i = 0; i < ARRAY_SIZE(wm8903_snd_controls); i++) {
  631. err = snd_ctl_add(codec->card,
  632. snd_soc_cnew(&wm8903_snd_controls[i],
  633. codec, NULL));
  634. if (err < 0)
  635. return err;
  636. }
  637. return 0;
  638. }
  639. static const struct snd_kcontrol_new linput_mode_mux =
  640. SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
  641. static const struct snd_kcontrol_new rinput_mode_mux =
  642. SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
  643. static const struct snd_kcontrol_new linput_mux =
  644. SOC_DAPM_ENUM("Left Input Mux", linput_enum);
  645. static const struct snd_kcontrol_new linput_inv_mux =
  646. SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
  647. static const struct snd_kcontrol_new rinput_mux =
  648. SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
  649. static const struct snd_kcontrol_new rinput_inv_mux =
  650. SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
  651. static const struct snd_kcontrol_new left_output_mixer[] = {
  652. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
  653. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
  654. SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
  655. SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
  656. };
  657. static const struct snd_kcontrol_new right_output_mixer[] = {
  658. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
  659. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
  660. SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
  661. SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
  662. };
  663. static const struct snd_kcontrol_new left_speaker_mixer[] = {
  664. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
  665. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
  666. SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
  667. SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
  668. 1, 1, 0),
  669. };
  670. static const struct snd_kcontrol_new right_speaker_mixer[] = {
  671. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
  672. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
  673. SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
  674. 1, 1, 0),
  675. SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
  676. 1, 1, 0),
  677. };
  678. static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
  679. SND_SOC_DAPM_INPUT("IN1L"),
  680. SND_SOC_DAPM_INPUT("IN1R"),
  681. SND_SOC_DAPM_INPUT("IN2L"),
  682. SND_SOC_DAPM_INPUT("IN2R"),
  683. SND_SOC_DAPM_INPUT("IN3L"),
  684. SND_SOC_DAPM_INPUT("IN3R"),
  685. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  686. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  687. SND_SOC_DAPM_OUTPUT("LINEOUTL"),
  688. SND_SOC_DAPM_OUTPUT("LINEOUTR"),
  689. SND_SOC_DAPM_OUTPUT("LOP"),
  690. SND_SOC_DAPM_OUTPUT("LON"),
  691. SND_SOC_DAPM_OUTPUT("ROP"),
  692. SND_SOC_DAPM_OUTPUT("RON"),
  693. SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
  694. SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
  695. SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
  696. &linput_inv_mux),
  697. SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
  698. SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
  699. SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
  700. &rinput_inv_mux),
  701. SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
  702. SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
  703. SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
  704. SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
  705. SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
  706. SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
  707. SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
  708. SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
  709. left_output_mixer, ARRAY_SIZE(left_output_mixer)),
  710. SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
  711. right_output_mixer, ARRAY_SIZE(right_output_mixer)),
  712. SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
  713. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
  714. SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
  715. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
  716. SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
  717. 1, 0, NULL, 0, wm8903_output_event,
  718. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  719. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  720. SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
  721. 0, 0, NULL, 0, wm8903_output_event,
  722. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  723. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  724. SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
  725. NULL, 0, wm8903_output_event,
  726. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  727. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  728. SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
  729. NULL, 0, wm8903_output_event,
  730. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  731. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  732. SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
  733. NULL, 0),
  734. SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
  735. NULL, 0),
  736. };
  737. static const struct snd_soc_dapm_route intercon[] = {
  738. { "Left Input Mux", "IN1L", "IN1L" },
  739. { "Left Input Mux", "IN2L", "IN2L" },
  740. { "Left Input Mux", "IN3L", "IN3L" },
  741. { "Left Input Inverting Mux", "IN1L", "IN1L" },
  742. { "Left Input Inverting Mux", "IN2L", "IN2L" },
  743. { "Left Input Inverting Mux", "IN3L", "IN3L" },
  744. { "Right Input Mux", "IN1R", "IN1R" },
  745. { "Right Input Mux", "IN2R", "IN2R" },
  746. { "Right Input Mux", "IN3R", "IN3R" },
  747. { "Right Input Inverting Mux", "IN1R", "IN1R" },
  748. { "Right Input Inverting Mux", "IN2R", "IN2R" },
  749. { "Right Input Inverting Mux", "IN3R", "IN3R" },
  750. { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
  751. { "Left Input Mode Mux", "Differential Line",
  752. "Left Input Mux" },
  753. { "Left Input Mode Mux", "Differential Line",
  754. "Left Input Inverting Mux" },
  755. { "Left Input Mode Mux", "Differential Mic",
  756. "Left Input Mux" },
  757. { "Left Input Mode Mux", "Differential Mic",
  758. "Left Input Inverting Mux" },
  759. { "Right Input Mode Mux", "Single-Ended",
  760. "Right Input Inverting Mux" },
  761. { "Right Input Mode Mux", "Differential Line",
  762. "Right Input Mux" },
  763. { "Right Input Mode Mux", "Differential Line",
  764. "Right Input Inverting Mux" },
  765. { "Right Input Mode Mux", "Differential Mic",
  766. "Right Input Mux" },
  767. { "Right Input Mode Mux", "Differential Mic",
  768. "Right Input Inverting Mux" },
  769. { "Left Input PGA", NULL, "Left Input Mode Mux" },
  770. { "Right Input PGA", NULL, "Right Input Mode Mux" },
  771. { "ADCL", NULL, "Left Input PGA" },
  772. { "ADCR", NULL, "Right Input PGA" },
  773. { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
  774. { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
  775. { "Left Output Mixer", "DACL Switch", "DACL" },
  776. { "Left Output Mixer", "DACR Switch", "DACR" },
  777. { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
  778. { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
  779. { "Right Output Mixer", "DACL Switch", "DACL" },
  780. { "Right Output Mixer", "DACR Switch", "DACR" },
  781. { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
  782. { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
  783. { "Left Speaker Mixer", "DACL Switch", "DACL" },
  784. { "Left Speaker Mixer", "DACR Switch", "DACR" },
  785. { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
  786. { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
  787. { "Right Speaker Mixer", "DACL Switch", "DACL" },
  788. { "Right Speaker Mixer", "DACR Switch", "DACR" },
  789. { "Left Line Output PGA", NULL, "Left Output Mixer" },
  790. { "Right Line Output PGA", NULL, "Right Output Mixer" },
  791. { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
  792. { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
  793. { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
  794. { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
  795. { "HPOUTL", NULL, "Left Headphone Output PGA" },
  796. { "HPOUTR", NULL, "Right Headphone Output PGA" },
  797. { "LINEOUTL", NULL, "Left Line Output PGA" },
  798. { "LINEOUTR", NULL, "Right Line Output PGA" },
  799. { "LOP", NULL, "Left Speaker PGA" },
  800. { "LON", NULL, "Left Speaker PGA" },
  801. { "ROP", NULL, "Right Speaker PGA" },
  802. { "RON", NULL, "Right Speaker PGA" },
  803. };
  804. static int wm8903_add_widgets(struct snd_soc_codec *codec)
  805. {
  806. snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
  807. ARRAY_SIZE(wm8903_dapm_widgets));
  808. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  809. snd_soc_dapm_new_widgets(codec);
  810. return 0;
  811. }
  812. static int wm8903_set_bias_level(struct snd_soc_codec *codec,
  813. enum snd_soc_bias_level level)
  814. {
  815. struct i2c_client *i2c = codec->control_data;
  816. u16 reg, reg2;
  817. switch (level) {
  818. case SND_SOC_BIAS_ON:
  819. case SND_SOC_BIAS_PREPARE:
  820. reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
  821. reg &= ~(WM8903_VMID_RES_MASK);
  822. reg |= WM8903_VMID_RES_50K;
  823. wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
  824. break;
  825. case SND_SOC_BIAS_STANDBY:
  826. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  827. wm8903_run_sequence(codec, 0);
  828. wm8903_sync_reg_cache(codec, codec->reg_cache);
  829. /* Enable low impedence charge pump output */
  830. reg = wm8903_read(codec,
  831. WM8903_CONTROL_INTERFACE_TEST_1);
  832. wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
  833. reg | WM8903_TEST_KEY);
  834. reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1);
  835. wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1,
  836. reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
  837. wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
  838. reg);
  839. /* By default no bypass paths are enabled so
  840. * enable Class W support.
  841. */
  842. dev_dbg(&i2c->dev, "Enabling Class W\n");
  843. wm8903_write(codec, WM8903_CLASS_W_0, reg |
  844. WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
  845. }
  846. reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
  847. reg &= ~(WM8903_VMID_RES_MASK);
  848. reg |= WM8903_VMID_RES_250K;
  849. wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
  850. break;
  851. case SND_SOC_BIAS_OFF:
  852. wm8903_run_sequence(codec, 32);
  853. break;
  854. }
  855. codec->bias_level = level;
  856. return 0;
  857. }
  858. static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  859. int clk_id, unsigned int freq, int dir)
  860. {
  861. struct snd_soc_codec *codec = codec_dai->codec;
  862. struct wm8903_priv *wm8903 = codec->private_data;
  863. wm8903->sysclk = freq;
  864. return 0;
  865. }
  866. static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
  867. unsigned int fmt)
  868. {
  869. struct snd_soc_codec *codec = codec_dai->codec;
  870. u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
  871. aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
  872. WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
  873. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  874. case SND_SOC_DAIFMT_CBS_CFS:
  875. break;
  876. case SND_SOC_DAIFMT_CBS_CFM:
  877. aif1 |= WM8903_LRCLK_DIR;
  878. break;
  879. case SND_SOC_DAIFMT_CBM_CFM:
  880. aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
  881. break;
  882. case SND_SOC_DAIFMT_CBM_CFS:
  883. aif1 |= WM8903_BCLK_DIR;
  884. break;
  885. default:
  886. return -EINVAL;
  887. }
  888. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  889. case SND_SOC_DAIFMT_DSP_A:
  890. aif1 |= 0x3;
  891. break;
  892. case SND_SOC_DAIFMT_DSP_B:
  893. aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
  894. break;
  895. case SND_SOC_DAIFMT_I2S:
  896. aif1 |= 0x2;
  897. break;
  898. case SND_SOC_DAIFMT_RIGHT_J:
  899. aif1 |= 0x1;
  900. break;
  901. case SND_SOC_DAIFMT_LEFT_J:
  902. break;
  903. default:
  904. return -EINVAL;
  905. }
  906. /* Clock inversion */
  907. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  908. case SND_SOC_DAIFMT_DSP_A:
  909. case SND_SOC_DAIFMT_DSP_B:
  910. /* frame inversion not valid for DSP modes */
  911. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  912. case SND_SOC_DAIFMT_NB_NF:
  913. break;
  914. case SND_SOC_DAIFMT_IB_NF:
  915. aif1 |= WM8903_AIF_BCLK_INV;
  916. break;
  917. default:
  918. return -EINVAL;
  919. }
  920. break;
  921. case SND_SOC_DAIFMT_I2S:
  922. case SND_SOC_DAIFMT_RIGHT_J:
  923. case SND_SOC_DAIFMT_LEFT_J:
  924. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  925. case SND_SOC_DAIFMT_NB_NF:
  926. break;
  927. case SND_SOC_DAIFMT_IB_IF:
  928. aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
  929. break;
  930. case SND_SOC_DAIFMT_IB_NF:
  931. aif1 |= WM8903_AIF_BCLK_INV;
  932. break;
  933. case SND_SOC_DAIFMT_NB_IF:
  934. aif1 |= WM8903_AIF_LRCLK_INV;
  935. break;
  936. default:
  937. return -EINVAL;
  938. }
  939. break;
  940. default:
  941. return -EINVAL;
  942. }
  943. wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
  944. return 0;
  945. }
  946. static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
  947. {
  948. struct snd_soc_codec *codec = codec_dai->codec;
  949. u16 reg;
  950. reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
  951. if (mute)
  952. reg |= WM8903_DAC_MUTE;
  953. else
  954. reg &= ~WM8903_DAC_MUTE;
  955. wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg);
  956. return 0;
  957. }
  958. /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
  959. * for optimal performance so we list the lower rates first and match
  960. * on the last match we find. */
  961. static struct {
  962. int div;
  963. int rate;
  964. int mode;
  965. int mclk_div;
  966. } clk_sys_ratios[] = {
  967. { 64, 0x0, 0x0, 1 },
  968. { 68, 0x0, 0x1, 1 },
  969. { 125, 0x0, 0x2, 1 },
  970. { 128, 0x1, 0x0, 1 },
  971. { 136, 0x1, 0x1, 1 },
  972. { 192, 0x2, 0x0, 1 },
  973. { 204, 0x2, 0x1, 1 },
  974. { 64, 0x0, 0x0, 2 },
  975. { 68, 0x0, 0x1, 2 },
  976. { 125, 0x0, 0x2, 2 },
  977. { 128, 0x1, 0x0, 2 },
  978. { 136, 0x1, 0x1, 2 },
  979. { 192, 0x2, 0x0, 2 },
  980. { 204, 0x2, 0x1, 2 },
  981. { 250, 0x2, 0x2, 1 },
  982. { 256, 0x3, 0x0, 1 },
  983. { 272, 0x3, 0x1, 1 },
  984. { 384, 0x4, 0x0, 1 },
  985. { 408, 0x4, 0x1, 1 },
  986. { 375, 0x4, 0x2, 1 },
  987. { 512, 0x5, 0x0, 1 },
  988. { 544, 0x5, 0x1, 1 },
  989. { 500, 0x5, 0x2, 1 },
  990. { 768, 0x6, 0x0, 1 },
  991. { 816, 0x6, 0x1, 1 },
  992. { 750, 0x6, 0x2, 1 },
  993. { 1024, 0x7, 0x0, 1 },
  994. { 1088, 0x7, 0x1, 1 },
  995. { 1000, 0x7, 0x2, 1 },
  996. { 1408, 0x8, 0x0, 1 },
  997. { 1496, 0x8, 0x1, 1 },
  998. { 1536, 0x9, 0x0, 1 },
  999. { 1632, 0x9, 0x1, 1 },
  1000. { 1500, 0x9, 0x2, 1 },
  1001. { 250, 0x2, 0x2, 2 },
  1002. { 256, 0x3, 0x0, 2 },
  1003. { 272, 0x3, 0x1, 2 },
  1004. { 384, 0x4, 0x0, 2 },
  1005. { 408, 0x4, 0x1, 2 },
  1006. { 375, 0x4, 0x2, 2 },
  1007. { 512, 0x5, 0x0, 2 },
  1008. { 544, 0x5, 0x1, 2 },
  1009. { 500, 0x5, 0x2, 2 },
  1010. { 768, 0x6, 0x0, 2 },
  1011. { 816, 0x6, 0x1, 2 },
  1012. { 750, 0x6, 0x2, 2 },
  1013. { 1024, 0x7, 0x0, 2 },
  1014. { 1088, 0x7, 0x1, 2 },
  1015. { 1000, 0x7, 0x2, 2 },
  1016. { 1408, 0x8, 0x0, 2 },
  1017. { 1496, 0x8, 0x1, 2 },
  1018. { 1536, 0x9, 0x0, 2 },
  1019. { 1632, 0x9, 0x1, 2 },
  1020. { 1500, 0x9, 0x2, 2 },
  1021. };
  1022. /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
  1023. static struct {
  1024. int ratio;
  1025. int div;
  1026. } bclk_divs[] = {
  1027. { 10, 0 },
  1028. { 15, 1 },
  1029. { 20, 2 },
  1030. { 30, 3 },
  1031. { 40, 4 },
  1032. { 50, 5 },
  1033. { 55, 6 },
  1034. { 60, 7 },
  1035. { 80, 8 },
  1036. { 100, 9 },
  1037. { 110, 10 },
  1038. { 120, 11 },
  1039. { 160, 12 },
  1040. { 200, 13 },
  1041. { 220, 14 },
  1042. { 240, 15 },
  1043. { 250, 16 },
  1044. { 300, 17 },
  1045. { 320, 18 },
  1046. { 440, 19 },
  1047. { 480, 20 },
  1048. };
  1049. /* Sample rates for DSP */
  1050. static struct {
  1051. int rate;
  1052. int value;
  1053. } sample_rates[] = {
  1054. { 8000, 0 },
  1055. { 11025, 1 },
  1056. { 12000, 2 },
  1057. { 16000, 3 },
  1058. { 22050, 4 },
  1059. { 24000, 5 },
  1060. { 32000, 6 },
  1061. { 44100, 7 },
  1062. { 48000, 8 },
  1063. { 88200, 9 },
  1064. { 96000, 10 },
  1065. { 0, 0 },
  1066. };
  1067. static int wm8903_startup(struct snd_pcm_substream *substream)
  1068. {
  1069. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1070. struct snd_soc_device *socdev = rtd->socdev;
  1071. struct snd_soc_codec *codec = socdev->codec;
  1072. struct wm8903_priv *wm8903 = codec->private_data;
  1073. struct i2c_client *i2c = codec->control_data;
  1074. struct snd_pcm_runtime *master_runtime;
  1075. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  1076. wm8903->playback_active++;
  1077. else
  1078. wm8903->capture_active++;
  1079. /* The DAI has shared clocks so if we already have a playback or
  1080. * capture going then constrain this substream to match it.
  1081. */
  1082. if (wm8903->master_substream) {
  1083. master_runtime = wm8903->master_substream->runtime;
  1084. dev_dbg(&i2c->dev, "Constraining to %d bits at %dHz\n",
  1085. master_runtime->sample_bits,
  1086. master_runtime->rate);
  1087. snd_pcm_hw_constraint_minmax(substream->runtime,
  1088. SNDRV_PCM_HW_PARAM_RATE,
  1089. master_runtime->rate,
  1090. master_runtime->rate);
  1091. snd_pcm_hw_constraint_minmax(substream->runtime,
  1092. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1093. master_runtime->sample_bits,
  1094. master_runtime->sample_bits);
  1095. wm8903->slave_substream = substream;
  1096. } else
  1097. wm8903->master_substream = substream;
  1098. return 0;
  1099. }
  1100. static void wm8903_shutdown(struct snd_pcm_substream *substream)
  1101. {
  1102. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1103. struct snd_soc_device *socdev = rtd->socdev;
  1104. struct snd_soc_codec *codec = socdev->codec;
  1105. struct wm8903_priv *wm8903 = codec->private_data;
  1106. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  1107. wm8903->playback_active--;
  1108. else
  1109. wm8903->capture_active--;
  1110. if (wm8903->master_substream == substream)
  1111. wm8903->master_substream = wm8903->slave_substream;
  1112. wm8903->slave_substream = NULL;
  1113. }
  1114. static int wm8903_hw_params(struct snd_pcm_substream *substream,
  1115. struct snd_pcm_hw_params *params)
  1116. {
  1117. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1118. struct snd_soc_device *socdev = rtd->socdev;
  1119. struct snd_soc_codec *codec = socdev->codec;
  1120. struct wm8903_priv *wm8903 = codec->private_data;
  1121. struct i2c_client *i2c = codec->control_data;
  1122. int fs = params_rate(params);
  1123. int bclk;
  1124. int bclk_div;
  1125. int i;
  1126. int dsp_config;
  1127. int clk_config;
  1128. int best_val;
  1129. int cur_val;
  1130. int clk_sys;
  1131. u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
  1132. u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2);
  1133. u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3);
  1134. u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0);
  1135. u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1);
  1136. if (substream == wm8903->slave_substream) {
  1137. dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
  1138. return 0;
  1139. }
  1140. /* Configure sample rate logic for DSP - choose nearest rate */
  1141. dsp_config = 0;
  1142. best_val = abs(sample_rates[dsp_config].rate - fs);
  1143. for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
  1144. cur_val = abs(sample_rates[i].rate - fs);
  1145. if (cur_val <= best_val) {
  1146. dsp_config = i;
  1147. best_val = cur_val;
  1148. }
  1149. }
  1150. /* Constraints should stop us hitting this but let's make sure */
  1151. if (wm8903->capture_active)
  1152. switch (sample_rates[dsp_config].rate) {
  1153. case 88200:
  1154. case 96000:
  1155. dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
  1156. fs);
  1157. return -EINVAL;
  1158. default:
  1159. break;
  1160. }
  1161. dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
  1162. clock1 &= ~WM8903_SAMPLE_RATE_MASK;
  1163. clock1 |= sample_rates[dsp_config].value;
  1164. aif1 &= ~WM8903_AIF_WL_MASK;
  1165. bclk = 2 * fs;
  1166. switch (params_format(params)) {
  1167. case SNDRV_PCM_FORMAT_S16_LE:
  1168. bclk *= 16;
  1169. break;
  1170. case SNDRV_PCM_FORMAT_S20_3LE:
  1171. bclk *= 20;
  1172. aif1 |= 0x4;
  1173. break;
  1174. case SNDRV_PCM_FORMAT_S24_LE:
  1175. bclk *= 24;
  1176. aif1 |= 0x8;
  1177. break;
  1178. case SNDRV_PCM_FORMAT_S32_LE:
  1179. bclk *= 32;
  1180. aif1 |= 0xc;
  1181. break;
  1182. default:
  1183. return -EINVAL;
  1184. }
  1185. dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
  1186. wm8903->sysclk, fs);
  1187. /* We may not have an MCLK which allows us to generate exactly
  1188. * the clock we want, particularly with USB derived inputs, so
  1189. * approximate.
  1190. */
  1191. clk_config = 0;
  1192. best_val = abs((wm8903->sysclk /
  1193. (clk_sys_ratios[0].mclk_div *
  1194. clk_sys_ratios[0].div)) - fs);
  1195. for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
  1196. cur_val = abs((wm8903->sysclk /
  1197. (clk_sys_ratios[i].mclk_div *
  1198. clk_sys_ratios[i].div)) - fs);
  1199. if (cur_val <= best_val) {
  1200. clk_config = i;
  1201. best_val = cur_val;
  1202. }
  1203. }
  1204. if (clk_sys_ratios[clk_config].mclk_div == 2) {
  1205. clock0 |= WM8903_MCLKDIV2;
  1206. clk_sys = wm8903->sysclk / 2;
  1207. } else {
  1208. clock0 &= ~WM8903_MCLKDIV2;
  1209. clk_sys = wm8903->sysclk;
  1210. }
  1211. clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
  1212. WM8903_CLK_SYS_MODE_MASK);
  1213. clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
  1214. clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
  1215. dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
  1216. clk_sys_ratios[clk_config].rate,
  1217. clk_sys_ratios[clk_config].mode,
  1218. clk_sys_ratios[clk_config].div);
  1219. dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
  1220. /* We may not get quite the right frequency if using
  1221. * approximate clocks so look for the closest match that is
  1222. * higher than the target (we need to ensure that there enough
  1223. * BCLKs to clock out the samples).
  1224. */
  1225. bclk_div = 0;
  1226. best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
  1227. i = 1;
  1228. while (i < ARRAY_SIZE(bclk_divs)) {
  1229. cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
  1230. if (cur_val < 0) /* BCLK table is sorted */
  1231. break;
  1232. bclk_div = i;
  1233. best_val = cur_val;
  1234. i++;
  1235. }
  1236. aif2 &= ~WM8903_BCLK_DIV_MASK;
  1237. aif3 &= ~WM8903_LRCLK_RATE_MASK;
  1238. dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
  1239. bclk_divs[bclk_div].ratio / 10, bclk,
  1240. (clk_sys * 10) / bclk_divs[bclk_div].ratio);
  1241. aif2 |= bclk_divs[bclk_div].div;
  1242. aif3 |= bclk / fs;
  1243. wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0);
  1244. wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1);
  1245. wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
  1246. wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
  1247. wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
  1248. return 0;
  1249. }
  1250. #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
  1251. SNDRV_PCM_RATE_11025 | \
  1252. SNDRV_PCM_RATE_16000 | \
  1253. SNDRV_PCM_RATE_22050 | \
  1254. SNDRV_PCM_RATE_32000 | \
  1255. SNDRV_PCM_RATE_44100 | \
  1256. SNDRV_PCM_RATE_48000 | \
  1257. SNDRV_PCM_RATE_88200 | \
  1258. SNDRV_PCM_RATE_96000)
  1259. #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
  1260. SNDRV_PCM_RATE_11025 | \
  1261. SNDRV_PCM_RATE_16000 | \
  1262. SNDRV_PCM_RATE_22050 | \
  1263. SNDRV_PCM_RATE_32000 | \
  1264. SNDRV_PCM_RATE_44100 | \
  1265. SNDRV_PCM_RATE_48000)
  1266. #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  1267. SNDRV_PCM_FMTBIT_S20_3LE |\
  1268. SNDRV_PCM_FMTBIT_S24_LE)
  1269. struct snd_soc_dai wm8903_dai = {
  1270. .name = "WM8903",
  1271. .playback = {
  1272. .stream_name = "Playback",
  1273. .channels_min = 2,
  1274. .channels_max = 2,
  1275. .rates = WM8903_PLAYBACK_RATES,
  1276. .formats = WM8903_FORMATS,
  1277. },
  1278. .capture = {
  1279. .stream_name = "Capture",
  1280. .channels_min = 2,
  1281. .channels_max = 2,
  1282. .rates = WM8903_CAPTURE_RATES,
  1283. .formats = WM8903_FORMATS,
  1284. },
  1285. .ops = {
  1286. .startup = wm8903_startup,
  1287. .shutdown = wm8903_shutdown,
  1288. .hw_params = wm8903_hw_params,
  1289. },
  1290. .dai_ops = {
  1291. .digital_mute = wm8903_digital_mute,
  1292. .set_fmt = wm8903_set_dai_fmt,
  1293. .set_sysclk = wm8903_set_dai_sysclk
  1294. }
  1295. };
  1296. EXPORT_SYMBOL_GPL(wm8903_dai);
  1297. static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
  1298. {
  1299. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1300. struct snd_soc_codec *codec = socdev->codec;
  1301. wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1302. return 0;
  1303. }
  1304. static int wm8903_resume(struct platform_device *pdev)
  1305. {
  1306. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1307. struct snd_soc_codec *codec = socdev->codec;
  1308. struct i2c_client *i2c = codec->control_data;
  1309. int i;
  1310. u16 *reg_cache = codec->reg_cache;
  1311. u16 *tmp_cache = kmemdup(codec->reg_cache, sizeof(wm8903_reg_defaults),
  1312. GFP_KERNEL);
  1313. /* Bring the codec back up to standby first to minimise pop/clicks */
  1314. wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1315. wm8903_set_bias_level(codec, codec->suspend_bias_level);
  1316. /* Sync back everything else */
  1317. if (tmp_cache) {
  1318. for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
  1319. if (tmp_cache[i] != reg_cache[i])
  1320. wm8903_write(codec, i, tmp_cache[i]);
  1321. } else {
  1322. dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
  1323. }
  1324. return 0;
  1325. }
  1326. /*
  1327. * initialise the WM8903 driver
  1328. * register the mixer and dsp interfaces with the kernel
  1329. */
  1330. static int wm8903_init(struct snd_soc_device *socdev)
  1331. {
  1332. struct snd_soc_codec *codec = socdev->codec;
  1333. struct i2c_client *i2c = codec->control_data;
  1334. int ret = 0;
  1335. u16 val;
  1336. val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID);
  1337. if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
  1338. dev_err(&i2c->dev,
  1339. "Device with ID register %x is not a WM8903\n", val);
  1340. return -ENODEV;
  1341. }
  1342. codec->name = "WM8903";
  1343. codec->owner = THIS_MODULE;
  1344. codec->read = wm8903_read;
  1345. codec->write = wm8903_write;
  1346. codec->bias_level = SND_SOC_BIAS_OFF;
  1347. codec->set_bias_level = wm8903_set_bias_level;
  1348. codec->dai = &wm8903_dai;
  1349. codec->num_dai = 1;
  1350. codec->reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults);
  1351. codec->reg_cache = kmemdup(wm8903_reg_defaults,
  1352. sizeof(wm8903_reg_defaults),
  1353. GFP_KERNEL);
  1354. if (codec->reg_cache == NULL) {
  1355. dev_err(&i2c->dev, "Failed to allocate register cache\n");
  1356. return -ENOMEM;
  1357. }
  1358. val = wm8903_read(codec, WM8903_REVISION_NUMBER);
  1359. dev_info(&i2c->dev, "WM8903 revision %d\n",
  1360. val & WM8903_CHIP_REV_MASK);
  1361. wm8903_reset(codec);
  1362. /* register pcms */
  1363. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1364. if (ret < 0) {
  1365. dev_err(&i2c->dev, "failed to create pcms\n");
  1366. goto pcm_err;
  1367. }
  1368. /* SYSCLK is required for pretty much anything */
  1369. wm8903_write(codec, WM8903_CLOCK_RATES_2, WM8903_CLK_SYS_ENA);
  1370. /* power on device */
  1371. wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1372. /* Latch volume update bits */
  1373. val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
  1374. val |= WM8903_ADCVU;
  1375. wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
  1376. wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
  1377. val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
  1378. val |= WM8903_DACVU;
  1379. wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
  1380. wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
  1381. val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
  1382. val |= WM8903_HPOUTVU;
  1383. wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
  1384. wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
  1385. val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
  1386. val |= WM8903_LINEOUTVU;
  1387. wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
  1388. wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
  1389. val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
  1390. val |= WM8903_SPKVU;
  1391. wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
  1392. wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
  1393. /* Enable DAC soft mute by default */
  1394. val = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
  1395. val |= WM8903_DAC_MUTEMODE;
  1396. wm8903_write(codec, WM8903_DAC_DIGITAL_1, val);
  1397. wm8903_add_controls(codec);
  1398. wm8903_add_widgets(codec);
  1399. ret = snd_soc_register_card(socdev);
  1400. if (ret < 0) {
  1401. dev_err(&i2c->dev, "wm8903: failed to register card\n");
  1402. goto card_err;
  1403. }
  1404. return ret;
  1405. card_err:
  1406. snd_soc_free_pcms(socdev);
  1407. snd_soc_dapm_free(socdev);
  1408. pcm_err:
  1409. kfree(codec->reg_cache);
  1410. return ret;
  1411. }
  1412. static struct snd_soc_device *wm8903_socdev;
  1413. static int wm8903_i2c_probe(struct i2c_client *i2c,
  1414. const struct i2c_device_id *id)
  1415. {
  1416. struct snd_soc_device *socdev = wm8903_socdev;
  1417. struct snd_soc_codec *codec = socdev->codec;
  1418. int ret;
  1419. i2c_set_clientdata(i2c, codec);
  1420. codec->control_data = i2c;
  1421. ret = wm8903_init(socdev);
  1422. if (ret < 0)
  1423. dev_err(&i2c->dev, "Device initialisation failed\n");
  1424. return ret;
  1425. }
  1426. static int wm8903_i2c_remove(struct i2c_client *client)
  1427. {
  1428. struct snd_soc_codec *codec = i2c_get_clientdata(client);
  1429. kfree(codec->reg_cache);
  1430. return 0;
  1431. }
  1432. /* i2c codec control layer */
  1433. static const struct i2c_device_id wm8903_i2c_id[] = {
  1434. { "wm8903", 0 },
  1435. { }
  1436. };
  1437. MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
  1438. static struct i2c_driver wm8903_i2c_driver = {
  1439. .driver = {
  1440. .name = "WM8903",
  1441. .owner = THIS_MODULE,
  1442. },
  1443. .probe = wm8903_i2c_probe,
  1444. .remove = wm8903_i2c_remove,
  1445. .id_table = wm8903_i2c_id,
  1446. };
  1447. static int wm8903_probe(struct platform_device *pdev)
  1448. {
  1449. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1450. struct wm8903_setup_data *setup;
  1451. struct snd_soc_codec *codec;
  1452. struct wm8903_priv *wm8903;
  1453. struct i2c_board_info board_info;
  1454. struct i2c_adapter *adapter;
  1455. struct i2c_client *i2c_client;
  1456. int ret = 0;
  1457. setup = socdev->codec_data;
  1458. if (!setup->i2c_address) {
  1459. dev_err(&pdev->dev, "No codec address provided\n");
  1460. return -ENODEV;
  1461. }
  1462. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1463. if (codec == NULL)
  1464. return -ENOMEM;
  1465. wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
  1466. if (wm8903 == NULL) {
  1467. ret = -ENOMEM;
  1468. goto err_codec;
  1469. }
  1470. codec->private_data = wm8903;
  1471. socdev->codec = codec;
  1472. mutex_init(&codec->mutex);
  1473. INIT_LIST_HEAD(&codec->dapm_widgets);
  1474. INIT_LIST_HEAD(&codec->dapm_paths);
  1475. wm8903_socdev = socdev;
  1476. codec->hw_write = (hw_write_t)i2c_master_send;
  1477. ret = i2c_add_driver(&wm8903_i2c_driver);
  1478. if (ret != 0) {
  1479. dev_err(&pdev->dev, "can't add i2c driver\n");
  1480. goto err_priv;
  1481. } else {
  1482. memset(&board_info, 0, sizeof(board_info));
  1483. strlcpy(board_info.type, "wm8903", I2C_NAME_SIZE);
  1484. board_info.addr = setup->i2c_address;
  1485. adapter = i2c_get_adapter(setup->i2c_bus);
  1486. if (!adapter) {
  1487. dev_err(&pdev->dev, "Can't get I2C bus %d\n",
  1488. setup->i2c_bus);
  1489. ret = -ENODEV;
  1490. goto err_adapter;
  1491. }
  1492. i2c_client = i2c_new_device(adapter, &board_info);
  1493. i2c_put_adapter(adapter);
  1494. if (i2c_client == NULL) {
  1495. dev_err(&pdev->dev,
  1496. "I2C driver registration failed\n");
  1497. ret = -ENODEV;
  1498. goto err_adapter;
  1499. }
  1500. }
  1501. return ret;
  1502. err_adapter:
  1503. i2c_del_driver(&wm8903_i2c_driver);
  1504. err_priv:
  1505. kfree(codec->private_data);
  1506. err_codec:
  1507. kfree(codec);
  1508. return ret;
  1509. }
  1510. /* power down chip */
  1511. static int wm8903_remove(struct platform_device *pdev)
  1512. {
  1513. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1514. struct snd_soc_codec *codec = socdev->codec;
  1515. if (codec->control_data)
  1516. wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1517. snd_soc_free_pcms(socdev);
  1518. snd_soc_dapm_free(socdev);
  1519. i2c_unregister_device(socdev->codec->control_data);
  1520. i2c_del_driver(&wm8903_i2c_driver);
  1521. kfree(codec->private_data);
  1522. kfree(codec);
  1523. return 0;
  1524. }
  1525. struct snd_soc_codec_device soc_codec_dev_wm8903 = {
  1526. .probe = wm8903_probe,
  1527. .remove = wm8903_remove,
  1528. .suspend = wm8903_suspend,
  1529. .resume = wm8903_resume,
  1530. };
  1531. EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
  1532. MODULE_DESCRIPTION("ASoC WM8903 driver");
  1533. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
  1534. MODULE_LICENSE("GPL");