at32-ssc.c 21 KB

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  1. /* sound/soc/at32/at32-ssc.c
  2. * ASoC platform driver for AT32 using SSC as DAI
  3. *
  4. * Copyright (C) 2008 Long Range Systems
  5. * Geoffrey Wossum <gwossum@acm.org>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Note that this is basically a port of the sound/soc/at91-ssc.c to
  12. * the AVR32 kernel. Thanks to Frank Mandarino for that code.
  13. */
  14. /* #define DEBUG */
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/device.h>
  19. #include <linux/delay.h>
  20. #include <linux/clk.h>
  21. #include <linux/io.h>
  22. #include <linux/atmel_pdc.h>
  23. #include <linux/atmel-ssc.h>
  24. #include <sound/core.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include <sound/initval.h>
  28. #include <sound/soc.h>
  29. #include "at32-pcm.h"
  30. #include "at32-ssc.h"
  31. /*-------------------------------------------------------------------------*\
  32. * Constants
  33. \*-------------------------------------------------------------------------*/
  34. #define NUM_SSC_DEVICES 3
  35. /*
  36. * SSC direction masks
  37. */
  38. #define SSC_DIR_MASK_UNUSED 0
  39. #define SSC_DIR_MASK_PLAYBACK 1
  40. #define SSC_DIR_MASK_CAPTURE 2
  41. /*
  42. * SSC register values that Atmel left out of <linux/atmel-ssc.h>. These
  43. * are expected to be used with SSC_BF
  44. */
  45. /* START bit field values */
  46. #define SSC_START_CONTINUOUS 0
  47. #define SSC_START_TX_RX 1
  48. #define SSC_START_LOW_RF 2
  49. #define SSC_START_HIGH_RF 3
  50. #define SSC_START_FALLING_RF 4
  51. #define SSC_START_RISING_RF 5
  52. #define SSC_START_LEVEL_RF 6
  53. #define SSC_START_EDGE_RF 7
  54. #define SSS_START_COMPARE_0 8
  55. /* CKI bit field values */
  56. #define SSC_CKI_FALLING 0
  57. #define SSC_CKI_RISING 1
  58. /* CKO bit field values */
  59. #define SSC_CKO_NONE 0
  60. #define SSC_CKO_CONTINUOUS 1
  61. #define SSC_CKO_TRANSFER 2
  62. /* CKS bit field values */
  63. #define SSC_CKS_DIV 0
  64. #define SSC_CKS_CLOCK 1
  65. #define SSC_CKS_PIN 2
  66. /* FSEDGE bit field values */
  67. #define SSC_FSEDGE_POSITIVE 0
  68. #define SSC_FSEDGE_NEGATIVE 1
  69. /* FSOS bit field values */
  70. #define SSC_FSOS_NONE 0
  71. #define SSC_FSOS_NEGATIVE 1
  72. #define SSC_FSOS_POSITIVE 2
  73. #define SSC_FSOS_LOW 3
  74. #define SSC_FSOS_HIGH 4
  75. #define SSC_FSOS_TOGGLE 5
  76. #define START_DELAY 1
  77. /*-------------------------------------------------------------------------*\
  78. * Module data
  79. \*-------------------------------------------------------------------------*/
  80. /*
  81. * SSC PDC registered required by the PCM DMA engine
  82. */
  83. static struct at32_pdc_regs pdc_tx_reg = {
  84. .xpr = SSC_PDC_TPR,
  85. .xcr = SSC_PDC_TCR,
  86. .xnpr = SSC_PDC_TNPR,
  87. .xncr = SSC_PDC_TNCR,
  88. };
  89. static struct at32_pdc_regs pdc_rx_reg = {
  90. .xpr = SSC_PDC_RPR,
  91. .xcr = SSC_PDC_RCR,
  92. .xnpr = SSC_PDC_RNPR,
  93. .xncr = SSC_PDC_RNCR,
  94. };
  95. /*
  96. * SSC and PDC status bits for transmit and receive
  97. */
  98. static struct at32_ssc_mask ssc_tx_mask = {
  99. .ssc_enable = SSC_BIT(CR_TXEN),
  100. .ssc_disable = SSC_BIT(CR_TXDIS),
  101. .ssc_endx = SSC_BIT(SR_ENDTX),
  102. .ssc_endbuf = SSC_BIT(SR_TXBUFE),
  103. .pdc_enable = SSC_BIT(PDC_PTCR_TXTEN),
  104. .pdc_disable = SSC_BIT(PDC_PTCR_TXTDIS),
  105. };
  106. static struct at32_ssc_mask ssc_rx_mask = {
  107. .ssc_enable = SSC_BIT(CR_RXEN),
  108. .ssc_disable = SSC_BIT(CR_RXDIS),
  109. .ssc_endx = SSC_BIT(SR_ENDRX),
  110. .ssc_endbuf = SSC_BIT(SR_RXBUFF),
  111. .pdc_enable = SSC_BIT(PDC_PTCR_RXTEN),
  112. .pdc_disable = SSC_BIT(PDC_PTCR_RXTDIS),
  113. };
  114. /*
  115. * DMA parameters for each SSC
  116. */
  117. static struct at32_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
  118. {
  119. {
  120. .name = "SSC0 PCM out",
  121. .pdc = &pdc_tx_reg,
  122. .mask = &ssc_tx_mask,
  123. },
  124. {
  125. .name = "SSC0 PCM in",
  126. .pdc = &pdc_rx_reg,
  127. .mask = &ssc_rx_mask,
  128. },
  129. },
  130. {
  131. {
  132. .name = "SSC1 PCM out",
  133. .pdc = &pdc_tx_reg,
  134. .mask = &ssc_tx_mask,
  135. },
  136. {
  137. .name = "SSC1 PCM in",
  138. .pdc = &pdc_rx_reg,
  139. .mask = &ssc_rx_mask,
  140. },
  141. },
  142. {
  143. {
  144. .name = "SSC2 PCM out",
  145. .pdc = &pdc_tx_reg,
  146. .mask = &ssc_tx_mask,
  147. },
  148. {
  149. .name = "SSC2 PCM in",
  150. .pdc = &pdc_rx_reg,
  151. .mask = &ssc_rx_mask,
  152. },
  153. },
  154. };
  155. static struct at32_ssc_info ssc_info[NUM_SSC_DEVICES] = {
  156. {
  157. .name = "ssc0",
  158. .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
  159. .dir_mask = SSC_DIR_MASK_UNUSED,
  160. .initialized = 0,
  161. },
  162. {
  163. .name = "ssc1",
  164. .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
  165. .dir_mask = SSC_DIR_MASK_UNUSED,
  166. .initialized = 0,
  167. },
  168. {
  169. .name = "ssc2",
  170. .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
  171. .dir_mask = SSC_DIR_MASK_UNUSED,
  172. .initialized = 0,
  173. },
  174. };
  175. /*-------------------------------------------------------------------------*\
  176. * ISR
  177. \*-------------------------------------------------------------------------*/
  178. /*
  179. * SSC interrupt handler. Passes PDC interrupts to the DMA interrupt
  180. * handler in the PCM driver.
  181. */
  182. static irqreturn_t at32_ssc_interrupt(int irq, void *dev_id)
  183. {
  184. struct at32_ssc_info *ssc_p = dev_id;
  185. struct at32_pcm_dma_params *dma_params;
  186. u32 ssc_sr;
  187. u32 ssc_substream_mask;
  188. int i;
  189. ssc_sr = (ssc_readl(ssc_p->ssc->regs, SR) &
  190. ssc_readl(ssc_p->ssc->regs, IMR));
  191. /*
  192. * Loop through substreams attached to this SSC. If a DMA-related
  193. * interrupt occured on that substream, call the DMA interrupt
  194. * handler function, if one has been registered in the dma_param
  195. * structure by the PCM driver.
  196. */
  197. for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
  198. dma_params = ssc_p->dma_params[i];
  199. if ((dma_params != NULL) &&
  200. (dma_params->dma_intr_handler != NULL)) {
  201. ssc_substream_mask = (dma_params->mask->ssc_endx |
  202. dma_params->mask->ssc_endbuf);
  203. if (ssc_sr & ssc_substream_mask) {
  204. dma_params->dma_intr_handler(ssc_sr,
  205. dma_params->
  206. substream);
  207. }
  208. }
  209. }
  210. return IRQ_HANDLED;
  211. }
  212. /*-------------------------------------------------------------------------*\
  213. * DAI functions
  214. \*-------------------------------------------------------------------------*/
  215. /*
  216. * Startup. Only that one substream allowed in each direction.
  217. */
  218. static int at32_ssc_startup(struct snd_pcm_substream *substream)
  219. {
  220. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  221. struct at32_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
  222. int dir_mask;
  223. dir_mask = ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
  224. SSC_DIR_MASK_PLAYBACK : SSC_DIR_MASK_CAPTURE);
  225. spin_lock_irq(&ssc_p->lock);
  226. if (ssc_p->dir_mask & dir_mask) {
  227. spin_unlock_irq(&ssc_p->lock);
  228. return -EBUSY;
  229. }
  230. ssc_p->dir_mask |= dir_mask;
  231. spin_unlock_irq(&ssc_p->lock);
  232. return 0;
  233. }
  234. /*
  235. * Shutdown. Clear DMA parameters and shutdown the SSC if there
  236. * are no other substreams open.
  237. */
  238. static void at32_ssc_shutdown(struct snd_pcm_substream *substream)
  239. {
  240. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  241. struct at32_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
  242. struct at32_pcm_dma_params *dma_params;
  243. int dir_mask;
  244. dma_params = ssc_p->dma_params[substream->stream];
  245. if (dma_params != NULL) {
  246. ssc_writel(dma_params->ssc->regs, CR,
  247. dma_params->mask->ssc_disable);
  248. pr_debug("%s disabled SSC_SR=0x%08x\n",
  249. (substream->stream ? "receiver" : "transmit"),
  250. ssc_readl(ssc_p->ssc->regs, SR));
  251. dma_params->ssc = NULL;
  252. dma_params->substream = NULL;
  253. ssc_p->dma_params[substream->stream] = NULL;
  254. }
  255. dir_mask = 1 << substream->stream;
  256. spin_lock_irq(&ssc_p->lock);
  257. ssc_p->dir_mask &= ~dir_mask;
  258. if (!ssc_p->dir_mask) {
  259. /* Shutdown the SSC clock */
  260. pr_debug("at32-ssc: Stopping user %d clock\n",
  261. ssc_p->ssc->user);
  262. clk_disable(ssc_p->ssc->clk);
  263. if (ssc_p->initialized) {
  264. free_irq(ssc_p->ssc->irq, ssc_p);
  265. ssc_p->initialized = 0;
  266. }
  267. /* Reset the SSC */
  268. ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
  269. /* clear the SSC dividers */
  270. ssc_p->cmr_div = 0;
  271. ssc_p->tcmr_period = 0;
  272. ssc_p->rcmr_period = 0;
  273. }
  274. spin_unlock_irq(&ssc_p->lock);
  275. }
  276. /*
  277. * Set the SSC system clock rate
  278. */
  279. static int at32_ssc_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  280. int clk_id, unsigned int freq, int dir)
  281. {
  282. /* TODO: What the heck do I do here? */
  283. return 0;
  284. }
  285. /*
  286. * Record DAI format for use by hw_params()
  287. */
  288. static int at32_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  289. unsigned int fmt)
  290. {
  291. struct at32_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
  292. ssc_p->daifmt = fmt;
  293. return 0;
  294. }
  295. /*
  296. * Record SSC clock dividers for use in hw_params()
  297. */
  298. static int at32_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
  299. int div_id, int div)
  300. {
  301. struct at32_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
  302. switch (div_id) {
  303. case AT32_SSC_CMR_DIV:
  304. /*
  305. * The same master clock divider is used for both
  306. * transmit and receive, so if a value has already
  307. * been set, it must match this value
  308. */
  309. if (ssc_p->cmr_div == 0)
  310. ssc_p->cmr_div = div;
  311. else if (div != ssc_p->cmr_div)
  312. return -EBUSY;
  313. break;
  314. case AT32_SSC_TCMR_PERIOD:
  315. ssc_p->tcmr_period = div;
  316. break;
  317. case AT32_SSC_RCMR_PERIOD:
  318. ssc_p->rcmr_period = div;
  319. break;
  320. default:
  321. return -EINVAL;
  322. }
  323. return 0;
  324. }
  325. /*
  326. * Configure the SSC
  327. */
  328. static int at32_ssc_hw_params(struct snd_pcm_substream *substream,
  329. struct snd_pcm_hw_params *params)
  330. {
  331. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  332. int id = rtd->dai->cpu_dai->id;
  333. struct at32_ssc_info *ssc_p = &ssc_info[id];
  334. struct at32_pcm_dma_params *dma_params;
  335. int channels, bits;
  336. u32 tfmr, rfmr, tcmr, rcmr;
  337. int start_event;
  338. int ret;
  339. /*
  340. * Currently, there is only one set of dma_params for each direction.
  341. * If more are added, this code will have to be changed to select
  342. * the proper set
  343. */
  344. dma_params = &ssc_dma_params[id][substream->stream];
  345. dma_params->ssc = ssc_p->ssc;
  346. dma_params->substream = substream;
  347. ssc_p->dma_params[substream->stream] = dma_params;
  348. /*
  349. * The cpu_dai->dma_data field is only used to communicate the
  350. * appropriate DMA parameters to the PCM driver's hw_params()
  351. * function. It should not be used for other purposes as it
  352. * is common to all substreams.
  353. */
  354. rtd->dai->cpu_dai->dma_data = dma_params;
  355. channels = params_channels(params);
  356. /*
  357. * Determine sample size in bits and the PDC increment
  358. */
  359. switch (params_format(params)) {
  360. case SNDRV_PCM_FORMAT_S8:
  361. bits = 8;
  362. dma_params->pdc_xfer_size = 1;
  363. break;
  364. case SNDRV_PCM_FORMAT_S16:
  365. bits = 16;
  366. dma_params->pdc_xfer_size = 2;
  367. break;
  368. case SNDRV_PCM_FORMAT_S24:
  369. bits = 24;
  370. dma_params->pdc_xfer_size = 4;
  371. break;
  372. case SNDRV_PCM_FORMAT_S32:
  373. bits = 32;
  374. dma_params->pdc_xfer_size = 4;
  375. break;
  376. default:
  377. pr_warning("at32-ssc: Unsupported PCM format %d",
  378. params_format(params));
  379. return -EINVAL;
  380. }
  381. pr_debug("at32-ssc: bits = %d, pdc_xfer_size = %d, channels = %d\n",
  382. bits, dma_params->pdc_xfer_size, channels);
  383. /*
  384. * The SSC only supports up to 16-bit samples in I2S format, due
  385. * to the size of the Frame Mode Register FSLEN field.
  386. */
  387. if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S)
  388. if (bits > 16) {
  389. pr_warning("at32-ssc: "
  390. "sample size %d is too large for I2S\n",
  391. bits);
  392. return -EINVAL;
  393. }
  394. /*
  395. * Compute the SSC register settings
  396. */
  397. switch (ssc_p->daifmt & (SND_SOC_DAIFMT_FORMAT_MASK |
  398. SND_SOC_DAIFMT_MASTER_MASK)) {
  399. case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
  400. /*
  401. * I2S format, SSC provides BCLK and LRS clocks.
  402. *
  403. * The SSC transmit and receive clocks are generated from the
  404. * MCK divider, and the BCLK signal is output on the SSC TK line
  405. */
  406. pr_debug("at32-ssc: SSC mode is I2S BCLK / FRAME master\n");
  407. rcmr = (SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) |
  408. SSC_BF(RCMR_STTDLY, START_DELAY) |
  409. SSC_BF(RCMR_START, SSC_START_FALLING_RF) |
  410. SSC_BF(RCMR_CKI, SSC_CKI_RISING) |
  411. SSC_BF(RCMR_CKO, SSC_CKO_NONE) |
  412. SSC_BF(RCMR_CKS, SSC_CKS_DIV));
  413. rfmr = (SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
  414. SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) |
  415. SSC_BF(RFMR_FSLEN, bits - 1) |
  416. SSC_BF(RFMR_DATNB, channels - 1) |
  417. SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_DATLEN, bits - 1));
  418. tcmr = (SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) |
  419. SSC_BF(TCMR_STTDLY, START_DELAY) |
  420. SSC_BF(TCMR_START, SSC_START_FALLING_RF) |
  421. SSC_BF(TCMR_CKI, SSC_CKI_FALLING) |
  422. SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) |
  423. SSC_BF(TCMR_CKS, SSC_CKS_DIV));
  424. tfmr = (SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
  425. SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) |
  426. SSC_BF(TFMR_FSLEN, bits - 1) |
  427. SSC_BF(TFMR_DATNB, channels - 1) | SSC_BIT(TFMR_MSBF) |
  428. SSC_BF(TFMR_DATLEN, bits - 1));
  429. break;
  430. case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
  431. /*
  432. * I2S format, CODEC supplies BCLK and LRC clock.
  433. *
  434. * The SSC transmit clock is obtained from the BCLK signal
  435. * on the TK line, and the SSC receive clock is generated from
  436. * the transmit clock.
  437. *
  438. * For single channel data, one sample is transferred on the
  439. * falling edge of the LRC clock. For two channel data, one
  440. * sample is transferred on both edges of the LRC clock.
  441. */
  442. pr_debug("at32-ssc: SSC mode is I2S BCLK / FRAME slave\n");
  443. start_event = ((channels == 1) ?
  444. SSC_START_FALLING_RF : SSC_START_EDGE_RF);
  445. rcmr = (SSC_BF(RCMR_STTDLY, START_DELAY) |
  446. SSC_BF(RCMR_START, start_event) |
  447. SSC_BF(RCMR_CKI, SSC_CKI_RISING) |
  448. SSC_BF(RCMR_CKO, SSC_CKO_NONE) |
  449. SSC_BF(RCMR_CKS, SSC_CKS_CLOCK));
  450. rfmr = (SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
  451. SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) |
  452. SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_DATLEN, bits - 1));
  453. tcmr = (SSC_BF(TCMR_STTDLY, START_DELAY) |
  454. SSC_BF(TCMR_START, start_event) |
  455. SSC_BF(TCMR_CKI, SSC_CKI_FALLING) |
  456. SSC_BF(TCMR_CKO, SSC_CKO_NONE) |
  457. SSC_BF(TCMR_CKS, SSC_CKS_PIN));
  458. tfmr = (SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
  459. SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) |
  460. SSC_BIT(TFMR_MSBF) | SSC_BF(TFMR_DATLEN, bits - 1));
  461. break;
  462. case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
  463. /*
  464. * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
  465. *
  466. * The SSC transmit and receive clocks are generated from the
  467. * MCK divider, and the BCLK signal is output on the SSC TK line
  468. */
  469. pr_debug("at32-ssc: SSC mode is DSP A BCLK / FRAME master\n");
  470. rcmr = (SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) |
  471. SSC_BF(RCMR_STTDLY, 1) |
  472. SSC_BF(RCMR_START, SSC_START_RISING_RF) |
  473. SSC_BF(RCMR_CKI, SSC_CKI_RISING) |
  474. SSC_BF(RCMR_CKO, SSC_CKO_NONE) |
  475. SSC_BF(RCMR_CKS, SSC_CKS_DIV));
  476. rfmr = (SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
  477. SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE) |
  478. SSC_BF(RFMR_DATNB, channels - 1) |
  479. SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_DATLEN, bits - 1));
  480. tcmr = (SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) |
  481. SSC_BF(TCMR_STTDLY, 1) |
  482. SSC_BF(TCMR_START, SSC_START_RISING_RF) |
  483. SSC_BF(TCMR_CKI, SSC_CKI_RISING) |
  484. SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) |
  485. SSC_BF(TCMR_CKS, SSC_CKS_DIV));
  486. tfmr = (SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
  487. SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE) |
  488. SSC_BF(TFMR_DATNB, channels - 1) |
  489. SSC_BIT(TFMR_MSBF) | SSC_BF(TFMR_DATLEN, bits - 1));
  490. break;
  491. case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
  492. default:
  493. pr_warning("at32-ssc: unsupported DAI format 0x%x\n",
  494. ssc_p->daifmt);
  495. return -EINVAL;
  496. break;
  497. }
  498. pr_debug("at32-ssc: RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
  499. rcmr, rfmr, tcmr, tfmr);
  500. if (!ssc_p->initialized) {
  501. /* enable peripheral clock */
  502. pr_debug("at32-ssc: Starting clock\n");
  503. clk_enable(ssc_p->ssc->clk);
  504. /* Reset the SSC and its PDC registers */
  505. ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
  506. ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
  507. ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
  508. ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
  509. ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
  510. ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
  511. ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
  512. ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
  513. ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
  514. ret = request_irq(ssc_p->ssc->irq, at32_ssc_interrupt, 0,
  515. ssc_p->name, ssc_p);
  516. if (ret < 0) {
  517. pr_warning("at32-ssc: request irq failed (%d)\n", ret);
  518. pr_debug("at32-ssc: Stopping clock\n");
  519. clk_disable(ssc_p->ssc->clk);
  520. return ret;
  521. }
  522. ssc_p->initialized = 1;
  523. }
  524. /* Set SSC clock mode register */
  525. ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
  526. /* set receive clock mode and format */
  527. ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
  528. ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
  529. /* set transmit clock mode and format */
  530. ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
  531. ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
  532. pr_debug("at32-ssc: SSC initialized\n");
  533. return 0;
  534. }
  535. static int at32_ssc_prepare(struct snd_pcm_substream *substream)
  536. {
  537. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  538. struct at32_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
  539. struct at32_pcm_dma_params *dma_params;
  540. dma_params = ssc_p->dma_params[substream->stream];
  541. ssc_writel(dma_params->ssc->regs, CR, dma_params->mask->ssc_enable);
  542. return 0;
  543. }
  544. #ifdef CONFIG_PM
  545. static int at32_ssc_suspend(struct platform_device *pdev,
  546. struct snd_soc_dai *cpu_dai)
  547. {
  548. struct at32_ssc_info *ssc_p;
  549. if (!cpu_dai->active)
  550. return 0;
  551. ssc_p = &ssc_info[cpu_dai->id];
  552. /* Save the status register before disabling transmit and receive */
  553. ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
  554. ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
  555. /* Save the current interrupt mask, then disable unmasked interrupts */
  556. ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
  557. ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
  558. ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
  559. ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
  560. ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
  561. ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
  562. ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
  563. return 0;
  564. }
  565. static int at32_ssc_resume(struct platform_device *pdev,
  566. struct snd_soc_dai *cpu_dai)
  567. {
  568. struct at32_ssc_info *ssc_p;
  569. u32 cr;
  570. if (!cpu_dai->active)
  571. return 0;
  572. ssc_p = &ssc_info[cpu_dai->id];
  573. /* restore SSC register settings */
  574. ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
  575. ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
  576. ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
  577. ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
  578. ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
  579. /* re-enable interrupts */
  580. ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
  581. /* Re-enable recieve and transmit as appropriate */
  582. cr = 0;
  583. cr |=
  584. (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
  585. cr |=
  586. (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
  587. ssc_writel(ssc_p->ssc->regs, CR, cr);
  588. return 0;
  589. }
  590. #else /* CONFIG_PM */
  591. # define at32_ssc_suspend NULL
  592. # define at32_ssc_resume NULL
  593. #endif /* CONFIG_PM */
  594. #define AT32_SSC_RATES \
  595. (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
  596. SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  597. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  598. #define AT32_SSC_FORMATS \
  599. (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16 | \
  600. SNDRV_PCM_FMTBIT_S24 | SNDRV_PCM_FMTBIT_S32)
  601. struct snd_soc_dai at32_ssc_dai[NUM_SSC_DEVICES] = {
  602. {
  603. .name = "at32-ssc0",
  604. .id = 0,
  605. .type = SND_SOC_DAI_PCM,
  606. .suspend = at32_ssc_suspend,
  607. .resume = at32_ssc_resume,
  608. .playback = {
  609. .channels_min = 1,
  610. .channels_max = 2,
  611. .rates = AT32_SSC_RATES,
  612. .formats = AT32_SSC_FORMATS,
  613. },
  614. .capture = {
  615. .channels_min = 1,
  616. .channels_max = 2,
  617. .rates = AT32_SSC_RATES,
  618. .formats = AT32_SSC_FORMATS,
  619. },
  620. .ops = {
  621. .startup = at32_ssc_startup,
  622. .shutdown = at32_ssc_shutdown,
  623. .prepare = at32_ssc_prepare,
  624. .hw_params = at32_ssc_hw_params,
  625. },
  626. .dai_ops = {
  627. .set_sysclk = at32_ssc_set_dai_sysclk,
  628. .set_fmt = at32_ssc_set_dai_fmt,
  629. .set_clkdiv = at32_ssc_set_dai_clkdiv,
  630. },
  631. .private_data = &ssc_info[0],
  632. },
  633. {
  634. .name = "at32-ssc1",
  635. .id = 1,
  636. .type = SND_SOC_DAI_PCM,
  637. .suspend = at32_ssc_suspend,
  638. .resume = at32_ssc_resume,
  639. .playback = {
  640. .channels_min = 1,
  641. .channels_max = 2,
  642. .rates = AT32_SSC_RATES,
  643. .formats = AT32_SSC_FORMATS,
  644. },
  645. .capture = {
  646. .channels_min = 1,
  647. .channels_max = 2,
  648. .rates = AT32_SSC_RATES,
  649. .formats = AT32_SSC_FORMATS,
  650. },
  651. .ops = {
  652. .startup = at32_ssc_startup,
  653. .shutdown = at32_ssc_shutdown,
  654. .prepare = at32_ssc_prepare,
  655. .hw_params = at32_ssc_hw_params,
  656. },
  657. .dai_ops = {
  658. .set_sysclk = at32_ssc_set_dai_sysclk,
  659. .set_fmt = at32_ssc_set_dai_fmt,
  660. .set_clkdiv = at32_ssc_set_dai_clkdiv,
  661. },
  662. .private_data = &ssc_info[1],
  663. },
  664. {
  665. .name = "at32-ssc2",
  666. .id = 2,
  667. .type = SND_SOC_DAI_PCM,
  668. .suspend = at32_ssc_suspend,
  669. .resume = at32_ssc_resume,
  670. .playback = {
  671. .channels_min = 1,
  672. .channels_max = 2,
  673. .rates = AT32_SSC_RATES,
  674. .formats = AT32_SSC_FORMATS,
  675. },
  676. .capture = {
  677. .channels_min = 1,
  678. .channels_max = 2,
  679. .rates = AT32_SSC_RATES,
  680. .formats = AT32_SSC_FORMATS,
  681. },
  682. .ops = {
  683. .startup = at32_ssc_startup,
  684. .shutdown = at32_ssc_shutdown,
  685. .prepare = at32_ssc_prepare,
  686. .hw_params = at32_ssc_hw_params,
  687. },
  688. .dai_ops = {
  689. .set_sysclk = at32_ssc_set_dai_sysclk,
  690. .set_fmt = at32_ssc_set_dai_fmt,
  691. .set_clkdiv = at32_ssc_set_dai_clkdiv,
  692. },
  693. .private_data = &ssc_info[2],
  694. },
  695. };
  696. EXPORT_SYMBOL_GPL(at32_ssc_dai);
  697. MODULE_AUTHOR("Geoffrey Wossum <gwossum@acm.org>");
  698. MODULE_DESCRIPTION("AT32 SSC ASoC Interface");
  699. MODULE_LICENSE("GPL");