isp1760-hcd.c 54 KB

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  1. /*
  2. * Driver for the NXP ISP1760 chip
  3. *
  4. * However, the code might contain some bugs. What doesn't work for sure is:
  5. * - ISO
  6. * - OTG
  7. e The interrupt line is configured as active low, level.
  8. *
  9. * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  10. *
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/slab.h>
  15. #include <linux/list.h>
  16. #include <linux/usb.h>
  17. #include <linux/debugfs.h>
  18. #include <linux/uaccess.h>
  19. #include <linux/io.h>
  20. #include <asm/unaligned.h>
  21. #include "../core/hcd.h"
  22. #include "isp1760-hcd.h"
  23. static struct kmem_cache *qtd_cachep;
  24. static struct kmem_cache *qh_cachep;
  25. struct isp1760_hcd {
  26. u32 hcs_params;
  27. spinlock_t lock;
  28. struct inter_packet_info atl_ints[32];
  29. struct inter_packet_info int_ints[32];
  30. struct memory_chunk memory_pool[BLOCKS];
  31. /* periodic schedule support */
  32. #define DEFAULT_I_TDPS 1024
  33. unsigned periodic_size;
  34. unsigned i_thresh;
  35. unsigned long reset_done;
  36. unsigned long next_statechange;
  37. unsigned int devflags;
  38. };
  39. static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  40. {
  41. return (struct isp1760_hcd *) (hcd->hcd_priv);
  42. }
  43. static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv)
  44. {
  45. return container_of((void *) priv, struct usb_hcd, hcd_priv);
  46. }
  47. /* Section 2.2 Host Controller Capability Registers */
  48. #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
  49. #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
  50. #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
  51. #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
  52. #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
  53. #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
  54. #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
  55. /* Section 2.3 Host Controller Operational Registers */
  56. #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
  57. #define CMD_RESET (1<<1) /* reset HC not bus */
  58. #define CMD_RUN (1<<0) /* start/stop HC */
  59. #define STS_PCD (1<<2) /* port change detect */
  60. #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
  61. #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
  62. #define PORT_POWER (1<<12) /* true: has power (see PPC) */
  63. #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
  64. #define PORT_RESET (1<<8) /* reset port */
  65. #define PORT_SUSPEND (1<<7) /* suspend port */
  66. #define PORT_RESUME (1<<6) /* resume it */
  67. #define PORT_PE (1<<2) /* port enable */
  68. #define PORT_CSC (1<<1) /* connect status change */
  69. #define PORT_CONNECT (1<<0) /* device connected */
  70. #define PORT_RWC_BITS (PORT_CSC)
  71. struct isp1760_qtd {
  72. struct isp1760_qtd *hw_next;
  73. u8 packet_type;
  74. u8 toggle;
  75. void *data_buffer;
  76. /* the rest is HCD-private */
  77. struct list_head qtd_list;
  78. struct urb *urb;
  79. size_t length;
  80. /* isp special*/
  81. u32 status;
  82. #define URB_COMPLETE_NOTIFY (1 << 0)
  83. #define URB_ENQUEUED (1 << 1)
  84. #define URB_TYPE_ATL (1 << 2)
  85. #define URB_TYPE_INT (1 << 3)
  86. };
  87. struct isp1760_qh {
  88. /* first part defined by EHCI spec */
  89. struct list_head qtd_list;
  90. struct isp1760_hcd *priv;
  91. /* periodic schedule info */
  92. unsigned short period; /* polling interval */
  93. struct usb_device *dev;
  94. u32 toggle;
  95. u32 ping;
  96. };
  97. #define ehci_port_speed(priv, portsc) (1 << USB_PORT_FEAT_HIGHSPEED)
  98. static unsigned int isp1760_readl(__u32 __iomem *regs)
  99. {
  100. return readl(regs);
  101. }
  102. static void isp1760_writel(const unsigned int val, __u32 __iomem *regs)
  103. {
  104. writel(val, regs);
  105. }
  106. /*
  107. * The next two copy via MMIO data to/from the device. memcpy_{to|from}io()
  108. * doesn't quite work because some people have to enforce 32-bit access
  109. */
  110. static void priv_read_copy(struct isp1760_hcd *priv, u32 *src,
  111. __u32 __iomem *dst, u32 len)
  112. {
  113. u32 val;
  114. u8 *buff8;
  115. if (!src) {
  116. printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len);
  117. return;
  118. }
  119. while (len >= 4) {
  120. *src = __raw_readl(dst);
  121. len -= 4;
  122. src++;
  123. dst++;
  124. }
  125. if (!len)
  126. return;
  127. /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
  128. * allocated.
  129. */
  130. val = isp1760_readl(dst);
  131. buff8 = (u8 *)src;
  132. while (len) {
  133. *buff8 = val;
  134. val >>= 8;
  135. len--;
  136. buff8++;
  137. }
  138. }
  139. static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src,
  140. __u32 __iomem *dst, u32 len)
  141. {
  142. while (len >= 4) {
  143. __raw_writel(*src, dst);
  144. len -= 4;
  145. src++;
  146. dst++;
  147. }
  148. if (!len)
  149. return;
  150. /* in case we have 3, 2 or 1 by left. The buffer is allocated and the
  151. * extra bytes should not be read by the HW
  152. */
  153. __raw_writel(*src, dst);
  154. }
  155. /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
  156. static void init_memory(struct isp1760_hcd *priv)
  157. {
  158. int i;
  159. u32 payload;
  160. payload = 0x1000;
  161. for (i = 0; i < BLOCK_1_NUM; i++) {
  162. priv->memory_pool[i].start = payload;
  163. priv->memory_pool[i].size = BLOCK_1_SIZE;
  164. priv->memory_pool[i].free = 1;
  165. payload += priv->memory_pool[i].size;
  166. }
  167. for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) {
  168. priv->memory_pool[i].start = payload;
  169. priv->memory_pool[i].size = BLOCK_2_SIZE;
  170. priv->memory_pool[i].free = 1;
  171. payload += priv->memory_pool[i].size;
  172. }
  173. for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) {
  174. priv->memory_pool[i].start = payload;
  175. priv->memory_pool[i].size = BLOCK_3_SIZE;
  176. priv->memory_pool[i].free = 1;
  177. payload += priv->memory_pool[i].size;
  178. }
  179. BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE);
  180. }
  181. static u32 alloc_mem(struct isp1760_hcd *priv, u32 size)
  182. {
  183. int i;
  184. if (!size)
  185. return ISP1760_NULL_POINTER;
  186. for (i = 0; i < BLOCKS; i++) {
  187. if (priv->memory_pool[i].size >= size &&
  188. priv->memory_pool[i].free) {
  189. priv->memory_pool[i].free = 0;
  190. return priv->memory_pool[i].start;
  191. }
  192. }
  193. printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n",
  194. size);
  195. printk(KERN_ERR "Current memory map:\n");
  196. for (i = 0; i < BLOCKS; i++) {
  197. printk(KERN_ERR "Pool %2d size %4d status: %d\n",
  198. i, priv->memory_pool[i].size,
  199. priv->memory_pool[i].free);
  200. }
  201. /* XXX maybe -ENOMEM could be possible */
  202. BUG();
  203. return 0;
  204. }
  205. static void free_mem(struct isp1760_hcd *priv, u32 mem)
  206. {
  207. int i;
  208. if (mem == ISP1760_NULL_POINTER)
  209. return;
  210. for (i = 0; i < BLOCKS; i++) {
  211. if (priv->memory_pool[i].start == mem) {
  212. BUG_ON(priv->memory_pool[i].free);
  213. priv->memory_pool[i].free = 1;
  214. return ;
  215. }
  216. }
  217. printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n",
  218. mem);
  219. BUG();
  220. }
  221. static void isp1760_init_regs(struct usb_hcd *hcd)
  222. {
  223. isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG);
  224. isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
  225. HC_ATL_PTD_SKIPMAP_REG);
  226. isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
  227. HC_INT_PTD_SKIPMAP_REG);
  228. isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
  229. HC_ISO_PTD_SKIPMAP_REG);
  230. isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
  231. HC_ATL_PTD_DONEMAP_REG);
  232. isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
  233. HC_INT_PTD_DONEMAP_REG);
  234. isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
  235. HC_ISO_PTD_DONEMAP_REG);
  236. }
  237. static int handshake(struct isp1760_hcd *priv, void __iomem *ptr,
  238. u32 mask, u32 done, int usec)
  239. {
  240. u32 result;
  241. do {
  242. result = isp1760_readl(ptr);
  243. if (result == ~0)
  244. return -ENODEV;
  245. result &= mask;
  246. if (result == done)
  247. return 0;
  248. udelay(1);
  249. usec--;
  250. } while (usec > 0);
  251. return -ETIMEDOUT;
  252. }
  253. /* reset a non-running (STS_HALT == 1) controller */
  254. static int ehci_reset(struct isp1760_hcd *priv)
  255. {
  256. int retval;
  257. struct usb_hcd *hcd = priv_to_hcd(priv);
  258. u32 command = isp1760_readl(hcd->regs + HC_USBCMD);
  259. command |= CMD_RESET;
  260. isp1760_writel(command, hcd->regs + HC_USBCMD);
  261. hcd->state = HC_STATE_HALT;
  262. priv->next_statechange = jiffies;
  263. retval = handshake(priv, hcd->regs + HC_USBCMD,
  264. CMD_RESET, 0, 250 * 1000);
  265. return retval;
  266. }
  267. static void qh_destroy(struct isp1760_qh *qh)
  268. {
  269. BUG_ON(!list_empty(&qh->qtd_list));
  270. kmem_cache_free(qh_cachep, qh);
  271. }
  272. static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv,
  273. gfp_t flags)
  274. {
  275. struct isp1760_qh *qh;
  276. qh = kmem_cache_zalloc(qh_cachep, flags);
  277. if (!qh)
  278. return qh;
  279. INIT_LIST_HEAD(&qh->qtd_list);
  280. qh->priv = priv;
  281. return qh;
  282. }
  283. /* magic numbers that can affect system performance */
  284. #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
  285. #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
  286. #define EHCI_TUNE_RL_TT 0
  287. #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
  288. #define EHCI_TUNE_MULT_TT 1
  289. #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
  290. /* one-time init, only for memory state */
  291. static int priv_init(struct usb_hcd *hcd)
  292. {
  293. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  294. u32 hcc_params;
  295. spin_lock_init(&priv->lock);
  296. /*
  297. * hw default: 1K periodic list heads, one per frame.
  298. * periodic_size can shrink by USBCMD update if hcc_params allows.
  299. */
  300. priv->periodic_size = DEFAULT_I_TDPS;
  301. /* controllers may cache some of the periodic schedule ... */
  302. hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS);
  303. /* full frame cache */
  304. if (HCC_ISOC_CACHE(hcc_params))
  305. priv->i_thresh = 8;
  306. else /* N microframes cached */
  307. priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
  308. return 0;
  309. }
  310. static int isp1760_hc_setup(struct usb_hcd *hcd)
  311. {
  312. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  313. int result;
  314. u32 scratch, hwmode;
  315. /* Setup HW Mode Control: This assumes a level active-low interrupt */
  316. hwmode = HW_DATA_BUS_32BIT;
  317. if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
  318. hwmode &= ~HW_DATA_BUS_32BIT;
  319. if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
  320. hwmode |= HW_ANA_DIGI_OC;
  321. if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
  322. hwmode |= HW_DACK_POL_HIGH;
  323. if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
  324. hwmode |= HW_DREQ_POL_HIGH;
  325. /*
  326. * We have to set this first in case we're in 16-bit mode.
  327. * Write it twice to ensure correct upper bits if switching
  328. * to 16-bit mode.
  329. */
  330. isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
  331. isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
  332. isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG);
  333. /* Change bus pattern */
  334. scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
  335. scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG);
  336. if (scratch != 0xdeadbabe) {
  337. printk(KERN_ERR "ISP1760: Scratch test failed.\n");
  338. return -ENODEV;
  339. }
  340. /* pre reset */
  341. isp1760_init_regs(hcd);
  342. /* reset */
  343. isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG);
  344. mdelay(100);
  345. isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG);
  346. mdelay(100);
  347. result = ehci_reset(priv);
  348. if (result)
  349. return result;
  350. /* Step 11 passed */
  351. isp1760_info(priv, "bus width: %d, oc: %s\n",
  352. (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
  353. 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
  354. "analog" : "digital");
  355. /* ATL reset */
  356. isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL);
  357. mdelay(10);
  358. isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
  359. isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG);
  360. isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE);
  361. /*
  362. * PORT 1 Control register of the ISP1760 is the OTG control
  363. * register on ISP1761.
  364. */
  365. if (!(priv->devflags & ISP1760_FLAG_ISP1761) &&
  366. !(priv->devflags & ISP1760_FLAG_PORT1_DIS)) {
  367. isp1760_writel(PORT1_POWER | PORT1_INIT2,
  368. hcd->regs + HC_PORT1_CTRL);
  369. mdelay(10);
  370. }
  371. priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS);
  372. return priv_init(hcd);
  373. }
  374. static void isp1760_init_maps(struct usb_hcd *hcd)
  375. {
  376. /*set last maps, for iso its only 1, else 32 tds bitmap*/
  377. isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG);
  378. isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG);
  379. isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG);
  380. }
  381. static void isp1760_enable_interrupts(struct usb_hcd *hcd)
  382. {
  383. isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG);
  384. isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  385. isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG);
  386. isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  387. isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG);
  388. isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG);
  389. /* step 23 passed */
  390. }
  391. static int isp1760_run(struct usb_hcd *hcd)
  392. {
  393. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  394. int retval;
  395. u32 temp;
  396. u32 command;
  397. u32 chipid;
  398. hcd->uses_new_polling = 1;
  399. hcd->poll_rh = 0;
  400. hcd->state = HC_STATE_RUNNING;
  401. isp1760_enable_interrupts(hcd);
  402. temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
  403. isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
  404. command = isp1760_readl(hcd->regs + HC_USBCMD);
  405. command &= ~(CMD_LRESET|CMD_RESET);
  406. command |= CMD_RUN;
  407. isp1760_writel(command, hcd->regs + HC_USBCMD);
  408. retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN,
  409. 250 * 1000);
  410. if (retval)
  411. return retval;
  412. /*
  413. * XXX
  414. * Spec says to write FLAG_CF as last config action, priv code grabs
  415. * the semaphore while doing so.
  416. */
  417. down_write(&ehci_cf_port_reset_rwsem);
  418. isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG);
  419. retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF,
  420. 250 * 1000);
  421. up_write(&ehci_cf_port_reset_rwsem);
  422. if (retval)
  423. return retval;
  424. chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
  425. isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff,
  426. chipid >> 16);
  427. /* PTD Register Init Part 2, Step 28 */
  428. /* enable INTs */
  429. isp1760_init_maps(hcd);
  430. /* GRR this is run-once init(), being done every time the HC starts.
  431. * So long as they're part of class devices, we can't do it init()
  432. * since the class device isn't created that early.
  433. */
  434. return 0;
  435. }
  436. static u32 base_to_chip(u32 base)
  437. {
  438. return ((base - 0x400) >> 3);
  439. }
  440. static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh,
  441. struct isp1760_qtd *qtd, struct urb *urb,
  442. u32 payload, struct ptd *ptd)
  443. {
  444. u32 dw0;
  445. u32 dw1;
  446. u32 dw2;
  447. u32 dw3;
  448. u32 maxpacket;
  449. u32 multi;
  450. u32 pid_code;
  451. u32 rl = RL_COUNTER;
  452. u32 nak = NAK_COUNTER;
  453. /* according to 3.6.2, max packet len can not be > 0x400 */
  454. maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
  455. multi = 1 + ((maxpacket >> 11) & 0x3);
  456. maxpacket &= 0x7ff;
  457. /* DW0 */
  458. dw0 = PTD_VALID;
  459. dw0 |= PTD_LENGTH(qtd->length);
  460. dw0 |= PTD_MAXPACKET(maxpacket);
  461. dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe));
  462. dw1 = usb_pipeendpoint(urb->pipe) >> 1;
  463. /* DW1 */
  464. dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe));
  465. pid_code = qtd->packet_type;
  466. dw1 |= PTD_PID_TOKEN(pid_code);
  467. if (usb_pipebulk(urb->pipe))
  468. dw1 |= PTD_TRANS_BULK;
  469. else if (usb_pipeint(urb->pipe))
  470. dw1 |= PTD_TRANS_INT;
  471. if (urb->dev->speed != USB_SPEED_HIGH) {
  472. /* split transaction */
  473. dw1 |= PTD_TRANS_SPLIT;
  474. if (urb->dev->speed == USB_SPEED_LOW)
  475. dw1 |= PTD_SE_USB_LOSPEED;
  476. dw1 |= PTD_PORT_NUM(urb->dev->ttport);
  477. dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum);
  478. /* SE bit for Split INT transfers */
  479. if (usb_pipeint(urb->pipe) &&
  480. (urb->dev->speed == USB_SPEED_LOW))
  481. dw1 |= 2 << 16;
  482. dw3 = 0;
  483. rl = 0;
  484. nak = 0;
  485. } else {
  486. dw0 |= PTD_MULTI(multi);
  487. if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe))
  488. dw3 = qh->ping;
  489. else
  490. dw3 = 0;
  491. }
  492. /* DW2 */
  493. dw2 = 0;
  494. dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload));
  495. dw2 |= PTD_RL_CNT(rl);
  496. dw3 |= PTD_NAC_CNT(nak);
  497. /* DW3 */
  498. if (usb_pipecontrol(urb->pipe))
  499. dw3 |= PTD_DATA_TOGGLE(qtd->toggle);
  500. else
  501. dw3 |= qh->toggle;
  502. dw3 |= PTD_ACTIVE;
  503. /* Cerr */
  504. dw3 |= PTD_CERR(ERR_COUNTER);
  505. memset(ptd, 0, sizeof(*ptd));
  506. ptd->dw0 = cpu_to_le32(dw0);
  507. ptd->dw1 = cpu_to_le32(dw1);
  508. ptd->dw2 = cpu_to_le32(dw2);
  509. ptd->dw3 = cpu_to_le32(dw3);
  510. }
  511. static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
  512. struct isp1760_qtd *qtd, struct urb *urb,
  513. u32 payload, struct ptd *ptd)
  514. {
  515. u32 maxpacket;
  516. u32 multi;
  517. u32 numberofusofs;
  518. u32 i;
  519. u32 usofmask, usof;
  520. u32 period;
  521. maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
  522. multi = 1 + ((maxpacket >> 11) & 0x3);
  523. maxpacket &= 0x7ff;
  524. /* length of the data per uframe */
  525. maxpacket = multi * maxpacket;
  526. numberofusofs = urb->transfer_buffer_length / maxpacket;
  527. if (urb->transfer_buffer_length % maxpacket)
  528. numberofusofs += 1;
  529. usofmask = 1;
  530. usof = 0;
  531. for (i = 0; i < numberofusofs; i++) {
  532. usof |= usofmask;
  533. usofmask <<= 1;
  534. }
  535. if (urb->dev->speed != USB_SPEED_HIGH) {
  536. /* split */
  537. ptd->dw5 = __constant_cpu_to_le32(0x1c);
  538. if (qh->period >= 32)
  539. period = qh->period / 2;
  540. else
  541. period = qh->period;
  542. } else {
  543. if (qh->period >= 8)
  544. period = qh->period/8;
  545. else
  546. period = qh->period;
  547. if (period >= 32)
  548. period = 16;
  549. if (qh->period >= 8) {
  550. /* millisecond period */
  551. period = (period << 3);
  552. } else {
  553. /* usof based tranmsfers */
  554. /* minimum 4 usofs */
  555. usof = 0x11;
  556. }
  557. }
  558. ptd->dw2 |= cpu_to_le32(period);
  559. ptd->dw4 = cpu_to_le32(usof);
  560. }
  561. static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
  562. struct isp1760_qtd *qtd, struct urb *urb,
  563. u32 payload, struct ptd *ptd)
  564. {
  565. transform_into_atl(priv, qh, qtd, urb, payload, ptd);
  566. transform_add_int(priv, qh, qtd, urb, payload, ptd);
  567. }
  568. static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
  569. u32 token)
  570. {
  571. int count;
  572. qtd->data_buffer = databuffer;
  573. qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
  574. qtd->toggle = GET_DATA_TOGGLE(token);
  575. if (len > HC_ATL_PL_SIZE)
  576. count = HC_ATL_PL_SIZE;
  577. else
  578. count = len;
  579. qtd->length = count;
  580. return count;
  581. }
  582. static int check_error(struct ptd *ptd)
  583. {
  584. int error = 0;
  585. u32 dw3;
  586. dw3 = le32_to_cpu(ptd->dw3);
  587. if (dw3 & DW3_HALT_BIT)
  588. error = -EPIPE;
  589. if (dw3 & DW3_ERROR_BIT) {
  590. printk(KERN_ERR "error bit is set in DW3\n");
  591. error = -EPIPE;
  592. }
  593. if (dw3 & DW3_QTD_ACTIVE) {
  594. printk(KERN_ERR "transfer active bit is set DW3\n");
  595. printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf,
  596. (le32_to_cpu(ptd->dw2) >> 25) & 0xf);
  597. }
  598. return error;
  599. }
  600. static void check_int_err_status(u32 dw4)
  601. {
  602. u32 i;
  603. dw4 >>= 8;
  604. for (i = 0; i < 8; i++) {
  605. switch (dw4 & 0x7) {
  606. case INT_UNDERRUN:
  607. printk(KERN_ERR "ERROR: under run , %d\n", i);
  608. break;
  609. case INT_EXACT:
  610. printk(KERN_ERR "ERROR: transaction error, %d\n", i);
  611. break;
  612. case INT_BABBLE:
  613. printk(KERN_ERR "ERROR: babble error, %d\n", i);
  614. break;
  615. }
  616. dw4 >>= 3;
  617. }
  618. }
  619. static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv,
  620. u32 payload)
  621. {
  622. u32 token;
  623. struct usb_hcd *hcd = priv_to_hcd(priv);
  624. token = qtd->packet_type;
  625. if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) {
  626. switch (token) {
  627. case IN_PID:
  628. break;
  629. case OUT_PID:
  630. case SETUP_PID:
  631. priv_write_copy(priv, qtd->data_buffer,
  632. hcd->regs + payload,
  633. qtd->length);
  634. }
  635. }
  636. }
  637. static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload,
  638. struct isp1760_hcd *priv, struct isp1760_qh *qh,
  639. struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
  640. {
  641. struct ptd ptd;
  642. struct usb_hcd *hcd = priv_to_hcd(priv);
  643. transform_into_atl(priv, qh, qtd, urb, payload, &ptd);
  644. priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd));
  645. enqueue_one_qtd(qtd, priv, payload);
  646. priv->atl_ints[slot].urb = urb;
  647. priv->atl_ints[slot].qh = qh;
  648. priv->atl_ints[slot].qtd = qtd;
  649. priv->atl_ints[slot].data_buffer = qtd->data_buffer;
  650. priv->atl_ints[slot].payload = payload;
  651. qtd->status |= URB_ENQUEUED | URB_TYPE_ATL;
  652. qtd->status |= slot << 16;
  653. }
  654. static void enqueue_one_int_qtd(u32 int_regs, u32 payload,
  655. struct isp1760_hcd *priv, struct isp1760_qh *qh,
  656. struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
  657. {
  658. struct ptd ptd;
  659. struct usb_hcd *hcd = priv_to_hcd(priv);
  660. transform_into_int(priv, qh, qtd, urb, payload, &ptd);
  661. priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd));
  662. enqueue_one_qtd(qtd, priv, payload);
  663. priv->int_ints[slot].urb = urb;
  664. priv->int_ints[slot].qh = qh;
  665. priv->int_ints[slot].qtd = qtd;
  666. priv->int_ints[slot].data_buffer = qtd->data_buffer;
  667. priv->int_ints[slot].payload = payload;
  668. qtd->status |= URB_ENQUEUED | URB_TYPE_INT;
  669. qtd->status |= slot << 16;
  670. }
  671. static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
  672. struct isp1760_qtd *qtd)
  673. {
  674. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  675. u32 skip_map, or_map;
  676. u32 queue_entry;
  677. u32 slot;
  678. u32 atl_regs, payload;
  679. u32 buffstatus;
  680. skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
  681. BUG_ON(!skip_map);
  682. slot = __ffs(skip_map);
  683. queue_entry = 1 << slot;
  684. atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd);
  685. payload = alloc_mem(priv, qtd->length);
  686. enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd);
  687. or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  688. or_map |= queue_entry;
  689. isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  690. skip_map &= ~queue_entry;
  691. isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
  692. buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
  693. buffstatus |= ATL_BUFFER;
  694. isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
  695. }
  696. static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
  697. struct isp1760_qtd *qtd)
  698. {
  699. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  700. u32 skip_map, or_map;
  701. u32 queue_entry;
  702. u32 slot;
  703. u32 int_regs, payload;
  704. u32 buffstatus;
  705. skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG);
  706. BUG_ON(!skip_map);
  707. slot = __ffs(skip_map);
  708. queue_entry = 1 << slot;
  709. int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd);
  710. payload = alloc_mem(priv, qtd->length);
  711. enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd);
  712. or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  713. or_map |= queue_entry;
  714. isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  715. skip_map &= ~queue_entry;
  716. isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG);
  717. buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
  718. buffstatus |= INT_BUFFER;
  719. isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
  720. }
  721. static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status)
  722. __releases(priv->lock)
  723. __acquires(priv->lock)
  724. {
  725. if (!urb->unlinked) {
  726. if (status == -EINPROGRESS)
  727. status = 0;
  728. }
  729. /* complete() can reenter this HCD */
  730. usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
  731. spin_unlock(&priv->lock);
  732. usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status);
  733. spin_lock(&priv->lock);
  734. }
  735. static void isp1760_qtd_free(struct isp1760_qtd *qtd)
  736. {
  737. kmem_cache_free(qtd_cachep, qtd);
  738. }
  739. static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd)
  740. {
  741. struct isp1760_qtd *tmp_qtd;
  742. tmp_qtd = qtd->hw_next;
  743. list_del(&qtd->qtd_list);
  744. isp1760_qtd_free(qtd);
  745. return tmp_qtd;
  746. }
  747. /*
  748. * Remove this QTD from the QH list and free its memory. If this QTD
  749. * isn't the last one than remove also his successor(s).
  750. * Returns the QTD which is part of an new URB and should be enqueued.
  751. */
  752. static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd)
  753. {
  754. struct isp1760_qtd *tmp_qtd;
  755. int last_one;
  756. do {
  757. tmp_qtd = qtd->hw_next;
  758. last_one = qtd->status & URB_COMPLETE_NOTIFY;
  759. list_del(&qtd->qtd_list);
  760. isp1760_qtd_free(qtd);
  761. qtd = tmp_qtd;
  762. } while (!last_one && qtd);
  763. return qtd;
  764. }
  765. static void do_atl_int(struct usb_hcd *usb_hcd)
  766. {
  767. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  768. u32 done_map, skip_map;
  769. struct ptd ptd;
  770. struct urb *urb = NULL;
  771. u32 atl_regs_base;
  772. u32 atl_regs;
  773. u32 queue_entry;
  774. u32 payload;
  775. u32 length;
  776. u32 or_map;
  777. u32 status = -EINVAL;
  778. int error;
  779. struct isp1760_qtd *qtd;
  780. struct isp1760_qh *qh;
  781. u32 rl;
  782. u32 nakcount;
  783. done_map = isp1760_readl(usb_hcd->regs +
  784. HC_ATL_PTD_DONEMAP_REG);
  785. skip_map = isp1760_readl(usb_hcd->regs +
  786. HC_ATL_PTD_SKIPMAP_REG);
  787. or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  788. or_map &= ~done_map;
  789. isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  790. atl_regs_base = ATL_REGS_OFFSET;
  791. while (done_map) {
  792. u32 dw1;
  793. u32 dw2;
  794. u32 dw3;
  795. status = 0;
  796. queue_entry = __ffs(done_map);
  797. done_map &= ~(1 << queue_entry);
  798. skip_map |= 1 << queue_entry;
  799. atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd);
  800. urb = priv->atl_ints[queue_entry].urb;
  801. qtd = priv->atl_ints[queue_entry].qtd;
  802. qh = priv->atl_ints[queue_entry].qh;
  803. payload = priv->atl_ints[queue_entry].payload;
  804. if (!qh) {
  805. printk(KERN_ERR "qh is 0\n");
  806. continue;
  807. }
  808. isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs +
  809. HC_MEMORY_REG);
  810. isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
  811. HC_MEMORY_REG);
  812. /*
  813. * write bank1 address twice to ensure the 90ns delay (time
  814. * between BANK0 write and the priv_read_copy() call is at
  815. * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns)
  816. */
  817. isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
  818. HC_MEMORY_REG);
  819. priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs +
  820. ISP_BANK(0), sizeof(ptd));
  821. dw1 = le32_to_cpu(ptd.dw1);
  822. dw2 = le32_to_cpu(ptd.dw2);
  823. dw3 = le32_to_cpu(ptd.dw3);
  824. rl = (dw2 >> 25) & 0x0f;
  825. nakcount = (dw3 >> 19) & 0xf;
  826. /* Transfer Error, *but* active and no HALT -> reload */
  827. if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) &&
  828. !(dw3 & DW3_HALT_BIT)) {
  829. /* according to ppriv code, we have to
  830. * reload this one if trasfered bytes != requested bytes
  831. * else act like everything went smooth..
  832. * XXX This just doesn't feel right and hasn't
  833. * triggered so far.
  834. */
  835. length = PTD_XFERRED_LENGTH(dw3);
  836. printk(KERN_ERR "Should reload now.... transfered %d "
  837. "of %zu\n", length, qtd->length);
  838. BUG();
  839. }
  840. if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) {
  841. u32 buffstatus;
  842. /* XXX
  843. * NAKs are handled in HW by the chip. Usually if the
  844. * device is not able to send data fast enough.
  845. * This did not trigger for a long time now.
  846. */
  847. printk(KERN_ERR "Reloading ptd %p/%p... qh %p readed: "
  848. "%d of %zu done: %08x cur: %08x\n", qtd,
  849. urb, qh, PTD_XFERRED_LENGTH(dw3),
  850. qtd->length, done_map,
  851. (1 << queue_entry));
  852. /* RL counter = ERR counter */
  853. dw3 &= ~(0xf << 19);
  854. dw3 |= rl << 19;
  855. dw3 &= ~(3 << (55 - 32));
  856. dw3 |= ERR_COUNTER << (55 - 32);
  857. /*
  858. * It is not needed to write skip map back because it
  859. * is unchanged. Just make sure that this entry is
  860. * unskipped once it gets written to the HW.
  861. */
  862. skip_map &= ~(1 << queue_entry);
  863. or_map = isp1760_readl(usb_hcd->regs +
  864. HC_ATL_IRQ_MASK_OR_REG);
  865. or_map |= 1 << queue_entry;
  866. isp1760_writel(or_map, usb_hcd->regs +
  867. HC_ATL_IRQ_MASK_OR_REG);
  868. ptd.dw3 = cpu_to_le32(dw3);
  869. priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
  870. atl_regs, sizeof(ptd));
  871. ptd.dw0 |= __constant_cpu_to_le32(PTD_VALID);
  872. priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
  873. atl_regs, sizeof(ptd));
  874. buffstatus = isp1760_readl(usb_hcd->regs +
  875. HC_BUFFER_STATUS_REG);
  876. buffstatus |= ATL_BUFFER;
  877. isp1760_writel(buffstatus, usb_hcd->regs +
  878. HC_BUFFER_STATUS_REG);
  879. continue;
  880. }
  881. error = check_error(&ptd);
  882. if (error) {
  883. status = error;
  884. priv->atl_ints[queue_entry].qh->toggle = 0;
  885. priv->atl_ints[queue_entry].qh->ping = 0;
  886. urb->status = -EPIPE;
  887. #if 0
  888. printk(KERN_ERR "Error in %s().\n", __func__);
  889. printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
  890. "dw3: %08x dw4: %08x dw5: %08x dw6: "
  891. "%08x dw7: %08x\n",
  892. ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
  893. ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
  894. #endif
  895. } else {
  896. if (usb_pipetype(urb->pipe) == PIPE_BULK) {
  897. priv->atl_ints[queue_entry].qh->toggle = dw3 &
  898. (1 << 25);
  899. priv->atl_ints[queue_entry].qh->ping = dw3 &
  900. (1 << 26);
  901. }
  902. }
  903. length = PTD_XFERRED_LENGTH(dw3);
  904. if (length) {
  905. switch (DW1_GET_PID(dw1)) {
  906. case IN_PID:
  907. priv_read_copy(priv,
  908. priv->atl_ints[queue_entry].data_buffer,
  909. usb_hcd->regs + payload + ISP_BANK(1),
  910. length);
  911. case OUT_PID:
  912. urb->actual_length += length;
  913. case SETUP_PID:
  914. break;
  915. }
  916. }
  917. priv->atl_ints[queue_entry].data_buffer = NULL;
  918. priv->atl_ints[queue_entry].urb = NULL;
  919. priv->atl_ints[queue_entry].qtd = NULL;
  920. priv->atl_ints[queue_entry].qh = NULL;
  921. free_mem(priv, payload);
  922. isp1760_writel(skip_map, usb_hcd->regs +
  923. HC_ATL_PTD_SKIPMAP_REG);
  924. if (urb->status == -EPIPE) {
  925. /* HALT was received */
  926. qtd = clean_up_qtdlist(qtd);
  927. isp1760_urb_done(priv, urb, urb->status);
  928. } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) {
  929. /* short BULK received */
  930. if (urb->transfer_flags & URB_SHORT_NOT_OK) {
  931. urb->status = -EREMOTEIO;
  932. isp1760_dbg(priv, "short bulk, %d instead %zu "
  933. "with URB_SHORT_NOT_OK flag.\n",
  934. length, qtd->length);
  935. }
  936. if (urb->status == -EINPROGRESS)
  937. urb->status = 0;
  938. qtd = clean_up_qtdlist(qtd);
  939. isp1760_urb_done(priv, urb, urb->status);
  940. } else if (qtd->status & URB_COMPLETE_NOTIFY) {
  941. /* that was the last qtd of that URB */
  942. if (urb->status == -EINPROGRESS)
  943. urb->status = 0;
  944. qtd = clean_this_qtd(qtd);
  945. isp1760_urb_done(priv, urb, urb->status);
  946. } else {
  947. /* next QTD of this URB */
  948. qtd = clean_this_qtd(qtd);
  949. BUG_ON(!qtd);
  950. }
  951. if (qtd)
  952. enqueue_an_ATL_packet(usb_hcd, qh, qtd);
  953. skip_map = isp1760_readl(usb_hcd->regs +
  954. HC_ATL_PTD_SKIPMAP_REG);
  955. }
  956. }
  957. static void do_intl_int(struct usb_hcd *usb_hcd)
  958. {
  959. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  960. u32 done_map, skip_map;
  961. struct ptd ptd;
  962. struct urb *urb = NULL;
  963. u32 int_regs;
  964. u32 int_regs_base;
  965. u32 payload;
  966. u32 length;
  967. u32 or_map;
  968. int error;
  969. u32 queue_entry;
  970. struct isp1760_qtd *qtd;
  971. struct isp1760_qh *qh;
  972. done_map = isp1760_readl(usb_hcd->regs +
  973. HC_INT_PTD_DONEMAP_REG);
  974. skip_map = isp1760_readl(usb_hcd->regs +
  975. HC_INT_PTD_SKIPMAP_REG);
  976. or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  977. or_map &= ~done_map;
  978. isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  979. int_regs_base = INT_REGS_OFFSET;
  980. while (done_map) {
  981. u32 dw1;
  982. u32 dw3;
  983. queue_entry = __ffs(done_map);
  984. done_map &= ~(1 << queue_entry);
  985. skip_map |= 1 << queue_entry;
  986. int_regs = int_regs_base + queue_entry * sizeof(struct ptd);
  987. urb = priv->int_ints[queue_entry].urb;
  988. qtd = priv->int_ints[queue_entry].qtd;
  989. qh = priv->int_ints[queue_entry].qh;
  990. payload = priv->int_ints[queue_entry].payload;
  991. if (!qh) {
  992. printk(KERN_ERR "(INT) qh is 0\n");
  993. continue;
  994. }
  995. isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs +
  996. HC_MEMORY_REG);
  997. isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
  998. HC_MEMORY_REG);
  999. /*
  1000. * write bank1 address twice to ensure the 90ns delay (time
  1001. * between BANK0 write and the priv_read_copy() call is at
  1002. * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns)
  1003. */
  1004. isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
  1005. HC_MEMORY_REG);
  1006. priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs +
  1007. ISP_BANK(0), sizeof(ptd));
  1008. dw1 = le32_to_cpu(ptd.dw1);
  1009. dw3 = le32_to_cpu(ptd.dw3);
  1010. check_int_err_status(le32_to_cpu(ptd.dw4));
  1011. error = check_error(&ptd);
  1012. if (error) {
  1013. #if 0
  1014. printk(KERN_ERR "Error in %s().\n", __func__);
  1015. printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
  1016. "dw3: %08x dw4: %08x dw5: %08x dw6: "
  1017. "%08x dw7: %08x\n",
  1018. ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
  1019. ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
  1020. #endif
  1021. urb->status = -EPIPE;
  1022. priv->int_ints[queue_entry].qh->toggle = 0;
  1023. priv->int_ints[queue_entry].qh->ping = 0;
  1024. } else {
  1025. priv->int_ints[queue_entry].qh->toggle =
  1026. dw3 & (1 << 25);
  1027. priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26);
  1028. }
  1029. if (urb->dev->speed != USB_SPEED_HIGH)
  1030. length = PTD_XFERRED_LENGTH_LO(dw3);
  1031. else
  1032. length = PTD_XFERRED_LENGTH(dw3);
  1033. if (length) {
  1034. switch (DW1_GET_PID(dw1)) {
  1035. case IN_PID:
  1036. priv_read_copy(priv,
  1037. priv->int_ints[queue_entry].data_buffer,
  1038. usb_hcd->regs + payload + ISP_BANK(1),
  1039. length);
  1040. case OUT_PID:
  1041. urb->actual_length += length;
  1042. case SETUP_PID:
  1043. break;
  1044. }
  1045. }
  1046. priv->int_ints[queue_entry].data_buffer = NULL;
  1047. priv->int_ints[queue_entry].urb = NULL;
  1048. priv->int_ints[queue_entry].qtd = NULL;
  1049. priv->int_ints[queue_entry].qh = NULL;
  1050. isp1760_writel(skip_map, usb_hcd->regs +
  1051. HC_INT_PTD_SKIPMAP_REG);
  1052. free_mem(priv, payload);
  1053. if (urb->status == -EPIPE) {
  1054. /* HALT received */
  1055. qtd = clean_up_qtdlist(qtd);
  1056. isp1760_urb_done(priv, urb, urb->status);
  1057. } else if (qtd->status & URB_COMPLETE_NOTIFY) {
  1058. if (urb->status == -EINPROGRESS)
  1059. urb->status = 0;
  1060. qtd = clean_this_qtd(qtd);
  1061. isp1760_urb_done(priv, urb, urb->status);
  1062. } else {
  1063. /* next QTD of this URB */
  1064. qtd = clean_this_qtd(qtd);
  1065. BUG_ON(!qtd);
  1066. }
  1067. if (qtd)
  1068. enqueue_an_INT_packet(usb_hcd, qh, qtd);
  1069. skip_map = isp1760_readl(usb_hcd->regs +
  1070. HC_INT_PTD_SKIPMAP_REG);
  1071. }
  1072. }
  1073. #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
  1074. static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb,
  1075. gfp_t flags)
  1076. {
  1077. struct isp1760_qh *qh;
  1078. int is_input, type;
  1079. qh = isp1760_qh_alloc(priv, flags);
  1080. if (!qh)
  1081. return qh;
  1082. /*
  1083. * init endpoint/device data for this QH
  1084. */
  1085. is_input = usb_pipein(urb->pipe);
  1086. type = usb_pipetype(urb->pipe);
  1087. if (type == PIPE_INTERRUPT) {
  1088. if (urb->dev->speed == USB_SPEED_HIGH) {
  1089. qh->period = urb->interval >> 3;
  1090. if (qh->period == 0 && urb->interval != 1) {
  1091. /* NOTE interval 2 or 4 uframes could work.
  1092. * But interval 1 scheduling is simpler, and
  1093. * includes high bandwidth.
  1094. */
  1095. printk(KERN_ERR "intr period %d uframes, NYET!",
  1096. urb->interval);
  1097. qh_destroy(qh);
  1098. return NULL;
  1099. }
  1100. } else {
  1101. qh->period = urb->interval;
  1102. }
  1103. }
  1104. /* support for tt scheduling, and access to toggles */
  1105. qh->dev = urb->dev;
  1106. if (!usb_pipecontrol(urb->pipe))
  1107. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
  1108. 1);
  1109. return qh;
  1110. }
  1111. /*
  1112. * For control/bulk/interrupt, return QH with these TDs appended.
  1113. * Allocates and initializes the QH if necessary.
  1114. * Returns null if it can't allocate a QH it needs to.
  1115. * If the QH has TDs (urbs) already, that's great.
  1116. */
  1117. static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv,
  1118. struct urb *urb, struct list_head *qtd_list, int epnum,
  1119. void **ptr)
  1120. {
  1121. struct isp1760_qh *qh;
  1122. struct isp1760_qtd *qtd;
  1123. struct isp1760_qtd *prev_qtd;
  1124. qh = (struct isp1760_qh *)*ptr;
  1125. if (!qh) {
  1126. /* can't sleep here, we have priv->lock... */
  1127. qh = qh_make(priv, urb, GFP_ATOMIC);
  1128. if (!qh)
  1129. return qh;
  1130. *ptr = qh;
  1131. }
  1132. qtd = list_entry(qtd_list->next, struct isp1760_qtd,
  1133. qtd_list);
  1134. if (!list_empty(&qh->qtd_list))
  1135. prev_qtd = list_entry(qh->qtd_list.prev,
  1136. struct isp1760_qtd, qtd_list);
  1137. else
  1138. prev_qtd = NULL;
  1139. list_splice(qtd_list, qh->qtd_list.prev);
  1140. if (prev_qtd) {
  1141. BUG_ON(prev_qtd->hw_next);
  1142. prev_qtd->hw_next = qtd;
  1143. }
  1144. urb->hcpriv = qh;
  1145. return qh;
  1146. }
  1147. static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb,
  1148. struct list_head *qtd_list)
  1149. {
  1150. struct list_head *entry, *temp;
  1151. list_for_each_safe(entry, temp, qtd_list) {
  1152. struct isp1760_qtd *qtd;
  1153. qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
  1154. list_del(&qtd->qtd_list);
  1155. isp1760_qtd_free(qtd);
  1156. }
  1157. }
  1158. static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb,
  1159. struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
  1160. {
  1161. struct isp1760_qtd *qtd;
  1162. int epnum;
  1163. unsigned long flags;
  1164. struct isp1760_qh *qh = NULL;
  1165. int rc;
  1166. int qh_busy;
  1167. qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
  1168. epnum = urb->ep->desc.bEndpointAddress;
  1169. spin_lock_irqsave(&priv->lock, flags);
  1170. if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &priv_to_hcd(priv)->flags)) {
  1171. rc = -ESHUTDOWN;
  1172. goto done;
  1173. }
  1174. rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb);
  1175. if (rc)
  1176. goto done;
  1177. qh = urb->ep->hcpriv;
  1178. if (qh)
  1179. qh_busy = !list_empty(&qh->qtd_list);
  1180. else
  1181. qh_busy = 0;
  1182. qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv);
  1183. if (!qh) {
  1184. usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
  1185. rc = -ENOMEM;
  1186. goto done;
  1187. }
  1188. if (!qh_busy)
  1189. p(priv_to_hcd(priv), qh, qtd);
  1190. done:
  1191. spin_unlock_irqrestore(&priv->lock, flags);
  1192. if (!qh)
  1193. qtd_list_free(priv, urb, qtd_list);
  1194. return rc;
  1195. }
  1196. static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv,
  1197. gfp_t flags)
  1198. {
  1199. struct isp1760_qtd *qtd;
  1200. qtd = kmem_cache_zalloc(qtd_cachep, flags);
  1201. if (qtd)
  1202. INIT_LIST_HEAD(&qtd->qtd_list);
  1203. return qtd;
  1204. }
  1205. /*
  1206. * create a list of filled qtds for this URB; won't link into qh.
  1207. */
  1208. static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
  1209. struct urb *urb, struct list_head *head, gfp_t flags)
  1210. {
  1211. struct isp1760_qtd *qtd, *qtd_prev;
  1212. void *buf;
  1213. int len, maxpacket;
  1214. int is_input;
  1215. u32 token;
  1216. /*
  1217. * URBs map to sequences of QTDs: one logical transaction
  1218. */
  1219. qtd = isp1760_qtd_alloc(priv, flags);
  1220. if (!qtd)
  1221. return NULL;
  1222. list_add_tail(&qtd->qtd_list, head);
  1223. qtd->urb = urb;
  1224. urb->status = -EINPROGRESS;
  1225. token = 0;
  1226. /* for split transactions, SplitXState initialized to zero */
  1227. len = urb->transfer_buffer_length;
  1228. is_input = usb_pipein(urb->pipe);
  1229. if (usb_pipecontrol(urb->pipe)) {
  1230. /* SETUP pid */
  1231. qtd_fill(qtd, urb->setup_packet,
  1232. sizeof(struct usb_ctrlrequest),
  1233. token | SETUP_PID);
  1234. /* ... and always at least one more pid */
  1235. token ^= DATA_TOGGLE;
  1236. qtd_prev = qtd;
  1237. qtd = isp1760_qtd_alloc(priv, flags);
  1238. if (!qtd)
  1239. goto cleanup;
  1240. qtd->urb = urb;
  1241. qtd_prev->hw_next = qtd;
  1242. list_add_tail(&qtd->qtd_list, head);
  1243. /* for zero length DATA stages, STATUS is always IN */
  1244. if (len == 0)
  1245. token |= IN_PID;
  1246. }
  1247. /*
  1248. * data transfer stage: buffer setup
  1249. */
  1250. buf = urb->transfer_buffer;
  1251. if (is_input)
  1252. token |= IN_PID;
  1253. else
  1254. token |= OUT_PID;
  1255. maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
  1256. /*
  1257. * buffer gets wrapped in one or more qtds;
  1258. * last one may be "short" (including zero len)
  1259. * and may serve as a control status ack
  1260. */
  1261. for (;;) {
  1262. int this_qtd_len;
  1263. if (!buf && len) {
  1264. /* XXX This looks like usb storage / SCSI bug */
  1265. printk(KERN_ERR "buf is null, dma is %08lx len is %d\n",
  1266. (long unsigned)urb->transfer_dma, len);
  1267. WARN_ON(1);
  1268. }
  1269. this_qtd_len = qtd_fill(qtd, buf, len, token);
  1270. len -= this_qtd_len;
  1271. buf += this_qtd_len;
  1272. /* qh makes control packets use qtd toggle; maybe switch it */
  1273. if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
  1274. token ^= DATA_TOGGLE;
  1275. if (len <= 0)
  1276. break;
  1277. qtd_prev = qtd;
  1278. qtd = isp1760_qtd_alloc(priv, flags);
  1279. if (!qtd)
  1280. goto cleanup;
  1281. qtd->urb = urb;
  1282. qtd_prev->hw_next = qtd;
  1283. list_add_tail(&qtd->qtd_list, head);
  1284. }
  1285. /*
  1286. * control requests may need a terminating data "status" ack;
  1287. * bulk ones may need a terminating short packet (zero length).
  1288. */
  1289. if (urb->transfer_buffer_length != 0) {
  1290. int one_more = 0;
  1291. if (usb_pipecontrol(urb->pipe)) {
  1292. one_more = 1;
  1293. /* "in" <--> "out" */
  1294. token ^= IN_PID;
  1295. /* force DATA1 */
  1296. token |= DATA_TOGGLE;
  1297. } else if (usb_pipebulk(urb->pipe)
  1298. && (urb->transfer_flags & URB_ZERO_PACKET)
  1299. && !(urb->transfer_buffer_length % maxpacket)) {
  1300. one_more = 1;
  1301. }
  1302. if (one_more) {
  1303. qtd_prev = qtd;
  1304. qtd = isp1760_qtd_alloc(priv, flags);
  1305. if (!qtd)
  1306. goto cleanup;
  1307. qtd->urb = urb;
  1308. qtd_prev->hw_next = qtd;
  1309. list_add_tail(&qtd->qtd_list, head);
  1310. /* never any data in such packets */
  1311. qtd_fill(qtd, NULL, 0, token);
  1312. }
  1313. }
  1314. qtd->status = URB_COMPLETE_NOTIFY;
  1315. return head;
  1316. cleanup:
  1317. qtd_list_free(priv, urb, head);
  1318. return NULL;
  1319. }
  1320. static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
  1321. gfp_t mem_flags)
  1322. {
  1323. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1324. struct list_head qtd_list;
  1325. packet_enqueue *pe;
  1326. INIT_LIST_HEAD(&qtd_list);
  1327. switch (usb_pipetype(urb->pipe)) {
  1328. case PIPE_CONTROL:
  1329. case PIPE_BULK:
  1330. if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
  1331. return -ENOMEM;
  1332. pe = enqueue_an_ATL_packet;
  1333. break;
  1334. case PIPE_INTERRUPT:
  1335. if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
  1336. return -ENOMEM;
  1337. pe = enqueue_an_INT_packet;
  1338. break;
  1339. case PIPE_ISOCHRONOUS:
  1340. printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n");
  1341. default:
  1342. return -EPIPE;
  1343. }
  1344. return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe);
  1345. }
  1346. static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
  1347. int status)
  1348. {
  1349. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1350. struct inter_packet_info *ints;
  1351. u32 i;
  1352. u32 reg_base, or_reg, skip_reg;
  1353. unsigned long flags;
  1354. struct ptd ptd;
  1355. switch (usb_pipetype(urb->pipe)) {
  1356. case PIPE_ISOCHRONOUS:
  1357. return -EPIPE;
  1358. break;
  1359. case PIPE_INTERRUPT:
  1360. ints = priv->int_ints;
  1361. reg_base = INT_REGS_OFFSET;
  1362. or_reg = HC_INT_IRQ_MASK_OR_REG;
  1363. skip_reg = HC_INT_PTD_SKIPMAP_REG;
  1364. break;
  1365. default:
  1366. ints = priv->atl_ints;
  1367. reg_base = ATL_REGS_OFFSET;
  1368. or_reg = HC_ATL_IRQ_MASK_OR_REG;
  1369. skip_reg = HC_ATL_PTD_SKIPMAP_REG;
  1370. break;
  1371. }
  1372. memset(&ptd, 0, sizeof(ptd));
  1373. spin_lock_irqsave(&priv->lock, flags);
  1374. for (i = 0; i < 32; i++) {
  1375. if (ints->urb == urb) {
  1376. u32 skip_map;
  1377. u32 or_map;
  1378. struct isp1760_qtd *qtd;
  1379. skip_map = isp1760_readl(hcd->regs + skip_reg);
  1380. skip_map |= 1 << i;
  1381. isp1760_writel(skip_map, hcd->regs + skip_reg);
  1382. or_map = isp1760_readl(hcd->regs + or_reg);
  1383. or_map &= ~(1 << i);
  1384. isp1760_writel(or_map, hcd->regs + or_reg);
  1385. priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base
  1386. + i * sizeof(ptd), sizeof(ptd));
  1387. qtd = ints->qtd;
  1388. clean_up_qtdlist(qtd);
  1389. free_mem(priv, ints->payload);
  1390. ints->urb = NULL;
  1391. ints->qh = NULL;
  1392. ints->qtd = NULL;
  1393. ints->data_buffer = NULL;
  1394. ints->payload = 0;
  1395. isp1760_urb_done(priv, urb, status);
  1396. break;
  1397. }
  1398. ints++;
  1399. }
  1400. spin_unlock_irqrestore(&priv->lock, flags);
  1401. return 0;
  1402. }
  1403. static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd)
  1404. {
  1405. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  1406. u32 imask;
  1407. irqreturn_t irqret = IRQ_NONE;
  1408. spin_lock(&priv->lock);
  1409. if (!(usb_hcd->state & HC_STATE_RUNNING))
  1410. goto leave;
  1411. imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG);
  1412. if (unlikely(!imask))
  1413. goto leave;
  1414. isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG);
  1415. if (imask & HC_ATL_INT)
  1416. do_atl_int(usb_hcd);
  1417. if (imask & HC_INTL_INT)
  1418. do_intl_int(usb_hcd);
  1419. irqret = IRQ_HANDLED;
  1420. leave:
  1421. spin_unlock(&priv->lock);
  1422. return irqret;
  1423. }
  1424. static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
  1425. {
  1426. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1427. u32 temp, status = 0;
  1428. u32 mask;
  1429. int retval = 1;
  1430. unsigned long flags;
  1431. /* if !USB_SUSPEND, root hub timers won't get shut down ... */
  1432. if (!HC_IS_RUNNING(hcd->state))
  1433. return 0;
  1434. /* init status to no-changes */
  1435. buf[0] = 0;
  1436. mask = PORT_CSC;
  1437. spin_lock_irqsave(&priv->lock, flags);
  1438. temp = isp1760_readl(hcd->regs + HC_PORTSC1);
  1439. if (temp & PORT_OWNER) {
  1440. if (temp & PORT_CSC) {
  1441. temp &= ~PORT_CSC;
  1442. isp1760_writel(temp, hcd->regs + HC_PORTSC1);
  1443. goto done;
  1444. }
  1445. }
  1446. /*
  1447. * Return status information even for ports with OWNER set.
  1448. * Otherwise khubd wouldn't see the disconnect event when a
  1449. * high-speed device is switched over to the companion
  1450. * controller by the user.
  1451. */
  1452. if ((temp & mask) != 0
  1453. || ((temp & PORT_RESUME) != 0
  1454. && time_after_eq(jiffies,
  1455. priv->reset_done))) {
  1456. buf [0] |= 1 << (0 + 1);
  1457. status = STS_PCD;
  1458. }
  1459. /* FIXME autosuspend idle root hubs */
  1460. done:
  1461. spin_unlock_irqrestore(&priv->lock, flags);
  1462. return status ? retval : 0;
  1463. }
  1464. static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
  1465. struct usb_hub_descriptor *desc)
  1466. {
  1467. int ports = HCS_N_PORTS(priv->hcs_params);
  1468. u16 temp;
  1469. desc->bDescriptorType = 0x29;
  1470. /* priv 1.0, 2.3.9 says 20ms max */
  1471. desc->bPwrOn2PwrGood = 10;
  1472. desc->bHubContrCurrent = 0;
  1473. desc->bNbrPorts = ports;
  1474. temp = 1 + (ports / 8);
  1475. desc->bDescLength = 7 + 2 * temp;
  1476. /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
  1477. memset(&desc->bitmap[0], 0, temp);
  1478. memset(&desc->bitmap[temp], 0xff, temp);
  1479. /* per-port overcurrent reporting */
  1480. temp = 0x0008;
  1481. if (HCS_PPC(priv->hcs_params))
  1482. /* per-port power control */
  1483. temp |= 0x0001;
  1484. else
  1485. /* no power switching */
  1486. temp |= 0x0002;
  1487. desc->wHubCharacteristics = cpu_to_le16(temp);
  1488. }
  1489. #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
  1490. static int check_reset_complete(struct isp1760_hcd *priv, int index,
  1491. u32 __iomem *status_reg, int port_status)
  1492. {
  1493. if (!(port_status & PORT_CONNECT))
  1494. return port_status;
  1495. /* if reset finished and it's still not enabled -- handoff */
  1496. if (!(port_status & PORT_PE)) {
  1497. printk(KERN_ERR "port %d full speed --> companion\n",
  1498. index + 1);
  1499. port_status |= PORT_OWNER;
  1500. port_status &= ~PORT_RWC_BITS;
  1501. isp1760_writel(port_status, status_reg);
  1502. } else
  1503. printk(KERN_ERR "port %d high speed\n", index + 1);
  1504. return port_status;
  1505. }
  1506. static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
  1507. u16 wValue, u16 wIndex, char *buf, u16 wLength)
  1508. {
  1509. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1510. int ports = HCS_N_PORTS(priv->hcs_params);
  1511. u32 __iomem *status_reg = hcd->regs + HC_PORTSC1;
  1512. u32 temp, status;
  1513. unsigned long flags;
  1514. int retval = 0;
  1515. unsigned selector;
  1516. /*
  1517. * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
  1518. * HCS_INDICATOR may say we can change LEDs to off/amber/green.
  1519. * (track current state ourselves) ... blink for diagnostics,
  1520. * power, "this is the one", etc. EHCI spec supports this.
  1521. */
  1522. spin_lock_irqsave(&priv->lock, flags);
  1523. switch (typeReq) {
  1524. case ClearHubFeature:
  1525. switch (wValue) {
  1526. case C_HUB_LOCAL_POWER:
  1527. case C_HUB_OVER_CURRENT:
  1528. /* no hub-wide feature/status flags */
  1529. break;
  1530. default:
  1531. goto error;
  1532. }
  1533. break;
  1534. case ClearPortFeature:
  1535. if (!wIndex || wIndex > ports)
  1536. goto error;
  1537. wIndex--;
  1538. temp = isp1760_readl(status_reg);
  1539. /*
  1540. * Even if OWNER is set, so the port is owned by the
  1541. * companion controller, khubd needs to be able to clear
  1542. * the port-change status bits (especially
  1543. * USB_PORT_FEAT_C_CONNECTION).
  1544. */
  1545. switch (wValue) {
  1546. case USB_PORT_FEAT_ENABLE:
  1547. isp1760_writel(temp & ~PORT_PE, status_reg);
  1548. break;
  1549. case USB_PORT_FEAT_C_ENABLE:
  1550. /* XXX error? */
  1551. break;
  1552. case USB_PORT_FEAT_SUSPEND:
  1553. if (temp & PORT_RESET)
  1554. goto error;
  1555. if (temp & PORT_SUSPEND) {
  1556. if ((temp & PORT_PE) == 0)
  1557. goto error;
  1558. /* resume signaling for 20 msec */
  1559. temp &= ~(PORT_RWC_BITS);
  1560. isp1760_writel(temp | PORT_RESUME,
  1561. status_reg);
  1562. priv->reset_done = jiffies +
  1563. msecs_to_jiffies(20);
  1564. }
  1565. break;
  1566. case USB_PORT_FEAT_C_SUSPEND:
  1567. /* we auto-clear this feature */
  1568. break;
  1569. case USB_PORT_FEAT_POWER:
  1570. if (HCS_PPC(priv->hcs_params))
  1571. isp1760_writel(temp & ~PORT_POWER, status_reg);
  1572. break;
  1573. case USB_PORT_FEAT_C_CONNECTION:
  1574. isp1760_writel(temp | PORT_CSC,
  1575. status_reg);
  1576. break;
  1577. case USB_PORT_FEAT_C_OVER_CURRENT:
  1578. /* XXX error ?*/
  1579. break;
  1580. case USB_PORT_FEAT_C_RESET:
  1581. /* GetPortStatus clears reset */
  1582. break;
  1583. default:
  1584. goto error;
  1585. }
  1586. isp1760_readl(hcd->regs + HC_USBCMD);
  1587. break;
  1588. case GetHubDescriptor:
  1589. isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
  1590. buf);
  1591. break;
  1592. case GetHubStatus:
  1593. /* no hub-wide feature/status flags */
  1594. memset(buf, 0, 4);
  1595. break;
  1596. case GetPortStatus:
  1597. if (!wIndex || wIndex > ports)
  1598. goto error;
  1599. wIndex--;
  1600. status = 0;
  1601. temp = isp1760_readl(status_reg);
  1602. /* wPortChange bits */
  1603. if (temp & PORT_CSC)
  1604. status |= 1 << USB_PORT_FEAT_C_CONNECTION;
  1605. /* whoever resumes must GetPortStatus to complete it!! */
  1606. if (temp & PORT_RESUME) {
  1607. printk(KERN_ERR "Port resume should be skipped.\n");
  1608. /* Remote Wakeup received? */
  1609. if (!priv->reset_done) {
  1610. /* resume signaling for 20 msec */
  1611. priv->reset_done = jiffies
  1612. + msecs_to_jiffies(20);
  1613. /* check the port again */
  1614. mod_timer(&priv_to_hcd(priv)->rh_timer,
  1615. priv->reset_done);
  1616. }
  1617. /* resume completed? */
  1618. else if (time_after_eq(jiffies,
  1619. priv->reset_done)) {
  1620. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  1621. priv->reset_done = 0;
  1622. /* stop resume signaling */
  1623. temp = isp1760_readl(status_reg);
  1624. isp1760_writel(
  1625. temp & ~(PORT_RWC_BITS | PORT_RESUME),
  1626. status_reg);
  1627. retval = handshake(priv, status_reg,
  1628. PORT_RESUME, 0, 2000 /* 2msec */);
  1629. if (retval != 0) {
  1630. isp1760_err(priv,
  1631. "port %d resume error %d\n",
  1632. wIndex + 1, retval);
  1633. goto error;
  1634. }
  1635. temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
  1636. }
  1637. }
  1638. /* whoever resets must GetPortStatus to complete it!! */
  1639. if ((temp & PORT_RESET)
  1640. && time_after_eq(jiffies,
  1641. priv->reset_done)) {
  1642. status |= 1 << USB_PORT_FEAT_C_RESET;
  1643. priv->reset_done = 0;
  1644. /* force reset to complete */
  1645. isp1760_writel(temp & ~PORT_RESET,
  1646. status_reg);
  1647. /* REVISIT: some hardware needs 550+ usec to clear
  1648. * this bit; seems too long to spin routinely...
  1649. */
  1650. retval = handshake(priv, status_reg,
  1651. PORT_RESET, 0, 750);
  1652. if (retval != 0) {
  1653. isp1760_err(priv, "port %d reset error %d\n",
  1654. wIndex + 1, retval);
  1655. goto error;
  1656. }
  1657. /* see what we found out */
  1658. temp = check_reset_complete(priv, wIndex, status_reg,
  1659. isp1760_readl(status_reg));
  1660. }
  1661. /*
  1662. * Even if OWNER is set, there's no harm letting khubd
  1663. * see the wPortStatus values (they should all be 0 except
  1664. * for PORT_POWER anyway).
  1665. */
  1666. if (temp & PORT_OWNER)
  1667. printk(KERN_ERR "Warning: PORT_OWNER is set\n");
  1668. if (temp & PORT_CONNECT) {
  1669. status |= 1 << USB_PORT_FEAT_CONNECTION;
  1670. /* status may be from integrated TT */
  1671. status |= ehci_port_speed(priv, temp);
  1672. }
  1673. if (temp & PORT_PE)
  1674. status |= 1 << USB_PORT_FEAT_ENABLE;
  1675. if (temp & (PORT_SUSPEND|PORT_RESUME))
  1676. status |= 1 << USB_PORT_FEAT_SUSPEND;
  1677. if (temp & PORT_RESET)
  1678. status |= 1 << USB_PORT_FEAT_RESET;
  1679. if (temp & PORT_POWER)
  1680. status |= 1 << USB_PORT_FEAT_POWER;
  1681. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  1682. break;
  1683. case SetHubFeature:
  1684. switch (wValue) {
  1685. case C_HUB_LOCAL_POWER:
  1686. case C_HUB_OVER_CURRENT:
  1687. /* no hub-wide feature/status flags */
  1688. break;
  1689. default:
  1690. goto error;
  1691. }
  1692. break;
  1693. case SetPortFeature:
  1694. selector = wIndex >> 8;
  1695. wIndex &= 0xff;
  1696. if (!wIndex || wIndex > ports)
  1697. goto error;
  1698. wIndex--;
  1699. temp = isp1760_readl(status_reg);
  1700. if (temp & PORT_OWNER)
  1701. break;
  1702. /* temp &= ~PORT_RWC_BITS; */
  1703. switch (wValue) {
  1704. case USB_PORT_FEAT_ENABLE:
  1705. isp1760_writel(temp | PORT_PE, status_reg);
  1706. break;
  1707. case USB_PORT_FEAT_SUSPEND:
  1708. if ((temp & PORT_PE) == 0
  1709. || (temp & PORT_RESET) != 0)
  1710. goto error;
  1711. isp1760_writel(temp | PORT_SUSPEND, status_reg);
  1712. break;
  1713. case USB_PORT_FEAT_POWER:
  1714. if (HCS_PPC(priv->hcs_params))
  1715. isp1760_writel(temp | PORT_POWER,
  1716. status_reg);
  1717. break;
  1718. case USB_PORT_FEAT_RESET:
  1719. if (temp & PORT_RESUME)
  1720. goto error;
  1721. /* line status bits may report this as low speed,
  1722. * which can be fine if this root hub has a
  1723. * transaction translator built in.
  1724. */
  1725. if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
  1726. && PORT_USB11(temp)) {
  1727. temp |= PORT_OWNER;
  1728. } else {
  1729. temp |= PORT_RESET;
  1730. temp &= ~PORT_PE;
  1731. /*
  1732. * caller must wait, then call GetPortStatus
  1733. * usb 2.0 spec says 50 ms resets on root
  1734. */
  1735. priv->reset_done = jiffies +
  1736. msecs_to_jiffies(50);
  1737. }
  1738. isp1760_writel(temp, status_reg);
  1739. break;
  1740. default:
  1741. goto error;
  1742. }
  1743. isp1760_readl(hcd->regs + HC_USBCMD);
  1744. break;
  1745. default:
  1746. error:
  1747. /* "stall" on error */
  1748. retval = -EPIPE;
  1749. }
  1750. spin_unlock_irqrestore(&priv->lock, flags);
  1751. return retval;
  1752. }
  1753. static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd,
  1754. struct usb_host_endpoint *ep)
  1755. {
  1756. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  1757. struct isp1760_qh *qh;
  1758. struct isp1760_qtd *qtd;
  1759. unsigned long flags;
  1760. spin_lock_irqsave(&priv->lock, flags);
  1761. qh = ep->hcpriv;
  1762. if (!qh)
  1763. goto out;
  1764. ep->hcpriv = NULL;
  1765. do {
  1766. /* more than entry might get removed */
  1767. if (list_empty(&qh->qtd_list))
  1768. break;
  1769. qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
  1770. qtd_list);
  1771. if (qtd->status & URB_ENQUEUED) {
  1772. spin_unlock_irqrestore(&priv->lock, flags);
  1773. isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET);
  1774. spin_lock_irqsave(&priv->lock, flags);
  1775. } else {
  1776. struct urb *urb;
  1777. urb = qtd->urb;
  1778. clean_up_qtdlist(qtd);
  1779. isp1760_urb_done(priv, urb, -ECONNRESET);
  1780. }
  1781. } while (1);
  1782. qh_destroy(qh);
  1783. /* remove requests and leak them.
  1784. * ATL are pretty fast done, INT could take a while...
  1785. * The latter shoule be removed
  1786. */
  1787. out:
  1788. spin_unlock_irqrestore(&priv->lock, flags);
  1789. }
  1790. static int isp1760_get_frame(struct usb_hcd *hcd)
  1791. {
  1792. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1793. u32 fr;
  1794. fr = isp1760_readl(hcd->regs + HC_FRINDEX);
  1795. return (fr >> 3) % priv->periodic_size;
  1796. }
  1797. static void isp1760_stop(struct usb_hcd *hcd)
  1798. {
  1799. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1800. u32 temp;
  1801. isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
  1802. NULL, 0);
  1803. mdelay(20);
  1804. spin_lock_irq(&priv->lock);
  1805. ehci_reset(priv);
  1806. /* Disable IRQ */
  1807. temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
  1808. isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
  1809. spin_unlock_irq(&priv->lock);
  1810. isp1760_writel(0, hcd->regs + HC_CONFIGFLAG);
  1811. }
  1812. static void isp1760_shutdown(struct usb_hcd *hcd)
  1813. {
  1814. u32 command, temp;
  1815. isp1760_stop(hcd);
  1816. temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
  1817. isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
  1818. command = isp1760_readl(hcd->regs + HC_USBCMD);
  1819. command &= ~CMD_RUN;
  1820. isp1760_writel(command, hcd->regs + HC_USBCMD);
  1821. }
  1822. static const struct hc_driver isp1760_hc_driver = {
  1823. .description = "isp1760-hcd",
  1824. .product_desc = "NXP ISP1760 USB Host Controller",
  1825. .hcd_priv_size = sizeof(struct isp1760_hcd),
  1826. .irq = isp1760_irq,
  1827. .flags = HCD_MEMORY | HCD_USB2,
  1828. .reset = isp1760_hc_setup,
  1829. .start = isp1760_run,
  1830. .stop = isp1760_stop,
  1831. .shutdown = isp1760_shutdown,
  1832. .urb_enqueue = isp1760_urb_enqueue,
  1833. .urb_dequeue = isp1760_urb_dequeue,
  1834. .endpoint_disable = isp1760_endpoint_disable,
  1835. .get_frame_number = isp1760_get_frame,
  1836. .hub_status_data = isp1760_hub_status_data,
  1837. .hub_control = isp1760_hub_control,
  1838. };
  1839. int __init init_kmem_once(void)
  1840. {
  1841. qtd_cachep = kmem_cache_create("isp1760_qtd",
  1842. sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
  1843. SLAB_MEM_SPREAD, NULL);
  1844. if (!qtd_cachep)
  1845. return -ENOMEM;
  1846. qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
  1847. 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
  1848. if (!qh_cachep) {
  1849. kmem_cache_destroy(qtd_cachep);
  1850. return -ENOMEM;
  1851. }
  1852. return 0;
  1853. }
  1854. void deinit_kmem_cache(void)
  1855. {
  1856. kmem_cache_destroy(qtd_cachep);
  1857. kmem_cache_destroy(qh_cachep);
  1858. }
  1859. struct usb_hcd *isp1760_register(u64 res_start, u64 res_len, int irq,
  1860. u64 irqflags, struct device *dev, const char *busname,
  1861. unsigned int devflags)
  1862. {
  1863. struct usb_hcd *hcd;
  1864. struct isp1760_hcd *priv;
  1865. int ret;
  1866. if (usb_disabled())
  1867. return ERR_PTR(-ENODEV);
  1868. /* prevent usb-core allocating DMA pages */
  1869. dev->dma_mask = NULL;
  1870. hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
  1871. if (!hcd)
  1872. return ERR_PTR(-ENOMEM);
  1873. priv = hcd_to_priv(hcd);
  1874. priv->devflags = devflags;
  1875. init_memory(priv);
  1876. hcd->regs = ioremap(res_start, res_len);
  1877. if (!hcd->regs) {
  1878. ret = -EIO;
  1879. goto err_put;
  1880. }
  1881. hcd->irq = irq;
  1882. hcd->rsrc_start = res_start;
  1883. hcd->rsrc_len = res_len;
  1884. ret = usb_add_hcd(hcd, irq, irqflags);
  1885. if (ret)
  1886. goto err_unmap;
  1887. return hcd;
  1888. err_unmap:
  1889. iounmap(hcd->regs);
  1890. err_put:
  1891. usb_put_hcd(hcd);
  1892. return ERR_PTR(ret);
  1893. }
  1894. MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
  1895. MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
  1896. MODULE_LICENSE("GPL v2");