arcmsr_hba.c 67 KB

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  1. /*
  2. *******************************************************************************
  3. ** O.S : Linux
  4. ** FILE NAME : arcmsr_hba.c
  5. ** BY : Erich Chen
  6. ** Description: SCSI RAID Device Driver for
  7. ** ARECA RAID Host adapter
  8. *******************************************************************************
  9. ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved
  10. **
  11. ** Web site: www.areca.com.tw
  12. ** E-mail: support@areca.com.tw
  13. **
  14. ** This program is free software; you can redistribute it and/or modify
  15. ** it under the terms of the GNU General Public License version 2 as
  16. ** published by the Free Software Foundation.
  17. ** This program is distributed in the hope that it will be useful,
  18. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. ** GNU General Public License for more details.
  21. *******************************************************************************
  22. ** Redistribution and use in source and binary forms, with or without
  23. ** modification, are permitted provided that the following conditions
  24. ** are met:
  25. ** 1. Redistributions of source code must retain the above copyright
  26. ** notice, this list of conditions and the following disclaimer.
  27. ** 2. Redistributions in binary form must reproduce the above copyright
  28. ** notice, this list of conditions and the following disclaimer in the
  29. ** documentation and/or other materials provided with the distribution.
  30. ** 3. The name of the author may not be used to endorse or promote products
  31. ** derived from this software without specific prior written permission.
  32. **
  33. ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  34. ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  35. ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  36. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  37. ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
  38. ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  39. ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  40. ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  41. ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  42. ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  43. *******************************************************************************
  44. ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
  45. ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
  46. *******************************************************************************
  47. */
  48. #include <linux/module.h>
  49. #include <linux/reboot.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/pci_ids.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/moduleparam.h>
  54. #include <linux/errno.h>
  55. #include <linux/types.h>
  56. #include <linux/delay.h>
  57. #include <linux/dma-mapping.h>
  58. #include <linux/timer.h>
  59. #include <linux/pci.h>
  60. #include <linux/aer.h>
  61. #include <asm/dma.h>
  62. #include <asm/io.h>
  63. #include <asm/system.h>
  64. #include <asm/uaccess.h>
  65. #include <scsi/scsi_host.h>
  66. #include <scsi/scsi.h>
  67. #include <scsi/scsi_cmnd.h>
  68. #include <scsi/scsi_tcq.h>
  69. #include <scsi/scsi_device.h>
  70. #include <scsi/scsi_transport.h>
  71. #include <scsi/scsicam.h>
  72. #include "arcmsr.h"
  73. MODULE_AUTHOR("Erich Chen <support@areca.com.tw>");
  74. MODULE_DESCRIPTION("ARECA (ARC11xx/12xx/13xx/16xx) SATA/SAS RAID HOST Adapter");
  75. MODULE_LICENSE("Dual BSD/GPL");
  76. MODULE_VERSION(ARCMSR_DRIVER_VERSION);
  77. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  78. struct scsi_cmnd *cmd);
  79. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
  80. static int arcmsr_abort(struct scsi_cmnd *);
  81. static int arcmsr_bus_reset(struct scsi_cmnd *);
  82. static int arcmsr_bios_param(struct scsi_device *sdev,
  83. struct block_device *bdev, sector_t capacity, int *info);
  84. static int arcmsr_queue_command(struct scsi_cmnd *cmd,
  85. void (*done) (struct scsi_cmnd *));
  86. static int arcmsr_probe(struct pci_dev *pdev,
  87. const struct pci_device_id *id);
  88. static void arcmsr_remove(struct pci_dev *pdev);
  89. static void arcmsr_shutdown(struct pci_dev *pdev);
  90. static void arcmsr_iop_init(struct AdapterControlBlock *acb);
  91. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
  92. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
  93. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
  94. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb);
  95. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb);
  96. static const char *arcmsr_info(struct Scsi_Host *);
  97. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
  98. static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
  99. int queue_depth)
  100. {
  101. if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
  102. queue_depth = ARCMSR_MAX_CMD_PERLUN;
  103. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth);
  104. return queue_depth;
  105. }
  106. static struct scsi_host_template arcmsr_scsi_host_template = {
  107. .module = THIS_MODULE,
  108. .name = "ARCMSR ARECA SATA/SAS RAID HOST Adapter"
  109. ARCMSR_DRIVER_VERSION,
  110. .info = arcmsr_info,
  111. .queuecommand = arcmsr_queue_command,
  112. .eh_abort_handler = arcmsr_abort,
  113. .eh_bus_reset_handler = arcmsr_bus_reset,
  114. .bios_param = arcmsr_bios_param,
  115. .change_queue_depth = arcmsr_adjust_disk_queue_depth,
  116. .can_queue = ARCMSR_MAX_OUTSTANDING_CMD,
  117. .this_id = ARCMSR_SCSI_INITIATOR_ID,
  118. .sg_tablesize = ARCMSR_MAX_SG_ENTRIES,
  119. .max_sectors = ARCMSR_MAX_XFER_SECTORS,
  120. .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
  121. .use_clustering = ENABLE_CLUSTERING,
  122. .shost_attrs = arcmsr_host_attrs,
  123. };
  124. #ifdef CONFIG_SCSI_ARCMSR_AER
  125. static pci_ers_result_t arcmsr_pci_slot_reset(struct pci_dev *pdev);
  126. static pci_ers_result_t arcmsr_pci_error_detected(struct pci_dev *pdev,
  127. pci_channel_state_t state);
  128. static struct pci_error_handlers arcmsr_pci_error_handlers = {
  129. .error_detected = arcmsr_pci_error_detected,
  130. .slot_reset = arcmsr_pci_slot_reset,
  131. };
  132. #endif
  133. static struct pci_device_id arcmsr_device_id_table[] = {
  134. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
  135. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120)},
  136. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130)},
  137. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160)},
  138. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170)},
  139. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681)},
  152. {0, 0}, /* Terminating entry */
  153. };
  154. MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
  155. static struct pci_driver arcmsr_pci_driver = {
  156. .name = "arcmsr",
  157. .id_table = arcmsr_device_id_table,
  158. .probe = arcmsr_probe,
  159. .remove = arcmsr_remove,
  160. .shutdown = arcmsr_shutdown,
  161. #ifdef CONFIG_SCSI_ARCMSR_AER
  162. .err_handler = &arcmsr_pci_error_handlers,
  163. #endif
  164. };
  165. static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
  166. {
  167. irqreturn_t handle_state;
  168. struct AdapterControlBlock *acb = dev_id;
  169. spin_lock(acb->host->host_lock);
  170. handle_state = arcmsr_interrupt(acb);
  171. spin_unlock(acb->host->host_lock);
  172. return handle_state;
  173. }
  174. static int arcmsr_bios_param(struct scsi_device *sdev,
  175. struct block_device *bdev, sector_t capacity, int *geom)
  176. {
  177. int ret, heads, sectors, cylinders, total_capacity;
  178. unsigned char *buffer;/* return copy of block device's partition table */
  179. buffer = scsi_bios_ptable(bdev);
  180. if (buffer) {
  181. ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
  182. kfree(buffer);
  183. if (ret != -1)
  184. return ret;
  185. }
  186. total_capacity = capacity;
  187. heads = 64;
  188. sectors = 32;
  189. cylinders = total_capacity / (heads * sectors);
  190. if (cylinders > 1024) {
  191. heads = 255;
  192. sectors = 63;
  193. cylinders = total_capacity / (heads * sectors);
  194. }
  195. geom[0] = heads;
  196. geom[1] = sectors;
  197. geom[2] = cylinders;
  198. return 0;
  199. }
  200. static void arcmsr_define_adapter_type(struct AdapterControlBlock *acb)
  201. {
  202. struct pci_dev *pdev = acb->pdev;
  203. u16 dev_id;
  204. pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
  205. switch (dev_id) {
  206. case 0x1201 : {
  207. acb->adapter_type = ACB_ADAPTER_TYPE_B;
  208. }
  209. break;
  210. default : acb->adapter_type = ACB_ADAPTER_TYPE_A;
  211. }
  212. }
  213. static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
  214. {
  215. switch (acb->adapter_type) {
  216. case ACB_ADAPTER_TYPE_A: {
  217. struct pci_dev *pdev = acb->pdev;
  218. void *dma_coherent;
  219. dma_addr_t dma_coherent_handle, dma_addr;
  220. struct CommandControlBlock *ccb_tmp;
  221. uint32_t intmask_org;
  222. int i, j;
  223. acb->pmuA = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  224. if (!acb->pmuA) {
  225. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n",
  226. acb->host->host_no);
  227. return -ENOMEM;
  228. }
  229. dma_coherent = dma_alloc_coherent(&pdev->dev,
  230. ARCMSR_MAX_FREECCB_NUM *
  231. sizeof (struct CommandControlBlock) + 0x20,
  232. &dma_coherent_handle, GFP_KERNEL);
  233. if (!dma_coherent) {
  234. iounmap(acb->pmuA);
  235. return -ENOMEM;
  236. }
  237. acb->dma_coherent = dma_coherent;
  238. acb->dma_coherent_handle = dma_coherent_handle;
  239. if (((unsigned long)dma_coherent & 0x1F)) {
  240. dma_coherent = dma_coherent +
  241. (0x20 - ((unsigned long)dma_coherent & 0x1F));
  242. dma_coherent_handle = dma_coherent_handle +
  243. (0x20 - ((unsigned long)dma_coherent_handle & 0x1F));
  244. }
  245. dma_addr = dma_coherent_handle;
  246. ccb_tmp = (struct CommandControlBlock *)dma_coherent;
  247. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  248. ccb_tmp->cdb_shifted_phyaddr = dma_addr >> 5;
  249. ccb_tmp->acb = acb;
  250. acb->pccb_pool[i] = ccb_tmp;
  251. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  252. dma_addr = dma_addr + sizeof(struct CommandControlBlock);
  253. ccb_tmp++;
  254. }
  255. acb->vir2phy_offset = (unsigned long)ccb_tmp -(unsigned long)dma_addr;
  256. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  257. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  258. acb->devstate[i][j] = ARECA_RAID_GONE;
  259. /*
  260. ** here we need to tell iop 331 our ccb_tmp.HighPart
  261. ** if ccb_tmp.HighPart is not zero
  262. */
  263. intmask_org = arcmsr_disable_outbound_ints(acb);
  264. }
  265. break;
  266. case ACB_ADAPTER_TYPE_B: {
  267. struct pci_dev *pdev = acb->pdev;
  268. struct MessageUnit_B *reg;
  269. void __iomem *mem_base0, *mem_base1;
  270. void *dma_coherent;
  271. dma_addr_t dma_coherent_handle, dma_addr;
  272. uint32_t intmask_org;
  273. struct CommandControlBlock *ccb_tmp;
  274. int i, j;
  275. dma_coherent = dma_alloc_coherent(&pdev->dev,
  276. ((ARCMSR_MAX_FREECCB_NUM *
  277. sizeof(struct CommandControlBlock) + 0x20) +
  278. sizeof(struct MessageUnit_B)),
  279. &dma_coherent_handle, GFP_KERNEL);
  280. if (!dma_coherent)
  281. return -ENOMEM;
  282. acb->dma_coherent = dma_coherent;
  283. acb->dma_coherent_handle = dma_coherent_handle;
  284. if (((unsigned long)dma_coherent & 0x1F)) {
  285. dma_coherent = dma_coherent +
  286. (0x20 - ((unsigned long)dma_coherent & 0x1F));
  287. dma_coherent_handle = dma_coherent_handle +
  288. (0x20 - ((unsigned long)dma_coherent_handle & 0x1F));
  289. }
  290. dma_addr = dma_coherent_handle;
  291. ccb_tmp = (struct CommandControlBlock *)dma_coherent;
  292. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  293. ccb_tmp->cdb_shifted_phyaddr = dma_addr >> 5;
  294. ccb_tmp->acb = acb;
  295. acb->pccb_pool[i] = ccb_tmp;
  296. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  297. dma_addr = dma_addr + sizeof(struct CommandControlBlock);
  298. ccb_tmp++;
  299. }
  300. reg = (struct MessageUnit_B *)(dma_coherent +
  301. ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock));
  302. acb->pmuB = reg;
  303. mem_base0 = ioremap(pci_resource_start(pdev, 0),
  304. pci_resource_len(pdev, 0));
  305. if (!mem_base0)
  306. goto out;
  307. mem_base1 = ioremap(pci_resource_start(pdev, 2),
  308. pci_resource_len(pdev, 2));
  309. if (!mem_base1) {
  310. iounmap(mem_base0);
  311. goto out;
  312. }
  313. reg->drv2iop_doorbell_reg = mem_base0 + ARCMSR_DRV2IOP_DOORBELL;
  314. reg->drv2iop_doorbell_mask_reg = mem_base0 +
  315. ARCMSR_DRV2IOP_DOORBELL_MASK;
  316. reg->iop2drv_doorbell_reg = mem_base0 + ARCMSR_IOP2DRV_DOORBELL;
  317. reg->iop2drv_doorbell_mask_reg = mem_base0 +
  318. ARCMSR_IOP2DRV_DOORBELL_MASK;
  319. reg->ioctl_wbuffer_reg = mem_base1 + ARCMSR_IOCTL_WBUFFER;
  320. reg->ioctl_rbuffer_reg = mem_base1 + ARCMSR_IOCTL_RBUFFER;
  321. reg->msgcode_rwbuffer_reg = mem_base1 + ARCMSR_MSGCODE_RWBUFFER;
  322. acb->vir2phy_offset = (unsigned long)ccb_tmp -(unsigned long)dma_addr;
  323. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  324. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  325. acb->devstate[i][j] = ARECA_RAID_GOOD;
  326. /*
  327. ** here we need to tell iop 331 our ccb_tmp.HighPart
  328. ** if ccb_tmp.HighPart is not zero
  329. */
  330. intmask_org = arcmsr_disable_outbound_ints(acb);
  331. }
  332. break;
  333. }
  334. return 0;
  335. out:
  336. dma_free_coherent(&acb->pdev->dev,
  337. (ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock) + 0x20 +
  338. sizeof(struct MessageUnit_B)), acb->dma_coherent, acb->dma_coherent_handle);
  339. return -ENOMEM;
  340. }
  341. static int arcmsr_probe(struct pci_dev *pdev,
  342. const struct pci_device_id *id)
  343. {
  344. struct Scsi_Host *host;
  345. struct AdapterControlBlock *acb;
  346. uint8_t bus, dev_fun;
  347. int error;
  348. error = pci_enable_device(pdev);
  349. if (error)
  350. goto out;
  351. pci_set_master(pdev);
  352. host = scsi_host_alloc(&arcmsr_scsi_host_template,
  353. sizeof(struct AdapterControlBlock));
  354. if (!host) {
  355. error = -ENOMEM;
  356. goto out_disable_device;
  357. }
  358. acb = (struct AdapterControlBlock *)host->hostdata;
  359. memset(acb, 0, sizeof (struct AdapterControlBlock));
  360. error = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  361. if (error) {
  362. error = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  363. if (error) {
  364. printk(KERN_WARNING
  365. "scsi%d: No suitable DMA mask available\n",
  366. host->host_no);
  367. goto out_host_put;
  368. }
  369. }
  370. bus = pdev->bus->number;
  371. dev_fun = pdev->devfn;
  372. acb->host = host;
  373. acb->pdev = pdev;
  374. host->max_sectors = ARCMSR_MAX_XFER_SECTORS;
  375. host->max_lun = ARCMSR_MAX_TARGETLUN;
  376. host->max_id = ARCMSR_MAX_TARGETID;/*16:8*/
  377. host->max_cmd_len = 16; /*this is issue of 64bit LBA, over 2T byte*/
  378. host->sg_tablesize = ARCMSR_MAX_SG_ENTRIES;
  379. host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */
  380. host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
  381. host->this_id = ARCMSR_SCSI_INITIATOR_ID;
  382. host->unique_id = (bus << 8) | dev_fun;
  383. host->irq = pdev->irq;
  384. error = pci_request_regions(pdev, "arcmsr");
  385. if (error) {
  386. goto out_host_put;
  387. }
  388. arcmsr_define_adapter_type(acb);
  389. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  390. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  391. ACB_F_MESSAGE_WQBUFFER_READED);
  392. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  393. INIT_LIST_HEAD(&acb->ccb_free_list);
  394. error = arcmsr_alloc_ccb_pool(acb);
  395. if (error)
  396. goto out_release_regions;
  397. error = request_irq(pdev->irq, arcmsr_do_interrupt,
  398. IRQF_SHARED, "arcmsr", acb);
  399. if (error)
  400. goto out_free_ccb_pool;
  401. arcmsr_iop_init(acb);
  402. pci_set_drvdata(pdev, host);
  403. if (strncmp(acb->firm_version, "V1.42", 5) >= 0)
  404. host->max_sectors= ARCMSR_MAX_XFER_SECTORS_B;
  405. error = scsi_add_host(host, &pdev->dev);
  406. if (error)
  407. goto out_free_irq;
  408. error = arcmsr_alloc_sysfs_attr(acb);
  409. if (error)
  410. goto out_free_sysfs;
  411. scsi_scan_host(host);
  412. #ifdef CONFIG_SCSI_ARCMSR_AER
  413. pci_enable_pcie_error_reporting(pdev);
  414. #endif
  415. return 0;
  416. out_free_sysfs:
  417. out_free_irq:
  418. free_irq(pdev->irq, acb);
  419. out_free_ccb_pool:
  420. arcmsr_free_ccb_pool(acb);
  421. out_release_regions:
  422. pci_release_regions(pdev);
  423. out_host_put:
  424. scsi_host_put(host);
  425. out_disable_device:
  426. pci_disable_device(pdev);
  427. out:
  428. return error;
  429. }
  430. static uint8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
  431. {
  432. struct MessageUnit_A __iomem *reg = acb->pmuA;
  433. uint32_t Index;
  434. uint8_t Retries = 0x00;
  435. do {
  436. for (Index = 0; Index < 100; Index++) {
  437. if (readl(&reg->outbound_intstatus) &
  438. ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  439. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
  440. &reg->outbound_intstatus);
  441. return 0x00;
  442. }
  443. msleep(10);
  444. }/*max 1 seconds*/
  445. } while (Retries++ < 20);/*max 20 sec*/
  446. return 0xff;
  447. }
  448. static uint8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
  449. {
  450. struct MessageUnit_B *reg = acb->pmuB;
  451. uint32_t Index;
  452. uint8_t Retries = 0x00;
  453. do {
  454. for (Index = 0; Index < 100; Index++) {
  455. if (readl(reg->iop2drv_doorbell_reg)
  456. & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  457. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN
  458. , reg->iop2drv_doorbell_reg);
  459. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell_reg);
  460. return 0x00;
  461. }
  462. msleep(10);
  463. }/*max 1 seconds*/
  464. } while (Retries++ < 20);/*max 20 sec*/
  465. return 0xff;
  466. }
  467. static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
  468. {
  469. struct MessageUnit_A __iomem *reg = acb->pmuA;
  470. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  471. if (arcmsr_hba_wait_msgint_ready(acb))
  472. printk(KERN_NOTICE
  473. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  474. , acb->host->host_no);
  475. }
  476. static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
  477. {
  478. struct MessageUnit_B *reg = acb->pmuB;
  479. writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell_reg);
  480. if (arcmsr_hbb_wait_msgint_ready(acb))
  481. printk(KERN_NOTICE
  482. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  483. , acb->host->host_no);
  484. }
  485. static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
  486. {
  487. switch (acb->adapter_type) {
  488. case ACB_ADAPTER_TYPE_A: {
  489. arcmsr_abort_hba_allcmd(acb);
  490. }
  491. break;
  492. case ACB_ADAPTER_TYPE_B: {
  493. arcmsr_abort_hbb_allcmd(acb);
  494. }
  495. }
  496. }
  497. static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
  498. {
  499. struct scsi_cmnd *pcmd = ccb->pcmd;
  500. scsi_dma_unmap(pcmd);
  501. }
  502. static void arcmsr_ccb_complete(struct CommandControlBlock *ccb, int stand_flag)
  503. {
  504. struct AdapterControlBlock *acb = ccb->acb;
  505. struct scsi_cmnd *pcmd = ccb->pcmd;
  506. arcmsr_pci_unmap_dma(ccb);
  507. if (stand_flag == 1)
  508. atomic_dec(&acb->ccboutstandingcount);
  509. ccb->startdone = ARCMSR_CCB_DONE;
  510. ccb->ccb_flags = 0;
  511. list_add_tail(&ccb->list, &acb->ccb_free_list);
  512. pcmd->scsi_done(pcmd);
  513. }
  514. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
  515. {
  516. struct MessageUnit_A __iomem *reg = acb->pmuA;
  517. int retry_count = 30;
  518. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  519. do {
  520. if (!arcmsr_hba_wait_msgint_ready(acb))
  521. break;
  522. else {
  523. retry_count--;
  524. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  525. timeout, retry count down = %d \n", acb->host->host_no, retry_count);
  526. }
  527. } while (retry_count != 0);
  528. }
  529. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
  530. {
  531. struct MessageUnit_B *reg = acb->pmuB;
  532. int retry_count = 30;
  533. writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell_reg);
  534. do {
  535. if (!arcmsr_hbb_wait_msgint_ready(acb))
  536. break;
  537. else {
  538. retry_count--;
  539. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  540. timeout,retry count down = %d \n", acb->host->host_no, retry_count);
  541. }
  542. } while (retry_count != 0);
  543. }
  544. static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
  545. {
  546. switch (acb->adapter_type) {
  547. case ACB_ADAPTER_TYPE_A: {
  548. arcmsr_flush_hba_cache(acb);
  549. }
  550. break;
  551. case ACB_ADAPTER_TYPE_B: {
  552. arcmsr_flush_hbb_cache(acb);
  553. }
  554. }
  555. }
  556. static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
  557. {
  558. struct scsi_cmnd *pcmd = ccb->pcmd;
  559. struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
  560. pcmd->result = DID_OK << 16;
  561. if (sensebuffer) {
  562. int sense_data_length =
  563. sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
  564. ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
  565. memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
  566. memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
  567. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  568. sensebuffer->Valid = 1;
  569. }
  570. }
  571. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
  572. {
  573. u32 orig_mask = 0;
  574. switch (acb->adapter_type) {
  575. case ACB_ADAPTER_TYPE_A : {
  576. struct MessageUnit_A __iomem *reg = acb->pmuA;
  577. orig_mask = readl(&reg->outbound_intmask)|\
  578. ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE;
  579. writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
  580. &reg->outbound_intmask);
  581. }
  582. break;
  583. case ACB_ADAPTER_TYPE_B : {
  584. struct MessageUnit_B *reg = acb->pmuB;
  585. orig_mask = readl(reg->iop2drv_doorbell_mask_reg) & \
  586. (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
  587. writel(0, reg->iop2drv_doorbell_mask_reg);
  588. }
  589. break;
  590. }
  591. return orig_mask;
  592. }
  593. static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb, \
  594. struct CommandControlBlock *ccb, uint32_t flag_ccb)
  595. {
  596. uint8_t id, lun;
  597. id = ccb->pcmd->device->id;
  598. lun = ccb->pcmd->device->lun;
  599. if (!(flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR)) {
  600. if (acb->devstate[id][lun] == ARECA_RAID_GONE)
  601. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  602. ccb->pcmd->result = DID_OK << 16;
  603. arcmsr_ccb_complete(ccb, 1);
  604. } else {
  605. switch (ccb->arcmsr_cdb.DeviceStatus) {
  606. case ARCMSR_DEV_SELECT_TIMEOUT: {
  607. acb->devstate[id][lun] = ARECA_RAID_GONE;
  608. ccb->pcmd->result = DID_NO_CONNECT << 16;
  609. arcmsr_ccb_complete(ccb, 1);
  610. }
  611. break;
  612. case ARCMSR_DEV_ABORTED:
  613. case ARCMSR_DEV_INIT_FAIL: {
  614. acb->devstate[id][lun] = ARECA_RAID_GONE;
  615. ccb->pcmd->result = DID_BAD_TARGET << 16;
  616. arcmsr_ccb_complete(ccb, 1);
  617. }
  618. break;
  619. case ARCMSR_DEV_CHECK_CONDITION: {
  620. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  621. arcmsr_report_sense_info(ccb);
  622. arcmsr_ccb_complete(ccb, 1);
  623. }
  624. break;
  625. default:
  626. printk(KERN_NOTICE
  627. "arcmsr%d: scsi id = %d lun = %d"
  628. " isr get command error done, "
  629. "but got unknown DeviceStatus = 0x%x \n"
  630. , acb->host->host_no
  631. , id
  632. , lun
  633. , ccb->arcmsr_cdb.DeviceStatus);
  634. acb->devstate[id][lun] = ARECA_RAID_GONE;
  635. ccb->pcmd->result = DID_NO_CONNECT << 16;
  636. arcmsr_ccb_complete(ccb, 1);
  637. break;
  638. }
  639. }
  640. }
  641. static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, uint32_t flag_ccb)
  642. {
  643. struct CommandControlBlock *ccb;
  644. ccb = (struct CommandControlBlock *)(acb->vir2phy_offset + (flag_ccb << 5));
  645. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  646. if (ccb->startdone == ARCMSR_CCB_ABORTED) {
  647. struct scsi_cmnd *abortcmd = ccb->pcmd;
  648. if (abortcmd) {
  649. abortcmd->result |= DID_ABORT << 16;
  650. arcmsr_ccb_complete(ccb, 1);
  651. printk(KERN_NOTICE "arcmsr%d: ccb ='0x%p' \
  652. isr got aborted command \n", acb->host->host_no, ccb);
  653. }
  654. }
  655. printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
  656. done acb = '0x%p'"
  657. "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
  658. " ccboutstandingcount = %d \n"
  659. , acb->host->host_no
  660. , acb
  661. , ccb
  662. , ccb->acb
  663. , ccb->startdone
  664. , atomic_read(&acb->ccboutstandingcount));
  665. }
  666. else
  667. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  668. }
  669. static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
  670. {
  671. int i = 0;
  672. uint32_t flag_ccb;
  673. switch (acb->adapter_type) {
  674. case ACB_ADAPTER_TYPE_A: {
  675. struct MessageUnit_A __iomem *reg = acb->pmuA;
  676. uint32_t outbound_intstatus;
  677. outbound_intstatus = readl(&reg->outbound_intstatus) &
  678. acb->outbound_int_enable;
  679. /*clear and abort all outbound posted Q*/
  680. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  681. while (((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
  682. && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  683. arcmsr_drain_donequeue(acb, flag_ccb);
  684. }
  685. }
  686. break;
  687. case ACB_ADAPTER_TYPE_B: {
  688. struct MessageUnit_B *reg = acb->pmuB;
  689. /*clear all outbound posted Q*/
  690. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  691. if ((flag_ccb = readl(&reg->done_qbuffer[i])) != 0) {
  692. writel(0, &reg->done_qbuffer[i]);
  693. arcmsr_drain_donequeue(acb, flag_ccb);
  694. }
  695. writel(0, &reg->post_qbuffer[i]);
  696. }
  697. reg->doneq_index = 0;
  698. reg->postq_index = 0;
  699. }
  700. break;
  701. }
  702. }
  703. static void arcmsr_remove(struct pci_dev *pdev)
  704. {
  705. struct Scsi_Host *host = pci_get_drvdata(pdev);
  706. struct AdapterControlBlock *acb =
  707. (struct AdapterControlBlock *) host->hostdata;
  708. int poll_count = 0;
  709. arcmsr_free_sysfs_attr(acb);
  710. scsi_remove_host(host);
  711. arcmsr_stop_adapter_bgrb(acb);
  712. arcmsr_flush_adapter_cache(acb);
  713. arcmsr_disable_outbound_ints(acb);
  714. acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
  715. acb->acb_flags &= ~ACB_F_IOP_INITED;
  716. for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++) {
  717. if (!atomic_read(&acb->ccboutstandingcount))
  718. break;
  719. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  720. msleep(25);
  721. }
  722. if (atomic_read(&acb->ccboutstandingcount)) {
  723. int i;
  724. arcmsr_abort_allcmd(acb);
  725. arcmsr_done4abort_postqueue(acb);
  726. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  727. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  728. if (ccb->startdone == ARCMSR_CCB_START) {
  729. ccb->startdone = ARCMSR_CCB_ABORTED;
  730. ccb->pcmd->result = DID_ABORT << 16;
  731. arcmsr_ccb_complete(ccb, 1);
  732. }
  733. }
  734. }
  735. free_irq(pdev->irq, acb);
  736. arcmsr_free_ccb_pool(acb);
  737. pci_release_regions(pdev);
  738. scsi_host_put(host);
  739. pci_disable_device(pdev);
  740. pci_set_drvdata(pdev, NULL);
  741. }
  742. static void arcmsr_shutdown(struct pci_dev *pdev)
  743. {
  744. struct Scsi_Host *host = pci_get_drvdata(pdev);
  745. struct AdapterControlBlock *acb =
  746. (struct AdapterControlBlock *)host->hostdata;
  747. arcmsr_stop_adapter_bgrb(acb);
  748. arcmsr_flush_adapter_cache(acb);
  749. }
  750. static int arcmsr_module_init(void)
  751. {
  752. int error = 0;
  753. error = pci_register_driver(&arcmsr_pci_driver);
  754. return error;
  755. }
  756. static void arcmsr_module_exit(void)
  757. {
  758. pci_unregister_driver(&arcmsr_pci_driver);
  759. }
  760. module_init(arcmsr_module_init);
  761. module_exit(arcmsr_module_exit);
  762. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, \
  763. u32 intmask_org)
  764. {
  765. u32 mask;
  766. switch (acb->adapter_type) {
  767. case ACB_ADAPTER_TYPE_A : {
  768. struct MessageUnit_A __iomem *reg = acb->pmuA;
  769. mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
  770. ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE);
  771. writel(mask, &reg->outbound_intmask);
  772. acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
  773. }
  774. break;
  775. case ACB_ADAPTER_TYPE_B : {
  776. struct MessageUnit_B *reg = acb->pmuB;
  777. mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK | \
  778. ARCMSR_IOP2DRV_DATA_READ_OK | ARCMSR_IOP2DRV_CDB_DONE);
  779. writel(mask, reg->iop2drv_doorbell_mask_reg);
  780. acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
  781. }
  782. }
  783. }
  784. static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
  785. struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
  786. {
  787. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  788. int8_t *psge = (int8_t *)&arcmsr_cdb->u;
  789. __le32 address_lo, address_hi;
  790. int arccdbsize = 0x30;
  791. int nseg;
  792. ccb->pcmd = pcmd;
  793. memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
  794. arcmsr_cdb->Bus = 0;
  795. arcmsr_cdb->TargetID = pcmd->device->id;
  796. arcmsr_cdb->LUN = pcmd->device->lun;
  797. arcmsr_cdb->Function = 1;
  798. arcmsr_cdb->CdbLength = (uint8_t)pcmd->cmd_len;
  799. arcmsr_cdb->Context = (unsigned long)arcmsr_cdb;
  800. memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
  801. nseg = scsi_dma_map(pcmd);
  802. if (nseg > ARCMSR_MAX_SG_ENTRIES)
  803. return FAILED;
  804. BUG_ON(nseg < 0);
  805. if (nseg) {
  806. __le32 length;
  807. int i, cdb_sgcount = 0;
  808. struct scatterlist *sg;
  809. /* map stor port SG list to our iop SG List. */
  810. scsi_for_each_sg(pcmd, sg, nseg, i) {
  811. /* Get the physical address of the current data pointer */
  812. length = cpu_to_le32(sg_dma_len(sg));
  813. address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
  814. address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
  815. if (address_hi == 0) {
  816. struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
  817. pdma_sg->address = address_lo;
  818. pdma_sg->length = length;
  819. psge += sizeof (struct SG32ENTRY);
  820. arccdbsize += sizeof (struct SG32ENTRY);
  821. } else {
  822. struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
  823. pdma_sg->addresshigh = address_hi;
  824. pdma_sg->address = address_lo;
  825. pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
  826. psge += sizeof (struct SG64ENTRY);
  827. arccdbsize += sizeof (struct SG64ENTRY);
  828. }
  829. cdb_sgcount++;
  830. }
  831. arcmsr_cdb->sgcount = (uint8_t)cdb_sgcount;
  832. arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
  833. if ( arccdbsize > 256)
  834. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
  835. }
  836. if (pcmd->sc_data_direction == DMA_TO_DEVICE ) {
  837. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
  838. ccb->ccb_flags |= CCB_FLAG_WRITE;
  839. }
  840. return SUCCESS;
  841. }
  842. static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
  843. {
  844. uint32_t cdb_shifted_phyaddr = ccb->cdb_shifted_phyaddr;
  845. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  846. atomic_inc(&acb->ccboutstandingcount);
  847. ccb->startdone = ARCMSR_CCB_START;
  848. switch (acb->adapter_type) {
  849. case ACB_ADAPTER_TYPE_A: {
  850. struct MessageUnit_A __iomem *reg = acb->pmuA;
  851. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
  852. writel(cdb_shifted_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
  853. &reg->inbound_queueport);
  854. else {
  855. writel(cdb_shifted_phyaddr, &reg->inbound_queueport);
  856. }
  857. }
  858. break;
  859. case ACB_ADAPTER_TYPE_B: {
  860. struct MessageUnit_B *reg = acb->pmuB;
  861. uint32_t ending_index, index = reg->postq_index;
  862. ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
  863. writel(0, &reg->post_qbuffer[ending_index]);
  864. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
  865. writel(cdb_shifted_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,\
  866. &reg->post_qbuffer[index]);
  867. }
  868. else {
  869. writel(cdb_shifted_phyaddr, &reg->post_qbuffer[index]);
  870. }
  871. index++;
  872. index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
  873. reg->postq_index = index;
  874. writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell_reg);
  875. }
  876. break;
  877. }
  878. }
  879. static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
  880. {
  881. struct MessageUnit_A __iomem *reg = acb->pmuA;
  882. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  883. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  884. if (arcmsr_hba_wait_msgint_ready(acb)) {
  885. printk(KERN_NOTICE
  886. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  887. , acb->host->host_no);
  888. }
  889. }
  890. static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
  891. {
  892. struct MessageUnit_B *reg = acb->pmuB;
  893. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  894. writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell_reg);
  895. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  896. printk(KERN_NOTICE
  897. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  898. , acb->host->host_no);
  899. }
  900. }
  901. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
  902. {
  903. switch (acb->adapter_type) {
  904. case ACB_ADAPTER_TYPE_A: {
  905. arcmsr_stop_hba_bgrb(acb);
  906. }
  907. break;
  908. case ACB_ADAPTER_TYPE_B: {
  909. arcmsr_stop_hbb_bgrb(acb);
  910. }
  911. break;
  912. }
  913. }
  914. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
  915. {
  916. switch (acb->adapter_type) {
  917. case ACB_ADAPTER_TYPE_A: {
  918. iounmap(acb->pmuA);
  919. dma_free_coherent(&acb->pdev->dev,
  920. ARCMSR_MAX_FREECCB_NUM * sizeof (struct CommandControlBlock) + 0x20,
  921. acb->dma_coherent,
  922. acb->dma_coherent_handle);
  923. break;
  924. }
  925. case ACB_ADAPTER_TYPE_B: {
  926. struct MessageUnit_B *reg = acb->pmuB;
  927. iounmap(reg->drv2iop_doorbell_reg - ARCMSR_DRV2IOP_DOORBELL);
  928. iounmap(reg->ioctl_wbuffer_reg - ARCMSR_IOCTL_WBUFFER);
  929. dma_free_coherent(&acb->pdev->dev,
  930. (ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock) + 0x20 +
  931. sizeof(struct MessageUnit_B)), acb->dma_coherent, acb->dma_coherent_handle);
  932. }
  933. }
  934. }
  935. void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
  936. {
  937. switch (acb->adapter_type) {
  938. case ACB_ADAPTER_TYPE_A: {
  939. struct MessageUnit_A __iomem *reg = acb->pmuA;
  940. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  941. }
  942. break;
  943. case ACB_ADAPTER_TYPE_B: {
  944. struct MessageUnit_B *reg = acb->pmuB;
  945. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell_reg);
  946. }
  947. break;
  948. }
  949. }
  950. static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
  951. {
  952. switch (acb->adapter_type) {
  953. case ACB_ADAPTER_TYPE_A: {
  954. struct MessageUnit_A __iomem *reg = acb->pmuA;
  955. /*
  956. ** push inbound doorbell tell iop, driver data write ok
  957. ** and wait reply on next hwinterrupt for next Qbuffer post
  958. */
  959. writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
  960. }
  961. break;
  962. case ACB_ADAPTER_TYPE_B: {
  963. struct MessageUnit_B *reg = acb->pmuB;
  964. /*
  965. ** push inbound doorbell tell iop, driver data write ok
  966. ** and wait reply on next hwinterrupt for next Qbuffer post
  967. */
  968. writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell_reg);
  969. }
  970. break;
  971. }
  972. }
  973. struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
  974. {
  975. struct QBUFFER __iomem *qbuffer = NULL;
  976. switch (acb->adapter_type) {
  977. case ACB_ADAPTER_TYPE_A: {
  978. struct MessageUnit_A __iomem *reg = acb->pmuA;
  979. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  980. }
  981. break;
  982. case ACB_ADAPTER_TYPE_B: {
  983. struct MessageUnit_B *reg = acb->pmuB;
  984. qbuffer = (struct QBUFFER __iomem *)reg->ioctl_rbuffer_reg;
  985. }
  986. break;
  987. }
  988. return qbuffer;
  989. }
  990. static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
  991. {
  992. struct QBUFFER __iomem *pqbuffer = NULL;
  993. switch (acb->adapter_type) {
  994. case ACB_ADAPTER_TYPE_A: {
  995. struct MessageUnit_A __iomem *reg = acb->pmuA;
  996. pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
  997. }
  998. break;
  999. case ACB_ADAPTER_TYPE_B: {
  1000. struct MessageUnit_B *reg = acb->pmuB;
  1001. pqbuffer = (struct QBUFFER __iomem *)reg->ioctl_wbuffer_reg;
  1002. }
  1003. break;
  1004. }
  1005. return pqbuffer;
  1006. }
  1007. static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
  1008. {
  1009. struct QBUFFER __iomem *prbuffer;
  1010. struct QBUFFER *pQbuffer;
  1011. uint8_t __iomem *iop_data;
  1012. int32_t my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
  1013. rqbuf_lastindex = acb->rqbuf_lastindex;
  1014. rqbuf_firstindex = acb->rqbuf_firstindex;
  1015. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1016. iop_data = (uint8_t __iomem *)prbuffer->data;
  1017. iop_len = prbuffer->data_len;
  1018. my_empty_len = (rqbuf_firstindex - rqbuf_lastindex -1)&(ARCMSR_MAX_QBUFFER -1);
  1019. if (my_empty_len >= iop_len)
  1020. {
  1021. while (iop_len > 0) {
  1022. pQbuffer = (struct QBUFFER *)&acb->rqbuffer[rqbuf_lastindex];
  1023. memcpy(pQbuffer, iop_data,1);
  1024. rqbuf_lastindex++;
  1025. rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1026. iop_data++;
  1027. iop_len--;
  1028. }
  1029. acb->rqbuf_lastindex = rqbuf_lastindex;
  1030. arcmsr_iop_message_read(acb);
  1031. }
  1032. else {
  1033. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1034. }
  1035. }
  1036. static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
  1037. {
  1038. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
  1039. if (acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
  1040. uint8_t *pQbuffer;
  1041. struct QBUFFER __iomem *pwbuffer;
  1042. uint8_t __iomem *iop_data;
  1043. int32_t allxfer_len = 0;
  1044. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1045. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1046. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1047. while ((acb->wqbuf_firstindex != acb->wqbuf_lastindex) && \
  1048. (allxfer_len < 124)) {
  1049. pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
  1050. memcpy(iop_data, pQbuffer, 1);
  1051. acb->wqbuf_firstindex++;
  1052. acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1053. iop_data++;
  1054. allxfer_len++;
  1055. }
  1056. pwbuffer->data_len = allxfer_len;
  1057. arcmsr_iop_message_wrote(acb);
  1058. }
  1059. if (acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
  1060. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1061. }
  1062. }
  1063. static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
  1064. {
  1065. uint32_t outbound_doorbell;
  1066. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1067. outbound_doorbell = readl(&reg->outbound_doorbell);
  1068. writel(outbound_doorbell, &reg->outbound_doorbell);
  1069. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
  1070. arcmsr_iop2drv_data_wrote_handle(acb);
  1071. }
  1072. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
  1073. arcmsr_iop2drv_data_read_handle(acb);
  1074. }
  1075. }
  1076. static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
  1077. {
  1078. uint32_t flag_ccb;
  1079. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1080. while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
  1081. arcmsr_drain_donequeue(acb, flag_ccb);
  1082. }
  1083. }
  1084. static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
  1085. {
  1086. uint32_t index;
  1087. uint32_t flag_ccb;
  1088. struct MessageUnit_B *reg = acb->pmuB;
  1089. index = reg->doneq_index;
  1090. while ((flag_ccb = readl(&reg->done_qbuffer[index])) != 0) {
  1091. writel(0, &reg->done_qbuffer[index]);
  1092. arcmsr_drain_donequeue(acb, flag_ccb);
  1093. index++;
  1094. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1095. reg->doneq_index = index;
  1096. }
  1097. }
  1098. static int arcmsr_handle_hba_isr(struct AdapterControlBlock *acb)
  1099. {
  1100. uint32_t outbound_intstatus;
  1101. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1102. outbound_intstatus = readl(&reg->outbound_intstatus) & \
  1103. acb->outbound_int_enable;
  1104. if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) {
  1105. return 1;
  1106. }
  1107. writel(outbound_intstatus, &reg->outbound_intstatus);
  1108. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
  1109. arcmsr_hba_doorbell_isr(acb);
  1110. }
  1111. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
  1112. arcmsr_hba_postqueue_isr(acb);
  1113. }
  1114. return 0;
  1115. }
  1116. static int arcmsr_handle_hbb_isr(struct AdapterControlBlock *acb)
  1117. {
  1118. uint32_t outbound_doorbell;
  1119. struct MessageUnit_B *reg = acb->pmuB;
  1120. outbound_doorbell = readl(reg->iop2drv_doorbell_reg) & \
  1121. acb->outbound_int_enable;
  1122. if (!outbound_doorbell)
  1123. return 1;
  1124. writel(~outbound_doorbell, reg->iop2drv_doorbell_reg);
  1125. /*in case the last action of doorbell interrupt clearance is cached, this action can push HW to write down the clear bit*/
  1126. readl(reg->iop2drv_doorbell_reg);
  1127. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell_reg);
  1128. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
  1129. arcmsr_iop2drv_data_wrote_handle(acb);
  1130. }
  1131. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
  1132. arcmsr_iop2drv_data_read_handle(acb);
  1133. }
  1134. if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
  1135. arcmsr_hbb_postqueue_isr(acb);
  1136. }
  1137. return 0;
  1138. }
  1139. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
  1140. {
  1141. switch (acb->adapter_type) {
  1142. case ACB_ADAPTER_TYPE_A: {
  1143. if (arcmsr_handle_hba_isr(acb)) {
  1144. return IRQ_NONE;
  1145. }
  1146. }
  1147. break;
  1148. case ACB_ADAPTER_TYPE_B: {
  1149. if (arcmsr_handle_hbb_isr(acb)) {
  1150. return IRQ_NONE;
  1151. }
  1152. }
  1153. break;
  1154. }
  1155. return IRQ_HANDLED;
  1156. }
  1157. static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
  1158. {
  1159. if (acb) {
  1160. /* stop adapter background rebuild */
  1161. if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
  1162. uint32_t intmask_org;
  1163. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1164. intmask_org = arcmsr_disable_outbound_ints(acb);
  1165. arcmsr_stop_adapter_bgrb(acb);
  1166. arcmsr_flush_adapter_cache(acb);
  1167. arcmsr_enable_outbound_ints(acb, intmask_org);
  1168. }
  1169. }
  1170. }
  1171. void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
  1172. {
  1173. int32_t wqbuf_firstindex, wqbuf_lastindex;
  1174. uint8_t *pQbuffer;
  1175. struct QBUFFER __iomem *pwbuffer;
  1176. uint8_t __iomem *iop_data;
  1177. int32_t allxfer_len = 0;
  1178. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1179. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1180. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1181. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1182. wqbuf_firstindex = acb->wqbuf_firstindex;
  1183. wqbuf_lastindex = acb->wqbuf_lastindex;
  1184. while ((wqbuf_firstindex != wqbuf_lastindex) && (allxfer_len < 124)) {
  1185. pQbuffer = &acb->wqbuffer[wqbuf_firstindex];
  1186. memcpy(iop_data, pQbuffer, 1);
  1187. wqbuf_firstindex++;
  1188. wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1189. iop_data++;
  1190. allxfer_len++;
  1191. }
  1192. acb->wqbuf_firstindex = wqbuf_firstindex;
  1193. pwbuffer->data_len = allxfer_len;
  1194. arcmsr_iop_message_wrote(acb);
  1195. }
  1196. }
  1197. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, \
  1198. struct scsi_cmnd *cmd)
  1199. {
  1200. struct CMD_MESSAGE_FIELD *pcmdmessagefld;
  1201. int retvalue = 0, transfer_len = 0;
  1202. char *buffer;
  1203. struct scatterlist *sg;
  1204. uint32_t controlcode = (uint32_t ) cmd->cmnd[5] << 24 |
  1205. (uint32_t ) cmd->cmnd[6] << 16 |
  1206. (uint32_t ) cmd->cmnd[7] << 8 |
  1207. (uint32_t ) cmd->cmnd[8];
  1208. /* 4 bytes: Areca io control code */
  1209. sg = scsi_sglist(cmd);
  1210. buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
  1211. if (scsi_sg_count(cmd) > 1) {
  1212. retvalue = ARCMSR_MESSAGE_FAIL;
  1213. goto message_out;
  1214. }
  1215. transfer_len += sg->length;
  1216. if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
  1217. retvalue = ARCMSR_MESSAGE_FAIL;
  1218. goto message_out;
  1219. }
  1220. pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
  1221. switch(controlcode) {
  1222. case ARCMSR_MESSAGE_READ_RQBUFFER: {
  1223. unsigned char *ver_addr;
  1224. uint8_t *pQbuffer, *ptmpQbuffer;
  1225. int32_t allxfer_len = 0;
  1226. ver_addr = kmalloc(1032, GFP_ATOMIC);
  1227. if (!ver_addr) {
  1228. retvalue = ARCMSR_MESSAGE_FAIL;
  1229. goto message_out;
  1230. }
  1231. ptmpQbuffer = ver_addr;
  1232. while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
  1233. && (allxfer_len < 1031)) {
  1234. pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
  1235. memcpy(ptmpQbuffer, pQbuffer, 1);
  1236. acb->rqbuf_firstindex++;
  1237. acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1238. ptmpQbuffer++;
  1239. allxfer_len++;
  1240. }
  1241. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1242. struct QBUFFER __iomem *prbuffer;
  1243. uint8_t __iomem *iop_data;
  1244. int32_t iop_len;
  1245. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1246. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1247. iop_data = prbuffer->data;
  1248. iop_len = readl(&prbuffer->data_len);
  1249. while (iop_len > 0) {
  1250. acb->rqbuffer[acb->rqbuf_lastindex] = readb(iop_data);
  1251. acb->rqbuf_lastindex++;
  1252. acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1253. iop_data++;
  1254. iop_len--;
  1255. }
  1256. arcmsr_iop_message_read(acb);
  1257. }
  1258. memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, allxfer_len);
  1259. pcmdmessagefld->cmdmessage.Length = allxfer_len;
  1260. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1261. kfree(ver_addr);
  1262. }
  1263. break;
  1264. case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
  1265. unsigned char *ver_addr;
  1266. int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
  1267. uint8_t *pQbuffer, *ptmpuserbuffer;
  1268. ver_addr = kmalloc(1032, GFP_ATOMIC);
  1269. if (!ver_addr) {
  1270. retvalue = ARCMSR_MESSAGE_FAIL;
  1271. goto message_out;
  1272. }
  1273. ptmpuserbuffer = ver_addr;
  1274. user_len = pcmdmessagefld->cmdmessage.Length;
  1275. memcpy(ptmpuserbuffer, pcmdmessagefld->messagedatabuffer, user_len);
  1276. wqbuf_lastindex = acb->wqbuf_lastindex;
  1277. wqbuf_firstindex = acb->wqbuf_firstindex;
  1278. if (wqbuf_lastindex != wqbuf_firstindex) {
  1279. struct SENSE_DATA *sensebuffer =
  1280. (struct SENSE_DATA *)cmd->sense_buffer;
  1281. arcmsr_post_ioctldata2iop(acb);
  1282. /* has error report sensedata */
  1283. sensebuffer->ErrorCode = 0x70;
  1284. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1285. sensebuffer->AdditionalSenseLength = 0x0A;
  1286. sensebuffer->AdditionalSenseCode = 0x20;
  1287. sensebuffer->Valid = 1;
  1288. retvalue = ARCMSR_MESSAGE_FAIL;
  1289. } else {
  1290. my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
  1291. &(ARCMSR_MAX_QBUFFER - 1);
  1292. if (my_empty_len >= user_len) {
  1293. while (user_len > 0) {
  1294. pQbuffer =
  1295. &acb->wqbuffer[acb->wqbuf_lastindex];
  1296. memcpy(pQbuffer, ptmpuserbuffer, 1);
  1297. acb->wqbuf_lastindex++;
  1298. acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1299. ptmpuserbuffer++;
  1300. user_len--;
  1301. }
  1302. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
  1303. acb->acb_flags &=
  1304. ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1305. arcmsr_post_ioctldata2iop(acb);
  1306. }
  1307. } else {
  1308. /* has error report sensedata */
  1309. struct SENSE_DATA *sensebuffer =
  1310. (struct SENSE_DATA *)cmd->sense_buffer;
  1311. sensebuffer->ErrorCode = 0x70;
  1312. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1313. sensebuffer->AdditionalSenseLength = 0x0A;
  1314. sensebuffer->AdditionalSenseCode = 0x20;
  1315. sensebuffer->Valid = 1;
  1316. retvalue = ARCMSR_MESSAGE_FAIL;
  1317. }
  1318. }
  1319. kfree(ver_addr);
  1320. }
  1321. break;
  1322. case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
  1323. uint8_t *pQbuffer = acb->rqbuffer;
  1324. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1325. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1326. arcmsr_iop_message_read(acb);
  1327. }
  1328. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  1329. acb->rqbuf_firstindex = 0;
  1330. acb->rqbuf_lastindex = 0;
  1331. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1332. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1333. }
  1334. break;
  1335. case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
  1336. uint8_t *pQbuffer = acb->wqbuffer;
  1337. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1338. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1339. arcmsr_iop_message_read(acb);
  1340. }
  1341. acb->acb_flags |=
  1342. (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  1343. ACB_F_MESSAGE_WQBUFFER_READED);
  1344. acb->wqbuf_firstindex = 0;
  1345. acb->wqbuf_lastindex = 0;
  1346. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1347. pcmdmessagefld->cmdmessage.ReturnCode =
  1348. ARCMSR_MESSAGE_RETURNCODE_OK;
  1349. }
  1350. break;
  1351. case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
  1352. uint8_t *pQbuffer;
  1353. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1354. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1355. arcmsr_iop_message_read(acb);
  1356. }
  1357. acb->acb_flags |=
  1358. (ACB_F_MESSAGE_WQBUFFER_CLEARED
  1359. | ACB_F_MESSAGE_RQBUFFER_CLEARED
  1360. | ACB_F_MESSAGE_WQBUFFER_READED);
  1361. acb->rqbuf_firstindex = 0;
  1362. acb->rqbuf_lastindex = 0;
  1363. acb->wqbuf_firstindex = 0;
  1364. acb->wqbuf_lastindex = 0;
  1365. pQbuffer = acb->rqbuffer;
  1366. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1367. pQbuffer = acb->wqbuffer;
  1368. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1369. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1370. }
  1371. break;
  1372. case ARCMSR_MESSAGE_RETURN_CODE_3F: {
  1373. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
  1374. }
  1375. break;
  1376. case ARCMSR_MESSAGE_SAY_HELLO: {
  1377. int8_t *hello_string = "Hello! I am ARCMSR";
  1378. memcpy(pcmdmessagefld->messagedatabuffer, hello_string
  1379. , (int16_t)strlen(hello_string));
  1380. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1381. }
  1382. break;
  1383. case ARCMSR_MESSAGE_SAY_GOODBYE:
  1384. arcmsr_iop_parking(acb);
  1385. break;
  1386. case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
  1387. arcmsr_flush_adapter_cache(acb);
  1388. break;
  1389. default:
  1390. retvalue = ARCMSR_MESSAGE_FAIL;
  1391. }
  1392. message_out:
  1393. sg = scsi_sglist(cmd);
  1394. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1395. return retvalue;
  1396. }
  1397. static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
  1398. {
  1399. struct list_head *head = &acb->ccb_free_list;
  1400. struct CommandControlBlock *ccb = NULL;
  1401. if (!list_empty(head)) {
  1402. ccb = list_entry(head->next, struct CommandControlBlock, list);
  1403. list_del(head->next);
  1404. }
  1405. return ccb;
  1406. }
  1407. static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
  1408. struct scsi_cmnd *cmd)
  1409. {
  1410. switch (cmd->cmnd[0]) {
  1411. case INQUIRY: {
  1412. unsigned char inqdata[36];
  1413. char *buffer;
  1414. struct scatterlist *sg;
  1415. if (cmd->device->lun) {
  1416. cmd->result = (DID_TIME_OUT << 16);
  1417. cmd->scsi_done(cmd);
  1418. return;
  1419. }
  1420. inqdata[0] = TYPE_PROCESSOR;
  1421. /* Periph Qualifier & Periph Dev Type */
  1422. inqdata[1] = 0;
  1423. /* rem media bit & Dev Type Modifier */
  1424. inqdata[2] = 0;
  1425. /* ISO, ECMA, & ANSI versions */
  1426. inqdata[4] = 31;
  1427. /* length of additional data */
  1428. strncpy(&inqdata[8], "Areca ", 8);
  1429. /* Vendor Identification */
  1430. strncpy(&inqdata[16], "RAID controller ", 16);
  1431. /* Product Identification */
  1432. strncpy(&inqdata[32], "R001", 4); /* Product Revision */
  1433. sg = scsi_sglist(cmd);
  1434. buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
  1435. memcpy(buffer, inqdata, sizeof(inqdata));
  1436. sg = scsi_sglist(cmd);
  1437. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1438. cmd->scsi_done(cmd);
  1439. }
  1440. break;
  1441. case WRITE_BUFFER:
  1442. case READ_BUFFER: {
  1443. if (arcmsr_iop_message_xfer(acb, cmd))
  1444. cmd->result = (DID_ERROR << 16);
  1445. cmd->scsi_done(cmd);
  1446. }
  1447. break;
  1448. default:
  1449. cmd->scsi_done(cmd);
  1450. }
  1451. }
  1452. static int arcmsr_queue_command(struct scsi_cmnd *cmd,
  1453. void (* done)(struct scsi_cmnd *))
  1454. {
  1455. struct Scsi_Host *host = cmd->device->host;
  1456. struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
  1457. struct CommandControlBlock *ccb;
  1458. int target = cmd->device->id;
  1459. int lun = cmd->device->lun;
  1460. cmd->scsi_done = done;
  1461. cmd->host_scribble = NULL;
  1462. cmd->result = 0;
  1463. if (acb->acb_flags & ACB_F_BUS_RESET) {
  1464. printk(KERN_NOTICE "arcmsr%d: bus reset"
  1465. " and return busy \n"
  1466. , acb->host->host_no);
  1467. return SCSI_MLQUEUE_HOST_BUSY;
  1468. }
  1469. if (target == 16) {
  1470. /* virtual device for iop message transfer */
  1471. arcmsr_handle_virtual_command(acb, cmd);
  1472. return 0;
  1473. }
  1474. if (acb->devstate[target][lun] == ARECA_RAID_GONE) {
  1475. uint8_t block_cmd;
  1476. block_cmd = cmd->cmnd[0] & 0x0f;
  1477. if (block_cmd == 0x08 || block_cmd == 0x0a) {
  1478. printk(KERN_NOTICE
  1479. "arcmsr%d: block 'read/write'"
  1480. "command with gone raid volume"
  1481. " Cmd = %2x, TargetId = %d, Lun = %d \n"
  1482. , acb->host->host_no
  1483. , cmd->cmnd[0]
  1484. , target, lun);
  1485. cmd->result = (DID_NO_CONNECT << 16);
  1486. cmd->scsi_done(cmd);
  1487. return 0;
  1488. }
  1489. }
  1490. if (atomic_read(&acb->ccboutstandingcount) >=
  1491. ARCMSR_MAX_OUTSTANDING_CMD)
  1492. return SCSI_MLQUEUE_HOST_BUSY;
  1493. ccb = arcmsr_get_freeccb(acb);
  1494. if (!ccb)
  1495. return SCSI_MLQUEUE_HOST_BUSY;
  1496. if ( arcmsr_build_ccb( acb, ccb, cmd ) == FAILED ) {
  1497. cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
  1498. cmd->scsi_done(cmd);
  1499. return 0;
  1500. }
  1501. arcmsr_post_ccb(acb, ccb);
  1502. return 0;
  1503. }
  1504. static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
  1505. {
  1506. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1507. char *acb_firm_model = acb->firm_model;
  1508. char *acb_firm_version = acb->firm_version;
  1509. char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
  1510. char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
  1511. int count;
  1512. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  1513. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1514. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  1515. miscellaneous data' timeout \n", acb->host->host_no);
  1516. }
  1517. count = 8;
  1518. while (count) {
  1519. *acb_firm_model = readb(iop_firm_model);
  1520. acb_firm_model++;
  1521. iop_firm_model++;
  1522. count--;
  1523. }
  1524. count = 16;
  1525. while (count) {
  1526. *acb_firm_version = readb(iop_firm_version);
  1527. acb_firm_version++;
  1528. iop_firm_version++;
  1529. count--;
  1530. }
  1531. printk(KERN_INFO "ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n"
  1532. , acb->host->host_no
  1533. , acb->firm_version);
  1534. acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
  1535. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
  1536. acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
  1537. acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
  1538. }
  1539. static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
  1540. {
  1541. struct MessageUnit_B *reg = acb->pmuB;
  1542. uint32_t __iomem *lrwbuffer = reg->msgcode_rwbuffer_reg;
  1543. char *acb_firm_model = acb->firm_model;
  1544. char *acb_firm_version = acb->firm_version;
  1545. char __iomem *iop_firm_model = (char __iomem *)(&lrwbuffer[15]);
  1546. /*firm_model,15,60-67*/
  1547. char __iomem *iop_firm_version = (char __iomem *)(&lrwbuffer[17]);
  1548. /*firm_version,17,68-83*/
  1549. int count;
  1550. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell_reg);
  1551. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1552. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  1553. miscellaneous data' timeout \n", acb->host->host_no);
  1554. }
  1555. count = 8;
  1556. while (count)
  1557. {
  1558. *acb_firm_model = readb(iop_firm_model);
  1559. acb_firm_model++;
  1560. iop_firm_model++;
  1561. count--;
  1562. }
  1563. count = 16;
  1564. while (count)
  1565. {
  1566. *acb_firm_version = readb(iop_firm_version);
  1567. acb_firm_version++;
  1568. iop_firm_version++;
  1569. count--;
  1570. }
  1571. printk(KERN_INFO "ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n",
  1572. acb->host->host_no,
  1573. acb->firm_version);
  1574. lrwbuffer++;
  1575. acb->firm_request_len = readl(lrwbuffer++);
  1576. /*firm_request_len,1,04-07*/
  1577. acb->firm_numbers_queue = readl(lrwbuffer++);
  1578. /*firm_numbers_queue,2,08-11*/
  1579. acb->firm_sdram_size = readl(lrwbuffer++);
  1580. /*firm_sdram_size,3,12-15*/
  1581. acb->firm_hd_channels = readl(lrwbuffer);
  1582. /*firm_ide_channels,4,16-19*/
  1583. }
  1584. static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
  1585. {
  1586. switch (acb->adapter_type) {
  1587. case ACB_ADAPTER_TYPE_A: {
  1588. arcmsr_get_hba_config(acb);
  1589. }
  1590. break;
  1591. case ACB_ADAPTER_TYPE_B: {
  1592. arcmsr_get_hbb_config(acb);
  1593. }
  1594. break;
  1595. }
  1596. }
  1597. static void arcmsr_polling_hba_ccbdone(struct AdapterControlBlock *acb,
  1598. struct CommandControlBlock *poll_ccb)
  1599. {
  1600. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1601. struct CommandControlBlock *ccb;
  1602. uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
  1603. polling_hba_ccb_retry:
  1604. poll_count++;
  1605. outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
  1606. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  1607. while (1) {
  1608. if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
  1609. if (poll_ccb_done)
  1610. break;
  1611. else {
  1612. msleep(25);
  1613. if (poll_count > 100)
  1614. break;
  1615. goto polling_hba_ccb_retry;
  1616. }
  1617. }
  1618. ccb = (struct CommandControlBlock *)(acb->vir2phy_offset + (flag_ccb << 5));
  1619. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  1620. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  1621. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  1622. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  1623. " poll command abort successfully \n"
  1624. , acb->host->host_no
  1625. , ccb->pcmd->device->id
  1626. , ccb->pcmd->device->lun
  1627. , ccb);
  1628. ccb->pcmd->result = DID_ABORT << 16;
  1629. arcmsr_ccb_complete(ccb, 1);
  1630. poll_ccb_done = 1;
  1631. continue;
  1632. }
  1633. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  1634. " command done ccb = '0x%p'"
  1635. "ccboutstandingcount = %d \n"
  1636. , acb->host->host_no
  1637. , ccb
  1638. , atomic_read(&acb->ccboutstandingcount));
  1639. continue;
  1640. }
  1641. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  1642. }
  1643. }
  1644. static void arcmsr_polling_hbb_ccbdone(struct AdapterControlBlock *acb,
  1645. struct CommandControlBlock *poll_ccb)
  1646. {
  1647. struct MessageUnit_B *reg = acb->pmuB;
  1648. struct CommandControlBlock *ccb;
  1649. uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
  1650. int index;
  1651. polling_hbb_ccb_retry:
  1652. poll_count++;
  1653. /* clear doorbell interrupt */
  1654. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell_reg);
  1655. while (1) {
  1656. index = reg->doneq_index;
  1657. if ((flag_ccb = readl(&reg->done_qbuffer[index])) == 0) {
  1658. if (poll_ccb_done)
  1659. break;
  1660. else {
  1661. msleep(25);
  1662. if (poll_count > 100)
  1663. break;
  1664. goto polling_hbb_ccb_retry;
  1665. }
  1666. }
  1667. writel(0, &reg->done_qbuffer[index]);
  1668. index++;
  1669. /*if last index number set it to 0 */
  1670. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1671. reg->doneq_index = index;
  1672. /* check ifcommand done with no error*/
  1673. ccb = (struct CommandControlBlock *)\
  1674. (acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1675. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  1676. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  1677. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  1678. printk(KERN_NOTICE "arcmsr%d: \
  1679. scsi id = %d lun = %d ccb = '0x%p' poll command abort successfully \n"
  1680. ,acb->host->host_no
  1681. ,ccb->pcmd->device->id
  1682. ,ccb->pcmd->device->lun
  1683. ,ccb);
  1684. ccb->pcmd->result = DID_ABORT << 16;
  1685. arcmsr_ccb_complete(ccb, 1);
  1686. continue;
  1687. }
  1688. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  1689. " command done ccb = '0x%p'"
  1690. "ccboutstandingcount = %d \n"
  1691. , acb->host->host_no
  1692. , ccb
  1693. , atomic_read(&acb->ccboutstandingcount));
  1694. continue;
  1695. }
  1696. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  1697. } /*drain reply FIFO*/
  1698. }
  1699. static void arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
  1700. struct CommandControlBlock *poll_ccb)
  1701. {
  1702. switch (acb->adapter_type) {
  1703. case ACB_ADAPTER_TYPE_A: {
  1704. arcmsr_polling_hba_ccbdone(acb,poll_ccb);
  1705. }
  1706. break;
  1707. case ACB_ADAPTER_TYPE_B: {
  1708. arcmsr_polling_hbb_ccbdone(acb,poll_ccb);
  1709. }
  1710. }
  1711. }
  1712. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
  1713. {
  1714. uint32_t cdb_phyaddr, ccb_phyaddr_hi32;
  1715. dma_addr_t dma_coherent_handle;
  1716. /*
  1717. ********************************************************************
  1718. ** here we need to tell iop 331 our freeccb.HighPart
  1719. ** if freeccb.HighPart is not zero
  1720. ********************************************************************
  1721. */
  1722. dma_coherent_handle = acb->dma_coherent_handle;
  1723. cdb_phyaddr = (uint32_t)(dma_coherent_handle);
  1724. ccb_phyaddr_hi32 = (uint32_t)((cdb_phyaddr >> 16) >> 16);
  1725. /*
  1726. ***********************************************************************
  1727. ** if adapter type B, set window of "post command Q"
  1728. ***********************************************************************
  1729. */
  1730. switch (acb->adapter_type) {
  1731. case ACB_ADAPTER_TYPE_A: {
  1732. if (ccb_phyaddr_hi32 != 0) {
  1733. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1734. uint32_t intmask_org;
  1735. intmask_org = arcmsr_disable_outbound_ints(acb);
  1736. writel(ARCMSR_SIGNATURE_SET_CONFIG, \
  1737. &reg->message_rwbuffer[0]);
  1738. writel(ccb_phyaddr_hi32, &reg->message_rwbuffer[1]);
  1739. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
  1740. &reg->inbound_msgaddr0);
  1741. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1742. printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
  1743. part physical address timeout\n",
  1744. acb->host->host_no);
  1745. return 1;
  1746. }
  1747. arcmsr_enable_outbound_ints(acb, intmask_org);
  1748. }
  1749. }
  1750. break;
  1751. case ACB_ADAPTER_TYPE_B: {
  1752. unsigned long post_queue_phyaddr;
  1753. uint32_t __iomem *rwbuffer;
  1754. struct MessageUnit_B *reg = acb->pmuB;
  1755. uint32_t intmask_org;
  1756. intmask_org = arcmsr_disable_outbound_ints(acb);
  1757. reg->postq_index = 0;
  1758. reg->doneq_index = 0;
  1759. writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell_reg);
  1760. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1761. printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
  1762. acb->host->host_no);
  1763. return 1;
  1764. }
  1765. post_queue_phyaddr = cdb_phyaddr + ARCMSR_MAX_FREECCB_NUM * \
  1766. sizeof(struct CommandControlBlock) + offsetof(struct MessageUnit_B, post_qbuffer) ;
  1767. rwbuffer = reg->msgcode_rwbuffer_reg;
  1768. /* driver "set config" signature */
  1769. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  1770. /* normal should be zero */
  1771. writel(ccb_phyaddr_hi32, rwbuffer++);
  1772. /* postQ size (256 + 8)*4 */
  1773. writel(post_queue_phyaddr, rwbuffer++);
  1774. /* doneQ size (256 + 8)*4 */
  1775. writel(post_queue_phyaddr + 1056, rwbuffer++);
  1776. /* ccb maxQ size must be --> [(256 + 8)*4]*/
  1777. writel(1056, rwbuffer);
  1778. writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell_reg);
  1779. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1780. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  1781. timeout \n",acb->host->host_no);
  1782. return 1;
  1783. }
  1784. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell_reg);
  1785. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1786. printk(KERN_NOTICE "arcmsr%d: 'can not set diver mode \n"\
  1787. ,acb->host->host_no);
  1788. return 1;
  1789. }
  1790. arcmsr_enable_outbound_ints(acb, intmask_org);
  1791. }
  1792. break;
  1793. }
  1794. return 0;
  1795. }
  1796. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
  1797. {
  1798. uint32_t firmware_state = 0;
  1799. switch (acb->adapter_type) {
  1800. case ACB_ADAPTER_TYPE_A: {
  1801. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1802. do {
  1803. firmware_state = readl(&reg->outbound_msgaddr1);
  1804. } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
  1805. }
  1806. break;
  1807. case ACB_ADAPTER_TYPE_B: {
  1808. struct MessageUnit_B *reg = acb->pmuB;
  1809. do {
  1810. firmware_state = readl(reg->iop2drv_doorbell_reg);
  1811. } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
  1812. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell_reg);
  1813. }
  1814. break;
  1815. }
  1816. }
  1817. static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
  1818. {
  1819. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1820. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  1821. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
  1822. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1823. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  1824. rebulid' timeout \n", acb->host->host_no);
  1825. }
  1826. }
  1827. static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
  1828. {
  1829. struct MessageUnit_B *reg = acb->pmuB;
  1830. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  1831. writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell_reg);
  1832. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1833. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  1834. rebulid' timeout \n",acb->host->host_no);
  1835. }
  1836. }
  1837. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
  1838. {
  1839. switch (acb->adapter_type) {
  1840. case ACB_ADAPTER_TYPE_A:
  1841. arcmsr_start_hba_bgrb(acb);
  1842. break;
  1843. case ACB_ADAPTER_TYPE_B:
  1844. arcmsr_start_hbb_bgrb(acb);
  1845. break;
  1846. }
  1847. }
  1848. static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
  1849. {
  1850. switch (acb->adapter_type) {
  1851. case ACB_ADAPTER_TYPE_A: {
  1852. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1853. uint32_t outbound_doorbell;
  1854. /* empty doorbell Qbuffer if door bell ringed */
  1855. outbound_doorbell = readl(&reg->outbound_doorbell);
  1856. /*clear doorbell interrupt */
  1857. writel(outbound_doorbell, &reg->outbound_doorbell);
  1858. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  1859. }
  1860. break;
  1861. case ACB_ADAPTER_TYPE_B: {
  1862. struct MessageUnit_B *reg = acb->pmuB;
  1863. /*clear interrupt and message state*/
  1864. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell_reg);
  1865. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell_reg);
  1866. /* let IOP know data has been read */
  1867. }
  1868. break;
  1869. }
  1870. }
  1871. static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
  1872. {
  1873. switch (acb->adapter_type) {
  1874. case ACB_ADAPTER_TYPE_A:
  1875. return;
  1876. case ACB_ADAPTER_TYPE_B:
  1877. {
  1878. struct MessageUnit_B *reg = acb->pmuB;
  1879. writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell_reg);
  1880. if(arcmsr_hbb_wait_msgint_ready(acb)) {
  1881. printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
  1882. return;
  1883. }
  1884. }
  1885. break;
  1886. }
  1887. return;
  1888. }
  1889. static void arcmsr_iop_init(struct AdapterControlBlock *acb)
  1890. {
  1891. uint32_t intmask_org;
  1892. /* disable all outbound interrupt */
  1893. intmask_org = arcmsr_disable_outbound_ints(acb);
  1894. arcmsr_wait_firmware_ready(acb);
  1895. arcmsr_iop_confirm(acb);
  1896. arcmsr_get_firmware_spec(acb);
  1897. /*start background rebuild*/
  1898. arcmsr_start_adapter_bgrb(acb);
  1899. /* empty doorbell Qbuffer if door bell ringed */
  1900. arcmsr_clear_doorbell_queue_buffer(acb);
  1901. arcmsr_enable_eoi_mode(acb);
  1902. /* enable outbound Post Queue,outbound doorbell Interrupt */
  1903. arcmsr_enable_outbound_ints(acb, intmask_org);
  1904. acb->acb_flags |= ACB_F_IOP_INITED;
  1905. }
  1906. static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
  1907. {
  1908. struct CommandControlBlock *ccb;
  1909. uint32_t intmask_org;
  1910. int i = 0;
  1911. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  1912. /* talk to iop 331 outstanding command aborted */
  1913. arcmsr_abort_allcmd(acb);
  1914. /* wait for 3 sec for all command aborted*/
  1915. ssleep(3);
  1916. /* disable all outbound interrupt */
  1917. intmask_org = arcmsr_disable_outbound_ints(acb);
  1918. /* clear all outbound posted Q */
  1919. arcmsr_done4abort_postqueue(acb);
  1920. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  1921. ccb = acb->pccb_pool[i];
  1922. if (ccb->startdone == ARCMSR_CCB_START) {
  1923. ccb->startdone = ARCMSR_CCB_ABORTED;
  1924. arcmsr_ccb_complete(ccb, 1);
  1925. }
  1926. }
  1927. /* enable all outbound interrupt */
  1928. arcmsr_enable_outbound_ints(acb, intmask_org);
  1929. }
  1930. }
  1931. static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
  1932. {
  1933. struct AdapterControlBlock *acb =
  1934. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  1935. int i;
  1936. acb->num_resets++;
  1937. acb->acb_flags |= ACB_F_BUS_RESET;
  1938. for (i = 0; i < 400; i++) {
  1939. if (!atomic_read(&acb->ccboutstandingcount))
  1940. break;
  1941. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  1942. msleep(25);
  1943. }
  1944. arcmsr_iop_reset(acb);
  1945. acb->acb_flags &= ~ACB_F_BUS_RESET;
  1946. return SUCCESS;
  1947. }
  1948. static void arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
  1949. struct CommandControlBlock *ccb)
  1950. {
  1951. u32 intmask;
  1952. ccb->startdone = ARCMSR_CCB_ABORTED;
  1953. /*
  1954. ** Wait for 3 sec for all command done.
  1955. */
  1956. ssleep(3);
  1957. intmask = arcmsr_disable_outbound_ints(acb);
  1958. arcmsr_polling_ccbdone(acb, ccb);
  1959. arcmsr_enable_outbound_ints(acb, intmask);
  1960. }
  1961. static int arcmsr_abort(struct scsi_cmnd *cmd)
  1962. {
  1963. struct AdapterControlBlock *acb =
  1964. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  1965. int i = 0;
  1966. printk(KERN_NOTICE
  1967. "arcmsr%d: abort device command of scsi id = %d lun = %d \n",
  1968. acb->host->host_no, cmd->device->id, cmd->device->lun);
  1969. acb->num_aborts++;
  1970. /*
  1971. ************************************************
  1972. ** the all interrupt service routine is locked
  1973. ** we need to handle it as soon as possible and exit
  1974. ************************************************
  1975. */
  1976. if (!atomic_read(&acb->ccboutstandingcount))
  1977. return SUCCESS;
  1978. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  1979. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  1980. if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
  1981. arcmsr_abort_one_cmd(acb, ccb);
  1982. break;
  1983. }
  1984. }
  1985. return SUCCESS;
  1986. }
  1987. static const char *arcmsr_info(struct Scsi_Host *host)
  1988. {
  1989. struct AdapterControlBlock *acb =
  1990. (struct AdapterControlBlock *) host->hostdata;
  1991. static char buf[256];
  1992. char *type;
  1993. int raid6 = 1;
  1994. switch (acb->pdev->device) {
  1995. case PCI_DEVICE_ID_ARECA_1110:
  1996. case PCI_DEVICE_ID_ARECA_1200:
  1997. case PCI_DEVICE_ID_ARECA_1202:
  1998. case PCI_DEVICE_ID_ARECA_1210:
  1999. raid6 = 0;
  2000. /*FALLTHRU*/
  2001. case PCI_DEVICE_ID_ARECA_1120:
  2002. case PCI_DEVICE_ID_ARECA_1130:
  2003. case PCI_DEVICE_ID_ARECA_1160:
  2004. case PCI_DEVICE_ID_ARECA_1170:
  2005. case PCI_DEVICE_ID_ARECA_1201:
  2006. case PCI_DEVICE_ID_ARECA_1220:
  2007. case PCI_DEVICE_ID_ARECA_1230:
  2008. case PCI_DEVICE_ID_ARECA_1260:
  2009. case PCI_DEVICE_ID_ARECA_1270:
  2010. case PCI_DEVICE_ID_ARECA_1280:
  2011. type = "SATA";
  2012. break;
  2013. case PCI_DEVICE_ID_ARECA_1380:
  2014. case PCI_DEVICE_ID_ARECA_1381:
  2015. case PCI_DEVICE_ID_ARECA_1680:
  2016. case PCI_DEVICE_ID_ARECA_1681:
  2017. type = "SAS";
  2018. break;
  2019. default:
  2020. type = "X-TYPE";
  2021. break;
  2022. }
  2023. sprintf(buf, "Areca %s Host Adapter RAID Controller%s\n %s",
  2024. type, raid6 ? "( RAID6 capable)" : "",
  2025. ARCMSR_DRIVER_VERSION);
  2026. return buf;
  2027. }
  2028. #ifdef CONFIG_SCSI_ARCMSR_AER
  2029. static pci_ers_result_t arcmsr_pci_slot_reset(struct pci_dev *pdev)
  2030. {
  2031. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2032. struct AdapterControlBlock *acb =
  2033. (struct AdapterControlBlock *) host->hostdata;
  2034. uint32_t intmask_org;
  2035. int i, j;
  2036. if (pci_enable_device(pdev)) {
  2037. return PCI_ERS_RESULT_DISCONNECT;
  2038. }
  2039. pci_set_master(pdev);
  2040. intmask_org = arcmsr_disable_outbound_ints(acb);
  2041. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2042. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  2043. ACB_F_MESSAGE_WQBUFFER_READED);
  2044. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  2045. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  2046. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  2047. acb->devstate[i][j] = ARECA_RAID_GONE;
  2048. arcmsr_wait_firmware_ready(acb);
  2049. arcmsr_iop_confirm(acb);
  2050. /* disable all outbound interrupt */
  2051. arcmsr_get_firmware_spec(acb);
  2052. /*start background rebuild*/
  2053. arcmsr_start_adapter_bgrb(acb);
  2054. /* empty doorbell Qbuffer if door bell ringed */
  2055. arcmsr_clear_doorbell_queue_buffer(acb);
  2056. arcmsr_enable_eoi_mode(acb);
  2057. /* enable outbound Post Queue,outbound doorbell Interrupt */
  2058. arcmsr_enable_outbound_ints(acb, intmask_org);
  2059. acb->acb_flags |= ACB_F_IOP_INITED;
  2060. pci_enable_pcie_error_reporting(pdev);
  2061. return PCI_ERS_RESULT_RECOVERED;
  2062. }
  2063. static void arcmsr_pci_ers_need_reset_forepart(struct pci_dev *pdev)
  2064. {
  2065. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2066. struct AdapterControlBlock *acb = (struct AdapterControlBlock *)host->hostdata;
  2067. struct CommandControlBlock *ccb;
  2068. uint32_t intmask_org;
  2069. int i = 0;
  2070. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  2071. /* talk to iop 331 outstanding command aborted */
  2072. arcmsr_abort_allcmd(acb);
  2073. /* wait for 3 sec for all command aborted*/
  2074. ssleep(3);
  2075. /* disable all outbound interrupt */
  2076. intmask_org = arcmsr_disable_outbound_ints(acb);
  2077. /* clear all outbound posted Q */
  2078. arcmsr_done4abort_postqueue(acb);
  2079. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  2080. ccb = acb->pccb_pool[i];
  2081. if (ccb->startdone == ARCMSR_CCB_START) {
  2082. ccb->startdone = ARCMSR_CCB_ABORTED;
  2083. arcmsr_ccb_complete(ccb, 1);
  2084. }
  2085. }
  2086. /* enable all outbound interrupt */
  2087. arcmsr_enable_outbound_ints(acb, intmask_org);
  2088. }
  2089. pci_disable_device(pdev);
  2090. }
  2091. static void arcmsr_pci_ers_disconnect_forepart(struct pci_dev *pdev)
  2092. {
  2093. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2094. struct AdapterControlBlock *acb = \
  2095. (struct AdapterControlBlock *)host->hostdata;
  2096. arcmsr_stop_adapter_bgrb(acb);
  2097. arcmsr_flush_adapter_cache(acb);
  2098. }
  2099. static pci_ers_result_t arcmsr_pci_error_detected(struct pci_dev *pdev,
  2100. pci_channel_state_t state)
  2101. {
  2102. switch (state) {
  2103. case pci_channel_io_frozen:
  2104. arcmsr_pci_ers_need_reset_forepart(pdev);
  2105. return PCI_ERS_RESULT_NEED_RESET;
  2106. case pci_channel_io_perm_failure:
  2107. arcmsr_pci_ers_disconnect_forepart(pdev);
  2108. return PCI_ERS_RESULT_DISCONNECT;
  2109. break;
  2110. default:
  2111. return PCI_ERS_RESULT_NEED_RESET;
  2112. }
  2113. }
  2114. #endif