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mpc8572ds.dts

mpc8572ds.dts 15 KB
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  1. /*
    2. 

  2.  * MPC8572 DS Device Tree Source
    3. 

  3.  *
    4. 

  4.  * Copyright 2007, 2008 Freescale Semiconductor Inc.
    5. 

  5.  *
    6. 

  6.  * This program is free software; you can redistribute  it and/or modify it
    7. 

  7.  * under  the terms of  the GNU General  Public License as published by the
    8. 

  8.  * Free Software Foundation;  either version 2 of the  License, or (at your
    9. 

  9.  * option) any later version.
    10. 

  10.  */
    11. 

  11. 

  12. /dts-v1/;
    13. 

  13. / {
    14. 

  14. 	model = "fsl,MPC8572DS";
    15. 

  15. 	compatible = "fsl,MPC8572DS";
    16. 

  16. 	#address-cells = <2>;
    17. 

  17. 	#size-cells = <2>;
    18. 

  18. 

  19. 	aliases {
    20. 

  20. 		ethernet0 = &enet0;
    21. 

  21. 		ethernet1 = &enet1;
    22. 

  22. 		ethernet2 = &enet2;
    23. 

  23. 		ethernet3 = &enet3;
    24. 

  24. 		serial0 = &serial0;
    25. 

  25. 		serial1 = &serial1;
    26. 

  26. 		pci0 = &pci0;
    27. 

  27. 		pci1 = &pci1;
    28. 

  28. 		pci2 = &pci2;
    29. 

  29. 	};
    30. 

  30. 

  31. 	cpus {
    32. 

  32. 		#address-cells = <1>;
    33. 

  33. 		#size-cells = <0>;
    34. 

  34. 

  35. 		PowerPC,8572@0 {
    36. 

  36. 			device_type = "cpu";
    37. 

  37. 			reg = <0x0>;
    38. 

  38. 			d-cache-line-size = <32>;	// 32 bytes
    39. 

  39. 			i-cache-line-size = <32>;	// 32 bytes
    40. 

  40. 			d-cache-size = <0x8000>;		// L1, 32K
    41. 

  41. 			i-cache-size = <0x8000>;		// L1, 32K
    42. 

  42. 			timebase-frequency = <0>;
    43. 

  43. 			bus-frequency = <0>;
    44. 

  44. 			clock-frequency = <0>;
    45. 

  45. 			next-level-cache = <&L2>;
    46. 

  46. 		};
    47. 

  47. 

  48. 		PowerPC,8572@1 {
    49. 

  49. 			device_type = "cpu";
    50. 

  50. 			reg = <0x1>;
    51. 

  51. 			d-cache-line-size = <32>;	// 32 bytes
    52. 

  52. 			i-cache-line-size = <32>;	// 32 bytes
    53. 

  53. 			d-cache-size = <0x8000>;		// L1, 32K
    54. 

  54. 			i-cache-size = <0x8000>;		// L1, 32K
    55. 

  55. 			timebase-frequency = <0>;
    56. 

  56. 			bus-frequency = <0>;
    57. 

  57. 			clock-frequency = <0>;
    58. 

  58. 			next-level-cache = <&L2>;
    59. 

  59. 		};
    60. 

  60. 	};
    61. 

  61. 

  62. 	memory {
    63. 

  63. 		device_type = "memory";
    64. 

  64. 	};
    65. 

  65. 

  66. 	soc8572@ffe00000 {
    67. 

  67. 		#address-cells = <1>;
    68. 

  68. 		#size-cells = <1>;
    69. 

  69. 		device_type = "soc";
    70. 

  70. 		compatible = "simple-bus";
    71. 

  71. 		ranges = <0x0 0 0xffe00000 0x100000>;
    72. 

  72. 		reg = <0 0xffe00000 0 0x1000>;	// CCSRBAR & soc regs, remove once parse code for immrbase fixed
    73. 

  73. 		bus-frequency = <0>;		// Filled out by uboot.
    74. 

  74. 

  75. 		memory-controller@2000 {
    76. 

  76. 			compatible = "fsl,mpc8572-memory-controller";
    77. 

  77. 			reg = <0x2000 0x1000>;
    78. 

  78. 			interrupt-parent = <&mpic>;
    79. 

  79. 			interrupts = <18 2>;
    80. 

  80. 		};
    81. 

  81. 

  82. 		memory-controller@6000 {
    83. 

  83. 			compatible = "fsl,mpc8572-memory-controller";
    84. 

  84. 			reg = <0x6000 0x1000>;
    85. 

  85. 			interrupt-parent = <&mpic>;
    86. 

  86. 			interrupts = <18 2>;
    87. 

  87. 		};
    88. 

  88. 

  89. 		L2: l2-cache-controller@20000 {
    90. 

  90. 			compatible = "fsl,mpc8572-l2-cache-controller";
    91. 

  91. 			reg = <0x20000 0x1000>;
    92. 

  92. 			cache-line-size = <32>;	// 32 bytes
    93. 

  93. 			cache-size = <0x80000>;	// L2, 512K
    94. 

  94. 			interrupt-parent = <&mpic>;
    95. 

  95. 			interrupts = <16 2>;
    96. 

  96. 		};
    97. 

  97. 

  98. 		i2c@3000 {
    99. 

  99. 			#address-cells = <1>;
    100. 

  100. 			#size-cells = <0>;
    101. 

  101. 			cell-index = <0>;
    102. 

  102. 			compatible = "fsl-i2c";
    103. 

  103. 			reg = <0x3000 0x100>;
    104. 

  104. 			interrupts = <43 2>;
    105. 

  105. 			interrupt-parent = <&mpic>;
    106. 

  106. 			dfsrr;
    107. 

  107. 		};
    108. 

  108. 

  109. 		i2c@3100 {
    110. 

  110. 			#address-cells = <1>;
    111. 

  111. 			#size-cells = <0>;
    112. 

  112. 			cell-index = <1>;
    113. 

  113. 			compatible = "fsl-i2c";
    114. 

  114. 			reg = <0x3100 0x100>;
    115. 

  115. 			interrupts = <43 2>;
    116. 

  116. 			interrupt-parent = <&mpic>;
    117. 

  117. 			dfsrr;
    118. 

  118. 		};
    119. 

  119. 

  120. 		dma@c300 {
    121. 

  121. 			#address-cells = <1>;
    122. 

  122. 			#size-cells = <1>;
    123. 

  123. 			compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
    124. 

  124. 			reg = <0xc300 0x4>;
    125. 

  125. 			ranges = <0x0 0xc100 0x200>;
    126. 

  126. 			cell-index = <1>;
    127. 

  127. 			dma-channel@0 {
    128. 

  128. 				compatible = "fsl,mpc8572-dma-channel",
    129. 

  129. 						"fsl,eloplus-dma-channel";
    130. 

  130. 				reg = <0x0 0x80>;
    131. 

  131. 				cell-index = <0>;
    132. 

  132. 				interrupt-parent = <&mpic>;
    133. 

  133. 				interrupts = <76 2>;
    134. 

  134. 			};
    135. 

  135. 			dma-channel@80 {
    136. 

  136. 				compatible = "fsl,mpc8572-dma-channel",
    137. 

  137. 						"fsl,eloplus-dma-channel";
    138. 

  138. 				reg = <0x80 0x80>;
    139. 

  139. 				cell-index = <1>;
    140. 

  140. 				interrupt-parent = <&mpic>;
    141. 

  141. 				interrupts = <77 2>;
    142. 

  142. 			};
    143. 

  143. 			dma-channel@100 {
    144. 

  144. 				compatible = "fsl,mpc8572-dma-channel",
    145. 

  145. 						"fsl,eloplus-dma-channel";
    146. 

  146. 				reg = <0x100 0x80>;
    147. 

  147. 				cell-index = <2>;
    148. 

  148. 				interrupt-parent = <&mpic>;
    149. 

  149. 				interrupts = <78 2>;
    150. 

  150. 			};
    151. 

  151. 			dma-channel@180 {
    152. 

  152. 				compatible = "fsl,mpc8572-dma-channel",
    153. 

  153. 						"fsl,eloplus-dma-channel";
    154. 

  154. 				reg = <0x180 0x80>;
    155. 

  155. 				cell-index = <3>;
    156. 

  156. 				interrupt-parent = <&mpic>;
    157. 

  157. 				interrupts = <79 2>;
    158. 

  158. 			};
    159. 

  159. 		};
    160. 

  160. 

  161. 		dma@21300 {
    162. 

  162. 			#address-cells = <1>;
    163. 

  163. 			#size-cells = <1>;
    164. 

  164. 			compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
    165. 

  165. 			reg = <0x21300 0x4>;
    166. 

  166. 			ranges = <0x0 0x21100 0x200>;
    167. 

  167. 			cell-index = <0>;
    168. 

  168. 			dma-channel@0 {
    169. 

  169. 				compatible = "fsl,mpc8572-dma-channel",
    170. 

  170. 						"fsl,eloplus-dma-channel";
    171. 

  171. 				reg = <0x0 0x80>;
    172. 

  172. 				cell-index = <0>;
    173. 

  173. 				interrupt-parent = <&mpic>;
    174. 

  174. 				interrupts = <20 2>;
    175. 

  175. 			};
    176. 

  176. 			dma-channel@80 {
    177. 

  177. 				compatible = "fsl,mpc8572-dma-channel",
    178. 

  178. 						"fsl,eloplus-dma-channel";
    179. 

  179. 				reg = <0x80 0x80>;
    180. 

  180. 				cell-index = <1>;
    181. 

  181. 				interrupt-parent = <&mpic>;
    182. 

  182. 				interrupts = <21 2>;
    183. 

  183. 			};
    184. 

  184. 			dma-channel@100 {
    185. 

  185. 				compatible = "fsl,mpc8572-dma-channel",
    186. 

  186. 						"fsl,eloplus-dma-channel";
    187. 

  187. 				reg = <0x100 0x80>;
    188. 

  188. 				cell-index = <2>;
    189. 

  189. 				interrupt-parent = <&mpic>;
    190. 

  190. 				interrupts = <22 2>;
    191. 

  191. 			};
    192. 

  192. 			dma-channel@180 {
    193. 

  193. 				compatible = "fsl,mpc8572-dma-channel",
    194. 

  194. 						"fsl,eloplus-dma-channel";
    195. 

  195. 				reg = <0x180 0x80>;
    196. 

  196. 				cell-index = <3>;
    197. 

  197. 				interrupt-parent = <&mpic>;
    198. 

  198. 				interrupts = <23 2>;
    199. 

  199. 			};
    200. 

  200. 		};
    201. 

  201. 

  202. 		mdio@24520 {
    203. 

  203. 			#address-cells = <1>;
    204. 

  204. 			#size-cells = <0>;
    205. 

  205. 			compatible = "fsl,gianfar-mdio";
    206. 

  206. 			reg = <0x24520 0x20>;
    207. 

  207. 

  208. 			phy0: ethernet-phy@0 {
    209. 

  209. 				interrupt-parent = <&mpic>;
    210. 

  210. 				interrupts = <10 1>;
    211. 

  211. 				reg = <0x0>;
    212. 

  212. 			};
    213. 

  213. 			phy1: ethernet-phy@1 {
    214. 

  214. 				interrupt-parent = <&mpic>;
    215. 

  215. 				interrupts = <10 1>;
    216. 

  216. 				reg = <0x1>;
    217. 

  217. 			};
    218. 

  218. 			phy2: ethernet-phy@2 {
    219. 

  219. 				interrupt-parent = <&mpic>;
    220. 

  220. 				interrupts = <10 1>;
    221. 

  221. 				reg = <0x2>;
    222. 

  222. 			};
    223. 

  223. 			phy3: ethernet-phy@3 {
    224. 

  224. 				interrupt-parent = <&mpic>;
    225. 

  225. 				interrupts = <10 1>;
    226. 

  226. 				reg = <0x3>;
    227. 

  227. 			};
    228. 

  228. 		};
    229. 

  229. 

  230. 		enet0: ethernet@24000 {
    231. 

  231. 			cell-index = <0>;
    232. 

  232. 			device_type = "network";
    233. 

  233. 			model = "eTSEC";
    234. 

  234. 			compatible = "gianfar";
    235. 

  235. 			reg = <0x24000 0x1000>;
    236. 

  236. 			local-mac-address = [ 00 00 00 00 00 00 ];
    237. 

  237. 			interrupts = <29 2 30 2 34 2>;
    238. 

  238. 			interrupt-parent = <&mpic>;
    239. 

  239. 			phy-handle = <&phy0>;
    240. 

  240. 			phy-connection-type = "rgmii-id";
    241. 

  241. 		};
    242. 

  242. 

  243. 		enet1: ethernet@25000 {
    244. 

  244. 			cell-index = <1>;
    245. 

  245. 			device_type = "network";
    246. 

  246. 			model = "eTSEC";
    247. 

  247. 			compatible = "gianfar";
    248. 

  248. 			reg = <0x25000 0x1000>;
    249. 

  249. 			local-mac-address = [ 00 00 00 00 00 00 ];
    250. 

  250. 			interrupts = <35 2 36 2 40 2>;
    251. 

  251. 			interrupt-parent = <&mpic>;
    252. 

  252. 			phy-handle = <&phy1>;
    253. 

  253. 			phy-connection-type = "rgmii-id";
    254. 

  254. 		};
    255. 

  255. 

  256. 		enet2: ethernet@26000 {
    257. 

  257. 			cell-index = <2>;
    258. 

  258. 			device_type = "network";
    259. 

  259. 			model = "eTSEC";
    260. 

  260. 			compatible = "gianfar";
    261. 

  261. 			reg = <0x26000 0x1000>;
    262. 

  262. 			local-mac-address = [ 00 00 00 00 00 00 ];
    263. 

  263. 			interrupts = <31 2 32 2 33 2>;
    264. 

  264. 			interrupt-parent = <&mpic>;
    265. 

  265. 			phy-handle = <&phy2>;
    266. 

  266. 			phy-connection-type = "rgmii-id";
    267. 

  267. 		};
    268. 

  268. 

  269. 		enet3: ethernet@27000 {
    270. 

  270. 			cell-index = <3>;
    271. 

  271. 			device_type = "network";
    272. 

  272. 			model = "eTSEC";
    273. 

  273. 			compatible = "gianfar";
    274. 

  274. 			reg = <0x27000 0x1000>;
    275. 

  275. 			local-mac-address = [ 00 00 00 00 00 00 ];
    276. 

  276. 			interrupts = <37 2 38 2 39 2>;
    277. 

  277. 			interrupt-parent = <&mpic>;
    278. 

  278. 			phy-handle = <&phy3>;
    279. 

  279. 			phy-connection-type = "rgmii-id";
    280. 

  280. 		};
    281. 

  281. 

  282. 		serial0: serial@4500 {
    283. 

  283. 			cell-index = <0>;
    284. 

  284. 			device_type = "serial";
    285. 

  285. 			compatible = "ns16550";
    286. 

  286. 			reg = <0x4500 0x100>;
    287. 

  287. 			clock-frequency = <0>;
    288. 

  288. 			interrupts = <42 2>;
    289. 

  289. 			interrupt-parent = <&mpic>;
    290. 

  290. 		};
    291. 

  291. 

  292. 		serial1: serial@4600 {
    293. 

  293. 			cell-index = <1>;
    294. 

  294. 			device_type = "serial";
    295. 

  295. 			compatible = "ns16550";
    296. 

  296. 			reg = <0x4600 0x100>;
    297. 

  297. 			clock-frequency = <0>;
    298. 

  298. 			interrupts = <42 2>;
    299. 

  299. 			interrupt-parent = <&mpic>;
    300. 

  300. 		};
    301. 

  301. 

  302. 		global-utilities@e0000 {	//global utilities block
    303. 

  303. 			compatible = "fsl,mpc8572-guts";
    304. 

  304. 			reg = <0xe0000 0x1000>;
    305. 

  305. 			fsl,has-rstcr;
    306. 

  306. 		};
    307. 

  307. 

  308. 		msi@41600 {
    309. 

  309. 			compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
    310. 

  310. 			reg = <0x41600 0x80>;
    311. 

  311. 			msi-available-ranges = <0 0x100>;
    312. 

  312. 			interrupts = <
    313. 

  313. 				0xe0 0
    314. 

  314. 				0xe1 0
    315. 

  315. 				0xe2 0
    316. 

  316. 				0xe3 0
    317. 

  317. 				0xe4 0
    318. 

  318. 				0xe5 0
    319. 

  319. 				0xe6 0
    320. 

  320. 				0xe7 0>;
    321. 

  321. 			interrupt-parent = <&mpic>;
    322. 

  322. 		};
    323. 

  323. 

  324. 		crypto@30000 {
    325. 

  325. 			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
    326. 

  326. 				     "fsl,sec2.1", "fsl,sec2.0";
    327. 

  327. 			reg = <0x30000 0x10000>;
    328. 

  328. 			interrupts = <45 2 58 2>;
    329. 

  329. 			interrupt-parent = <&mpic>;
    330. 

  330. 			fsl,num-channels = <4>;
    331. 

  331. 			fsl,channel-fifo-len = <24>;
    332. 

  332. 			fsl,exec-units-mask = <0x9fe>;
    333. 

  333. 			fsl,descriptor-types-mask = <0x3ab0ebf>;
    334. 

  334. 		};
    335. 

  335. 

  336. 		mpic: pic@40000 {
    337. 

  337. 			interrupt-controller;
    338. 

  338. 			#address-cells = <0>;
    339. 

  339. 			#interrupt-cells = <2>;
    340. 

  340. 			reg = <0x40000 0x40000>;
    341. 

  341. 			compatible = "chrp,open-pic";
    342. 

  342. 			device_type = "open-pic";
    343. 

  343. 		};
    344. 

  344. 	};
    345. 

  345. 

  346. 	pci0: pcie@ffe08000 {
    347. 

  347. 		cell-index = <0>;
    348. 

  348. 		compatible = "fsl,mpc8548-pcie";
    349. 

  349. 		device_type = "pci";
    350. 

  350. 		#interrupt-cells = <1>;
    351. 

  351. 		#size-cells = <2>;
    352. 

  352. 		#address-cells = <3>;
    353. 

  353. 		reg = <0 0xffe08000 0 0x1000>;
    354. 

  354. 		bus-range = <0 255>;
    355. 

  355. 		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
    356. 

  356. 			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
    357. 

  357. 		clock-frequency = <33333333>;
    358. 

  358. 		interrupt-parent = <&mpic>;
    359. 

  359. 		interrupts = <24 2>;
    360. 

  360. 		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
    361. 

  361. 		interrupt-map = <
    362. 

  362. 			/* IDSEL 0x11 func 0 - PCI slot 1 */
    363. 

  363. 			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
    364. 

  364. 			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
    365. 

  365. 			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
    366. 

  366. 			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
    367. 

  367. 

  368. 			/* IDSEL 0x11 func 1 - PCI slot 1 */
    369. 

  369. 			0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
    370. 

  370. 			0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
    371. 

  371. 			0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
    372. 

  372. 			0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
    373. 

  373. 

  374. 			/* IDSEL 0x11 func 2 - PCI slot 1 */
    375. 

  375. 			0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
    376. 

  376. 			0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
    377. 

  377. 			0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
    378. 

  378. 			0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
    379. 

  379. 

  380. 			/* IDSEL 0x11 func 3 - PCI slot 1 */
    381. 

  381. 			0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
    382. 

  382. 			0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
    383. 

  383. 			0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
    384. 

  384. 			0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
    385. 

  385. 

  386. 			/* IDSEL 0x11 func 4 - PCI slot 1 */
    387. 

  387. 			0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
    388. 

  388. 			0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
    389. 

  389. 			0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
    390. 

  390. 			0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
    391. 

  391. 

  392. 			/* IDSEL 0x11 func 5 - PCI slot 1 */
    393. 

  393. 			0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
    394. 

  394. 			0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
    395. 

  395. 			0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
    396. 

  396. 			0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
    397. 

  397. 

  398. 			/* IDSEL 0x11 func 6 - PCI slot 1 */
    399. 

  399. 			0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
    400. 

  400. 			0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
    401. 

  401. 			0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
    402. 

  402. 			0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
    403. 

  403. 

  404. 			/* IDSEL 0x11 func 7 - PCI slot 1 */
    405. 

  405. 			0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
    406. 

  406. 			0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
    407. 

  407. 			0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
    408. 

  408. 			0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
    409. 

  409. 

  410. 			/* IDSEL 0x12 func 0 - PCI slot 2 */
    411. 

  411. 			0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
    412. 

  412. 			0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
    413. 

  413. 			0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
    414. 

  414. 			0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
    415. 

  415. 

  416. 			/* IDSEL 0x12 func 1 - PCI slot 2 */
    417. 

  417. 			0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
    418. 

  418. 			0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
    419. 

  419. 			0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
    420. 

  420. 			0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
    421. 

  421. 

  422. 			/* IDSEL 0x12 func 2 - PCI slot 2 */
    423. 

  423. 			0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
    424. 

  424. 			0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
    425. 

  425. 			0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
    426. 

  426. 			0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
    427. 

  427. 

  428. 			/* IDSEL 0x12 func 3 - PCI slot 2 */
    429. 

  429. 			0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
    430. 

  430. 			0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
    431. 

  431. 			0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
    432. 

  432. 			0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
    433. 

  433. 

  434. 			/* IDSEL 0x12 func 4 - PCI slot 2 */
    435. 

  435. 			0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
    436. 

  436. 			0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
    437. 

  437. 			0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
    438. 

  438. 			0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
    439. 

  439. 

  440. 			/* IDSEL 0x12 func 5 - PCI slot 2 */
    441. 

  441. 			0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
    442. 

  442. 			0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
    443. 

  443. 			0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
    444. 

  444. 			0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
    445. 

  445. 

  446. 			/* IDSEL 0x12 func 6 - PCI slot 2 */
    447. 

  447. 			0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
    448. 

  448. 			0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
    449. 

  449. 			0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
    450. 

  450. 			0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
    451. 

  451. 

  452. 			/* IDSEL 0x12 func 7 - PCI slot 2 */
    453. 

  453. 			0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
    454. 

  454. 			0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
    455. 

  455. 			0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
    456. 

  456. 			0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
    457. 

  457. 

  458. 			// IDSEL 0x1c  USB
    459. 

  459. 			0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
    460. 

  460. 			0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
    461. 

  461. 			0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
    462. 

  462. 			0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
    463. 

  463. 

  464. 			// IDSEL 0x1d  Audio
    465. 

  465. 			0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
    466. 

  466. 

  467. 			// IDSEL 0x1e Legacy
    468. 

  468. 			0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
    469. 

  469. 			0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
    470. 

  470. 

  471. 			// IDSEL 0x1f IDE/SATA
    472. 

  472. 			0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
    473. 

  473. 			0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
    474. 

  474. 

  475. 			>;
    476. 

  476. 

  477. 		pcie@0 {
    478. 

  478. 			reg = <0x0 0x0 0x0 0x0 0x0>;
    479. 

  479. 			#size-cells = <2>;
    480. 

  480. 			#address-cells = <3>;
    481. 

  481. 			device_type = "pci";
    482. 

  482. 			ranges = <0x2000000 0x0 0x80000000
    483. 

  483. 				  0x2000000 0x0 0x80000000
    484. 

  484. 				  0x0 0x20000000
    485. 

  485. 

  486. 				  0x1000000 0x0 0x0
    487. 

  487. 				  0x1000000 0x0 0x0
    488. 

  488. 				  0x0 0x100000>;
    489. 

  489. 			uli1575@0 {
    490. 

  490. 				reg = <0x0 0x0 0x0 0x0 0x0>;
    491. 

  491. 				#size-cells = <2>;
    492. 

  492. 				#address-cells = <3>;
    493. 

  493. 				ranges = <0x2000000 0x0 0x80000000
    494. 

  494. 					  0x2000000 0x0 0x80000000
    495. 

  495. 					  0x0 0x20000000
    496. 

  496. 

  497. 					  0x1000000 0x0 0x0
    498. 

  498. 					  0x1000000 0x0 0x0
    499. 

  499. 					  0x0 0x100000>;
    500. 

  500. 				isa@1e {
    501. 

  501. 					device_type = "isa";
    502. 

  502. 					#interrupt-cells = <2>;
    503. 

  503. 					#size-cells = <1>;
    504. 

  504. 					#address-cells = <2>;
    505. 

  505. 					reg = <0xf000 0x0 0x0 0x0 0x0>;
    506. 

  506. 					ranges = <0x1 0x0 0x1000000 0x0 0x0
    507. 

  507. 						  0x1000>;
    508. 

  508. 					interrupt-parent = <&i8259>;
    509. 

  509. 

  510. 					i8259: interrupt-controller@20 {
    511. 

  511. 						reg = <0x1 0x20 0x2
    512. 

  512. 						       0x1 0xa0 0x2
    513. 

  513. 						       0x1 0x4d0 0x2>;
    514. 

  514. 						interrupt-controller;
    515. 

  515. 						device_type = "interrupt-controller";
    516. 

  516. 						#address-cells = <0>;
    517. 

  517. 						#interrupt-cells = <2>;
    518. 

  518. 						compatible = "chrp,iic";
    519. 

  519. 						interrupts = <9 2>;
    520. 

  520. 						interrupt-parent = <&mpic>;
    521. 

  521. 					};
    522. 

  522. 

  523. 					i8042@60 {
    524. 

  524. 						#size-cells = <0>;
    525. 

  525. 						#address-cells = <1>;
    526. 

  526. 						reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
    527. 

  527. 						interrupts = <1 3 12 3>;
    528. 

  528. 						interrupt-parent =
    529. 

  529. 							<&i8259>;
    530. 

  530. 

  531. 						keyboard@0 {
    532. 

  532. 							reg = <0x0>;
    533. 

  533. 							compatible = "pnpPNP,303";
    534. 

  534. 						};
    535. 

  535. 

  536. 						mouse@1 {
    537. 

  537. 							reg = <0x1>;
    538. 

  538. 							compatible = "pnpPNP,f03";
    539. 

  539. 						};
    540. 

  540. 					};
    541. 

  541. 

  542. 					rtc@70 {
    543. 

  543. 						compatible = "pnpPNP,b00";
    544. 

  544. 						reg = <0x1 0x70 0x2>;
    545. 

  545. 					};
    546. 

  546. 

  547. 					gpio@400 {
    548. 

  548. 						reg = <0x1 0x400 0x80>;
    549. 

  549. 					};
    550. 

  550. 				};
    551. 

  551. 			};
    552. 

  552. 		};
    553. 

  553. 

  554. 	};
    555. 

  555. 

  556. 	pci1: pcie@ffe09000 {
    557. 

  557. 		cell-index = <1>;
    558. 

  558. 		compatible = "fsl,mpc8548-pcie";
    559. 

  559. 		device_type = "pci";
    560. 

  560. 		#interrupt-cells = <1>;
    561. 

  561. 		#size-cells = <2>;
    562. 

  562. 		#address-cells = <3>;
    563. 

  563. 		reg = <0 0xffe09000 0 0x1000>;
    564. 

  564. 		bus-range = <0 255>;
    565. 

  565. 		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
    566. 

  566. 			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
    567. 

  567. 		clock-frequency = <33333333>;
    568. 

  568. 		interrupt-parent = <&mpic>;
    569. 

  569. 		interrupts = <26 2>;
    570. 

  570. 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
    571. 

  571. 		interrupt-map = <
    572. 

  572. 			/* IDSEL 0x0 */
    573. 

  573. 			0000 0x0 0x0 0x1 &mpic 0x4 0x1
    574. 

  574. 			0000 0x0 0x0 0x2 &mpic 0x5 0x1
    575. 

  575. 			0000 0x0 0x0 0x3 &mpic 0x6 0x1
    576. 

  576. 			0000 0x0 0x0 0x4 &mpic 0x7 0x1
    577. 

  577. 			>;
    578. 

  578. 		pcie@0 {
    579. 

  579. 			reg = <0x0 0x0 0x0 0x0 0x0>;
    580. 

  580. 			#size-cells = <2>;
    581. 

  581. 			#address-cells = <3>;
    582. 

  582. 			device_type = "pci";
    583. 

  583. 			ranges = <0x2000000 0x0 0xa0000000
    584. 

  584. 				  0x2000000 0x0 0xa0000000
    585. 

  585. 				  0x0 0x20000000
    586. 

  586. 

  587. 				  0x1000000 0x0 0x0
    588. 

  588. 				  0x1000000 0x0 0x0
    589. 

  589. 				  0x0 0x100000>;
    590. 

  590. 		};
    591. 

  591. 	};
    592. 

  592. 

  593. 	pci2: pcie@ffe0a000 {
    594. 

  594. 		cell-index = <2>;
    595. 

  595. 		compatible = "fsl,mpc8548-pcie";
    596. 

  596. 		device_type = "pci";
    597. 

  597. 		#interrupt-cells = <1>;
    598. 

  598. 		#size-cells = <2>;
    599. 

  599. 		#address-cells = <3>;
    600. 

  600. 		reg = <0 0xffe0a000 0 0x1000>;
    601. 

  601. 		bus-range = <0 255>;
    602. 

  602. 		ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
    603. 

  603. 			  0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
    604. 

  604. 		clock-frequency = <33333333>;
    605. 

  605. 		interrupt-parent = <&mpic>;
    606. 

  606. 		interrupts = <27 2>;
    607. 

  607. 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
    608. 

  608. 		interrupt-map = <
    609. 

  609. 			/* IDSEL 0x0 */
    610. 

  610. 			0000 0x0 0x0 0x1 &mpic 0x0 0x1
    611. 

  611. 			0000 0x0 0x0 0x2 &mpic 0x1 0x1
    612. 

  612. 			0000 0x0 0x0 0x3 &mpic 0x2 0x1
    613. 

  613. 			0000 0x0 0x0 0x4 &mpic 0x3 0x1
    614. 

  614. 			>;
    615. 

  615. 		pcie@0 {
    616. 

  616. 			reg = <0x0 0x0 0x0 0x0 0x0>;
    617. 

  617. 			#size-cells = <2>;
    618. 

  618. 			#address-cells = <3>;
    619. 

  619. 			device_type = "pci";
    620. 

  620. 			ranges = <0x2000000 0x0 0xc0000000
    621. 

  621. 				  0x2000000 0x0 0xc0000000
    622. 

  622. 				  0x0 0x20000000
    623. 

  623. 

  624. 				  0x1000000 0x0 0x0
    625. 

  625. 				  0x1000000 0x0 0x0
    626. 

  626. 				  0x0 0x100000>;
    627. 

  627. 		};
    628. 

  628. 	};
    629. 

  629. };
    630.