stx_gp3_8560.dts 5.0 KB

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  1. /*
  2. * STX GP3 - 8560 ADS Device Tree Source
  3. *
  4. * Copyright 2008 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "stx,gp3";
  14. compatible = "stx,gp3-8560", "stx,gp3";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8560@0 {
  27. device_type = "cpu";
  28. reg = <0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>;
  34. bus-frequency = <0>;
  35. clock-frequency = <0>;
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x10000000>;
  41. };
  42. soc@fdf00000 {
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. device_type = "soc";
  46. ranges = <0 0xfdf00000 0x100000>;
  47. reg = <0xfdf00000 0x1000>;
  48. bus-frequency = <0>;
  49. compatible = "fsl,mpc8560-immr", "simple-bus";
  50. memory-controller@2000 {
  51. compatible = "fsl,8540-memory-controller";
  52. reg = <0x2000 0x1000>;
  53. interrupt-parent = <&mpic>;
  54. interrupts = <18 2>;
  55. };
  56. l2-cache-controller@20000 {
  57. compatible = "fsl,8540-l2-cache-controller";
  58. reg = <0x20000 0x1000>;
  59. cache-line-size = <32>;
  60. cache-size = <0x40000>; // L2, 256K
  61. interrupt-parent = <&mpic>;
  62. interrupts = <16 2>;
  63. };
  64. i2c@3000 {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. cell-index = <0>;
  68. compatible = "fsl-i2c";
  69. reg = <0x3000 0x100>;
  70. interrupts = <43 2>;
  71. interrupt-parent = <&mpic>;
  72. dfsrr;
  73. };
  74. mdio@24520 {
  75. #address-cells = <1>;
  76. #size-cells = <0>;
  77. compatible = "fsl,gianfar-mdio";
  78. reg = <0x24520 0x20>;
  79. phy2: ethernet-phy@2 {
  80. interrupt-parent = <&mpic>;
  81. interrupts = <5 4>;
  82. reg = <2>;
  83. device_type = "ethernet-phy";
  84. };
  85. phy4: ethernet-phy@4 {
  86. interrupt-parent = <&mpic>;
  87. interrupts = <5 4>;
  88. reg = <4>;
  89. device_type = "ethernet-phy";
  90. };
  91. };
  92. enet0: ethernet@24000 {
  93. cell-index = <0>;
  94. device_type = "network";
  95. model = "TSEC";
  96. compatible = "gianfar";
  97. reg = <0x24000 0x1000>;
  98. local-mac-address = [ 00 00 00 00 00 00 ];
  99. interrupts = <29 2 30 2 34 2>;
  100. interrupt-parent = <&mpic>;
  101. phy-handle = <&phy2>;
  102. };
  103. enet1: ethernet@25000 {
  104. cell-index = <1>;
  105. device_type = "network";
  106. model = "TSEC";
  107. compatible = "gianfar";
  108. reg = <0x25000 0x1000>;
  109. local-mac-address = [ 00 00 00 00 00 00 ];
  110. interrupts = <35 2 36 2 40 2>;
  111. interrupt-parent = <&mpic>;
  112. phy-handle = <&phy4>;
  113. };
  114. mpic: pic@40000 {
  115. interrupt-controller;
  116. #address-cells = <0>;
  117. #interrupt-cells = <2>;
  118. reg = <0x40000 0x40000>;
  119. compatible = "chrp,open-pic";
  120. device_type = "open-pic";
  121. };
  122. cpm@919c0 {
  123. #address-cells = <1>;
  124. #size-cells = <1>;
  125. compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
  126. reg = <0x919c0 0x30>;
  127. ranges;
  128. muram@80000 {
  129. #address-cells = <1>;
  130. #size-cells = <1>;
  131. ranges = <0 0x80000 0x10000>;
  132. data@0 {
  133. compatible = "fsl,cpm-muram-data";
  134. reg = <0 0x4000 0x9000 0x2000>;
  135. };
  136. };
  137. brg@919f0 {
  138. compatible = "fsl,mpc8560-brg",
  139. "fsl,cpm2-brg",
  140. "fsl,cpm-brg";
  141. reg = <0x919f0 0x10 0x915f0 0x10>;
  142. clock-frequency = <0>;
  143. };
  144. cpmpic: pic@90c00 {
  145. interrupt-controller;
  146. #address-cells = <0>;
  147. #interrupt-cells = <2>;
  148. interrupts = <46 2>;
  149. interrupt-parent = <&mpic>;
  150. reg = <0x90c00 0x80>;
  151. compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
  152. };
  153. serial0: serial@91a20 {
  154. device_type = "serial";
  155. compatible = "fsl,mpc8560-scc-uart",
  156. "fsl,cpm2-scc-uart";
  157. reg = <0x91a20 0x20 0x88100 0x100>;
  158. fsl,cpm-brg = <2>;
  159. fsl,cpm-command = <0x4a00000>;
  160. interrupts = <41 8>;
  161. interrupt-parent = <&cpmpic>;
  162. };
  163. };
  164. };
  165. pci0: pci@fdf08000 {
  166. cell-index = <0>;
  167. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  168. interrupt-map = <
  169. /* IDSEL 0x0c */
  170. 0x6000 0 0 1 &mpic 1 1
  171. 0x6000 0 0 2 &mpic 2 1
  172. 0x6000 0 0 3 &mpic 3 1
  173. 0x6000 0 0 4 &mpic 4 1
  174. /* IDSEL 0x0d */
  175. 0x6800 0 0 1 &mpic 4 1
  176. 0x6800 0 0 2 &mpic 1 1
  177. 0x6800 0 0 3 &mpic 2 1
  178. 0x6800 0 0 4 &mpic 3 1
  179. /* IDSEL 0x0e */
  180. 0x7000 0 0 1 &mpic 3 1
  181. 0x7000 0 0 2 &mpic 4 1
  182. 0x7000 0 0 3 &mpic 1 1
  183. 0x7000 0 0 4 &mpic 2 1
  184. /* IDSEL 0x0f */
  185. 0x7800 0 0 1 &mpic 2 1
  186. 0x7800 0 0 2 &mpic 3 1
  187. 0x7800 0 0 3 &mpic 4 1
  188. 0x7800 0 0 4 &mpic 1 1>;
  189. interrupt-parent = <&mpic>;
  190. interrupts = <24 2>;
  191. bus-range = <0 0>;
  192. ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
  193. 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
  194. clock-frequency = <66666666>;
  195. #interrupt-cells = <1>;
  196. #size-cells = <2>;
  197. #address-cells = <3>;
  198. reg = <0xfdf08000 0x1000>;
  199. compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
  200. device_type = "pci";
  201. };
  202. };