mpc8641_hpcn.dts 11 KB

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  1. /*
  2. * MPC8641 HPCN Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8641HPCN";
  14. compatible = "fsl,mpc8641hpcn";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. ethernet2 = &enet2;
  21. ethernet3 = &enet3;
  22. serial0 = &serial0;
  23. serial1 = &serial1;
  24. pci0 = &pci0;
  25. pci1 = &pci1;
  26. rapidio0 = &rapidio0;
  27. };
  28. cpus {
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. PowerPC,8641@0 {
  32. device_type = "cpu";
  33. reg = <0>;
  34. d-cache-line-size = <32>;
  35. i-cache-line-size = <32>;
  36. d-cache-size = <32768>; // L1
  37. i-cache-size = <32768>; // L1
  38. timebase-frequency = <0>; // From uboot
  39. bus-frequency = <0>; // From uboot
  40. clock-frequency = <0>; // From uboot
  41. };
  42. PowerPC,8641@1 {
  43. device_type = "cpu";
  44. reg = <1>;
  45. d-cache-line-size = <32>;
  46. i-cache-line-size = <32>;
  47. d-cache-size = <32768>;
  48. i-cache-size = <32768>;
  49. timebase-frequency = <0>; // From uboot
  50. bus-frequency = <0>; // From uboot
  51. clock-frequency = <0>; // From uboot
  52. };
  53. };
  54. memory {
  55. device_type = "memory";
  56. reg = <0x00000000 0x40000000>; // 1G at 0x0
  57. };
  58. localbus@f8005000 {
  59. #address-cells = <2>;
  60. #size-cells = <1>;
  61. compatible = "fsl,mpc8641-localbus", "simple-bus";
  62. reg = <0xf8005000 0x1000>;
  63. interrupts = <19 2>;
  64. interrupt-parent = <&mpic>;
  65. ranges = <0 0 0xff800000 0x00800000
  66. 1 0 0xfe000000 0x01000000
  67. 2 0 0xf8200000 0x00100000
  68. 3 0 0xf8100000 0x00100000>;
  69. flash@0,0 {
  70. compatible = "cfi-flash";
  71. reg = <0 0 0x00800000>;
  72. bank-width = <2>;
  73. device-width = <2>;
  74. #address-cells = <1>;
  75. #size-cells = <1>;
  76. partition@0 {
  77. label = "kernel";
  78. reg = <0x00000000 0x00300000>;
  79. };
  80. partition@300000 {
  81. label = "firmware b";
  82. reg = <0x00300000 0x00100000>;
  83. read-only;
  84. };
  85. partition@400000 {
  86. label = "fs";
  87. reg = <0x00400000 0x00300000>;
  88. };
  89. partition@700000 {
  90. label = "firmware a";
  91. reg = <0x00700000 0x00100000>;
  92. read-only;
  93. };
  94. };
  95. };
  96. soc8641@f8000000 {
  97. #address-cells = <1>;
  98. #size-cells = <1>;
  99. device_type = "soc";
  100. compatible = "simple-bus";
  101. ranges = <0x00000000 0xf8000000 0x00100000>;
  102. reg = <0xf8000000 0x00001000>; // CCSRBAR
  103. bus-frequency = <0>;
  104. i2c@3000 {
  105. #address-cells = <1>;
  106. #size-cells = <0>;
  107. cell-index = <0>;
  108. compatible = "fsl-i2c";
  109. reg = <0x3000 0x100>;
  110. interrupts = <43 2>;
  111. interrupt-parent = <&mpic>;
  112. dfsrr;
  113. };
  114. i2c@3100 {
  115. #address-cells = <1>;
  116. #size-cells = <0>;
  117. cell-index = <1>;
  118. compatible = "fsl-i2c";
  119. reg = <0x3100 0x100>;
  120. interrupts = <43 2>;
  121. interrupt-parent = <&mpic>;
  122. dfsrr;
  123. };
  124. mdio@24520 {
  125. #address-cells = <1>;
  126. #size-cells = <0>;
  127. compatible = "fsl,gianfar-mdio";
  128. reg = <0x24520 0x20>;
  129. phy0: ethernet-phy@0 {
  130. interrupt-parent = <&mpic>;
  131. interrupts = <10 1>;
  132. reg = <0>;
  133. device_type = "ethernet-phy";
  134. };
  135. phy1: ethernet-phy@1 {
  136. interrupt-parent = <&mpic>;
  137. interrupts = <10 1>;
  138. reg = <1>;
  139. device_type = "ethernet-phy";
  140. };
  141. phy2: ethernet-phy@2 {
  142. interrupt-parent = <&mpic>;
  143. interrupts = <10 1>;
  144. reg = <2>;
  145. device_type = "ethernet-phy";
  146. };
  147. phy3: ethernet-phy@3 {
  148. interrupt-parent = <&mpic>;
  149. interrupts = <10 1>;
  150. reg = <3>;
  151. device_type = "ethernet-phy";
  152. };
  153. };
  154. enet0: ethernet@24000 {
  155. cell-index = <0>;
  156. device_type = "network";
  157. model = "TSEC";
  158. compatible = "gianfar";
  159. reg = <0x24000 0x1000>;
  160. local-mac-address = [ 00 00 00 00 00 00 ];
  161. interrupts = <29 2 30 2 34 2>;
  162. interrupt-parent = <&mpic>;
  163. phy-handle = <&phy0>;
  164. phy-connection-type = "rgmii-id";
  165. };
  166. enet1: ethernet@25000 {
  167. cell-index = <1>;
  168. device_type = "network";
  169. model = "TSEC";
  170. compatible = "gianfar";
  171. reg = <0x25000 0x1000>;
  172. local-mac-address = [ 00 00 00 00 00 00 ];
  173. interrupts = <35 2 36 2 40 2>;
  174. interrupt-parent = <&mpic>;
  175. phy-handle = <&phy1>;
  176. phy-connection-type = "rgmii-id";
  177. };
  178. enet2: ethernet@26000 {
  179. cell-index = <2>;
  180. device_type = "network";
  181. model = "TSEC";
  182. compatible = "gianfar";
  183. reg = <0x26000 0x1000>;
  184. local-mac-address = [ 00 00 00 00 00 00 ];
  185. interrupts = <31 2 32 2 33 2>;
  186. interrupt-parent = <&mpic>;
  187. phy-handle = <&phy2>;
  188. phy-connection-type = "rgmii-id";
  189. };
  190. enet3: ethernet@27000 {
  191. cell-index = <3>;
  192. device_type = "network";
  193. model = "TSEC";
  194. compatible = "gianfar";
  195. reg = <0x27000 0x1000>;
  196. local-mac-address = [ 00 00 00 00 00 00 ];
  197. interrupts = <37 2 38 2 39 2>;
  198. interrupt-parent = <&mpic>;
  199. phy-handle = <&phy3>;
  200. phy-connection-type = "rgmii-id";
  201. };
  202. serial0: serial@4500 {
  203. cell-index = <0>;
  204. device_type = "serial";
  205. compatible = "ns16550";
  206. reg = <0x4500 0x100>;
  207. clock-frequency = <0>;
  208. interrupts = <42 2>;
  209. interrupt-parent = <&mpic>;
  210. };
  211. serial1: serial@4600 {
  212. cell-index = <1>;
  213. device_type = "serial";
  214. compatible = "ns16550";
  215. reg = <0x4600 0x100>;
  216. clock-frequency = <0>;
  217. interrupts = <28 2>;
  218. interrupt-parent = <&mpic>;
  219. };
  220. mpic: pic@40000 {
  221. interrupt-controller;
  222. #address-cells = <0>;
  223. #interrupt-cells = <2>;
  224. reg = <0x40000 0x40000>;
  225. compatible = "chrp,open-pic";
  226. device_type = "open-pic";
  227. };
  228. global-utilities@e0000 {
  229. compatible = "fsl,mpc8641-guts";
  230. reg = <0xe0000 0x1000>;
  231. fsl,has-rstcr;
  232. };
  233. };
  234. pci0: pcie@f8008000 {
  235. cell-index = <0>;
  236. compatible = "fsl,mpc8641-pcie";
  237. device_type = "pci";
  238. #interrupt-cells = <1>;
  239. #size-cells = <2>;
  240. #address-cells = <3>;
  241. reg = <0xf8008000 0x1000>;
  242. bus-range = <0x0 0xff>;
  243. ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
  244. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  245. clock-frequency = <33333333>;
  246. interrupt-parent = <&mpic>;
  247. interrupts = <24 2>;
  248. interrupt-map-mask = <0xff00 0 0 7>;
  249. interrupt-map = <
  250. /* IDSEL 0x11 func 0 - PCI slot 1 */
  251. 0x8800 0 0 1 &mpic 2 1
  252. 0x8800 0 0 2 &mpic 3 1
  253. 0x8800 0 0 3 &mpic 4 1
  254. 0x8800 0 0 4 &mpic 1 1
  255. /* IDSEL 0x11 func 1 - PCI slot 1 */
  256. 0x8900 0 0 1 &mpic 2 1
  257. 0x8900 0 0 2 &mpic 3 1
  258. 0x8900 0 0 3 &mpic 4 1
  259. 0x8900 0 0 4 &mpic 1 1
  260. /* IDSEL 0x11 func 2 - PCI slot 1 */
  261. 0x8a00 0 0 1 &mpic 2 1
  262. 0x8a00 0 0 2 &mpic 3 1
  263. 0x8a00 0 0 3 &mpic 4 1
  264. 0x8a00 0 0 4 &mpic 1 1
  265. /* IDSEL 0x11 func 3 - PCI slot 1 */
  266. 0x8b00 0 0 1 &mpic 2 1
  267. 0x8b00 0 0 2 &mpic 3 1
  268. 0x8b00 0 0 3 &mpic 4 1
  269. 0x8b00 0 0 4 &mpic 1 1
  270. /* IDSEL 0x11 func 4 - PCI slot 1 */
  271. 0x8c00 0 0 1 &mpic 2 1
  272. 0x8c00 0 0 2 &mpic 3 1
  273. 0x8c00 0 0 3 &mpic 4 1
  274. 0x8c00 0 0 4 &mpic 1 1
  275. /* IDSEL 0x11 func 5 - PCI slot 1 */
  276. 0x8d00 0 0 1 &mpic 2 1
  277. 0x8d00 0 0 2 &mpic 3 1
  278. 0x8d00 0 0 3 &mpic 4 1
  279. 0x8d00 0 0 4 &mpic 1 1
  280. /* IDSEL 0x11 func 6 - PCI slot 1 */
  281. 0x8e00 0 0 1 &mpic 2 1
  282. 0x8e00 0 0 2 &mpic 3 1
  283. 0x8e00 0 0 3 &mpic 4 1
  284. 0x8e00 0 0 4 &mpic 1 1
  285. /* IDSEL 0x11 func 7 - PCI slot 1 */
  286. 0x8f00 0 0 1 &mpic 2 1
  287. 0x8f00 0 0 2 &mpic 3 1
  288. 0x8f00 0 0 3 &mpic 4 1
  289. 0x8f00 0 0 4 &mpic 1 1
  290. /* IDSEL 0x12 func 0 - PCI slot 2 */
  291. 0x9000 0 0 1 &mpic 3 1
  292. 0x9000 0 0 2 &mpic 4 1
  293. 0x9000 0 0 3 &mpic 1 1
  294. 0x9000 0 0 4 &mpic 2 1
  295. /* IDSEL 0x12 func 1 - PCI slot 2 */
  296. 0x9100 0 0 1 &mpic 3 1
  297. 0x9100 0 0 2 &mpic 4 1
  298. 0x9100 0 0 3 &mpic 1 1
  299. 0x9100 0 0 4 &mpic 2 1
  300. /* IDSEL 0x12 func 2 - PCI slot 2 */
  301. 0x9200 0 0 1 &mpic 3 1
  302. 0x9200 0 0 2 &mpic 4 1
  303. 0x9200 0 0 3 &mpic 1 1
  304. 0x9200 0 0 4 &mpic 2 1
  305. /* IDSEL 0x12 func 3 - PCI slot 2 */
  306. 0x9300 0 0 1 &mpic 3 1
  307. 0x9300 0 0 2 &mpic 4 1
  308. 0x9300 0 0 3 &mpic 1 1
  309. 0x9300 0 0 4 &mpic 2 1
  310. /* IDSEL 0x12 func 4 - PCI slot 2 */
  311. 0x9400 0 0 1 &mpic 3 1
  312. 0x9400 0 0 2 &mpic 4 1
  313. 0x9400 0 0 3 &mpic 1 1
  314. 0x9400 0 0 4 &mpic 2 1
  315. /* IDSEL 0x12 func 5 - PCI slot 2 */
  316. 0x9500 0 0 1 &mpic 3 1
  317. 0x9500 0 0 2 &mpic 4 1
  318. 0x9500 0 0 3 &mpic 1 1
  319. 0x9500 0 0 4 &mpic 2 1
  320. /* IDSEL 0x12 func 6 - PCI slot 2 */
  321. 0x9600 0 0 1 &mpic 3 1
  322. 0x9600 0 0 2 &mpic 4 1
  323. 0x9600 0 0 3 &mpic 1 1
  324. 0x9600 0 0 4 &mpic 2 1
  325. /* IDSEL 0x12 func 7 - PCI slot 2 */
  326. 0x9700 0 0 1 &mpic 3 1
  327. 0x9700 0 0 2 &mpic 4 1
  328. 0x9700 0 0 3 &mpic 1 1
  329. 0x9700 0 0 4 &mpic 2 1
  330. // IDSEL 0x1c USB
  331. 0xe000 0 0 1 &i8259 12 2
  332. 0xe100 0 0 2 &i8259 9 2
  333. 0xe200 0 0 3 &i8259 10 2
  334. 0xe300 0 0 4 &i8259 112
  335. // IDSEL 0x1d Audio
  336. 0xe800 0 0 1 &i8259 6 2
  337. // IDSEL 0x1e Legacy
  338. 0xf000 0 0 1 &i8259 7 2
  339. 0xf100 0 0 1 &i8259 7 2
  340. // IDSEL 0x1f IDE/SATA
  341. 0xf800 0 0 1 &i8259 14 2
  342. 0xf900 0 0 1 &i8259 5 2
  343. >;
  344. pcie@0 {
  345. reg = <0 0 0 0 0>;
  346. #size-cells = <2>;
  347. #address-cells = <3>;
  348. device_type = "pci";
  349. ranges = <0x02000000 0x0 0x80000000
  350. 0x02000000 0x0 0x80000000
  351. 0x0 0x20000000
  352. 0x01000000 0x0 0x00000000
  353. 0x01000000 0x0 0x00000000
  354. 0x0 0x00100000>;
  355. uli1575@0 {
  356. reg = <0 0 0 0 0>;
  357. #size-cells = <2>;
  358. #address-cells = <3>;
  359. ranges = <0x02000000 0x0 0x80000000
  360. 0x02000000 0x0 0x80000000
  361. 0x0 0x20000000
  362. 0x01000000 0x0 0x00000000
  363. 0x01000000 0x0 0x00000000
  364. 0x0 0x00100000>;
  365. isa@1e {
  366. device_type = "isa";
  367. #interrupt-cells = <2>;
  368. #size-cells = <1>;
  369. #address-cells = <2>;
  370. reg = <0xf000 0 0 0 0>;
  371. ranges = <1 0 0x01000000 0 0
  372. 0x00001000>;
  373. interrupt-parent = <&i8259>;
  374. i8259: interrupt-controller@20 {
  375. reg = <1 0x20 2
  376. 1 0xa0 2
  377. 1 0x4d0 2>;
  378. interrupt-controller;
  379. device_type = "interrupt-controller";
  380. #address-cells = <0>;
  381. #interrupt-cells = <2>;
  382. compatible = "chrp,iic";
  383. interrupts = <9 2>;
  384. interrupt-parent = <&mpic>;
  385. };
  386. i8042@60 {
  387. #size-cells = <0>;
  388. #address-cells = <1>;
  389. reg = <1 0x60 1 1 0x64 1>;
  390. interrupts = <1 3 12 3>;
  391. interrupt-parent =
  392. <&i8259>;
  393. keyboard@0 {
  394. reg = <0>;
  395. compatible = "pnpPNP,303";
  396. };
  397. mouse@1 {
  398. reg = <1>;
  399. compatible = "pnpPNP,f03";
  400. };
  401. };
  402. rtc@70 {
  403. compatible =
  404. "pnpPNP,b00";
  405. reg = <1 0x70 2>;
  406. };
  407. gpio@400 {
  408. reg = <1 0x400 0x80>;
  409. };
  410. };
  411. };
  412. };
  413. };
  414. pci1: pcie@f8009000 {
  415. cell-index = <1>;
  416. compatible = "fsl,mpc8641-pcie";
  417. device_type = "pci";
  418. #interrupt-cells = <1>;
  419. #size-cells = <2>;
  420. #address-cells = <3>;
  421. reg = <0xf8009000 0x1000>;
  422. bus-range = <0 0xff>;
  423. ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
  424. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
  425. clock-frequency = <33333333>;
  426. interrupt-parent = <&mpic>;
  427. interrupts = <25 2>;
  428. interrupt-map-mask = <0xf800 0 0 7>;
  429. interrupt-map = <
  430. /* IDSEL 0x0 */
  431. 0x0000 0 0 1 &mpic 4 1
  432. 0x0000 0 0 2 &mpic 5 1
  433. 0x0000 0 0 3 &mpic 6 1
  434. 0x0000 0 0 4 &mpic 7 1
  435. >;
  436. pcie@0 {
  437. reg = <0 0 0 0 0>;
  438. #size-cells = <2>;
  439. #address-cells = <3>;
  440. device_type = "pci";
  441. ranges = <0x02000000 0x0 0xa0000000
  442. 0x02000000 0x0 0xa0000000
  443. 0x0 0x20000000
  444. 0x01000000 0x0 0x00000000
  445. 0x01000000 0x0 0x00000000
  446. 0x0 0x00100000>;
  447. };
  448. };
  449. rapidio0: rapidio@f80c0000 {
  450. #address-cells = <2>;
  451. #size-cells = <2>;
  452. compatible = "fsl,rapidio-delta";
  453. reg = <0xf80c0000 0x20000>;
  454. ranges = <0 0 0xc0000000 0 0x20000000>;
  455. interrupt-parent = <&mpic>;
  456. /* err_irq bell_outb_irq bell_inb_irq
  457. msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
  458. interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>;
  459. };
  460. };