fusb300_udc.c 38 KB

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  1. /*
  2. * Fusb300 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2010 Faraday Technology Corp.
  5. *
  6. * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/dma-mapping.h>
  23. #include <linux/err.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/usb/ch9.h>
  28. #include <linux/usb/gadget.h>
  29. #include "fusb300_udc.h"
  30. MODULE_DESCRIPTION("FUSB300 USB gadget driver");
  31. MODULE_LICENSE("GPL");
  32. MODULE_AUTHOR("Yuan Hsin Chen <yhchen@faraday-tech.com>");
  33. MODULE_ALIAS("platform:fusb300_udc");
  34. #define DRIVER_VERSION "20 October 2010"
  35. static const char udc_name[] = "fusb300_udc";
  36. static const char * const fusb300_ep_name[] = {
  37. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7", "ep8", "ep9",
  38. "ep10", "ep11", "ep12", "ep13", "ep14", "ep15"
  39. };
  40. static void done(struct fusb300_ep *ep, struct fusb300_request *req,
  41. int status);
  42. static void fusb300_enable_bit(struct fusb300 *fusb300, u32 offset,
  43. u32 value)
  44. {
  45. u32 reg = ioread32(fusb300->reg + offset);
  46. reg |= value;
  47. iowrite32(reg, fusb300->reg + offset);
  48. }
  49. static void fusb300_disable_bit(struct fusb300 *fusb300, u32 offset,
  50. u32 value)
  51. {
  52. u32 reg = ioread32(fusb300->reg + offset);
  53. reg &= ~value;
  54. iowrite32(reg, fusb300->reg + offset);
  55. }
  56. static void fusb300_ep_setting(struct fusb300_ep *ep,
  57. struct fusb300_ep_info info)
  58. {
  59. ep->epnum = info.epnum;
  60. ep->type = info.type;
  61. }
  62. static int fusb300_ep_release(struct fusb300_ep *ep)
  63. {
  64. if (!ep->epnum)
  65. return 0;
  66. ep->epnum = 0;
  67. ep->stall = 0;
  68. ep->wedged = 0;
  69. return 0;
  70. }
  71. static void fusb300_set_fifo_entry(struct fusb300 *fusb300,
  72. u32 ep)
  73. {
  74. u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  75. val &= ~FUSB300_EPSET1_FIFOENTRY_MSK;
  76. val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM);
  77. iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  78. }
  79. static void fusb300_set_start_entry(struct fusb300 *fusb300,
  80. u8 ep)
  81. {
  82. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  83. u32 start_entry = fusb300->fifo_entry_num * FUSB300_FIFO_ENTRY_NUM;
  84. reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ;
  85. reg |= FUSB300_EPSET1_START_ENTRY(start_entry);
  86. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  87. if (fusb300->fifo_entry_num == FUSB300_MAX_FIFO_ENTRY) {
  88. fusb300->fifo_entry_num = 0;
  89. fusb300->addrofs = 0;
  90. pr_err("fifo entry is over the maximum number!\n");
  91. } else
  92. fusb300->fifo_entry_num++;
  93. }
  94. /* set fusb300_set_start_entry first before fusb300_set_epaddrofs */
  95. static void fusb300_set_epaddrofs(struct fusb300 *fusb300,
  96. struct fusb300_ep_info info)
  97. {
  98. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  99. reg &= ~FUSB300_EPSET2_ADDROFS_MSK;
  100. reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs);
  101. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  102. fusb300->addrofs += (info.maxpacket + 7) / 8 * FUSB300_FIFO_ENTRY_NUM;
  103. }
  104. static void ep_fifo_setting(struct fusb300 *fusb300,
  105. struct fusb300_ep_info info)
  106. {
  107. fusb300_set_fifo_entry(fusb300, info.epnum);
  108. fusb300_set_start_entry(fusb300, info.epnum);
  109. fusb300_set_epaddrofs(fusb300, info);
  110. }
  111. static void fusb300_set_eptype(struct fusb300 *fusb300,
  112. struct fusb300_ep_info info)
  113. {
  114. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  115. reg &= ~FUSB300_EPSET1_TYPE_MSK;
  116. reg |= FUSB300_EPSET1_TYPE(info.type);
  117. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  118. }
  119. static void fusb300_set_epdir(struct fusb300 *fusb300,
  120. struct fusb300_ep_info info)
  121. {
  122. u32 reg;
  123. if (!info.dir_in)
  124. return;
  125. reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  126. reg &= ~FUSB300_EPSET1_DIR_MSK;
  127. reg |= FUSB300_EPSET1_DIRIN;
  128. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  129. }
  130. static void fusb300_set_ep_active(struct fusb300 *fusb300,
  131. u8 ep)
  132. {
  133. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  134. reg |= FUSB300_EPSET1_ACTEN;
  135. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  136. }
  137. static void fusb300_set_epmps(struct fusb300 *fusb300,
  138. struct fusb300_ep_info info)
  139. {
  140. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  141. reg &= ~FUSB300_EPSET2_MPS_MSK;
  142. reg |= FUSB300_EPSET2_MPS(info.maxpacket);
  143. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  144. }
  145. static void fusb300_set_interval(struct fusb300 *fusb300,
  146. struct fusb300_ep_info info)
  147. {
  148. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  149. reg &= ~FUSB300_EPSET1_INTERVAL(0x7);
  150. reg |= FUSB300_EPSET1_INTERVAL(info.interval);
  151. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  152. }
  153. static void fusb300_set_bwnum(struct fusb300 *fusb300,
  154. struct fusb300_ep_info info)
  155. {
  156. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  157. reg &= ~FUSB300_EPSET1_BWNUM(0x3);
  158. reg |= FUSB300_EPSET1_BWNUM(info.bw_num);
  159. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  160. }
  161. static void set_ep_reg(struct fusb300 *fusb300,
  162. struct fusb300_ep_info info)
  163. {
  164. fusb300_set_eptype(fusb300, info);
  165. fusb300_set_epdir(fusb300, info);
  166. fusb300_set_epmps(fusb300, info);
  167. if (info.interval)
  168. fusb300_set_interval(fusb300, info);
  169. if (info.bw_num)
  170. fusb300_set_bwnum(fusb300, info);
  171. fusb300_set_ep_active(fusb300, info.epnum);
  172. }
  173. static int config_ep(struct fusb300_ep *ep,
  174. const struct usb_endpoint_descriptor *desc)
  175. {
  176. struct fusb300 *fusb300 = ep->fusb300;
  177. struct fusb300_ep_info info;
  178. ep->desc = desc;
  179. info.interval = 0;
  180. info.addrofs = 0;
  181. info.bw_num = 0;
  182. info.type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  183. info.dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
  184. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  185. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  186. if ((info.type == USB_ENDPOINT_XFER_INT) ||
  187. (info.type == USB_ENDPOINT_XFER_ISOC)) {
  188. info.interval = desc->bInterval;
  189. if (info.type == USB_ENDPOINT_XFER_ISOC)
  190. info.bw_num = ((desc->wMaxPacketSize & 0x1800) >> 11);
  191. }
  192. ep_fifo_setting(fusb300, info);
  193. set_ep_reg(fusb300, info);
  194. fusb300_ep_setting(ep, info);
  195. fusb300->ep[info.epnum] = ep;
  196. return 0;
  197. }
  198. static int fusb300_enable(struct usb_ep *_ep,
  199. const struct usb_endpoint_descriptor *desc)
  200. {
  201. struct fusb300_ep *ep;
  202. ep = container_of(_ep, struct fusb300_ep, ep);
  203. if (ep->fusb300->reenum) {
  204. ep->fusb300->fifo_entry_num = 0;
  205. ep->fusb300->addrofs = 0;
  206. ep->fusb300->reenum = 0;
  207. }
  208. return config_ep(ep, desc);
  209. }
  210. static int fusb300_disable(struct usb_ep *_ep)
  211. {
  212. struct fusb300_ep *ep;
  213. struct fusb300_request *req;
  214. unsigned long flags;
  215. ep = container_of(_ep, struct fusb300_ep, ep);
  216. BUG_ON(!ep);
  217. while (!list_empty(&ep->queue)) {
  218. req = list_entry(ep->queue.next, struct fusb300_request, queue);
  219. spin_lock_irqsave(&ep->fusb300->lock, flags);
  220. done(ep, req, -ECONNRESET);
  221. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  222. }
  223. return fusb300_ep_release(ep);
  224. }
  225. static struct usb_request *fusb300_alloc_request(struct usb_ep *_ep,
  226. gfp_t gfp_flags)
  227. {
  228. struct fusb300_request *req;
  229. req = kzalloc(sizeof(struct fusb300_request), gfp_flags);
  230. if (!req)
  231. return NULL;
  232. INIT_LIST_HEAD(&req->queue);
  233. return &req->req;
  234. }
  235. static void fusb300_free_request(struct usb_ep *_ep, struct usb_request *_req)
  236. {
  237. struct fusb300_request *req;
  238. req = container_of(_req, struct fusb300_request, req);
  239. kfree(req);
  240. }
  241. static int enable_fifo_int(struct fusb300_ep *ep)
  242. {
  243. struct fusb300 *fusb300 = ep->fusb300;
  244. if (ep->epnum) {
  245. fusb300_enable_bit(fusb300, FUSB300_OFFSET_IGER0,
  246. FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
  247. } else {
  248. pr_err("can't enable_fifo_int ep0\n");
  249. return -EINVAL;
  250. }
  251. return 0;
  252. }
  253. static int disable_fifo_int(struct fusb300_ep *ep)
  254. {
  255. struct fusb300 *fusb300 = ep->fusb300;
  256. if (ep->epnum) {
  257. fusb300_disable_bit(fusb300, FUSB300_OFFSET_IGER0,
  258. FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
  259. } else {
  260. pr_err("can't disable_fifo_int ep0\n");
  261. return -EINVAL;
  262. }
  263. return 0;
  264. }
  265. static void fusb300_set_cxlen(struct fusb300 *fusb300, u32 length)
  266. {
  267. u32 reg;
  268. reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
  269. reg &= ~FUSB300_CSR_LEN_MSK;
  270. reg |= FUSB300_CSR_LEN(length);
  271. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR);
  272. }
  273. /* write data to cx fifo */
  274. static void fusb300_wrcxf(struct fusb300_ep *ep,
  275. struct fusb300_request *req)
  276. {
  277. int i = 0;
  278. u8 *tmp;
  279. u32 data;
  280. struct fusb300 *fusb300 = ep->fusb300;
  281. u32 length = req->req.length - req->req.actual;
  282. tmp = req->req.buf + req->req.actual;
  283. if (length > SS_CTL_MAX_PACKET_SIZE) {
  284. fusb300_set_cxlen(fusb300, SS_CTL_MAX_PACKET_SIZE);
  285. for (i = (SS_CTL_MAX_PACKET_SIZE >> 2); i > 0; i--) {
  286. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
  287. *(tmp + 3) << 24;
  288. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  289. tmp += 4;
  290. }
  291. req->req.actual += SS_CTL_MAX_PACKET_SIZE;
  292. } else { /* length is less than max packet size */
  293. fusb300_set_cxlen(fusb300, length);
  294. for (i = length >> 2; i > 0; i--) {
  295. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
  296. *(tmp + 3) << 24;
  297. printk(KERN_DEBUG " 0x%x\n", data);
  298. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  299. tmp = tmp + 4;
  300. }
  301. switch (length % 4) {
  302. case 1:
  303. data = *tmp;
  304. printk(KERN_DEBUG " 0x%x\n", data);
  305. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  306. break;
  307. case 2:
  308. data = *tmp | *(tmp + 1) << 8;
  309. printk(KERN_DEBUG " 0x%x\n", data);
  310. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  311. break;
  312. case 3:
  313. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
  314. printk(KERN_DEBUG " 0x%x\n", data);
  315. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  316. break;
  317. default:
  318. break;
  319. }
  320. req->req.actual += length;
  321. }
  322. }
  323. static void fusb300_set_epnstall(struct fusb300 *fusb300, u8 ep)
  324. {
  325. fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
  326. FUSB300_EPSET0_STL);
  327. }
  328. static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep)
  329. {
  330. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  331. if (reg & FUSB300_EPSET0_STL) {
  332. printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep);
  333. reg &= ~FUSB300_EPSET0_STL;
  334. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  335. }
  336. }
  337. static void ep0_queue(struct fusb300_ep *ep, struct fusb300_request *req)
  338. {
  339. if (ep->fusb300->ep0_dir) { /* if IN */
  340. if (req->req.length) {
  341. fusb300_wrcxf(ep, req);
  342. } else
  343. printk(KERN_DEBUG "%s : req->req.length = 0x%x\n",
  344. __func__, req->req.length);
  345. if ((req->req.length == req->req.actual) ||
  346. (req->req.actual < ep->ep.maxpacket))
  347. done(ep, req, 0);
  348. } else { /* OUT */
  349. if (!req->req.length)
  350. done(ep, req, 0);
  351. else
  352. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER1,
  353. FUSB300_IGER1_CX_OUT_INT);
  354. }
  355. }
  356. static int fusb300_queue(struct usb_ep *_ep, struct usb_request *_req,
  357. gfp_t gfp_flags)
  358. {
  359. struct fusb300_ep *ep;
  360. struct fusb300_request *req;
  361. unsigned long flags;
  362. int request = 0;
  363. ep = container_of(_ep, struct fusb300_ep, ep);
  364. req = container_of(_req, struct fusb300_request, req);
  365. if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
  366. return -ESHUTDOWN;
  367. spin_lock_irqsave(&ep->fusb300->lock, flags);
  368. if (list_empty(&ep->queue))
  369. request = 1;
  370. list_add_tail(&req->queue, &ep->queue);
  371. req->req.actual = 0;
  372. req->req.status = -EINPROGRESS;
  373. if (ep->desc == NULL) /* ep0 */
  374. ep0_queue(ep, req);
  375. else if (request && !ep->stall)
  376. enable_fifo_int(ep);
  377. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  378. return 0;
  379. }
  380. static int fusb300_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  381. {
  382. struct fusb300_ep *ep;
  383. struct fusb300_request *req;
  384. unsigned long flags;
  385. ep = container_of(_ep, struct fusb300_ep, ep);
  386. req = container_of(_req, struct fusb300_request, req);
  387. spin_lock_irqsave(&ep->fusb300->lock, flags);
  388. if (!list_empty(&ep->queue))
  389. done(ep, req, -ECONNRESET);
  390. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  391. return 0;
  392. }
  393. static int fusb300_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
  394. {
  395. struct fusb300_ep *ep;
  396. struct fusb300 *fusb300;
  397. unsigned long flags;
  398. int ret = 0;
  399. ep = container_of(_ep, struct fusb300_ep, ep);
  400. fusb300 = ep->fusb300;
  401. spin_lock_irqsave(&ep->fusb300->lock, flags);
  402. if (!list_empty(&ep->queue)) {
  403. ret = -EAGAIN;
  404. goto out;
  405. }
  406. if (value) {
  407. fusb300_set_epnstall(fusb300, ep->epnum);
  408. ep->stall = 1;
  409. if (wedge)
  410. ep->wedged = 1;
  411. } else {
  412. fusb300_clear_epnstall(fusb300, ep->epnum);
  413. ep->stall = 0;
  414. ep->wedged = 0;
  415. }
  416. out:
  417. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  418. return ret;
  419. }
  420. static int fusb300_set_halt(struct usb_ep *_ep, int value)
  421. {
  422. return fusb300_set_halt_and_wedge(_ep, value, 0);
  423. }
  424. static int fusb300_set_wedge(struct usb_ep *_ep)
  425. {
  426. return fusb300_set_halt_and_wedge(_ep, 1, 1);
  427. }
  428. static void fusb300_fifo_flush(struct usb_ep *_ep)
  429. {
  430. }
  431. static struct usb_ep_ops fusb300_ep_ops = {
  432. .enable = fusb300_enable,
  433. .disable = fusb300_disable,
  434. .alloc_request = fusb300_alloc_request,
  435. .free_request = fusb300_free_request,
  436. .queue = fusb300_queue,
  437. .dequeue = fusb300_dequeue,
  438. .set_halt = fusb300_set_halt,
  439. .fifo_flush = fusb300_fifo_flush,
  440. .set_wedge = fusb300_set_wedge,
  441. };
  442. /*****************************************************************************/
  443. static void fusb300_clear_int(struct fusb300 *fusb300, u32 offset,
  444. u32 value)
  445. {
  446. iowrite32(value, fusb300->reg + offset);
  447. }
  448. static void fusb300_reset(void)
  449. {
  450. }
  451. static void fusb300_set_cxstall(struct fusb300 *fusb300)
  452. {
  453. fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
  454. FUSB300_CSR_STL);
  455. }
  456. static void fusb300_set_cxdone(struct fusb300 *fusb300)
  457. {
  458. fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
  459. FUSB300_CSR_DONE);
  460. }
  461. /* read data from cx fifo */
  462. void fusb300_rdcxf(struct fusb300 *fusb300,
  463. u8 *buffer, u32 length)
  464. {
  465. int i = 0;
  466. u8 *tmp;
  467. u32 data;
  468. tmp = buffer;
  469. for (i = (length >> 2); i > 0; i--) {
  470. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  471. printk(KERN_DEBUG " 0x%x\n", data);
  472. *tmp = data & 0xFF;
  473. *(tmp + 1) = (data >> 8) & 0xFF;
  474. *(tmp + 2) = (data >> 16) & 0xFF;
  475. *(tmp + 3) = (data >> 24) & 0xFF;
  476. tmp = tmp + 4;
  477. }
  478. switch (length % 4) {
  479. case 1:
  480. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  481. printk(KERN_DEBUG " 0x%x\n", data);
  482. *tmp = data & 0xFF;
  483. break;
  484. case 2:
  485. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  486. printk(KERN_DEBUG " 0x%x\n", data);
  487. *tmp = data & 0xFF;
  488. *(tmp + 1) = (data >> 8) & 0xFF;
  489. break;
  490. case 3:
  491. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  492. printk(KERN_DEBUG " 0x%x\n", data);
  493. *tmp = data & 0xFF;
  494. *(tmp + 1) = (data >> 8) & 0xFF;
  495. *(tmp + 2) = (data >> 16) & 0xFF;
  496. break;
  497. default:
  498. break;
  499. }
  500. }
  501. static void fusb300_rdfifo(struct fusb300_ep *ep,
  502. struct fusb300_request *req,
  503. u32 length)
  504. {
  505. int i = 0;
  506. u8 *tmp;
  507. u32 data, reg;
  508. struct fusb300 *fusb300 = ep->fusb300;
  509. tmp = req->req.buf + req->req.actual;
  510. req->req.actual += length;
  511. if (req->req.actual > req->req.length)
  512. printk(KERN_DEBUG "req->req.actual > req->req.length\n");
  513. for (i = (length >> 2); i > 0; i--) {
  514. data = ioread32(fusb300->reg +
  515. FUSB300_OFFSET_EPPORT(ep->epnum));
  516. *tmp = data & 0xFF;
  517. *(tmp + 1) = (data >> 8) & 0xFF;
  518. *(tmp + 2) = (data >> 16) & 0xFF;
  519. *(tmp + 3) = (data >> 24) & 0xFF;
  520. tmp = tmp + 4;
  521. }
  522. switch (length % 4) {
  523. case 1:
  524. data = ioread32(fusb300->reg +
  525. FUSB300_OFFSET_EPPORT(ep->epnum));
  526. *tmp = data & 0xFF;
  527. break;
  528. case 2:
  529. data = ioread32(fusb300->reg +
  530. FUSB300_OFFSET_EPPORT(ep->epnum));
  531. *tmp = data & 0xFF;
  532. *(tmp + 1) = (data >> 8) & 0xFF;
  533. break;
  534. case 3:
  535. data = ioread32(fusb300->reg +
  536. FUSB300_OFFSET_EPPORT(ep->epnum));
  537. *tmp = data & 0xFF;
  538. *(tmp + 1) = (data >> 8) & 0xFF;
  539. *(tmp + 2) = (data >> 16) & 0xFF;
  540. break;
  541. default:
  542. break;
  543. }
  544. do {
  545. reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
  546. reg &= FUSB300_IGR1_SYNF0_EMPTY_INT;
  547. if (i)
  548. printk(KERN_INFO "sync fifo is not empty!\n");
  549. i++;
  550. } while (!reg);
  551. }
  552. static u8 fusb300_get_epnstall(struct fusb300 *fusb300, u8 ep)
  553. {
  554. u8 value;
  555. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  556. value = reg & FUSB300_EPSET0_STL;
  557. return value;
  558. }
  559. static u8 fusb300_get_cxstall(struct fusb300 *fusb300)
  560. {
  561. u8 value;
  562. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
  563. value = (reg & FUSB300_CSR_STL) >> 1;
  564. return value;
  565. }
  566. static void request_error(struct fusb300 *fusb300)
  567. {
  568. fusb300_set_cxstall(fusb300);
  569. printk(KERN_DEBUG "request error!!\n");
  570. }
  571. static void get_status(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  572. __releases(fusb300->lock)
  573. __acquires(fusb300->lock)
  574. {
  575. u8 ep;
  576. u16 status = 0;
  577. u16 w_index = ctrl->wIndex;
  578. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  579. case USB_RECIP_DEVICE:
  580. status = 1 << USB_DEVICE_SELF_POWERED;
  581. break;
  582. case USB_RECIP_INTERFACE:
  583. status = 0;
  584. break;
  585. case USB_RECIP_ENDPOINT:
  586. ep = w_index & USB_ENDPOINT_NUMBER_MASK;
  587. if (ep) {
  588. if (fusb300_get_epnstall(fusb300, ep))
  589. status = 1 << USB_ENDPOINT_HALT;
  590. } else {
  591. if (fusb300_get_cxstall(fusb300))
  592. status = 0;
  593. }
  594. break;
  595. default:
  596. request_error(fusb300);
  597. return; /* exit */
  598. }
  599. fusb300->ep0_data = cpu_to_le16(status);
  600. fusb300->ep0_req->buf = &fusb300->ep0_data;
  601. fusb300->ep0_req->length = 2;
  602. spin_unlock(&fusb300->lock);
  603. fusb300_queue(fusb300->gadget.ep0, fusb300->ep0_req, GFP_KERNEL);
  604. spin_lock(&fusb300->lock);
  605. }
  606. static void set_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  607. {
  608. u8 ep;
  609. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  610. case USB_RECIP_DEVICE:
  611. fusb300_set_cxdone(fusb300);
  612. break;
  613. case USB_RECIP_INTERFACE:
  614. fusb300_set_cxdone(fusb300);
  615. break;
  616. case USB_RECIP_ENDPOINT: {
  617. u16 w_index = le16_to_cpu(ctrl->wIndex);
  618. ep = w_index & USB_ENDPOINT_NUMBER_MASK;
  619. if (ep)
  620. fusb300_set_epnstall(fusb300, ep);
  621. else
  622. fusb300_set_cxstall(fusb300);
  623. fusb300_set_cxdone(fusb300);
  624. }
  625. break;
  626. default:
  627. request_error(fusb300);
  628. break;
  629. }
  630. }
  631. static void fusb300_clear_seqnum(struct fusb300 *fusb300, u8 ep)
  632. {
  633. fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
  634. FUSB300_EPSET0_CLRSEQNUM);
  635. }
  636. static void clear_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  637. {
  638. struct fusb300_ep *ep =
  639. fusb300->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
  640. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  641. case USB_RECIP_DEVICE:
  642. fusb300_set_cxdone(fusb300);
  643. break;
  644. case USB_RECIP_INTERFACE:
  645. fusb300_set_cxdone(fusb300);
  646. break;
  647. case USB_RECIP_ENDPOINT:
  648. if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
  649. if (ep->wedged) {
  650. fusb300_set_cxdone(fusb300);
  651. break;
  652. }
  653. if (ep->stall) {
  654. ep->stall = 0;
  655. fusb300_clear_seqnum(fusb300, ep->epnum);
  656. fusb300_clear_epnstall(fusb300, ep->epnum);
  657. if (!list_empty(&ep->queue))
  658. enable_fifo_int(ep);
  659. }
  660. }
  661. fusb300_set_cxdone(fusb300);
  662. break;
  663. default:
  664. request_error(fusb300);
  665. break;
  666. }
  667. }
  668. static void fusb300_set_dev_addr(struct fusb300 *fusb300, u16 addr)
  669. {
  670. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR);
  671. reg &= ~FUSB300_DAR_DRVADDR_MSK;
  672. reg |= FUSB300_DAR_DRVADDR(addr);
  673. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR);
  674. }
  675. static void set_address(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  676. {
  677. if (ctrl->wValue >= 0x0100)
  678. request_error(fusb300);
  679. else {
  680. fusb300_set_dev_addr(fusb300, ctrl->wValue);
  681. fusb300_set_cxdone(fusb300);
  682. }
  683. }
  684. #define UVC_COPY_DESCRIPTORS(mem, src) \
  685. do { \
  686. const struct usb_descriptor_header * const *__src; \
  687. for (__src = src; *__src; ++__src) { \
  688. memcpy(mem, *__src, (*__src)->bLength); \
  689. mem += (*__src)->bLength; \
  690. } \
  691. } while (0)
  692. static int setup_packet(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  693. {
  694. u8 *p = (u8 *)ctrl;
  695. u8 ret = 0;
  696. u8 i = 0;
  697. fusb300_rdcxf(fusb300, p, 8);
  698. fusb300->ep0_dir = ctrl->bRequestType & USB_DIR_IN;
  699. fusb300->ep0_length = ctrl->wLength;
  700. /* check request */
  701. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  702. switch (ctrl->bRequest) {
  703. case USB_REQ_GET_STATUS:
  704. get_status(fusb300, ctrl);
  705. break;
  706. case USB_REQ_CLEAR_FEATURE:
  707. clear_feature(fusb300, ctrl);
  708. break;
  709. case USB_REQ_SET_FEATURE:
  710. set_feature(fusb300, ctrl);
  711. break;
  712. case USB_REQ_SET_ADDRESS:
  713. set_address(fusb300, ctrl);
  714. break;
  715. case USB_REQ_SET_CONFIGURATION:
  716. fusb300_enable_bit(fusb300, FUSB300_OFFSET_DAR,
  717. FUSB300_DAR_SETCONFG);
  718. /* clear sequence number */
  719. for (i = 1; i <= FUSB300_MAX_NUM_EP; i++)
  720. fusb300_clear_seqnum(fusb300, i);
  721. fusb300->reenum = 1;
  722. ret = 1;
  723. break;
  724. default:
  725. ret = 1;
  726. break;
  727. }
  728. } else
  729. ret = 1;
  730. return ret;
  731. }
  732. static void done(struct fusb300_ep *ep, struct fusb300_request *req,
  733. int status)
  734. {
  735. list_del_init(&req->queue);
  736. /* don't modify queue heads during completion callback */
  737. if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
  738. req->req.status = -ESHUTDOWN;
  739. else
  740. req->req.status = status;
  741. spin_unlock(&ep->fusb300->lock);
  742. req->req.complete(&ep->ep, &req->req);
  743. spin_lock(&ep->fusb300->lock);
  744. if (ep->epnum) {
  745. disable_fifo_int(ep);
  746. if (!list_empty(&ep->queue))
  747. enable_fifo_int(ep);
  748. } else
  749. fusb300_set_cxdone(ep->fusb300);
  750. }
  751. static void fusb300_fill_idma_prdtbl(struct fusb300_ep *ep, dma_addr_t d,
  752. u32 len)
  753. {
  754. u32 value;
  755. u32 reg;
  756. /* wait SW owner */
  757. do {
  758. reg = ioread32(ep->fusb300->reg +
  759. FUSB300_OFFSET_EPPRD_W0(ep->epnum));
  760. reg &= FUSB300_EPPRD0_H;
  761. } while (reg);
  762. iowrite32(d, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W1(ep->epnum));
  763. value = FUSB300_EPPRD0_BTC(len) | FUSB300_EPPRD0_H |
  764. FUSB300_EPPRD0_F | FUSB300_EPPRD0_L | FUSB300_EPPRD0_I;
  765. iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum));
  766. iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum));
  767. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_EPPRDRDY,
  768. FUSB300_EPPRDR_EP_PRD_RDY(ep->epnum));
  769. }
  770. static void fusb300_wait_idma_finished(struct fusb300_ep *ep)
  771. {
  772. u32 reg;
  773. do {
  774. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1);
  775. if ((reg & FUSB300_IGR1_VBUS_CHG_INT) ||
  776. (reg & FUSB300_IGR1_WARM_RST_INT) ||
  777. (reg & FUSB300_IGR1_HOT_RST_INT) ||
  778. (reg & FUSB300_IGR1_USBRST_INT)
  779. )
  780. goto IDMA_RESET;
  781. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0);
  782. reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum);
  783. } while (!reg);
  784. fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGR0,
  785. FUSB300_IGR0_EPn_PRD_INT(ep->epnum));
  786. IDMA_RESET:
  787. fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGER0,
  788. FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
  789. }
  790. static void fusb300_set_idma(struct fusb300_ep *ep,
  791. struct fusb300_request *req)
  792. {
  793. dma_addr_t d;
  794. d = dma_map_single(NULL, req->req.buf, req->req.length, DMA_TO_DEVICE);
  795. if (dma_mapping_error(NULL, d)) {
  796. printk(KERN_DEBUG "dma_mapping_error\n");
  797. return;
  798. }
  799. dma_sync_single_for_device(NULL, d, req->req.length, DMA_TO_DEVICE);
  800. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER0,
  801. FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
  802. fusb300_fill_idma_prdtbl(ep, d, req->req.length);
  803. /* check idma is done */
  804. fusb300_wait_idma_finished(ep);
  805. dma_unmap_single(NULL, d, req->req.length, DMA_TO_DEVICE);
  806. }
  807. static void in_ep_fifo_handler(struct fusb300_ep *ep)
  808. {
  809. struct fusb300_request *req = list_entry(ep->queue.next,
  810. struct fusb300_request, queue);
  811. if (req->req.length)
  812. fusb300_set_idma(ep, req);
  813. done(ep, req, 0);
  814. }
  815. static void out_ep_fifo_handler(struct fusb300_ep *ep)
  816. {
  817. struct fusb300 *fusb300 = ep->fusb300;
  818. struct fusb300_request *req = list_entry(ep->queue.next,
  819. struct fusb300_request, queue);
  820. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
  821. u32 length = reg & FUSB300_FFR_BYCNT;
  822. fusb300_rdfifo(ep, req, length);
  823. /* finish out transfer */
  824. if ((req->req.length == req->req.actual) || (length < ep->ep.maxpacket))
  825. done(ep, req, 0);
  826. }
  827. static void check_device_mode(struct fusb300 *fusb300)
  828. {
  829. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR);
  830. switch (reg & FUSB300_GCR_DEVEN_MSK) {
  831. case FUSB300_GCR_DEVEN_SS:
  832. fusb300->gadget.speed = USB_SPEED_SUPER;
  833. break;
  834. case FUSB300_GCR_DEVEN_HS:
  835. fusb300->gadget.speed = USB_SPEED_HIGH;
  836. break;
  837. case FUSB300_GCR_DEVEN_FS:
  838. fusb300->gadget.speed = USB_SPEED_FULL;
  839. break;
  840. default:
  841. fusb300->gadget.speed = USB_SPEED_UNKNOWN;
  842. break;
  843. }
  844. printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK));
  845. }
  846. static void fusb300_ep0out(struct fusb300 *fusb300)
  847. {
  848. struct fusb300_ep *ep = fusb300->ep[0];
  849. u32 reg;
  850. if (!list_empty(&ep->queue)) {
  851. struct fusb300_request *req;
  852. req = list_first_entry(&ep->queue,
  853. struct fusb300_request, queue);
  854. if (req->req.length)
  855. fusb300_rdcxf(ep->fusb300, req->req.buf,
  856. req->req.length);
  857. done(ep, req, 0);
  858. reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
  859. reg &= ~FUSB300_IGER1_CX_OUT_INT;
  860. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1);
  861. } else
  862. pr_err("%s : empty queue\n", __func__);
  863. }
  864. static void fusb300_ep0in(struct fusb300 *fusb300)
  865. {
  866. struct fusb300_request *req;
  867. struct fusb300_ep *ep = fusb300->ep[0];
  868. if ((!list_empty(&ep->queue)) && (fusb300->ep0_dir)) {
  869. req = list_entry(ep->queue.next,
  870. struct fusb300_request, queue);
  871. if (req->req.length)
  872. fusb300_wrcxf(ep, req);
  873. if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
  874. done(ep, req, 0);
  875. } else
  876. fusb300_set_cxdone(fusb300);
  877. }
  878. static void fusb300_grp2_handler(void)
  879. {
  880. }
  881. static void fusb300_grp3_handler(void)
  882. {
  883. }
  884. static void fusb300_grp4_handler(void)
  885. {
  886. }
  887. static void fusb300_grp5_handler(void)
  888. {
  889. }
  890. static irqreturn_t fusb300_irq(int irq, void *_fusb300)
  891. {
  892. struct fusb300 *fusb300 = _fusb300;
  893. u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
  894. u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
  895. u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0);
  896. u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0);
  897. struct usb_ctrlrequest ctrl;
  898. u8 in;
  899. u32 reg;
  900. int i;
  901. spin_lock(&fusb300->lock);
  902. int_grp1 &= int_grp1_en;
  903. int_grp0 &= int_grp0_en;
  904. if (int_grp1 & FUSB300_IGR1_WARM_RST_INT) {
  905. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  906. FUSB300_IGR1_WARM_RST_INT);
  907. printk(KERN_INFO"fusb300_warmreset\n");
  908. fusb300_reset();
  909. }
  910. if (int_grp1 & FUSB300_IGR1_HOT_RST_INT) {
  911. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  912. FUSB300_IGR1_HOT_RST_INT);
  913. printk(KERN_INFO"fusb300_hotreset\n");
  914. fusb300_reset();
  915. }
  916. if (int_grp1 & FUSB300_IGR1_USBRST_INT) {
  917. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  918. FUSB300_IGR1_USBRST_INT);
  919. fusb300_reset();
  920. }
  921. /* COMABT_INT has a highest priority */
  922. if (int_grp1 & FUSB300_IGR1_CX_COMABT_INT) {
  923. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  924. FUSB300_IGR1_CX_COMABT_INT);
  925. printk(KERN_INFO"fusb300_ep0abt\n");
  926. }
  927. if (int_grp1 & FUSB300_IGR1_VBUS_CHG_INT) {
  928. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  929. FUSB300_IGR1_VBUS_CHG_INT);
  930. printk(KERN_INFO"fusb300_vbus_change\n");
  931. }
  932. if (int_grp1 & FUSB300_IGR1_U3_EXIT_FAIL_INT) {
  933. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  934. FUSB300_IGR1_U3_EXIT_FAIL_INT);
  935. }
  936. if (int_grp1 & FUSB300_IGR1_U2_EXIT_FAIL_INT) {
  937. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  938. FUSB300_IGR1_U2_EXIT_FAIL_INT);
  939. }
  940. if (int_grp1 & FUSB300_IGR1_U1_EXIT_FAIL_INT) {
  941. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  942. FUSB300_IGR1_U1_EXIT_FAIL_INT);
  943. }
  944. if (int_grp1 & FUSB300_IGR1_U2_ENTRY_FAIL_INT) {
  945. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  946. FUSB300_IGR1_U2_ENTRY_FAIL_INT);
  947. }
  948. if (int_grp1 & FUSB300_IGR1_U1_ENTRY_FAIL_INT) {
  949. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  950. FUSB300_IGR1_U1_ENTRY_FAIL_INT);
  951. }
  952. if (int_grp1 & FUSB300_IGR1_U3_EXIT_INT) {
  953. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  954. FUSB300_IGR1_U3_EXIT_INT);
  955. printk(KERN_INFO "FUSB300_IGR1_U3_EXIT_INT\n");
  956. }
  957. if (int_grp1 & FUSB300_IGR1_U2_EXIT_INT) {
  958. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  959. FUSB300_IGR1_U2_EXIT_INT);
  960. printk(KERN_INFO "FUSB300_IGR1_U2_EXIT_INT\n");
  961. }
  962. if (int_grp1 & FUSB300_IGR1_U1_EXIT_INT) {
  963. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  964. FUSB300_IGR1_U1_EXIT_INT);
  965. printk(KERN_INFO "FUSB300_IGR1_U1_EXIT_INT\n");
  966. }
  967. if (int_grp1 & FUSB300_IGR1_U3_ENTRY_INT) {
  968. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  969. FUSB300_IGR1_U3_ENTRY_INT);
  970. printk(KERN_INFO "FUSB300_IGR1_U3_ENTRY_INT\n");
  971. fusb300_enable_bit(fusb300, FUSB300_OFFSET_SSCR1,
  972. FUSB300_SSCR1_GO_U3_DONE);
  973. }
  974. if (int_grp1 & FUSB300_IGR1_U2_ENTRY_INT) {
  975. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  976. FUSB300_IGR1_U2_ENTRY_INT);
  977. printk(KERN_INFO "FUSB300_IGR1_U2_ENTRY_INT\n");
  978. }
  979. if (int_grp1 & FUSB300_IGR1_U1_ENTRY_INT) {
  980. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  981. FUSB300_IGR1_U1_ENTRY_INT);
  982. printk(KERN_INFO "FUSB300_IGR1_U1_ENTRY_INT\n");
  983. }
  984. if (int_grp1 & FUSB300_IGR1_RESM_INT) {
  985. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  986. FUSB300_IGR1_RESM_INT);
  987. printk(KERN_INFO "fusb300_resume\n");
  988. }
  989. if (int_grp1 & FUSB300_IGR1_SUSP_INT) {
  990. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  991. FUSB300_IGR1_SUSP_INT);
  992. printk(KERN_INFO "fusb300_suspend\n");
  993. }
  994. if (int_grp1 & FUSB300_IGR1_HS_LPM_INT) {
  995. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  996. FUSB300_IGR1_HS_LPM_INT);
  997. printk(KERN_INFO "fusb300_HS_LPM_INT\n");
  998. }
  999. if (int_grp1 & FUSB300_IGR1_DEV_MODE_CHG_INT) {
  1000. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1001. FUSB300_IGR1_DEV_MODE_CHG_INT);
  1002. check_device_mode(fusb300);
  1003. }
  1004. if (int_grp1 & FUSB300_IGR1_CX_COMFAIL_INT) {
  1005. fusb300_set_cxstall(fusb300);
  1006. printk(KERN_INFO "fusb300_ep0fail\n");
  1007. }
  1008. if (int_grp1 & FUSB300_IGR1_CX_SETUP_INT) {
  1009. printk(KERN_INFO "fusb300_ep0setup\n");
  1010. if (setup_packet(fusb300, &ctrl)) {
  1011. spin_unlock(&fusb300->lock);
  1012. if (fusb300->driver->setup(&fusb300->gadget, &ctrl) < 0)
  1013. fusb300_set_cxstall(fusb300);
  1014. spin_lock(&fusb300->lock);
  1015. }
  1016. }
  1017. if (int_grp1 & FUSB300_IGR1_CX_CMDEND_INT)
  1018. printk(KERN_INFO "fusb300_cmdend\n");
  1019. if (int_grp1 & FUSB300_IGR1_CX_OUT_INT) {
  1020. printk(KERN_INFO "fusb300_cxout\n");
  1021. fusb300_ep0out(fusb300);
  1022. }
  1023. if (int_grp1 & FUSB300_IGR1_CX_IN_INT) {
  1024. printk(KERN_INFO "fusb300_cxin\n");
  1025. fusb300_ep0in(fusb300);
  1026. }
  1027. if (int_grp1 & FUSB300_IGR1_INTGRP5)
  1028. fusb300_grp5_handler();
  1029. if (int_grp1 & FUSB300_IGR1_INTGRP4)
  1030. fusb300_grp4_handler();
  1031. if (int_grp1 & FUSB300_IGR1_INTGRP3)
  1032. fusb300_grp3_handler();
  1033. if (int_grp1 & FUSB300_IGR1_INTGRP2)
  1034. fusb300_grp2_handler();
  1035. if (int_grp0) {
  1036. for (i = 1; i < FUSB300_MAX_NUM_EP; i++) {
  1037. if (int_grp0 & FUSB300_IGR0_EPn_FIFO_INT(i)) {
  1038. reg = ioread32(fusb300->reg +
  1039. FUSB300_OFFSET_EPSET1(i));
  1040. in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0;
  1041. if (in)
  1042. in_ep_fifo_handler(fusb300->ep[i]);
  1043. else
  1044. out_ep_fifo_handler(fusb300->ep[i]);
  1045. }
  1046. }
  1047. }
  1048. spin_unlock(&fusb300->lock);
  1049. return IRQ_HANDLED;
  1050. }
  1051. static void fusb300_set_u2_timeout(struct fusb300 *fusb300,
  1052. u32 time)
  1053. {
  1054. u32 reg;
  1055. reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
  1056. reg &= ~0xff;
  1057. reg |= FUSB300_SSCR2_U2TIMEOUT(time);
  1058. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
  1059. }
  1060. static void fusb300_set_u1_timeout(struct fusb300 *fusb300,
  1061. u32 time)
  1062. {
  1063. u32 reg;
  1064. reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
  1065. reg &= ~(0xff << 8);
  1066. reg |= FUSB300_SSCR2_U1TIMEOUT(time);
  1067. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
  1068. }
  1069. static void init_controller(struct fusb300 *fusb300)
  1070. {
  1071. u32 reg;
  1072. u32 mask = 0;
  1073. u32 val = 0;
  1074. /* split on */
  1075. mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON;
  1076. reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR);
  1077. reg &= ~mask;
  1078. reg |= val;
  1079. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR);
  1080. /* enable high-speed LPM */
  1081. mask = val = FUSB300_HSCR_HS_LPM_PERMIT;
  1082. reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR);
  1083. reg &= ~mask;
  1084. reg |= val;
  1085. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR);
  1086. /*set u1 u2 timmer*/
  1087. fusb300_set_u2_timeout(fusb300, 0xff);
  1088. fusb300_set_u1_timeout(fusb300, 0xff);
  1089. /* enable all grp1 interrupt */
  1090. iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1);
  1091. }
  1092. /*------------------------------------------------------------------------*/
  1093. static struct fusb300 *the_controller;
  1094. static int fusb300_udc_start(struct usb_gadget_driver *driver,
  1095. int (*bind)(struct usb_gadget *))
  1096. {
  1097. struct fusb300 *fusb300 = the_controller;
  1098. int retval;
  1099. if (!driver
  1100. || driver->speed < USB_SPEED_FULL
  1101. || !bind
  1102. || !driver->setup)
  1103. return -EINVAL;
  1104. if (!fusb300)
  1105. return -ENODEV;
  1106. if (fusb300->driver)
  1107. return -EBUSY;
  1108. /* hook up the driver */
  1109. driver->driver.bus = NULL;
  1110. fusb300->driver = driver;
  1111. fusb300->gadget.dev.driver = &driver->driver;
  1112. retval = device_add(&fusb300->gadget.dev);
  1113. if (retval) {
  1114. pr_err("device_add error (%d)\n", retval);
  1115. goto error;
  1116. }
  1117. retval = bind(&fusb300->gadget);
  1118. if (retval) {
  1119. pr_err("bind to driver error (%d)\n", retval);
  1120. device_del(&fusb300->gadget.dev);
  1121. goto error;
  1122. }
  1123. return 0;
  1124. error:
  1125. fusb300->driver = NULL;
  1126. fusb300->gadget.dev.driver = NULL;
  1127. return retval;
  1128. }
  1129. static int fusb300_udc_stop(struct usb_gadget_driver *driver)
  1130. {
  1131. struct fusb300 *fusb300 = the_controller;
  1132. if (driver != fusb300->driver || !driver->unbind)
  1133. return -EINVAL;
  1134. driver->unbind(&fusb300->gadget);
  1135. fusb300->gadget.dev.driver = NULL;
  1136. init_controller(fusb300);
  1137. device_del(&fusb300->gadget.dev);
  1138. fusb300->driver = NULL;
  1139. return 0;
  1140. }
  1141. /*--------------------------------------------------------------------------*/
  1142. static int fusb300_udc_pullup(struct usb_gadget *_gadget, int is_active)
  1143. {
  1144. return 0;
  1145. }
  1146. static struct usb_gadget_ops fusb300_gadget_ops = {
  1147. .pullup = fusb300_udc_pullup,
  1148. .start = fusb300_udc_start,
  1149. .stop = fusb300_udc_stop,
  1150. };
  1151. static int __exit fusb300_remove(struct platform_device *pdev)
  1152. {
  1153. struct fusb300 *fusb300 = dev_get_drvdata(&pdev->dev);
  1154. usb_del_gadget_udc(&fusb300->gadget);
  1155. iounmap(fusb300->reg);
  1156. free_irq(platform_get_irq(pdev, 0), fusb300);
  1157. fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
  1158. kfree(fusb300);
  1159. return 0;
  1160. }
  1161. static int __init fusb300_probe(struct platform_device *pdev)
  1162. {
  1163. struct resource *res, *ires, *ires1;
  1164. void __iomem *reg = NULL;
  1165. struct fusb300 *fusb300 = NULL;
  1166. struct fusb300_ep *_ep[FUSB300_MAX_NUM_EP];
  1167. int ret = 0;
  1168. int i;
  1169. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1170. if (!res) {
  1171. ret = -ENODEV;
  1172. pr_err("platform_get_resource error.\n");
  1173. goto clean_up;
  1174. }
  1175. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1176. if (!ires) {
  1177. ret = -ENODEV;
  1178. dev_err(&pdev->dev,
  1179. "platform_get_resource IORESOURCE_IRQ error.\n");
  1180. goto clean_up;
  1181. }
  1182. ires1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
  1183. if (!ires1) {
  1184. ret = -ENODEV;
  1185. dev_err(&pdev->dev,
  1186. "platform_get_resource IORESOURCE_IRQ 1 error.\n");
  1187. goto clean_up;
  1188. }
  1189. reg = ioremap(res->start, resource_size(res));
  1190. if (reg == NULL) {
  1191. ret = -ENOMEM;
  1192. pr_err("ioremap error.\n");
  1193. goto clean_up;
  1194. }
  1195. /* initialize udc */
  1196. fusb300 = kzalloc(sizeof(struct fusb300), GFP_KERNEL);
  1197. if (fusb300 == NULL) {
  1198. pr_err("kzalloc error\n");
  1199. goto clean_up;
  1200. }
  1201. for (i = 0; i < FUSB300_MAX_NUM_EP; i++) {
  1202. _ep[i] = kzalloc(sizeof(struct fusb300_ep), GFP_KERNEL);
  1203. if (_ep[i] == NULL) {
  1204. pr_err("_ep kzalloc error\n");
  1205. goto clean_up;
  1206. }
  1207. fusb300->ep[i] = _ep[i];
  1208. }
  1209. spin_lock_init(&fusb300->lock);
  1210. dev_set_drvdata(&pdev->dev, fusb300);
  1211. fusb300->gadget.ops = &fusb300_gadget_ops;
  1212. device_initialize(&fusb300->gadget.dev);
  1213. dev_set_name(&fusb300->gadget.dev, "gadget");
  1214. fusb300->gadget.is_dualspeed = 1;
  1215. fusb300->gadget.dev.parent = &pdev->dev;
  1216. fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1217. fusb300->gadget.dev.release = pdev->dev.release;
  1218. fusb300->gadget.name = udc_name;
  1219. fusb300->reg = reg;
  1220. ret = request_irq(ires->start, fusb300_irq, IRQF_DISABLED | IRQF_SHARED,
  1221. udc_name, fusb300);
  1222. if (ret < 0) {
  1223. pr_err("request_irq error (%d)\n", ret);
  1224. goto clean_up;
  1225. }
  1226. ret = request_irq(ires1->start, fusb300_irq,
  1227. IRQF_DISABLED | IRQF_SHARED, udc_name, fusb300);
  1228. if (ret < 0) {
  1229. pr_err("request_irq1 error (%d)\n", ret);
  1230. goto clean_up;
  1231. }
  1232. INIT_LIST_HEAD(&fusb300->gadget.ep_list);
  1233. for (i = 0; i < FUSB300_MAX_NUM_EP ; i++) {
  1234. struct fusb300_ep *ep = fusb300->ep[i];
  1235. if (i != 0) {
  1236. INIT_LIST_HEAD(&fusb300->ep[i]->ep.ep_list);
  1237. list_add_tail(&fusb300->ep[i]->ep.ep_list,
  1238. &fusb300->gadget.ep_list);
  1239. }
  1240. ep->fusb300 = fusb300;
  1241. INIT_LIST_HEAD(&ep->queue);
  1242. ep->ep.name = fusb300_ep_name[i];
  1243. ep->ep.ops = &fusb300_ep_ops;
  1244. ep->ep.maxpacket = HS_BULK_MAX_PACKET_SIZE;
  1245. }
  1246. fusb300->ep[0]->ep.maxpacket = HS_CTL_MAX_PACKET_SIZE;
  1247. fusb300->ep[0]->epnum = 0;
  1248. fusb300->gadget.ep0 = &fusb300->ep[0]->ep;
  1249. INIT_LIST_HEAD(&fusb300->gadget.ep0->ep_list);
  1250. the_controller = fusb300;
  1251. fusb300->ep0_req = fusb300_alloc_request(&fusb300->ep[0]->ep,
  1252. GFP_KERNEL);
  1253. if (fusb300->ep0_req == NULL)
  1254. goto clean_up3;
  1255. init_controller(fusb300);
  1256. ret = usb_add_gadget_udc(&pdev->dev, &fusb300->gadget);
  1257. if (ret)
  1258. goto err_add_udc;
  1259. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1260. return 0;
  1261. err_add_udc:
  1262. fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
  1263. clean_up3:
  1264. free_irq(ires->start, fusb300);
  1265. clean_up:
  1266. if (fusb300) {
  1267. if (fusb300->ep0_req)
  1268. fusb300_free_request(&fusb300->ep[0]->ep,
  1269. fusb300->ep0_req);
  1270. kfree(fusb300);
  1271. }
  1272. if (reg)
  1273. iounmap(reg);
  1274. return ret;
  1275. }
  1276. static struct platform_driver fusb300_driver = {
  1277. .remove = __exit_p(fusb300_remove),
  1278. .driver = {
  1279. .name = (char *) udc_name,
  1280. .owner = THIS_MODULE,
  1281. },
  1282. };
  1283. static int __init fusb300_udc_init(void)
  1284. {
  1285. return platform_driver_probe(&fusb300_driver, fusb300_probe);
  1286. }
  1287. module_init(fusb300_udc_init);
  1288. static void __exit fusb300_udc_cleanup(void)
  1289. {
  1290. platform_driver_unregister(&fusb300_driver);
  1291. }
  1292. module_exit(fusb300_udc_cleanup);